1 /* 2 * Copyright © 2017 Advanced Micro Devices, Inc. 3 * 4 * SPDX-License-Identifier: MIT 5 */ 6 7 #ifndef AC_SURFACE_H 8 #define AC_SURFACE_H 9 10 #include "amd_family.h" 11 #include "util/format/u_format.h" 12 13 /* NIR is optional. Some components don't want to include NIR with ac_surface.h. */ 14 #ifdef AC_SURFACE_INCLUDE_NIR 15 #include "compiler/nir/nir_builder.h" 16 #endif 17 18 #include <stdbool.h> 19 #include <stdint.h> 20 #include <stdio.h> 21 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 26 /* Forward declarations. */ 27 struct ac_addrlib; 28 29 struct amdgpu_gpu_info; 30 struct radeon_info; 31 32 #define RADEON_SURF_MAX_LEVELS 17 33 34 enum radeon_surf_mode 35 { 36 RADEON_SURF_MODE_LINEAR_ALIGNED = 1, 37 RADEON_SURF_MODE_1D = 2, 38 RADEON_SURF_MODE_2D = 3, 39 }; 40 41 /* This describes D/S/Z/R swizzle modes. 42 * Defined in the GB_TILE_MODEn.MICRO_TILE_MODE_NEW order. 43 */ 44 enum radeon_micro_mode 45 { 46 RADEON_MICRO_MODE_DISPLAY = 0, 47 RADEON_MICRO_MODE_STANDARD = 1, 48 RADEON_MICRO_MODE_DEPTH = 2, 49 RADEON_MICRO_MODE_RENDER = 3, /* gfx9 and older: rotated */ 50 }; 51 52 /* the first 16 bits are reserved for libdrm_radeon, don't use them */ 53 #define RADEON_SURF_SCANOUT (1 << 16) 54 #define RADEON_SURF_ZBUFFER (1 << 17) 55 #define RADEON_SURF_SBUFFER (1 << 18) 56 #define RADEON_SURF_Z_OR_SBUFFER (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER) 57 /* bits 19 and 20 are reserved for libdrm_radeon, don't use them */ 58 #define RADEON_SURF_FMASK (1 << 21) 59 #define RADEON_SURF_DISABLE_DCC (1ull << 22) 60 #define RADEON_SURF_TC_COMPATIBLE_HTILE (1ull << 23) 61 #define RADEON_SURF_IMPORTED (1ull << 24) 62 #define RADEON_SURF_CONTIGUOUS_DCC_LAYERS (1ull << 25) 63 #define RADEON_SURF_SHAREABLE (1ull << 26) 64 #define RADEON_SURF_NO_RENDER_TARGET (1ull << 27) 65 /* Force a swizzle mode (gfx9+) or tile mode (gfx6-8). 66 * If this is not set, optimize for space. */ 67 #define RADEON_SURF_FORCE_SWIZZLE_MODE (1ull << 28) 68 #define RADEON_SURF_NO_FMASK (1ull << 29) 69 /* This disables HTILE on gfx6-11, and HiZ/HiS on gfx12, */ 70 #define RADEON_SURF_NO_HTILE (1ull << 30) 71 #define RADEON_SURF_FORCE_MICRO_TILE_MODE (1ull << 31) 72 #define RADEON_SURF_PRT (1ull << 32) 73 #define RADEON_SURF_VRS_RATE (1ull << 33) 74 /* Block compressed + linear format is not supported in addrlib. These surface can be 75 * used as transfer resource. This flag indicates not to set flags.texture flag for 76 * color surface in gfx9_compute_surface(). */ 77 #define RADEON_SURF_NO_TEXTURE (1ull << 34) 78 #define RADEON_SURF_NO_STENCIL_ADJUST (1ull << 35) 79 #define RADEON_SURF_PREFER_4K_ALIGNMENT (1ull << 36) 80 #define RADEON_SURF_PREFER_64K_ALIGNMENT (1ull << 37) 81 #define RADEON_SURF_VIDEO_REFERENCE (1ull << 38) 82 83 struct legacy_surf_level { 84 uint32_t offset_256B; /* divided by 256, the hw can only do 40-bit addresses */ 85 uint32_t slice_size_dw; /* in dwords; max = 4GB / 4. */ 86 unsigned nblk_x : 15; 87 unsigned nblk_y : 15; 88 enum radeon_surf_mode mode : 2; 89 }; 90 91 struct legacy_surf_dcc_level { 92 uint32_t dcc_offset; /* relative offset within DCC mip tree */ 93 uint32_t dcc_fast_clear_size; 94 uint32_t dcc_slice_fast_clear_size; 95 }; 96 97 struct legacy_surf_fmask { 98 unsigned slice_tile_max; /* max 4M */ 99 uint8_t tiling_index; /* max 31 */ 100 uint8_t bankh; /* max 8 */ 101 uint16_t pitch_in_pixels; 102 }; 103 104 struct legacy_surf_layout { 105 unsigned bankw : 4; /* max 8 */ 106 unsigned bankh : 4; /* max 8 */ 107 unsigned mtilea : 4; /* max 8 */ 108 unsigned tile_split : 13; /* max 4K */ 109 unsigned stencil_tile_split : 13; /* max 4K */ 110 unsigned pipe_config : 5; /* max 17 */ 111 unsigned num_banks : 5; /* max 16 */ 112 unsigned macro_tile_index : 4; /* max 15 */ 113 114 /* Whether the depth miptree or stencil miptree as used by the DB are 115 * adjusted from their TC compatible form to ensure depth/stencil 116 * compatibility. If either is true, the corresponding plane cannot be 117 * sampled from. 118 */ 119 unsigned depth_adjusted : 1; 120 unsigned stencil_adjusted : 1; 121 122 struct legacy_surf_level level[RADEON_SURF_MAX_LEVELS]; 123 uint8_t tiling_index[RADEON_SURF_MAX_LEVELS]; 124 125 union { 126 /* Color layout */ 127 struct { 128 struct legacy_surf_dcc_level dcc_level[RADEON_SURF_MAX_LEVELS]; 129 struct legacy_surf_fmask fmask; 130 unsigned cmask_slice_tile_max; 131 } color; 132 133 /* Z/S layout */ 134 struct { 135 struct legacy_surf_level stencil_level[RADEON_SURF_MAX_LEVELS]; 136 uint8_t stencil_tiling_index[RADEON_SURF_MAX_LEVELS]; 137 } zs; 138 }; 139 }; 140 141 /* Same as addrlib - AddrResourceType. */ 142 enum gfx9_resource_type 143 { 144 RADEON_RESOURCE_1D = 0, 145 RADEON_RESOURCE_2D, 146 RADEON_RESOURCE_3D, 147 }; 148 149 struct gfx9_surf_meta_flags { 150 uint8_t rb_aligned : 1; /* optimal for RBs */ 151 uint8_t pipe_aligned : 1; /* optimal for L2 */ 152 uint8_t independent_64B_blocks : 1; 153 uint8_t independent_128B_blocks : 1; 154 uint8_t max_compressed_block_size : 2; 155 uint8_t display_equation_valid : 1; 156 }; 157 158 struct gfx9_surf_meta_level { 159 unsigned offset; 160 unsigned size; /* the size of one level in one layer (the image is an array of layers 161 * where each layer has an array of levels) */ 162 }; 163 164 /** 165 * Meta address equation. 166 * 167 * DCC/HTILE address equation for doing DCC/HTILE address computations in shaders. 168 * 169 * ac_surface_meta_address_test.c contains the reference implementation. 170 * ac_nir_{dcc,htile}_addr_from_coord is the NIR implementation. 171 * 172 * For DCC: 173 * The gfx9 equation doesn't support mipmapping. 174 * The gfx10 equation doesn't support mipmapping and MSAA. 175 * (those are also limitations of Addr2ComputeDccAddrFromCoord) 176 * 177 * For HTILE: 178 * The gfx9 equation isn't implemented. 179 * The gfx10 equation doesn't support mipmapping. 180 */ 181 struct gfx9_meta_equation { 182 uint16_t meta_block_width; 183 uint16_t meta_block_height; 184 uint16_t meta_block_depth; 185 186 union { 187 /* The gfx9 DCC equation is chip-specific, and it varies with: 188 * - resource type 189 * - swizzle_mode 190 * - bpp 191 * - number of samples 192 * - number of fragments 193 * - pipe_aligned 194 * - rb_aligned 195 */ 196 struct { 197 uint8_t num_bits; 198 uint8_t num_pipe_bits; 199 200 struct { 201 struct { 202 uint8_t dim:3; /* 0..4 */ 203 uint8_t ord:5; /* 0..31 */ 204 } coord[5]; /* 0..num_coords-1 */ 205 } bit[20]; /* 0..num_bits-1 */ 206 } gfx9; 207 208 /* The gfx10 DCC equation is chip-specific, it requires 64KB_R_X, and it varies with: 209 * - bpp 210 * - number of samples 211 * - number of fragments 212 * - pipe_aligned 213 * 214 * The gfx10 HTILE equation is chip-specific, it requires 64KB_Z_X, and it varies with: 215 * - number of samples 216 */ 217 uint16_t gfx10_bits[64]; 218 } u; 219 }; 220 221 struct gfx12_hiz_his_layout { 222 uint64_t offset; 223 uint32_t size; 224 uint16_t width_in_tiles; 225 uint16_t height_in_tiles; 226 uint8_t swizzle_mode; 227 uint8_t alignment_log2; 228 }; 229 230 struct gfx9_surf_layout { 231 uint16_t epitch; /* gfx9 only, not on gfx10 */ 232 uint8_t swizzle_mode; /* color or depth */ 233 bool uses_custom_pitch; /* only used by gfx10.3+ */ 234 bool gfx12_enable_dcc; /* set AMDGPU_GEM_CREATE_GFX12_DCC if the placement is VRAM */ 235 236 enum gfx9_resource_type resource_type:8; /* 1D, 2D or 3D */ 237 uint32_t surf_pitch; /* up to 64K (in blocks) */ 238 uint32_t surf_height; /* up to 64K */ 239 240 uint64_t surf_offset; /* 0 unless imported with an offset */ 241 /* The size of the 2D plane containing all mipmap levels. */ 242 uint64_t surf_slice_size; 243 /* Mipmap level offset within the slice in bytes. Only valid for LINEAR. */ 244 uint64_t offset[RADEON_SURF_MAX_LEVELS]; /* up to 64K * 64K * 16 * ~1.33 */ 245 /* Mipmap level pitch in elements. Only valid for LINEAR. */ 246 uint32_t pitch[RADEON_SURF_MAX_LEVELS]; /* up to 64K */ 247 248 uint32_t base_mip_width; /* up to 64K */ 249 uint32_t base_mip_height; /* up to 64K */ 250 251 /* Pitch of level in blocks, only valid for prt images. */ 252 uint32_t prt_level_pitch[RADEON_SURF_MAX_LEVELS]; /* up to 64K */ 253 /* Offset within slice in bytes, only valid for prt images. */ 254 uint64_t prt_level_offset[RADEON_SURF_MAX_LEVELS]; /* up to 64K * 64K * 16 * ~1.33 */ 255 256 /* DCC or HTILE level info */ 257 struct gfx9_surf_meta_level meta_levels[RADEON_SURF_MAX_LEVELS]; 258 259 union { 260 /* Color */ 261 struct { 262 struct gfx9_surf_meta_flags dcc; /* metadata of color */ 263 uint8_t fmask_swizzle_mode; 264 uint16_t fmask_epitch; /* gfx9 only, not on gfx10 */ 265 266 uint16_t dcc_pitch_max; 267 uint16_t dcc_height; 268 269 uint8_t dcc_block_width; 270 uint8_t dcc_block_height; 271 uint8_t dcc_block_depth; 272 273 /* Gfx12 DCC recompression settings used by kernel memory management. 274 * The driver sets these, not ac_compute_surface. 275 */ 276 uint8_t dcc_number_type; /* CB_COLOR0_INFO.NUMBER_TYPE */ 277 uint8_t dcc_data_format; /* [0:4]:CB_COLOR0_INFO.FORMAT, [5]:MM */ 278 bool dcc_write_compress_disable; 279 280 /* Displayable DCC. This is always rb_aligned=0 and pipe_aligned=0. 281 * The 3D engine doesn't support that layout except for chips with 1 RB. 282 * All other chips must set rb_aligned=1. 283 * A compute shader needs to convert from aligned DCC to unaligned. 284 */ 285 uint8_t display_dcc_alignment_log2; 286 uint32_t display_dcc_size; 287 uint16_t display_dcc_pitch_max; /* (mip chain pitch - 1) */ 288 uint16_t display_dcc_height; 289 bool dcc_retile_use_uint16; /* if all values fit into uint16_t */ 290 uint32_t dcc_retile_num_elements; 291 void *dcc_retile_map; 292 293 /* CMASK level info (only level 0) */ 294 struct gfx9_surf_meta_level cmask_level0; 295 296 /* For DCC retiling. */ 297 struct gfx9_meta_equation dcc_equation; /* 2D only */ 298 struct gfx9_meta_equation display_dcc_equation; 299 300 /* For FCE compute. */ 301 struct gfx9_meta_equation cmask_equation; /* 2D only */ 302 } color; 303 304 /* Z/S */ 305 struct { 306 uint64_t stencil_offset; /* separate stencil */ 307 uint16_t stencil_epitch; /* gfx9 only, not on gfx10 */ 308 uint8_t stencil_swizzle_mode; 309 310 struct gfx12_hiz_his_layout hiz, his; 311 312 /* For HTILE VRS. (only Gfx103-Gfx11) */ 313 struct gfx9_meta_equation htile_equation; 314 } zs; 315 }; 316 }; 317 318 struct radeon_surf { 319 /* Format properties. */ 320 uint8_t blk_w : 4; 321 uint8_t blk_h : 4; 322 uint8_t bpe : 5; 323 /* Display, standard(thin), depth, render(rotated). AKA D,S,Z,R swizzle modes. */ 324 uint8_t micro_tile_mode : 3; 325 /* Number of mipmap levels where DCC or HTILE is enabled starting from level 0. 326 * Non-zero levels may be disabled due to alignment constraints, but not 327 * the first level. 328 */ 329 uint8_t num_meta_levels : 4; 330 uint8_t is_linear : 1; 331 uint8_t has_stencil : 1; 332 /* This might be true even if micro_tile_mode isn't displayable or rotated. */ 333 uint8_t is_displayable : 1; 334 /* Thick tiling means 3D tiles. Use 3D compute workgroups for blits. (4x4x4 works well) */ 335 uint8_t thick_tiling : 1; 336 uint8_t first_mip_tail_level : 4; 337 338 /* These are return values. Some of them can be set by the caller, but 339 * they will be treated as hints (e.g. bankw, bankh) and might be 340 * changed by the calculator. 341 */ 342 343 /* Not supported yet for depth + stencil. */ 344 uint16_t prt_tile_width; /* up to 256 roughly (for 64KB tiles) */ 345 uint16_t prt_tile_height; /* up to 256 roughly (for 64KB tiles) */ 346 uint16_t prt_tile_depth; /* up to 32 roughly (for 64KB thick tiles) */ 347 348 /* Tile swizzle can be OR'd with low bits of the BASE_256B address. 349 * The value is the same for all mipmap levels. Supported tile modes: 350 * - GFX6: Only macro tiling. 351 * - GFX9: Only *_X and *_T swizzle modes. Level 0 must not be in the mip 352 * tail. 353 * 354 * Only these surfaces are allowed to set it: 355 * - color (if it doesn't have to be displayable) 356 * - DCC (same tile swizzle as color) 357 * - FMASK 358 * - CMASK if it's TC-compatible or if the gen is GFX9 359 * - depth/stencil if HTILE is not TC-compatible and if the gen is not GFX9 360 */ 361 uint16_t tile_swizzle; /* it has 16 bits because gfx11 shifts it by 2 bits */ 362 uint8_t fmask_tile_swizzle; 363 364 /* Use (1 << log2) to compute the alignment. */ 365 uint8_t surf_alignment_log2; 366 uint8_t fmask_alignment_log2; 367 uint8_t meta_alignment_log2; /* DCC or HTILE */ 368 uint8_t cmask_alignment_log2; 369 uint8_t alignment_log2; 370 371 /* DRM format modifier. Set to DRM_FORMAT_MOD_INVALID to have addrlib 372 * select tiling parameters instead. 373 */ 374 uint64_t modifier; 375 uint64_t flags; 376 377 uint64_t surf_size; 378 uint64_t fmask_size; 379 uint32_t fmask_slice_size; /* max 2^31 (16K * 16K * 8) */ 380 381 /* DCC and HTILE (they are very small) */ 382 uint32_t meta_size; 383 uint32_t meta_slice_size; 384 uint32_t meta_pitch; 385 386 uint32_t cmask_size; 387 uint32_t cmask_slice_size; 388 uint16_t cmask_pitch; /* GFX9+ */ 389 uint16_t cmask_height; /* GFX9+ */ 390 391 /* All buffers combined. */ 392 uint64_t meta_offset; /* DCC (Gfx8-Gfx11) or HTILE (Gfx6-Gfx11) */ 393 uint64_t fmask_offset; /* Gfx6-Gfx10 */ 394 uint64_t cmask_offset; /* Gfx6-Gfx10 */ 395 uint64_t display_dcc_offset; /* Gfx9-Gfx11 */ 396 uint64_t total_size; 397 398 union { 399 /* Gfx3-8 surface info. 400 * 401 * Some of them can be set by the caller if certain parameters are 402 * desirable. The allocator will try to obey them. 403 */ 404 struct legacy_surf_layout legacy; 405 406 /* Gfx9+ surface info. */ 407 struct gfx9_surf_layout gfx9; 408 } u; 409 }; 410 411 struct ac_surf_info { 412 uint32_t width; /* up to 64K */ 413 uint32_t height; /* up to 64K */ 414 uint32_t depth; /* up to 16K */ 415 uint8_t samples; /* For Z/S: samples; For color: FMASK coverage samples */ 416 uint8_t storage_samples; /* For color: allocated samples */ 417 uint8_t levels; 418 uint8_t num_channels; /* heuristic for displayability */ 419 uint16_t array_size; 420 uint32_t *surf_index; /* Set a monotonic counter for tile swizzling. */ 421 uint32_t *fmask_surf_index; 422 }; 423 424 struct ac_surf_config { 425 struct ac_surf_info info; 426 unsigned is_1d : 1; 427 unsigned is_3d : 1; 428 unsigned is_cube : 1; 429 unsigned is_array : 1; 430 }; 431 432 /* Output parameters for ac_surface_compute_nbc_view */ 433 struct ac_surf_nbc_view { 434 bool valid; 435 uint32_t width; /* up to 64K */ 436 uint32_t height; /* up to 64K */ 437 uint32_t level; 438 uint32_t num_levels; /* Used for max_mip in the resource descriptor */ 439 uint8_t tile_swizzle; 440 uint64_t base_address_offset; 441 }; 442 443 struct ac_addrlib *ac_addrlib_create(const struct radeon_info *info, uint64_t *max_alignment); 444 void ac_addrlib_destroy(struct ac_addrlib *addrlib); 445 void *ac_addrlib_get_handle(struct ac_addrlib *addrlib); 446 447 int ac_compute_surface(struct ac_addrlib *addrlib, const struct radeon_info *info, 448 const struct ac_surf_config *config, enum radeon_surf_mode mode, 449 struct radeon_surf *surf); 450 void ac_surface_zero_dcc_fields(struct radeon_surf *surf); 451 unsigned ac_pipe_config_to_num_pipes(unsigned pipe_config); 452 453 #define AC_SURF_METADATA_FLAG_EXTRA_MD_BIT 0 454 #define AC_SURF_METADATA_FLAG_FAMILY_OVERRIDEN_BIT 1 455 void ac_surface_apply_bo_metadata(enum amd_gfx_level gfx_level, struct radeon_surf *surf, 456 uint64_t tiling_flags, enum radeon_surf_mode *mode); 457 void ac_surface_compute_bo_metadata(const struct radeon_info *info, struct radeon_surf *surf, 458 uint64_t *tiling_flags); 459 460 bool ac_surface_apply_umd_metadata(const struct radeon_info *info, struct radeon_surf *surf, 461 unsigned num_storage_samples, unsigned num_mipmap_levels, 462 unsigned size_metadata, const uint32_t metadata[64]); 463 void ac_surface_compute_umd_metadata(const struct radeon_info *info, struct radeon_surf *surf, 464 unsigned num_mipmap_levels, uint32_t desc[8], 465 unsigned *size_metadata, uint32_t metadata[64], 466 bool include_tool_md); 467 468 bool ac_surface_override_offset_stride(const struct radeon_info *info, struct radeon_surf *surf, 469 unsigned num_layers, unsigned num_mipmap_levels, 470 uint64_t offset, unsigned pitch); 471 472 struct ac_modifier_options { 473 bool dcc; /* Whether to allow DCC. */ 474 bool dcc_retile; /* Whether to allow use of a DCC retile map. */ 475 }; 476 477 bool ac_is_modifier_supported(const struct radeon_info *info, 478 const struct ac_modifier_options *options, 479 enum pipe_format format, 480 uint64_t modifier); 481 bool ac_get_supported_modifiers(const struct radeon_info *info, 482 const struct ac_modifier_options *options, 483 enum pipe_format format, 484 unsigned *mod_count, 485 uint64_t *mods); 486 bool ac_modifier_has_dcc(uint64_t modifier); 487 bool ac_modifier_has_dcc_retile(uint64_t modifier); 488 bool ac_modifier_supports_dcc_image_stores(enum amd_gfx_level gfx_level, uint64_t modifier); 489 void ac_modifier_max_extent(const struct radeon_info *info, 490 uint64_t modifier, uint32_t *width, uint32_t *height); 491 492 unsigned ac_surface_get_nplanes(const struct radeon_surf *surf); 493 uint64_t ac_surface_get_plane_offset(enum amd_gfx_level gfx_level, 494 const struct radeon_surf *surf, 495 unsigned plane, unsigned layer); 496 uint64_t ac_surface_get_plane_stride(enum amd_gfx_level gfx_level, 497 const struct radeon_surf *surf, 498 unsigned plane, unsigned level); 499 /* Of the whole miplevel, not an individual layer */ 500 uint64_t ac_surface_get_plane_size(const struct radeon_surf *surf, 501 unsigned plane); 502 503 uint64_t ac_surface_addr_from_coord(struct ac_addrlib *addrlib, const struct radeon_info *info, 504 const struct radeon_surf *surf, 505 const struct ac_surf_info *surf_info, unsigned level, 506 unsigned x, unsigned y, unsigned layer, bool is_3d); 507 void ac_surface_compute_nbc_view(struct ac_addrlib *addrlib, const struct radeon_info *info, 508 const struct radeon_surf *surf, 509 const struct ac_surf_info *surf_info, unsigned level, 510 unsigned layer, struct ac_surf_nbc_view *out); 511 512 void ac_surface_print_info(FILE *out, const struct radeon_info *info, 513 const struct radeon_surf *surf); 514 515 bool ac_surface_supports_dcc_image_stores(enum amd_gfx_level gfx_level, 516 const struct radeon_surf *surf); 517 518 #ifdef AC_SURFACE_INCLUDE_NIR 519 nir_def *ac_nir_dcc_addr_from_coord(nir_builder *b, const struct radeon_info *info, 520 unsigned bpe, const struct gfx9_meta_equation *equation, 521 nir_def *dcc_pitch, nir_def *dcc_height, 522 nir_def *dcc_slice_size, 523 nir_def *x, nir_def *y, nir_def *z, 524 nir_def *sample, nir_def *pipe_xor); 525 526 nir_def *ac_nir_cmask_addr_from_coord(nir_builder *b, const struct radeon_info *info, 527 const struct gfx9_meta_equation *equation, 528 nir_def *cmask_pitch, nir_def *cmask_height, 529 nir_def *cmask_slice_size, 530 nir_def *x, nir_def *y, nir_def *z, 531 nir_def *pipe_xor, 532 nir_def **bit_position); 533 534 nir_def *ac_nir_htile_addr_from_coord(nir_builder *b, const struct radeon_info *info, 535 const struct gfx9_meta_equation *equation, 536 nir_def *htile_pitch, 537 nir_def *htile_slice_size, 538 nir_def *x, nir_def *y, nir_def *z, 539 nir_def *pipe_xor); 540 #endif 541 542 #ifdef __cplusplus 543 } 544 #endif 545 546 #endif /* AC_SURFACE_H */ 547