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1377 { 1378 "chips": ["gfx9"], 1379 "map": {"at": 2524, "to": "mm"}, 1380 "name": "SQ_WAVE_TTMP11" 1381 }, 1382 { 1383 "chips": ["gfx9"], 1384 "map": {"at": 2528, "to": "mm"}, 1385 "name": "SQ_WAVE_TTMP12" 1386 }, 1387 { 1388 "chips": ["gfx9"], 1389 "map": {"at": 2532, "to": "mm"}, 1390 "name": "SQ_WAVE_TTMP13" 1391 }, 1392 { 1393 "chips": ["gfx9"], 1394 "map": {"at": 2536, "to": "mm"}, 1395 "name": "SQ_WAVE_TTMP14" 1396 }, 1397 { 1398 "chips": ["gfx9"], 1399 "map": {"at": 2540, "to": "mm"}, 1400 "name": "SQ_WAVE_TTMP15" 1401 }, 1402 { 1403 "chips": ["gfx9"], 1404 "map": {"at": 2544, "to": "mm"}, 1405 "name": "SQ_WAVE_M0" 1406 }, 1407 { 1408 "chips": ["gfx9"], 1409 "map": {"at": 2552, "to": "mm"}, 1410 "name": "SQ_WAVE_EXEC_LO" 1411 }, 1412 { 1413 "chips": ["gfx9"], 1414 "map": {"at": 2556, "to": "mm"}, 1415 "name": "SQ_WAVE_EXEC_HI" 1416 }, 1417 { 1418 "chips": ["gfx9"], 1419 "map": {"at": 32776, "to": "mm"}, 1420 "name": "GRBM_STATUS2", 1421 "type_ref": "GRBM_STATUS2" 1422 }, 1423 { 1424 "chips": ["gfx9"], 1425 "map": {"at": 32784, "to": "mm"}, 1426 "name": "GRBM_STATUS", 1427 "type_ref": "GRBM_STATUS" 1428 }, 1429 { 1430 "chips": ["gfx9"], 1431 "map": {"at": 32788, "to": "mm"}, 1432 "name": "GRBM_STATUS_SE0", 1433 "type_ref": "GRBM_STATUS_SE0" 1434 }, 1435 { 1436 "chips": ["gfx9"], 1437 "map": {"at": 32792, "to": "mm"}, 1438 "name": "GRBM_STATUS_SE1", 1439 "type_ref": "GRBM_STATUS_SE0" 1440 }, 1441 { 1442 "chips": ["gfx9"], 1443 "map": {"at": 32824, "to": "mm"}, 1444 "name": "GRBM_STATUS_SE2", 1445 "type_ref": "GRBM_STATUS_SE0" 1446 }, 1447 { 1448 "chips": ["gfx9"], 1449 "map": {"at": 32828, "to": "mm"}, 1450 "name": "GRBM_STATUS_SE3", 1451 "type_ref": "GRBM_STATUS_SE0" 1452 }, 1453 { 1454 "chips": ["gfx9"], 1455 "map": {"at": 33296, "to": "mm"}, 1456 "name": "CP_CPC_STATUS", 1457 "type_ref": "CP_CPC_STATUS" 1458 }, 1459 { 1460 "chips": ["gfx9"], 1461 "map": {"at": 33300, "to": "mm"}, 1462 "name": "CP_CPC_BUSY_STAT", 1463 "type_ref": "CP_CPC_BUSY_STAT" 1464 }, 1465 { 1466 "chips": ["gfx9"], 1467 "map": {"at": 33304, "to": "mm"}, 1468 "name": "CP_CPC_STALLED_STAT1", 1469 "type_ref": "CP_CPC_STALLED_STAT1" 1470 }, 1471 { 1472 "chips": ["gfx9"], 1473 "map": {"at": 33308, "to": "mm"}, 1474 "name": "CP_CPF_STATUS", 1475 "type_ref": "CP_CPF_STATUS" 1476 }, 1477 { 1478 "chips": ["gfx9"], 1479 "map": {"at": 33312, "to": "mm"}, 1480 "name": "CP_CPF_BUSY_STAT", 1481 "type_ref": "CP_CPF_BUSY_STAT" 1482 }, 1483 { 1484 "chips": ["gfx9"], 1485 "map": {"at": 33316, "to": "mm"}, 1486 "name": "CP_CPF_STALLED_STAT1", 1487 "type_ref": "CP_CPF_STALLED_STAT1" 1488 }, 1489 { 1490 "chips": ["gfx9"], 1491 "map": {"at": 33324, "to": "mm"}, 1492 "name": "CP_CPC_GRBM_FREE_COUNT", 1493 "type_ref": "CP_CPC_GRBM_FREE_COUNT" 1494 }, 1495 { 1496 "chips": ["gfx9"], 1497 "map": {"at": 33344, "to": "mm"}, 1498 "name": "CP_CPC_SCRATCH_INDEX", 1499 "type_ref": "CP_CPC_SCRATCH_INDEX" 1500 }, 1501 { 1502 "chips": ["gfx9"], 1503 "map": {"at": 33348, "to": "mm"}, 1504 "name": "CP_CPC_SCRATCH_DATA" 1505 }, 1506 { 1507 "chips": ["gfx9"], 1508 "map": {"at": 33352, "to": "mm"}, 1509 "name": "CP_CPF_GRBM_FREE_COUNT", 1510 "type_ref": "CP_CPF_GRBM_FREE_COUNT" 1511 }, 1512 { 1513 "chips": ["gfx9"], 1514 "map": {"at": 33436, "to": "mm"}, 1515 "name": "CP_CPC_HALT_HYST_COUNT", 1516 "type_ref": "CP_CPC_HALT_HYST_COUNT" 1517 }, 1518 { 1519 "chips": ["gfx9"], 1520 "map": {"at": 36608, "to": "mm"}, 1521 "name": "SQ_BUF_RSRC_WORD0" 1522 }, 1523 { 1524 "chips": ["gfx9"], 1525 "map": {"at": 36612, "to": "mm"}, 1526 "name": "SQ_BUF_RSRC_WORD1", 1527 "type_ref": "SQ_BUF_RSRC_WORD1" 1528 }, 1529 { 1530 "chips": ["gfx9"], 1531 "map": {"at": 36616, "to": "mm"}, 1532 "name": "SQ_BUF_RSRC_WORD2" 1533 }, 1534 { 1535 "chips": ["gfx9"], 1536 "map": {"at": 36620, "to": "mm"}, 1537 "name": "SQ_BUF_RSRC_WORD3", 1538 "type_ref": "SQ_BUF_RSRC_WORD3" 1539 }, 1540 { 1541 "chips": ["gfx9"], 1542 "map": {"at": 36624, "to": "mm"}, 1543 "name": "SQ_IMG_RSRC_WORD0" 1544 }, 1545 { 1546 "chips": ["gfx9"], 1547 "map": {"at": 36628, "to": "mm"}, 1548 "name": "SQ_IMG_RSRC_WORD1", 1549 "type_ref": "SQ_IMG_RSRC_WORD1" 1550 }, 1551 { 1552 "chips": ["gfx9"], 1553 "map": {"at": 36632, "to": "mm"}, 1554 "name": "SQ_IMG_RSRC_WORD2", 1555 "type_ref": "SQ_IMG_RSRC_WORD2" 1556 }, 1557 { 1558 "chips": ["gfx9"], 1559 "map": {"at": 36636, "to": "mm"}, 1560 "name": "SQ_IMG_RSRC_WORD3", 1561 "type_ref": "SQ_IMG_RSRC_WORD3" 1562 }, 1563 { 1564 "chips": ["gfx9"], 1565 "map": {"at": 36640, "to": "mm"}, 1566 "name": "SQ_IMG_RSRC_WORD4", 1567 "type_ref": "SQ_IMG_RSRC_WORD4" 1568 }, 1569 { 1570 "chips": ["gfx9"], 1571 "map": {"at": 36644, "to": "mm"}, 1572 "name": "SQ_IMG_RSRC_WORD5", 1573 "type_ref": "SQ_IMG_RSRC_WORD5" 1574 }, 1575 { 1576 "chips": ["gfx9"], 1577 "map": {"at": 36648, "to": "mm"}, 1578 "name": "SQ_IMG_RSRC_WORD6", 1579 "type_ref": "SQ_IMG_RSRC_WORD6" 1580 }, 1581 { 1582 "chips": ["gfx9"], 1583 "map": {"at": 36652, "to": "mm"}, 1584 "name": "SQ_IMG_RSRC_WORD7" 1585 }, 1586 { 1587 "chips": ["gfx9"], 1588 "map": {"at": 36656, "to": "mm"}, 1589 "name": "SQ_IMG_SAMP_WORD0", 1590 "type_ref": "SQ_IMG_SAMP_WORD0" 1591 }, 1592 { 1593 "chips": ["gfx9"], 1594 "map": {"at": 36660, "to": "mm"}, 1595 "name": "SQ_IMG_SAMP_WORD1", 1596 "type_ref": "SQ_IMG_SAMP_WORD1" 1597 }, 1598 { 1599 "chips": ["gfx9"], 1600 "map": {"at": 36664, "to": "mm"}, 1601 "name": "SQ_IMG_SAMP_WORD2", 1602 "type_ref": "SQ_IMG_SAMP_WORD2" 1603 }, 1604 { 1605 "chips": ["gfx9"], 1606 "map": {"at": 36668, "to": "mm"}, 1607 "name": "SQ_IMG_SAMP_WORD3", 1608 "type_ref": "SQ_IMG_SAMP_WORD3" 1609 }, 1610 { 1611 "chips": ["gfx9"], 1612 "map": {"at": 39160, "to": "mm"}, 1613 "name": "GB_ADDR_CONFIG", 1614 "type_ref": "GB_ADDR_CONFIG" 1615 }, 1616 { 1617 "chips": ["gfx9"], 1618 "map": {"at": 39184, "to": "mm"}, 1619 "name": "GB_TILE_MODE0", 1620 "type_ref": "GB_TILE_MODE0" 1621 }, 1622 { 1623 "chips": ["gfx9"], 1624 "map": {"at": 39188, "to": "mm"}, 1625 "name": "GB_TILE_MODE1", 1626 "type_ref": "GB_TILE_MODE0" 1627 }, 1628 { 1629 "chips": ["gfx9"], 1630 "map": {"at": 39192, "to": "mm"}, 1631 "name": "GB_TILE_MODE2", 1632 "type_ref": "GB_TILE_MODE0" 1633 }, 1634 { 1635 "chips": ["gfx9"], 1636 "map": {"at": 39196, "to": "mm"}, 1637 "name": "GB_TILE_MODE3", 1638 "type_ref": "GB_TILE_MODE0" 1639 }, 1640 { 1641 "chips": ["gfx9"], 1642 "map": {"at": 39200, "to": "mm"}, 1643 "name": "GB_TILE_MODE4", 1644 "type_ref": "GB_TILE_MODE0" 1645 }, 1646 { 1647 "chips": ["gfx9"], 1648 "map": {"at": 39204, "to": "mm"}, 1649 "name": "GB_TILE_MODE5", 1650 "type_ref": "GB_TILE_MODE0" 1651 }, 1652 { 1653 "chips": ["gfx9"], 1654 "map": {"at": 39208, "to": "mm"}, 1655 "name": "GB_TILE_MODE6", 1656 "type_ref": "GB_TILE_MODE0" 1657 }, 1658 { 1659 "chips": ["gfx9"], 1660 "map": {"at": 39212, "to": "mm"}, 1661 "name": "GB_TILE_MODE7", 1662 "type_ref": "GB_TILE_MODE0" 1663 }, 1664 { 1665 "chips": ["gfx9"], 1666 "map": {"at": 39216, "to": "mm"}, 1667 "name": "GB_TILE_MODE8", 1668 "type_ref": "GB_TILE_MODE0" 1669 }, 1670 { 1671 "chips": ["gfx9"], 1672 "map": {"at": 39220, "to": "mm"}, 1673 "name": "GB_TILE_MODE9", 1674 "type_ref": "GB_TILE_MODE0" 1675 }, 1676 { 1677 "chips": ["gfx9"], 1678 "map": {"at": 39224, "to": "mm"}, 1679 "name": "GB_TILE_MODE10", 1680 "type_ref": "GB_TILE_MODE0" 1681 }, 1682 { 1683 "chips": ["gfx9"], 1684 "map": {"at": 39228, "to": "mm"}, 1685 "name": "GB_TILE_MODE11", 1686 "type_ref": "GB_TILE_MODE0" 1687 }, 1688 { 1689 "chips": ["gfx9"], 1690 "map": {"at": 39232, "to": "mm"}, 1691 "name": "GB_TILE_MODE12", 1692 "type_ref": "GB_TILE_MODE0" 1693 }, 1694 { 1695 "chips": ["gfx9"], 1696 "map": {"at": 39236, "to": "mm"}, 1697 "name": "GB_TILE_MODE13", 1698 "type_ref": "GB_TILE_MODE0" 1699 }, 1700 { 1701 "chips": ["gfx9"], 1702 "map": {"at": 39240, "to": "mm"}, 1703 "name": "GB_TILE_MODE14", 1704 "type_ref": "GB_TILE_MODE0" 1705 }, 1706 { 1707 "chips": ["gfx9"], 1708 "map": {"at": 39244, "to": "mm"}, 1709 "name": "GB_TILE_MODE15", 1710 "type_ref": "GB_TILE_MODE0" 1711 }, 1712 { 1713 "chips": ["gfx9"], 1714 "map": {"at": 39248, "to": "mm"}, 1715 "name": "GB_TILE_MODE16", 1716 "type_ref": "GB_TILE_MODE0" 1717 }, 1718 { 1719 "chips": ["gfx9"], 1720 "map": {"at": 39252, "to": "mm"}, 1721 "name": "GB_TILE_MODE17", 1722 "type_ref": "GB_TILE_MODE0" 1723 }, 1724 { 1725 "chips": ["gfx9"], 1726 "map": {"at": 39256, "to": "mm"}, 1727 "name": "GB_TILE_MODE18", 1728 "type_ref": "GB_TILE_MODE0" 1729 }, 1730 { 1731 "chips": ["gfx9"], 1732 "map": {"at": 39260, "to": "mm"}, 1733 "name": "GB_TILE_MODE19", 1734 "type_ref": "GB_TILE_MODE0" 1735 }, 1736 { 1737 "chips": ["gfx9"], 1738 "map": {"at": 39264, "to": "mm"}, 1739 "name": "GB_TILE_MODE20", 1740 "type_ref": "GB_TILE_MODE0" 1741 }, 1742 { 1743 "chips": ["gfx9"], 1744 "map": {"at": 39268, "to": "mm"}, 1745 "name": "GB_TILE_MODE21", 1746 "type_ref": "GB_TILE_MODE0" 1747 }, 1748 { 1749 "chips": ["gfx9"], 1750 "map": {"at": 39272, "to": "mm"}, 1751 "name": "GB_TILE_MODE22", 1752 "type_ref": "GB_TILE_MODE0" 1753 }, 1754 { 1755 "chips": ["gfx9"], 1756 "map": {"at": 39276, "to": "mm"}, 1757 "name": "GB_TILE_MODE23", 1758 "type_ref": "GB_TILE_MODE0" 1759 }, 1760 { 1761 "chips": ["gfx9"], 1762 "map": {"at": 39280, "to": "mm"}, 1763 "name": "GB_TILE_MODE24", 1764 "type_ref": "GB_TILE_MODE0" 1765 }, 1766 { 1767 "chips": ["gfx9"], 1768 "map": {"at": 39284, "to": "mm"}, 1769 "name": "GB_TILE_MODE25", 1770 "type_ref": "GB_TILE_MODE0" 1771 }, 1772 { 1773 "chips": ["gfx9"], 1774 "map": {"at": 39288, "to": "mm"}, 1775 "name": "GB_TILE_MODE26", 1776 "type_ref": "GB_TILE_MODE0" 1777 }, 1778 { 1779 "chips": ["gfx9"], 1780 "map": {"at": 39292, "to": "mm"}, 1781 "name": "GB_TILE_MODE27", 1782 "type_ref": "GB_TILE_MODE0" 1783 }, 1784 { 1785 "chips": ["gfx9"], 1786 "map": {"at": 39296, "to": "mm"}, 1787 "name": "GB_TILE_MODE28", 1788 "type_ref": "GB_TILE_MODE0" 1789 }, 1790 { 1791 "chips": ["gfx9"], 1792 "map": {"at": 39300, "to": "mm"}, 1793 "name": "GB_TILE_MODE29", 1794 "type_ref": "GB_TILE_MODE0" 1795 }, 1796 { 1797 "chips": ["gfx9"], 1798 "map": {"at": 39304, "to": "mm"}, 1799 "name": "GB_TILE_MODE30", 1800 "type_ref": "GB_TILE_MODE0" 1801 }, 1802 { 1803 "chips": ["gfx9"], 1804 "map": {"at": 39308, "to": "mm"}, 1805 "name": "GB_TILE_MODE31", 1806 "type_ref": "GB_TILE_MODE0" 1807 }, 1808 { 1809 "chips": ["gfx9"], 1810 "map": {"at": 39312, "to": "mm"}, 1811 "name": "GB_MACROTILE_MODE0", 1812 "type_ref": "GB_MACROTILE_MODE0" 1813 }, 1814 { 1815 "chips": ["gfx9"], 1816 "map": {"at": 39316, "to": "mm"}, 1817 "name": "GB_MACROTILE_MODE1", 1818 "type_ref": "GB_MACROTILE_MODE0" 1819 }, 1820 { 1821 "chips": ["gfx9"], 1822 "map": {"at": 39320, "to": "mm"}, 1823 "name": "GB_MACROTILE_MODE2", 1824 "type_ref": "GB_MACROTILE_MODE0" 1825 }, 1826 { 1827 "chips": ["gfx9"], 1828 "map": {"at": 39324, "to": "mm"}, 1829 "name": "GB_MACROTILE_MODE3", 1830 "type_ref": "GB_MACROTILE_MODE0" 1831 }, 1832 { 1833 "chips": ["gfx9"], 1834 "map": {"at": 39328, "to": "mm"}, 1835 "name": "GB_MACROTILE_MODE4", 1836 "type_ref": "GB_MACROTILE_MODE0" 1837 }, 1838 { 1839 "chips": ["gfx9"], 1840 "map": {"at": 39332, "to": "mm"}, 1841 "name": "GB_MACROTILE_MODE5", 1842 "type_ref": "GB_MACROTILE_MODE0" 1843 }, 1844 { 1845 "chips": ["gfx9"], 1846 "map": {"at": 39336, "to": "mm"}, 1847 "name": "GB_MACROTILE_MODE6", 1848 "type_ref": "GB_MACROTILE_MODE0" 1849 }, 1850 { 1851 "chips": ["gfx9"], 1852 "map": {"at": 39340, "to": "mm"}, 1853 "name": "GB_MACROTILE_MODE7", 1854 "type_ref": "GB_MACROTILE_MODE0" 1855 }, 1856 { 1857 "chips": ["gfx9"], 1858 "map": {"at": 39344, "to": "mm"}, 1859 "name": "GB_MACROTILE_MODE8", 1860 "type_ref": "GB_MACROTILE_MODE0" 1861 }, 1862 { 1863 "chips": ["gfx9"], 1864 "map": {"at": 39348, "to": "mm"}, 1865 "name": "GB_MACROTILE_MODE9", 1866 "type_ref": "GB_MACROTILE_MODE0" 1867 }, 1868 { 1869 "chips": ["gfx9"], 1870 "map": {"at": 39352, "to": "mm"}, 1871 "name": "GB_MACROTILE_MODE10", 1872 "type_ref": "GB_MACROTILE_MODE0" 1873 }, 1874 { 1875 "chips": ["gfx9"], 1876 "map": {"at": 39356, "to": "mm"}, 1877 "name": "GB_MACROTILE_MODE11", 1878 "type_ref": "GB_MACROTILE_MODE0" 1879 }, 1880 { 1881 "chips": ["gfx9"], 1882 "map": {"at": 39360, "to": "mm"}, 1883 "name": "GB_MACROTILE_MODE12", 1884 "type_ref": "GB_MACROTILE_MODE0" 1885 }, 1886 { 1887 "chips": ["gfx9"], 1888 "map": {"at": 39364, "to": "mm"}, 1889 "name": "GB_MACROTILE_MODE13", 1890 "type_ref": "GB_MACROTILE_MODE0" 1891 }, 1892 { 1893 "chips": ["gfx9"], 1894 "map": {"at": 39368, "to": "mm"}, 1895 "name": "GB_MACROTILE_MODE14", 1896 "type_ref": "GB_MACROTILE_MODE0" 1897 }, 1898 { 1899 "chips": ["gfx9"], 1900 "map": {"at": 39372, "to": "mm"}, 1901 "name": "GB_MACROTILE_MODE15", 1902 "type_ref": "GB_MACROTILE_MODE0" 1903 }, 1904 { 1905 "chips": ["gfx9"], 1906 "map": {"at": 45084, "to": "mm"}, 1907 "name": "SPI_SHADER_PGM_RSRC3_PS", 1908 "type_ref": "SPI_SHADER_PGM_RSRC3_PS" 1909 }, 1910 { 1911 "chips": ["gfx9"], 1912 "map": {"at": 45088, "to": "mm"}, 1913 "name": "SPI_SHADER_PGM_LO_PS" 1914 }, 1915 { 1916 "chips": ["gfx9"], 1917 "map": {"at": 45092, "to": "mm"}, 1918 "name": "SPI_SHADER_PGM_HI_PS", 1919 "type_ref": "SPI_SHADER_PGM_HI_PS" 1920 }, 1921 { 1922 "chips": ["gfx9"], 1923 "map": {"at": 45096, "to": "mm"}, 1924 "name": "SPI_SHADER_PGM_RSRC1_PS", 1925 "type_ref": "SPI_SHADER_PGM_RSRC1_PS" 1926 }, 1927 { 1928 "chips": ["gfx9"], 1929 "map": {"at": 45100, "to": "mm"}, 1930 "name": "SPI_SHADER_PGM_RSRC2_PS", 1931 "type_ref": "SPI_SHADER_PGM_RSRC2_PS" 1932 }, 1933 { 1934 "chips": ["gfx9"], 1935 "map": {"at": 45104, "to": "mm"}, 1936 "name": "SPI_SHADER_USER_DATA_PS_0" 1937 }, 1938 { 1939 "chips": ["gfx9"], 1940 "map": {"at": 45108, "to": "mm"}, 1941 "name": "SPI_SHADER_USER_DATA_PS_1" 1942 }, 1943 { 1944 "chips": ["gfx9"], 1945 "map": {"at": 45112, "to": "mm"}, 1946 "name": "SPI_SHADER_USER_DATA_PS_2" 1947 }, 1948 { 1949 "chips": ["gfx9"], 1950 "map": {"at": 45116, "to": "mm"}, 1951 "name": "SPI_SHADER_USER_DATA_PS_3" 1952 }, 1953 { 1954 "chips": ["gfx9"], 1955 "map": {"at": 45120, "to": "mm"}, 1956 "name": "SPI_SHADER_USER_DATA_PS_4" 1957 }, 1958 { 1959 "chips": ["gfx9"], 1960 "map": {"at": 45124, "to": "mm"}, 1961 "name": "SPI_SHADER_USER_DATA_PS_5" 1962 }, 1963 { 1964 "chips": ["gfx9"], 1965 "map": {"at": 45128, "to": "mm"}, 1966 "name": "SPI_SHADER_USER_DATA_PS_6" 1967 }, 1968 { 1969 "chips": ["gfx9"], 1970 "map": {"at": 45132, "to": "mm"}, 1971 "name": "SPI_SHADER_USER_DATA_PS_7" 1972 }, 1973 { 1974 "chips": ["gfx9"], 1975 "map": {"at": 45136, "to": "mm"}, 1976 "name": "SPI_SHADER_USER_DATA_PS_8" 1977 }, 1978 { 1979 "chips": ["gfx9"], 1980 "map": {"at": 45140, "to": "mm"}, 1981 "name": "SPI_SHADER_USER_DATA_PS_9" 1982 }, 1983 { 1984 "chips": ["gfx9"], 1985 "map": {"at": 45144, "to": "mm"}, 1986 "name": "SPI_SHADER_USER_DATA_PS_10" 1987 }, 1988 { 1989 "chips": ["gfx9"], 1990 "map": {"at": 45148, "to": "mm"}, 1991 "name": "SPI_SHADER_USER_DATA_PS_11" 1992 }, 1993 { 1994 "chips": ["gfx9"], 1995 "map": {"at": 45152, "to": "mm"}, 1996 "name": "SPI_SHADER_USER_DATA_PS_12" 1997 }, 1998 { 1999 "chips": ["gfx9"], 2000 "map": {"at": 45156, "to": "mm"}, 2001 "name": "SPI_SHADER_USER_DATA_PS_13" 2002 }, 2003 { 2004 "chips": ["gfx9"], 2005 "map": {"at": 45160, "to": "mm"}, 2006 "name": "SPI_SHADER_USER_DATA_PS_14" 2007 }, 2008 { 2009 "chips": ["gfx9"], 2010 "map": {"at": 45164, "to": "mm"}, 2011 "name": "SPI_SHADER_USER_DATA_PS_15" 2012 }, 2013 { 2014 "chips": ["gfx9"], 2015 "map": {"at": 45168, "to": "mm"}, 2016 "name": "SPI_SHADER_USER_DATA_PS_16" 2017 }, 2018 { 2019 "chips": ["gfx9"], 2020 "map": {"at": 45172, "to": "mm"}, 2021 "name": "SPI_SHADER_USER_DATA_PS_17" 2022 }, 2023 { 2024 "chips": ["gfx9"], 2025 "map": {"at": 45176, "to": "mm"}, 2026 "name": "SPI_SHADER_USER_DATA_PS_18" 2027 }, 2028 { 2029 "chips": ["gfx9"], 2030 "map": {"at": 45180, "to": "mm"}, 2031 "name": "SPI_SHADER_USER_DATA_PS_19" 2032 }, 2033 { 2034 "chips": ["gfx9"], 2035 "map": {"at": 45184, "to": "mm"}, 2036 "name": "SPI_SHADER_USER_DATA_PS_20" 2037 }, 2038 { 2039 "chips": ["gfx9"], 2040 "map": {"at": 45188, "to": "mm"}, 2041 "name": "SPI_SHADER_USER_DATA_PS_21" 2042 }, 2043 { 2044 "chips": ["gfx9"], 2045 "map": {"at": 45192, "to": "mm"}, 2046 "name": "SPI_SHADER_USER_DATA_PS_22" 2047 }, 2048 { 2049 "chips": ["gfx9"], 2050 "map": {"at": 45196, "to": "mm"}, 2051 "name": "SPI_SHADER_USER_DATA_PS_23" 2052 }, 2053 { 2054 "chips": ["gfx9"], 2055 "map": {"at": 45200, "to": "mm"}, 2056 "name": "SPI_SHADER_USER_DATA_PS_24" 2057 }, 2058 { 2059 "chips": ["gfx9"], 2060 "map": {"at": 45204, "to": "mm"}, 2061 "name": "SPI_SHADER_USER_DATA_PS_25" 2062 }, 2063 { 2064 "chips": ["gfx9"], 2065 "map": {"at": 45208, "to": "mm"}, 2066 "name": "SPI_SHADER_USER_DATA_PS_26" 2067 }, 2068 { 2069 "chips": ["gfx9"], 2070 "map": {"at": 45212, "to": "mm"}, 2071 "name": "SPI_SHADER_USER_DATA_PS_27" 2072 }, 2073 { 2074 "chips": ["gfx9"], 2075 "map": {"at": 45216, "to": "mm"}, 2076 "name": "SPI_SHADER_USER_DATA_PS_28" 2077 }, 2078 { 2079 "chips": ["gfx9"], 2080 "map": {"at": 45220, "to": "mm"}, 2081 "name": "SPI_SHADER_USER_DATA_PS_29" 2082 }, 2083 { 2084 "chips": ["gfx9"], 2085 "map": {"at": 45224, "to": "mm"}, 2086 "name": "SPI_SHADER_USER_DATA_PS_30" 2087 }, 2088 { 2089 "chips": ["gfx9"], 2090 "map": {"at": 45228, "to": "mm"}, 2091 "name": "SPI_SHADER_USER_DATA_PS_31" 2092 }, 2093 { 2094 "chips": ["gfx9"], 2095 "map": {"at": 45336, "to": "mm"}, 2096 "name": "SPI_SHADER_PGM_RSRC3_VS", 2097 "type_ref": "SPI_SHADER_PGM_RSRC3_PS" 2098 }, 2099 { 2100 "chips": ["gfx9"], 2101 "map": {"at": 45340, "to": "mm"}, 2102 "name": "SPI_SHADER_LATE_ALLOC_VS", 2103 "type_ref": "SPI_SHADER_LATE_ALLOC_VS" 2104 }, 2105 { 2106 "chips": ["gfx9"], 2107 "map": {"at": 45344, "to": "mm"}, 2108 "name": "SPI_SHADER_PGM_LO_VS" 2109 }, 2110 { 2111 "chips": ["gfx9"], 2112 "map": {"at": 45348, "to": "mm"}, 2113 "name": "SPI_SHADER_PGM_HI_VS", 2114 "type_ref": "SPI_SHADER_PGM_HI_PS" 2115 }, 2116 { 2117 "chips": ["gfx9"], 2118 "map": {"at": 45352, "to": "mm"}, 2119 "name": "SPI_SHADER_PGM_RSRC1_VS", 2120 "type_ref": "SPI_SHADER_PGM_RSRC1_VS" 2121 }, 2122 { 2123 "chips": ["gfx9"], 2124 "map": {"at": 45356, "to": "mm"}, 2125 "name": "SPI_SHADER_PGM_RSRC2_VS", 2126 "type_ref": "SPI_SHADER_PGM_RSRC2_VS" 2127 }, 2128 { 2129 "chips": ["gfx9"], 2130 "map": {"at": 45360, "to": "mm"}, 2131 "name": "SPI_SHADER_USER_DATA_VS_0" 2132 }, 2133 { 2134 "chips": ["gfx9"], 2135 "map": {"at": 45364, "to": "mm"}, 2136 "name": "SPI_SHADER_USER_DATA_VS_1" 2137 }, 2138 { 2139 "chips": ["gfx9"], 2140 "map": {"at": 45368, "to": "mm"}, 2141 "name": "SPI_SHADER_USER_DATA_VS_2" 2142 }, 2143 { 2144 "chips": ["gfx9"], 2145 "map": {"at": 45372, "to": "mm"}, 2146 "name": "SPI_SHADER_USER_DATA_VS_3" 2147 }, 2148 { 2149 "chips": ["gfx9"], 2150 "map": {"at": 45376, "to": "mm"}, 2151 "name": "SPI_SHADER_USER_DATA_VS_4" 2152 }, 2153 { 2154 "chips": ["gfx9"], 2155 "map": {"at": 45380, "to": "mm"}, 2156 "name": "SPI_SHADER_USER_DATA_VS_5" 2157 }, 2158 { 2159 "chips": ["gfx9"], 2160 "map": {"at": 45384, "to": "mm"}, 2161 "name": "SPI_SHADER_USER_DATA_VS_6" 2162 }, 2163 { 2164 "chips": ["gfx9"], 2165 "map": {"at": 45388, "to": "mm"}, 2166 "name": "SPI_SHADER_USER_DATA_VS_7" 2167 }, 2168 { 2169 "chips": ["gfx9"], 2170 "map": {"at": 45392, "to": "mm"}, 2171 "name": "SPI_SHADER_USER_DATA_VS_8" 2172 }, 2173 { 2174 "chips": ["gfx9"], 2175 "map": {"at": 45396, "to": "mm"}, 2176 "name": "SPI_SHADER_USER_DATA_VS_9" 2177 }, 2178 { 2179 "chips": ["gfx9"], 2180 "map": {"at": 45400, "to": "mm"}, 2181 "name": "SPI_SHADER_USER_DATA_VS_10" 2182 }, 2183 { 2184 "chips": ["gfx9"], 2185 "map": {"at": 45404, "to": "mm"}, 2186 "name": "SPI_SHADER_USER_DATA_VS_11" 2187 }, 2188 { 2189 "chips": ["gfx9"], 2190 "map": {"at": 45408, "to": "mm"}, 2191 "name": "SPI_SHADER_USER_DATA_VS_12" 2192 }, 2193 { 2194 "chips": ["gfx9"], 2195 "map": {"at": 45412, "to": "mm"}, 2196 "name": "SPI_SHADER_USER_DATA_VS_13" 2197 }, 2198 { 2199 "chips": ["gfx9"], 2200 "map": {"at": 45416, "to": "mm"}, 2201 "name": "SPI_SHADER_USER_DATA_VS_14" 2202 }, 2203 { 2204 "chips": ["gfx9"], 2205 "map": {"at": 45420, "to": "mm"}, 2206 "name": "SPI_SHADER_USER_DATA_VS_15" 2207 }, 2208 { 2209 "chips": ["gfx9"], 2210 "map": {"at": 45424, "to": "mm"}, 2211 "name": "SPI_SHADER_USER_DATA_VS_16" 2212 }, 2213 { 2214 "chips": ["gfx9"], 2215 "map": {"at": 45428, "to": "mm"}, 2216 "name": "SPI_SHADER_USER_DATA_VS_17" 2217 }, 2218 { 2219 "chips": ["gfx9"], 2220 "map": {"at": 45432, "to": "mm"}, 2221 "name": "SPI_SHADER_USER_DATA_VS_18" 2222 }, 2223 { 2224 "chips": ["gfx9"], 2225 "map": {"at": 45436, "to": "mm"}, 2226 "name": "SPI_SHADER_USER_DATA_VS_19" 2227 }, 2228 { 2229 "chips": ["gfx9"], 2230 "map": {"at": 45440, "to": "mm"}, 2231 "name": "SPI_SHADER_USER_DATA_VS_20" 2232 }, 2233 { 2234 "chips": ["gfx9"], 2235 "map": {"at": 45444, "to": "mm"}, 2236 "name": "SPI_SHADER_USER_DATA_VS_21" 2237 }, 2238 { 2239 "chips": ["gfx9"], 2240 "map": {"at": 45448, "to": "mm"}, 2241 "name": "SPI_SHADER_USER_DATA_VS_22" 2242 }, 2243 { 2244 "chips": ["gfx9"], 2245 "map": {"at": 45452, "to": "mm"}, 2246 "name": "SPI_SHADER_USER_DATA_VS_23" 2247 }, 2248 { 2249 "chips": ["gfx9"], 2250 "map": {"at": 45456, "to": "mm"}, 2251 "name": "SPI_SHADER_USER_DATA_VS_24" 2252 }, 2253 { 2254 "chips": ["gfx9"], 2255 "map": {"at": 45460, "to": "mm"}, 2256 "name": "SPI_SHADER_USER_DATA_VS_25" 2257 }, 2258 { 2259 "chips": ["gfx9"], 2260 "map": {"at": 45464, "to": "mm"}, 2261 "name": "SPI_SHADER_USER_DATA_VS_26" 2262 }, 2263 { 2264 "chips": ["gfx9"], 2265 "map": {"at": 45468, "to": "mm"}, 2266 "name": "SPI_SHADER_USER_DATA_VS_27" 2267 }, 2268 { 2269 "chips": ["gfx9"], 2270 "map": {"at": 45472, "to": "mm"}, 2271 "name": "SPI_SHADER_USER_DATA_VS_28" 2272 }, 2273 { 2274 "chips": ["gfx9"], 2275 "map": {"at": 45476, "to": "mm"}, 2276 "name": "SPI_SHADER_USER_DATA_VS_29" 2277 }, 2278 { 2279 "chips": ["gfx9"], 2280 "map": {"at": 45480, "to": "mm"}, 2281 "name": "SPI_SHADER_USER_DATA_VS_30" 2282 }, 2283 { 2284 "chips": ["gfx9"], 2285 "map": {"at": 45484, "to": "mm"}, 2286 "name": "SPI_SHADER_USER_DATA_VS_31" 2287 }, 2288 { 2289 "chips": ["gfx9"], 2290 "map": {"at": 45552, "to": "mm"}, 2291 "name": "SPI_SHADER_PGM_RSRC2_GS_VS", 2292 "type_ref": "SPI_SHADER_PGM_RSRC2_GS_VS" 2293 }, 2294 { 2295 "chips": ["gfx9"], 2296 "map": {"at": 45572, "to": "mm"}, 2297 "name": "SPI_SHADER_PGM_RSRC4_GS", 2298 "type_ref": "SPI_SHADER_PGM_RSRC4_GS" 2299 }, 2300 { 2301 "chips": ["gfx9"], 2302 "map": {"at": 45576, "to": "mm"}, 2303 "name": "SPI_SHADER_USER_DATA_ADDR_LO_GS" 2304 }, 2305 { 2306 "chips": ["gfx9"], 2307 "map": {"at": 45580, "to": "mm"}, 2308 "name": "SPI_SHADER_USER_DATA_ADDR_HI_GS" 2309 }, 2310 { 2311 "chips": ["gfx9"], 2312 "map": {"at": 45584, "to": "mm"}, 2313 "name": "SPI_SHADER_PGM_LO_ES" 2314 }, 2315 { 2316 "chips": ["gfx9"], 2317 "map": {"at": 45588, "to": "mm"}, 2318 "name": "SPI_SHADER_PGM_HI_ES", 2319 "type_ref": "SPI_SHADER_PGM_HI_PS" 2320 }, 2321 { 2322 "chips": ["gfx9"], 2323 "map": {"at": 45596, "to": "mm"}, 2324 "name": "SPI_SHADER_PGM_RSRC3_GS", 2325 "type_ref": "SPI_SHADER_PGM_RSRC3_PS" 2326 }, 2327 { 2328 "chips": ["gfx9"], 2329 "map": {"at": 45600, "to": "mm"}, 2330 "name": "SPI_SHADER_PGM_LO_GS" 2331 }, 2332 { 2333 "chips": ["gfx9"], 2334 "map": {"at": 45604, "to": "mm"}, 2335 "name": "SPI_SHADER_PGM_HI_GS", 2336 "type_ref": "SPI_SHADER_PGM_HI_PS" 2337 }, 2338 { 2339 "chips": ["gfx9"], 2340 "map": {"at": 45608, "to": "mm"}, 2341 "name": "SPI_SHADER_PGM_RSRC1_GS", 2342 "type_ref": "SPI_SHADER_PGM_RSRC1_GS" 2343 }, 2344 { 2345 "chips": ["gfx9"], 2346 "map": {"at": 45612, "to": "mm"}, 2347 "name": "SPI_SHADER_PGM_RSRC2_GS", 2348 "type_ref": "SPI_SHADER_PGM_RSRC2_GS" 2349 }, 2350 { 2351 "chips": ["gfx9"], 2352 "map": {"at": 45872, "to": "mm"}, 2353 "name": "SPI_SHADER_USER_DATA_ES_0" 2354 }, 2355 { 2356 "chips": ["gfx9"], 2357 "map": {"at": 45876, "to": "mm"}, 2358 "name": "SPI_SHADER_USER_DATA_ES_1" 2359 }, 2360 { 2361 "chips": ["gfx9"], 2362 "map": {"at": 45880, "to": "mm"}, 2363 "name": "SPI_SHADER_USER_DATA_ES_2" 2364 }, 2365 { 2366 "chips": ["gfx9"], 2367 "map": {"at": 45884, "to": "mm"}, 2368 "name": "SPI_SHADER_USER_DATA_ES_3" 2369 }, 2370 { 2371 "chips": ["gfx9"], 2372 "map": {"at": 45888, "to": "mm"}, 2373 "name": "SPI_SHADER_USER_DATA_ES_4" 2374 }, 2375 { 2376 "chips": ["gfx9"], 2377 "map": {"at": 45892, "to": "mm"}, 2378 "name": "SPI_SHADER_USER_DATA_ES_5" 2379 }, 2380 { 2381 "chips": ["gfx9"], 2382 "map": {"at": 45896, "to": "mm"}, 2383 "name": "SPI_SHADER_USER_DATA_ES_6" 2384 }, 2385 { 2386 "chips": ["gfx9"], 2387 "map": {"at": 45900, "to": "mm"}, 2388 "name": "SPI_SHADER_USER_DATA_ES_7" 2389 }, 2390 { 2391 "chips": ["gfx9"], 2392 "map": {"at": 45904, "to": "mm"}, 2393 "name": "SPI_SHADER_USER_DATA_ES_8" 2394 }, 2395 { 2396 "chips": ["gfx9"], 2397 "map": {"at": 45908, "to": "mm"}, 2398 "name": "SPI_SHADER_USER_DATA_ES_9" 2399 }, 2400 { 2401 "chips": ["gfx9"], 2402 "map": {"at": 45912, "to": "mm"}, 2403 "name": "SPI_SHADER_USER_DATA_ES_10" 2404 }, 2405 { 2406 "chips": ["gfx9"], 2407 "map": {"at": 45916, "to": "mm"}, 2408 "name": "SPI_SHADER_USER_DATA_ES_11" 2409 }, 2410 { 2411 "chips": ["gfx9"], 2412 "map": {"at": 45920, "to": "mm"}, 2413 "name": "SPI_SHADER_USER_DATA_ES_12" 2414 }, 2415 { 2416 "chips": ["gfx9"], 2417 "map": {"at": 45924, "to": "mm"}, 2418 "name": "SPI_SHADER_USER_DATA_ES_13" 2419 }, 2420 { 2421 "chips": ["gfx9"], 2422 "map": {"at": 45928, "to": "mm"}, 2423 "name": "SPI_SHADER_USER_DATA_ES_14" 2424 }, 2425 { 2426 "chips": ["gfx9"], 2427 "map": {"at": 45932, "to": "mm"}, 2428 "name": "SPI_SHADER_USER_DATA_ES_15" 2429 }, 2430 { 2431 "chips": ["gfx9"], 2432 "map": {"at": 45936, "to": "mm"}, 2433 "name": "SPI_SHADER_USER_DATA_ES_16" 2434 }, 2435 { 2436 "chips": ["gfx9"], 2437 "map": {"at": 45940, "to": "mm"}, 2438 "name": "SPI_SHADER_USER_DATA_ES_17" 2439 }, 2440 { 2441 "chips": ["gfx9"], 2442 "map": {"at": 45944, "to": "mm"}, 2443 "name": "SPI_SHADER_USER_DATA_ES_18" 2444 }, 2445 { 2446 "chips": ["gfx9"], 2447 "map": {"at": 45948, "to": "mm"}, 2448 "name": "SPI_SHADER_USER_DATA_ES_19" 2449 }, 2450 { 2451 "chips": ["gfx9"], 2452 "map": {"at": 45952, "to": "mm"}, 2453 "name": "SPI_SHADER_USER_DATA_ES_20" 2454 }, 2455 { 2456 "chips": ["gfx9"], 2457 "map": {"at": 45956, "to": "mm"}, 2458 "name": "SPI_SHADER_USER_DATA_ES_21" 2459 }, 2460 { 2461 "chips": ["gfx9"], 2462 "map": {"at": 45960, "to": "mm"}, 2463 "name": "SPI_SHADER_USER_DATA_ES_22" 2464 }, 2465 { 2466 "chips": ["gfx9"], 2467 "map": {"at": 45964, "to": "mm"}, 2468 "name": "SPI_SHADER_USER_DATA_ES_23" 2469 }, 2470 { 2471 "chips": ["gfx9"], 2472 "map": {"at": 45968, "to": "mm"}, 2473 "name": "SPI_SHADER_USER_DATA_ES_24" 2474 }, 2475 { 2476 "chips": ["gfx9"], 2477 "map": {"at": 45972, "to": "mm"}, 2478 "name": "SPI_SHADER_USER_DATA_ES_25" 2479 }, 2480 { 2481 "chips": ["gfx9"], 2482 "map": {"at": 45976, "to": "mm"}, 2483 "name": "SPI_SHADER_USER_DATA_ES_26" 2484 }, 2485 { 2486 "chips": ["gfx9"], 2487 "map": {"at": 45980, "to": "mm"}, 2488 "name": "SPI_SHADER_USER_DATA_ES_27" 2489 }, 2490 { 2491 "chips": ["gfx9"], 2492 "map": {"at": 45984, "to": "mm"}, 2493 "name": "SPI_SHADER_USER_DATA_ES_28" 2494 }, 2495 { 2496 "chips": ["gfx9"], 2497 "map": {"at": 45988, "to": "mm"}, 2498 "name": "SPI_SHADER_USER_DATA_ES_29" 2499 }, 2500 { 2501 "chips": ["gfx9"], 2502 "map": {"at": 45992, "to": "mm"}, 2503 "name": "SPI_SHADER_USER_DATA_ES_30" 2504 }, 2505 { 2506 "chips": ["gfx9"], 2507 "map": {"at": 45996, "to": "mm"}, 2508 "name": "SPI_SHADER_USER_DATA_ES_31" 2509 }, 2510 { 2511 "chips": ["gfx9"], 2512 "map": {"at": 46084, "to": "mm"}, 2513 "name": "SPI_SHADER_PGM_RSRC4_HS", 2514 "type_ref": "SPI_SHADER_PGM_RSRC4_HS" 2515 }, 2516 { 2517 "chips": ["gfx9"], 2518 "map": {"at": 46088, "to": "mm"}, 2519 "name": "SPI_SHADER_USER_DATA_ADDR_LO_HS" 2520 }, 2521 { 2522 "chips": ["gfx9"], 2523 "map": {"at": 46092, "to": "mm"}, 2524 "name": "SPI_SHADER_USER_DATA_ADDR_HI_HS" 2525 }, 2526 { 2527 "chips": ["gfx9"], 2528 "map": {"at": 46096, "to": "mm"}, 2529 "name": "SPI_SHADER_PGM_LO_LS" 2530 }, 2531 { 2532 "chips": ["gfx9"], 2533 "map": {"at": 46100, "to": "mm"}, 2534 "name": "SPI_SHADER_PGM_HI_LS", 2535 "type_ref": "SPI_SHADER_PGM_HI_PS" 2536 }, 2537 { 2538 "chips": ["gfx9"], 2539 "map": {"at": 46108, "to": "mm"}, 2540 "name": "SPI_SHADER_PGM_RSRC3_HS", 2541 "type_ref": "SPI_SHADER_PGM_RSRC3_HS" 2542 }, 2543 { 2544 "chips": ["gfx9"], 2545 "map": {"at": 46112, "to": "mm"}, 2546 "name": "SPI_SHADER_PGM_LO_HS" 2547 }, 2548 { 2549 "chips": ["gfx9"], 2550 "map": {"at": 46116, "to": "mm"}, 2551 "name": "SPI_SHADER_PGM_HI_HS", 2552 "type_ref": "SPI_SHADER_PGM_HI_PS" 2553 }, 2554 { 2555 "chips": ["gfx9"], 2556 "map": {"at": 46120, "to": "mm"}, 2557 "name": "SPI_SHADER_PGM_RSRC1_HS", 2558 "type_ref": "SPI_SHADER_PGM_RSRC1_HS" 2559 }, 2560 { 2561 "chips": ["gfx9"], 2562 "map": {"at": 46124, "to": "mm"}, 2563 "name": "SPI_SHADER_PGM_RSRC2_HS", 2564 "type_ref": "SPI_SHADER_PGM_RSRC2_HS" 2565 }, 2566 { 2567 "chips": ["gfx9"], 2568 "map": {"at": 46128, "to": "mm"}, 2569 "name": "SPI_SHADER_USER_DATA_LS_0" 2570 }, 2571 { 2572 "chips": ["gfx9"], 2573 "map": {"at": 46132, "to": "mm"}, 2574 "name": "SPI_SHADER_USER_DATA_LS_1" 2575 }, 2576 { 2577 "chips": ["gfx9"], 2578 "map": {"at": 46136, "to": "mm"}, 2579 "name": "SPI_SHADER_USER_DATA_LS_2" 2580 }, 2581 { 2582 "chips": ["gfx9"], 2583 "map": {"at": 46140, "to": "mm"}, 2584 "name": "SPI_SHADER_USER_DATA_LS_3" 2585 }, 2586 { 2587 "chips": ["gfx9"], 2588 "map": {"at": 46144, "to": "mm"}, 2589 "name": "SPI_SHADER_USER_DATA_LS_4" 2590 }, 2591 { 2592 "chips": ["gfx9"], 2593 "map": {"at": 46148, "to": "mm"}, 2594 "name": "SPI_SHADER_USER_DATA_LS_5" 2595 }, 2596 { 2597 "chips": ["gfx9"], 2598 "map": {"at": 46152, "to": "mm"}, 2599 "name": "SPI_SHADER_USER_DATA_LS_6" 2600 }, 2601 { 2602 "chips": ["gfx9"], 2603 "map": {"at": 46156, "to": "mm"}, 2604 "name": "SPI_SHADER_USER_DATA_LS_7" 2605 }, 2606 { 2607 "chips": ["gfx9"], 2608 "map": {"at": 46160, "to": "mm"}, 2609 "name": "SPI_SHADER_USER_DATA_LS_8" 2610 }, 2611 { 2612 "chips": ["gfx9"], 2613 "map": {"at": 46164, "to": "mm"}, 2614 "name": "SPI_SHADER_USER_DATA_LS_9" 2615 }, 2616 { 2617 "chips": ["gfx9"], 2618 "map": {"at": 46168, "to": "mm"}, 2619 "name": "SPI_SHADER_USER_DATA_LS_10" 2620 }, 2621 { 2622 "chips": ["gfx9"], 2623 "map": {"at": 46172, "to": "mm"}, 2624 "name": "SPI_SHADER_USER_DATA_LS_11" 2625 }, 2626 { 2627 "chips": ["gfx9"], 2628 "map": {"at": 46176, "to": "mm"}, 2629 "name": "SPI_SHADER_USER_DATA_LS_12" 2630 }, 2631 { 2632 "chips": ["gfx9"], 2633 "map": {"at": 46180, "to": "mm"}, 2634 "name": "SPI_SHADER_USER_DATA_LS_13" 2635 }, 2636 { 2637 "chips": ["gfx9"], 2638 "map": {"at": 46184, "to": "mm"}, 2639 "name": "SPI_SHADER_USER_DATA_LS_14" 2640 }, 2641 { 2642 "chips": ["gfx9"], 2643 "map": {"at": 46188, "to": "mm"}, 2644 "name": "SPI_SHADER_USER_DATA_LS_15" 2645 }, 2646 { 2647 "chips": ["gfx9"], 2648 "map": {"at": 46192, "to": "mm"}, 2649 "name": "SPI_SHADER_USER_DATA_LS_16" 2650 }, 2651 { 2652 "chips": ["gfx9"], 2653 "map": {"at": 46196, "to": "mm"}, 2654 "name": "SPI_SHADER_USER_DATA_LS_17" 2655 }, 2656 { 2657 "chips": ["gfx9"], 2658 "map": {"at": 46200, "to": "mm"}, 2659 "name": "SPI_SHADER_USER_DATA_LS_18" 2660 }, 2661 { 2662 "chips": ["gfx9"], 2663 "map": {"at": 46204, "to": "mm"}, 2664 "name": "SPI_SHADER_USER_DATA_LS_19" 2665 }, 2666 { 2667 "chips": ["gfx9"], 2668 "map": {"at": 46208, "to": "mm"}, 2669 "name": "SPI_SHADER_USER_DATA_LS_20" 2670 }, 2671 { 2672 "chips": ["gfx9"], 2673 "map": {"at": 46212, "to": "mm"}, 2674 "name": "SPI_SHADER_USER_DATA_LS_21" 2675 }, 2676 { 2677 "chips": ["gfx9"], 2678 "map": {"at": 46216, "to": "mm"}, 2679 "name": "SPI_SHADER_USER_DATA_LS_22" 2680 }, 2681 { 2682 "chips": ["gfx9"], 2683 "map": {"at": 46220, "to": "mm"}, 2684 "name": "SPI_SHADER_USER_DATA_LS_23" 2685 }, 2686 { 2687 "chips": ["gfx9"], 2688 "map": {"at": 46224, "to": "mm"}, 2689 "name": "SPI_SHADER_USER_DATA_LS_24" 2690 }, 2691 { 2692 "chips": ["gfx9"], 2693 "map": {"at": 46228, "to": "mm"}, 2694 "name": "SPI_SHADER_USER_DATA_LS_25" 2695 }, 2696 { 2697 "chips": ["gfx9"], 2698 "map": {"at": 46232, "to": "mm"}, 2699 "name": "SPI_SHADER_USER_DATA_LS_26" 2700 }, 2701 { 2702 "chips": ["gfx9"], 2703 "map": {"at": 46236, "to": "mm"}, 2704 "name": "SPI_SHADER_USER_DATA_LS_27" 2705 }, 2706 { 2707 "chips": ["gfx9"], 2708 "map": {"at": 46240, "to": "mm"}, 2709 "name": "SPI_SHADER_USER_DATA_LS_28" 2710 }, 2711 { 2712 "chips": ["gfx9"], 2713 "map": {"at": 46244, "to": "mm"}, 2714 "name": "SPI_SHADER_USER_DATA_LS_29" 2715 }, 2716 { 2717 "chips": ["gfx9"], 2718 "map": {"at": 46248, "to": "mm"}, 2719 "name": "SPI_SHADER_USER_DATA_LS_30" 2720 }, 2721 { 2722 "chips": ["gfx9"], 2723 "map": {"at": 46252, "to": "mm"}, 2724 "name": "SPI_SHADER_USER_DATA_LS_31" 2725 }, 2726 { 2727 "chips": ["gfx9"], 2728 "map": {"at": 46384, "to": "mm"}, 2729 "name": "SPI_SHADER_USER_DATA_COMMON_0" 2730 }, 2731 { 2732 "chips": ["gfx9"], 2733 "map": {"at": 46388, "to": "mm"}, 2734 "name": "SPI_SHADER_USER_DATA_COMMON_1" 2735 }, 2736 { 2737 "chips": ["gfx9"], 2738 "map": {"at": 46392, "to": "mm"}, 2739 "name": "SPI_SHADER_USER_DATA_COMMON_2" 2740 }, 2741 { 2742 "chips": ["gfx9"], 2743 "map": {"at": 46396, "to": "mm"}, 2744 "name": "SPI_SHADER_USER_DATA_COMMON_3" 2745 }, 2746 { 2747 "chips": ["gfx9"], 2748 "map": {"at": 46400, "to": "mm"}, 2749 "name": "SPI_SHADER_USER_DATA_COMMON_4" 2750 }, 2751 { 2752 "chips": ["gfx9"], 2753 "map": {"at": 46404, "to": "mm"}, 2754 "name": "SPI_SHADER_USER_DATA_COMMON_5" 2755 }, 2756 { 2757 "chips": ["gfx9"], 2758 "map": {"at": 46408, "to": "mm"}, 2759 "name": "SPI_SHADER_USER_DATA_COMMON_6" 2760 }, 2761 { 2762 "chips": ["gfx9"], 2763 "map": {"at": 46412, "to": "mm"}, 2764 "name": "SPI_SHADER_USER_DATA_COMMON_7" 2765 }, 2766 { 2767 "chips": ["gfx9"], 2768 "map": {"at": 46416, "to": "mm"}, 2769 "name": "SPI_SHADER_USER_DATA_COMMON_8" 2770 }, 2771 { 2772 "chips": ["gfx9"], 2773 "map": {"at": 46420, "to": "mm"}, 2774 "name": "SPI_SHADER_USER_DATA_COMMON_9" 2775 }, 2776 { 2777 "chips": ["gfx9"], 2778 "map": {"at": 46424, "to": "mm"}, 2779 "name": "SPI_SHADER_USER_DATA_COMMON_10" 2780 }, 2781 { 2782 "chips": ["gfx9"], 2783 "map": {"at": 46428, "to": "mm"}, 2784 "name": "SPI_SHADER_USER_DATA_COMMON_11" 2785 }, 2786 { 2787 "chips": ["gfx9"], 2788 "map": {"at": 46432, "to": "mm"}, 2789 "name": "SPI_SHADER_USER_DATA_COMMON_12" 2790 }, 2791 { 2792 "chips": ["gfx9"], 2793 "map": {"at": 46436, "to": "mm"}, 2794 "name": "SPI_SHADER_USER_DATA_COMMON_13" 2795 }, 2796 { 2797 "chips": ["gfx9"], 2798 "map": {"at": 46440, "to": "mm"}, 2799 "name": "SPI_SHADER_USER_DATA_COMMON_14" 2800 }, 2801 { 2802 "chips": ["gfx9"], 2803 "map": {"at": 46444, "to": "mm"}, 2804 "name": "SPI_SHADER_USER_DATA_COMMON_15" 2805 }, 2806 { 2807 "chips": ["gfx9"], 2808 "map": {"at": 46448, "to": "mm"}, 2809 "name": "SPI_SHADER_USER_DATA_COMMON_16" 2810 }, 2811 { 2812 "chips": ["gfx9"], 2813 "map": {"at": 46452, "to": "mm"}, 2814 "name": "SPI_SHADER_USER_DATA_COMMON_17" 2815 }, 2816 { 2817 "chips": ["gfx9"], 2818 "map": {"at": 46456, "to": "mm"}, 2819 "name": "SPI_SHADER_USER_DATA_COMMON_18" 2820 }, 2821 { 2822 "chips": ["gfx9"], 2823 "map": {"at": 46460, "to": "mm"}, 2824 "name": "SPI_SHADER_USER_DATA_COMMON_19" 2825 }, 2826 { 2827 "chips": ["gfx9"], 2828 "map": {"at": 46464, "to": "mm"}, 2829 "name": "SPI_SHADER_USER_DATA_COMMON_20" 2830 }, 2831 { 2832 "chips": ["gfx9"], 2833 "map": {"at": 46468, "to": "mm"}, 2834 "name": "SPI_SHADER_USER_DATA_COMMON_21" 2835 }, 2836 { 2837 "chips": ["gfx9"], 2838 "map": {"at": 46472, "to": "mm"}, 2839 "name": "SPI_SHADER_USER_DATA_COMMON_22" 2840 }, 2841 { 2842 "chips": ["gfx9"], 2843 "map": {"at": 46476, "to": "mm"}, 2844 "name": "SPI_SHADER_USER_DATA_COMMON_23" 2845 }, 2846 { 2847 "chips": ["gfx9"], 2848 "map": {"at": 46480, "to": "mm"}, 2849 "name": "SPI_SHADER_USER_DATA_COMMON_24" 2850 }, 2851 { 2852 "chips": ["gfx9"], 2853 "map": {"at": 46484, "to": "mm"}, 2854 "name": "SPI_SHADER_USER_DATA_COMMON_25" 2855 }, 2856 { 2857 "chips": ["gfx9"], 2858 "map": {"at": 46488, "to": "mm"}, 2859 "name": "SPI_SHADER_USER_DATA_COMMON_26" 2860 }, 2861 { 2862 "chips": ["gfx9"], 2863 "map": {"at": 46492, "to": "mm"}, 2864 "name": "SPI_SHADER_USER_DATA_COMMON_27" 2865 }, 2866 { 2867 "chips": ["gfx9"], 2868 "map": {"at": 46496, "to": "mm"}, 2869 "name": "SPI_SHADER_USER_DATA_COMMON_28" 2870 }, 2871 { 2872 "chips": ["gfx9"], 2873 "map": {"at": 46500, "to": "mm"}, 2874 "name": "SPI_SHADER_USER_DATA_COMMON_29" 2875 }, 2876 { 2877 "chips": ["gfx9"], 2878 "map": {"at": 46504, "to": "mm"}, 2879 "name": "SPI_SHADER_USER_DATA_COMMON_30" 2880 }, 2881 { 2882 "chips": ["gfx9"], 2883 "map": {"at": 46508, "to": "mm"}, 2884 "name": "SPI_SHADER_USER_DATA_COMMON_31" 2885 }, 2886 { 2887 "chips": ["gfx9"], 2888 "map": {"at": 47104, "to": "mm"}, 2889 "name": "COMPUTE_DISPATCH_INITIATOR", 2890 "type_ref": "COMPUTE_DISPATCH_INITIATOR" 2891 }, 2892 { 2893 "chips": ["gfx9"], 2894 "map": {"at": 47108, "to": "mm"}, 2895 "name": "COMPUTE_DIM_X" 2896 }, 2897 { 2898 "chips": ["gfx9"], 2899 "map": {"at": 47112, "to": "mm"}, 2900 "name": "COMPUTE_DIM_Y" 2901 }, 2902 { 2903 "chips": ["gfx9"], 2904 "map": {"at": 47116, "to": "mm"}, 2905 "name": "COMPUTE_DIM_Z" 2906 }, 2907 { 2908 "chips": ["gfx9"], 2909 "map": {"at": 47120, "to": "mm"}, 2910 "name": "COMPUTE_START_X" 2911 }, 2912 { 2913 "chips": ["gfx9"], 2914 "map": {"at": 47124, "to": "mm"}, 2915 "name": "COMPUTE_START_Y" 2916 }, 2917 { 2918 "chips": ["gfx9"], 2919 "map": {"at": 47128, "to": "mm"}, 2920 "name": "COMPUTE_START_Z" 2921 }, 2922 { 2923 "chips": ["gfx9"], 2924 "map": {"at": 47132, "to": "mm"}, 2925 "name": "COMPUTE_NUM_THREAD_X", 2926 "type_ref": "COMPUTE_NUM_THREAD_X" 2927 }, 2928 { 2929 "chips": ["gfx9"], 2930 "map": {"at": 47136, "to": "mm"}, 2931 "name": "COMPUTE_NUM_THREAD_Y", 2932 "type_ref": "COMPUTE_NUM_THREAD_X" 2933 }, 2934 { 2935 "chips": ["gfx9"], 2936 "map": {"at": 47140, "to": "mm"}, 2937 "name": "COMPUTE_NUM_THREAD_Z", 2938 "type_ref": "COMPUTE_NUM_THREAD_X" 2939 }, 2940 { 2941 "chips": ["gfx9"], 2942 "map": {"at": 47144, "to": "mm"}, 2943 "name": "COMPUTE_PIPELINESTAT_ENABLE", 2944 "type_ref": "COMPUTE_PIPELINESTAT_ENABLE" 2945 }, 2946 { 2947 "chips": ["gfx9"], 2948 "map": {"at": 47148, "to": "mm"}, 2949 "name": "COMPUTE_PERFCOUNT_ENABLE", 2950 "type_ref": "COMPUTE_PERFCOUNT_ENABLE" 2951 }, 2952 { 2953 "chips": ["gfx9"], 2954 "map": {"at": 47152, "to": "mm"}, 2955 "name": "COMPUTE_PGM_LO" 2956 }, 2957 { 2958 "chips": ["gfx9"], 2959 "map": {"at": 47156, "to": "mm"}, 2960 "name": "COMPUTE_PGM_HI", 2961 "type_ref": "COMPUTE_PGM_HI" 2962 }, 2963 { 2964 "chips": ["gfx9"], 2965 "map": {"at": 47160, "to": "mm"}, 2966 "name": "COMPUTE_DISPATCH_PKT_ADDR_LO" 2967 }, 2968 { 2969 "chips": ["gfx9"], 2970 "map": {"at": 47164, "to": "mm"}, 2971 "name": "COMPUTE_DISPATCH_PKT_ADDR_HI", 2972 "type_ref": "COMPUTE_PGM_HI" 2973 }, 2974 { 2975 "chips": ["gfx9"], 2976 "map": {"at": 47168, "to": "mm"}, 2977 "name": "COMPUTE_DISPATCH_SCRATCH_BASE_LO" 2978 }, 2979 { 2980 "chips": ["gfx9"], 2981 "map": {"at": 47172, "to": "mm"}, 2982 "name": "COMPUTE_DISPATCH_SCRATCH_BASE_HI", 2983 "type_ref": "COMPUTE_PGM_HI" 2984 }, 2985 { 2986 "chips": ["gfx9"], 2987 "map": {"at": 47176, "to": "mm"}, 2988 "name": "COMPUTE_PGM_RSRC1", 2989 "type_ref": "COMPUTE_PGM_RSRC1" 2990 }, 2991 { 2992 "chips": ["gfx9"], 2993 "map": {"at": 47180, "to": "mm"}, 2994 "name": "COMPUTE_PGM_RSRC2", 2995 "type_ref": "COMPUTE_PGM_RSRC2" 2996 }, 2997 { 2998 "chips": ["gfx9"], 2999 "map": {"at": 47184, "to": "mm"}, 3000 "name": "COMPUTE_VMID", 3001 "type_ref": "COMPUTE_VMID" 3002 }, 3003 { 3004 "chips": ["gfx9"], 3005 "map": {"at": 47188, "to": "mm"}, 3006 "name": "COMPUTE_RESOURCE_LIMITS", 3007 "type_ref": "COMPUTE_RESOURCE_LIMITS" 3008 }, 3009 { 3010 "chips": ["gfx9"], 3011 "map": {"at": 47192, "to": "mm"}, 3012 "name": "COMPUTE_STATIC_THREAD_MGMT_SE0", 3013 "type_ref": "COMPUTE_STATIC_THREAD_MGMT_SE0" 3014 }, 3015 { 3016 "chips": ["gfx9"], 3017 "map": {"at": 47196, "to": "mm"}, 3018 "name": "COMPUTE_STATIC_THREAD_MGMT_SE1", 3019 "type_ref": "COMPUTE_STATIC_THREAD_MGMT_SE0" 3020 }, 3021 { 3022 "chips": ["gfx9"], 3023 "map": {"at": 47200, "to": "mm"}, 3024 "name": "COMPUTE_TMPRING_SIZE", 3025 "type_ref": "COMPUTE_TMPRING_SIZE" 3026 }, 3027 { 3028 "chips": ["gfx9"], 3029 "map": {"at": 47204, "to": "mm"}, 3030 "name": "COMPUTE_STATIC_THREAD_MGMT_SE2", 3031 "type_ref": "COMPUTE_STATIC_THREAD_MGMT_SE0" 3032 }, 3033 { 3034 "chips": ["gfx9"], 3035 "map": {"at": 47208, "to": "mm"}, 3036 "name": "COMPUTE_STATIC_THREAD_MGMT_SE3", 3037 "type_ref": "COMPUTE_STATIC_THREAD_MGMT_SE0" 3038 }, 3039 { 3040 "chips": ["gfx9"], 3041 "map": {"at": 47212, "to": "mm"}, 3042 "name": "COMPUTE_RESTART_X" 3043 }, 3044 { 3045 "chips": ["gfx9"], 3046 "map": {"at": 47216, "to": "mm"}, 3047 "name": "COMPUTE_RESTART_Y" 3048 }, 3049 { 3050 "chips": ["gfx9"], 3051 "map": {"at": 47220, "to": "mm"}, 3052 "name": "COMPUTE_RESTART_Z" 3053 }, 3054 { 3055 "chips": ["gfx9"], 3056 "map": {"at": 47224, "to": "mm"}, 3057 "name": "COMPUTE_THREAD_TRACE_ENABLE", 3058 "type_ref": "COMPUTE_THREAD_TRACE_ENABLE" 3059 }, 3060 { 3061 "chips": ["gfx9"], 3062 "map": {"at": 47228, "to": "mm"}, 3063 "name": "COMPUTE_MISC_RESERVED", 3064 "type_ref": "COMPUTE_MISC_RESERVED" 3065 }, 3066 { 3067 "chips": ["gfx9"], 3068 "map": {"at": 47232, "to": "mm"}, 3069 "name": "COMPUTE_DISPATCH_ID" 3070 }, 3071 { 3072 "chips": ["gfx9"], 3073 "map": {"at": 47236, "to": "mm"}, 3074 "name": "COMPUTE_THREADGROUP_ID" 3075 }, 3076 { 3077 "chips": ["gfx9"], 3078 "map": {"at": 47240, "to": "mm"}, 3079 "name": "COMPUTE_RELAUNCH", 3080 "type_ref": "COMPUTE_RELAUNCH" 3081 }, 3082 { 3083 "chips": ["gfx9"], 3084 "map": {"at": 47244, "to": "mm"}, 3085 "name": "COMPUTE_WAVE_RESTORE_ADDR_LO" 3086 }, 3087 { 3088 "chips": ["gfx9"], 3089 "map": {"at": 47248, "to": "mm"}, 3090 "name": "COMPUTE_WAVE_RESTORE_ADDR_HI", 3091 "type_ref": "COMPUTE_WAVE_RESTORE_ADDR_HI" 3092 }, 3093 { 3094 "chips": ["gfx9"], 3095 "map": {"at": 47252, "to": "mm"}, 3096 "name": "COMPUTE_SHADER_CHKSUM" 3097 }, 3098 { 3099 "chips": ["gfx9"], 3100 "map": {"at": 47360, "to": "mm"}, 3101 "name": "COMPUTE_USER_DATA_0" 3102 }, 3103 { 3104 "chips": ["gfx9"], 3105 "map": {"at": 47364, "to": "mm"}, 3106 "name": "COMPUTE_USER_DATA_1" 3107 }, 3108 { 3109 "chips": ["gfx9"], 3110 "map": {"at": 47368, "to": "mm"}, 3111 "name": "COMPUTE_USER_DATA_2" 3112 }, 3113 { 3114 "chips": ["gfx9"], 3115 "map": {"at": 47372, "to": "mm"}, 3116 "name": "COMPUTE_USER_DATA_3" 3117 }, 3118 { 3119 "chips": ["gfx9"], 3120 "map": {"at": 47376, "to": "mm"}, 3121 "name": "COMPUTE_USER_DATA_4" 3122 }, 3123 { 3124 "chips": ["gfx9"], 3125 "map": {"at": 47380, "to": "mm"}, 3126 "name": "COMPUTE_USER_DATA_5" 3127 }, 3128 { 3129 "chips": ["gfx9"], 3130 "map": {"at": 47384, "to": "mm"}, 3131 "name": "COMPUTE_USER_DATA_6" 3132 }, 3133 { 3134 "chips": ["gfx9"], 3135 "map": {"at": 47388, "to": "mm"}, 3136 "name": "COMPUTE_USER_DATA_7" 3137 }, 3138 { 3139 "chips": ["gfx9"], 3140 "map": {"at": 47392, "to": "mm"}, 3141 "name": "COMPUTE_USER_DATA_8" 3142 }, 3143 { 3144 "chips": ["gfx9"], 3145 "map": {"at": 47396, "to": "mm"}, 3146 "name": "COMPUTE_USER_DATA_9" 3147 }, 3148 { 3149 "chips": ["gfx9"], 3150 "map": {"at": 47400, "to": "mm"}, 3151 "name": "COMPUTE_USER_DATA_10" 3152 }, 3153 { 3154 "chips": ["gfx9"], 3155 "map": {"at": 47404, "to": "mm"}, 3156 "name": "COMPUTE_USER_DATA_11" 3157 }, 3158 { 3159 "chips": ["gfx9"], 3160 "map": {"at": 47408, "to": "mm"}, 3161 "name": "COMPUTE_USER_DATA_12" 3162 }, 3163 { 3164 "chips": ["gfx9"], 3165 "map": {"at": 47412, "to": "mm"}, 3166 "name": "COMPUTE_USER_DATA_13" 3167 }, 3168 { 3169 "chips": ["gfx9"], 3170 "map": {"at": 47416, "to": "mm"}, 3171 "name": "COMPUTE_USER_DATA_14" 3172 }, 3173 { 3174 "chips": ["gfx9"], 3175 "map": {"at": 47420, "to": "mm"}, 3176 "name": "COMPUTE_USER_DATA_15" 3177 }, 3178 { 3179 "chips": ["gfx9"], 3180 "map": {"at": 47608, "to": "mm"}, 3181 "name": "COMPUTE_DISPATCH_END" 3182 }, 3183 { 3184 "chips": ["gfx9"], 3185 "map": {"at": 47612, "to": "mm"}, 3186 "name": "COMPUTE_NOWHERE" 3187 }, 3188 { 3189 "chips": ["gfx9"], 3190 "map": {"at": 163840, "to": "mm"}, 3191 "name": "DB_RENDER_CONTROL", 3192 "type_ref": "DB_RENDER_CONTROL" 3193 }, 3194 { 3195 "chips": ["gfx9"], 3196 "map": {"at": 163844, "to": "mm"}, 3197 "name": "DB_COUNT_CONTROL", 3198 "type_ref": "DB_COUNT_CONTROL" 3199 }, 3200 { 3201 "chips": ["gfx9"], 3202 "map": {"at": 163848, "to": "mm"}, 3203 "name": "DB_DEPTH_VIEW", 3204 "type_ref": "DB_DEPTH_VIEW" 3205 }, 3206 { 3207 "chips": ["gfx9"], 3208 "map": {"at": 163852, "to": "mm"}, 3209 "name": "DB_RENDER_OVERRIDE", 3210 "type_ref": "DB_RENDER_OVERRIDE" 3211 }, 3212 { 3213 "chips": ["gfx9"], 3214 "map": {"at": 163856, "to": "mm"}, 3215 "name": "DB_RENDER_OVERRIDE2", 3216 "type_ref": "DB_RENDER_OVERRIDE2" 3217 }, 3218 { 3219 "chips": ["gfx9"], 3220 "map": {"at": 163860, "to": "mm"}, 3221 "name": "DB_HTILE_DATA_BASE" 3222 }, 3223 { 3224 "chips": ["gfx9"], 3225 "map": {"at": 163864, "to": "mm"}, 3226 "name": "DB_HTILE_DATA_BASE_HI", 3227 "type_ref": "DB_HTILE_DATA_BASE_HI" 3228 }, 3229 { 3230 "chips": ["gfx9"], 3231 "map": {"at": 163868, "to": "mm"}, 3232 "name": "DB_DEPTH_SIZE", 3233 "type_ref": "DB_DEPTH_SIZE" 3234 }, 3235 { 3236 "chips": ["gfx9"], 3237 "map": {"at": 163872, "to": "mm"}, 3238 "name": "DB_DEPTH_BOUNDS_MIN" 3239 }, 3240 { 3241 "chips": ["gfx9"], 3242 "map": {"at": 163876, "to": "mm"}, 3243 "name": "DB_DEPTH_BOUNDS_MAX" 3244 }, 3245 { 3246 "chips": ["gfx9"], 3247 "map": {"at": 163880, "to": "mm"}, 3248 "name": "DB_STENCIL_CLEAR", 3249 "type_ref": "DB_STENCIL_CLEAR" 3250 }, 3251 { 3252 "chips": ["gfx9"], 3253 "map": {"at": 163884, "to": "mm"}, 3254 "name": "DB_DEPTH_CLEAR" 3255 }, 3256 { 3257 "chips": ["gfx9"], 3258 "map": {"at": 163888, "to": "mm"}, 3259 "name": "PA_SC_SCREEN_SCISSOR_TL", 3260 "type_ref": "PA_SC_SCREEN_SCISSOR_TL" 3261 }, 3262 { 3263 "chips": ["gfx9"], 3264 "map": {"at": 163892, "to": "mm"}, 3265 "name": "PA_SC_SCREEN_SCISSOR_BR", 3266 "type_ref": "PA_SC_SCREEN_SCISSOR_BR" 3267 }, 3268 { 3269 "chips": ["gfx9"], 3270 "map": {"at": 163896, "to": "mm"}, 3271 "name": "DB_Z_INFO", 3272 "type_ref": "DB_Z_INFO" 3273 }, 3274 { 3275 "chips": ["gfx9"], 3276 "map": {"at": 163900, "to": "mm"}, 3277 "name": "DB_STENCIL_INFO", 3278 "type_ref": "DB_STENCIL_INFO" 3279 }, 3280 { 3281 "chips": ["gfx9"], 3282 "map": {"at": 163904, "to": "mm"}, 3283 "name": "DB_Z_READ_BASE" 3284 }, 3285 { 3286 "chips": ["gfx9"], 3287 "map": {"at": 163908, "to": "mm"}, 3288 "name": "DB_Z_READ_BASE_HI", 3289 "type_ref": "DB_HTILE_DATA_BASE_HI" 3290 }, 3291 { 3292 "chips": ["gfx9"], 3293 "map": {"at": 163912, "to": "mm"}, 3294 "name": "DB_STENCIL_READ_BASE" 3295 }, 3296 { 3297 "chips": ["gfx9"], 3298 "map": {"at": 163916, "to": "mm"}, 3299 "name": "DB_STENCIL_READ_BASE_HI", 3300 "type_ref": "DB_HTILE_DATA_BASE_HI" 3301 }, 3302 { 3303 "chips": ["gfx9"], 3304 "map": {"at": 163920, "to": "mm"}, 3305 "name": "DB_Z_WRITE_BASE" 3306 }, 3307 { 3308 "chips": ["gfx9"], 3309 "map": {"at": 163924, "to": "mm"}, 3310 "name": "DB_Z_WRITE_BASE_HI", 3311 "type_ref": "DB_HTILE_DATA_BASE_HI" 3312 }, 3313 { 3314 "chips": ["gfx9"], 3315 "map": {"at": 163928, "to": "mm"}, 3316 "name": "DB_STENCIL_WRITE_BASE" 3317 }, 3318 { 3319 "chips": ["gfx9"], 3320 "map": {"at": 163932, "to": "mm"}, 3321 "name": "DB_STENCIL_WRITE_BASE_HI", 3322 "type_ref": "DB_HTILE_DATA_BASE_HI" 3323 }, 3324 { 3325 "chips": ["gfx9"], 3326 "map": {"at": 163936, "to": "mm"}, 3327 "name": "DB_DFSM_CONTROL", 3328 "type_ref": "DB_DFSM_CONTROL" 3329 }, 3330 { 3331 "chips": ["gfx9"], 3332 "map": {"at": 163944, "to": "mm"}, 3333 "name": "DB_Z_INFO2", 3334 "type_ref": "DB_Z_INFO2" 3335 }, 3336 { 3337 "chips": ["gfx9"], 3338 "map": {"at": 163948, "to": "mm"}, 3339 "name": "DB_STENCIL_INFO2", 3340 "type_ref": "DB_Z_INFO2" 3341 }, 3342 { 3343 "chips": ["gfx9"], 3344 "map": {"at": 163968, "to": "mm"}, 3345 "name": "TA_BC_BASE_ADDR" 3346 }, 3347 { 3348 "chips": ["gfx9"], 3349 "map": {"at": 163972, "to": "mm"}, 3350 "name": "TA_BC_BASE_ADDR_HI", 3351 "type_ref": "TA_BC_BASE_ADDR_HI" 3352 }, 3353 { 3354 "chips": ["gfx9"], 3355 "map": {"at": 164328, "to": "mm"}, 3356 "name": "COHER_DEST_BASE_HI_0", 3357 "type_ref": "COHER_DEST_BASE_HI_0" 3358 }, 3359 { 3360 "chips": ["gfx9"], 3361 "map": {"at": 164332, "to": "mm"}, 3362 "name": "COHER_DEST_BASE_HI_1", 3363 "type_ref": "COHER_DEST_BASE_HI_0" 3364 }, 3365 { 3366 "chips": ["gfx9"], 3367 "map": {"at": 164336, "to": "mm"}, 3368 "name": "COHER_DEST_BASE_HI_2", 3369 "type_ref": "COHER_DEST_BASE_HI_0" 3370 }, 3371 { 3372 "chips": ["gfx9"], 3373 "map": {"at": 164340, "to": "mm"}, 3374 "name": "COHER_DEST_BASE_HI_3", 3375 "type_ref": "COHER_DEST_BASE_HI_0" 3376 }, 3377 { 3378 "chips": ["gfx9"], 3379 "map": {"at": 164344, "to": "mm"}, 3380 "name": "COHER_DEST_BASE_2" 3381 }, 3382 { 3383 "chips": ["gfx9"], 3384 "map": {"at": 164348, "to": "mm"}, 3385 "name": "COHER_DEST_BASE_3" 3386 }, 3387 { 3388 "chips": ["gfx9"], 3389 "map": {"at": 164352, "to": "mm"}, 3390 "name": "PA_SC_WINDOW_OFFSET", 3391 "type_ref": "PA_SC_WINDOW_OFFSET" 3392 }, 3393 { 3394 "chips": ["gfx9"], 3395 "map": {"at": 164356, "to": "mm"}, 3396 "name": "PA_SC_WINDOW_SCISSOR_TL", 3397 "type_ref": "PA_SC_WINDOW_SCISSOR_TL" 3398 }, 3399 { 3400 "chips": ["gfx9"], 3401 "map": {"at": 164360, "to": "mm"}, 3402 "name": "PA_SC_WINDOW_SCISSOR_BR", 3403 "type_ref": "PA_SC_WINDOW_SCISSOR_BR" 3404 }, 3405 { 3406 "chips": ["gfx9"], 3407 "map": {"at": 164364, "to": "mm"}, 3408 "name": "PA_SC_CLIPRECT_RULE", 3409 "type_ref": "PA_SC_CLIPRECT_RULE" 3410 }, 3411 { 3412 "chips": ["gfx9"], 3413 "map": {"at": 164368, "to": "mm"}, 3414 "name": "PA_SC_CLIPRECT_0_TL", 3415 "type_ref": "PA_SC_CLIPRECT_0_TL" 3416 }, 3417 { 3418 "chips": ["gfx9"], 3419 "map": {"at": 164372, "to": "mm"}, 3420 "name": "PA_SC_CLIPRECT_0_BR", 3421 "type_ref": "PA_SC_WINDOW_SCISSOR_BR" 3422 }, 3423 { 3424 "chips": ["gfx9"], 3425 "map": {"at": 164376, "to": "mm"}, 3426 "name": "PA_SC_CLIPRECT_1_TL", 3427 "type_ref": "PA_SC_CLIPRECT_0_TL" 3428 }, 3429 { 3430 "chips": ["gfx9"], 3431 "map": {"at": 164380, "to": "mm"}, 3432 "name": "PA_SC_CLIPRECT_1_BR", 3433 "type_ref": "PA_SC_WINDOW_SCISSOR_BR" 3434 }, 3435 { 3436 "chips": ["gfx9"], 3437 "map": {"at": 164384, "to": "mm"}, 3438 "name": "PA_SC_CLIPRECT_2_TL", 3439 "type_ref": "PA_SC_CLIPRECT_0_TL" 3440 }, 3441 { 3442 "chips": ["gfx9"], 3443 "map": {"at": 164388, "to": "mm"}, 3444 "name": "PA_SC_CLIPRECT_2_BR", 3445 "type_ref": "PA_SC_WINDOW_SCISSOR_BR" 3446 }, 3447 { 3448 "chips": ["gfx9"], 3449 "map": {"at": 164392, "to": "mm"}, 3450 "name": "PA_SC_CLIPRECT_3_TL", 3451 "type_ref": "PA_SC_CLIPRECT_0_TL" 3452 }, 3453 { 3454 "chips": ["gfx9"], 3455 "map": {"at": 164396, "to": "mm"}, 3456 "name": "PA_SC_CLIPRECT_3_BR", 3457 "type_ref": "PA_SC_WINDOW_SCISSOR_BR" 3458 }, 3459 { 3460 "chips": ["gfx9"], 3461 "map": {"at": 164400, "to": "mm"}, 3462 "name": "PA_SC_EDGERULE", 3463 "type_ref": "PA_SC_EDGERULE" 3464 }, 3465 { 3466 "chips": ["gfx9"], 3467 "map": {"at": 164404, "to": "mm"}, 3468 "name": "PA_SU_HARDWARE_SCREEN_OFFSET", 3469 "type_ref": "PA_SU_HARDWARE_SCREEN_OFFSET" 3470 }, 3471 { 3472 "chips": ["gfx9"], 3473 "map": {"at": 164408, "to": "mm"}, 3474 "name": "CB_TARGET_MASK", 3475 "type_ref": "CB_TARGET_MASK" 3476 }, 3477 { 3478 "chips": ["gfx9"], 3479 "map": {"at": 164412, "to": "mm"}, 3480 "name": "CB_SHADER_MASK", 3481 "type_ref": "CB_SHADER_MASK" 3482 }, 3483 { 3484 "chips": ["gfx9"], 3485 "map": {"at": 164416, "to": "mm"}, 3486 "name": "PA_SC_GENERIC_SCISSOR_TL", 3487 "type_ref": "PA_SC_WINDOW_SCISSOR_TL" 3488 }, 3489 { 3490 "chips": ["gfx9"], 3491 "map": {"at": 164420, "to": "mm"}, 3492 "name": "PA_SC_GENERIC_SCISSOR_BR", 3493 "type_ref": "PA_SC_WINDOW_SCISSOR_BR" 3494 }, 3495 { 3496 "chips": ["gfx9"], 3497 "map": {"at": 164424, "to": "mm"}, 3498 "name": "COHER_DEST_BASE_0" 3499 }, 3500 { 3501 "chips": ["gfx9"], 3502 "map": {"at": 164428, "to": "mm"}, 3503 "name": "COHER_DEST_BASE_1" 3504 }, 3505 { 3506 "chips": ["gfx9"], 3507 "map": {"at": 164432, "to": "mm"}, 3508 "name": "PA_SC_VPORT_SCISSOR_0_TL", 3509 "type_ref": "PA_SC_WINDOW_SCISSOR_TL" 3510 }, 3511 { 3512 "chips": ["gfx9"], 3513 "map": {"at": 164436, "to": "mm"}, 3514 "name": "PA_SC_VPORT_SCISSOR_0_BR", 3515 "type_ref": "PA_SC_WINDOW_SCISSOR_BR" 3516 }, 3517 { 3518 "chips": ["gfx9"], 3519 "map": {"at": 164440, "to": "mm"}, 3520 "name": "PA_SC_VPORT_SCISSOR_1_TL", 3521 "type_ref": "PA_SC_WINDOW_SCISSOR_TL" 3522 }, 3523 { 3524 "chips": ["gfx9"], 3525 "map": {"at": 164444, "to": "mm"}, 3526 "name": "PA_SC_VPORT_SCISSOR_1_BR", 3527 "type_ref": "PA_SC_WINDOW_SCISSOR_BR" 3528 }, 3529 { 3530 "chips": ["gfx9"], 3531 "map": {"at": 164448, "to": "mm"}, 3532 "name": "PA_SC_VPORT_SCISSOR_2_TL", 3533 "type_ref": "PA_SC_WINDOW_SCISSOR_TL" 3534 }, 3535 { 3536 "chips": ["gfx9"], 3537 "map": {"at": 164452, "to": "mm"}, 3538 "name": "PA_SC_VPORT_SCISSOR_2_BR", 3539 "type_ref": "PA_SC_WINDOW_SCISSOR_BR" 3540 }, 3541 { 3542 "chips": ["gfx9"], 3543 "map": {"at": 164456, "to": "mm"}, 3544 "name": "PA_SC_VPORT_SCISSOR_3_TL", 3545 "type_ref": "PA_SC_WINDOW_SCISSOR_TL" 3546 }, 3547 { 3548 "chips": ["gfx9"], 3549 "map": {"at": 164460, "to": "mm"}, 3550 "name": "PA_SC_VPORT_SCISSOR_3_BR", 3551 "type_ref": "PA_SC_WINDOW_SCISSOR_BR" 3552 }, 3553 { 3554 "chips": ["gfx9"], 3555 "map": {"at": 164464, "to": "mm"}, 3556 "name": "PA_SC_VPORT_SCISSOR_4_TL", 3557 "type_ref": "PA_SC_WINDOW_SCISSOR_TL" 3558 }, 3559 { 3560 "chips": ["gfx9"], 3561 "map": {"at": 164468, "to": "mm"}, 3562 "name": "PA_SC_VPORT_SCISSOR_4_BR", 3563 "type_ref": "PA_SC_WINDOW_SCISSOR_BR" 3564 }, 3565 { 3566 "chips": ["gfx9"], 3567 "map": {"at": 164472, "to": "mm"}, 3568 "name": "PA_SC_VPORT_SCISSOR_5_TL", 3569 "type_ref": "PA_SC_WINDOW_SCISSOR_TL" 3570 }, 3571 { 3572 "chips": ["gfx9"], 3573 "map": {"at": 164476, "to": "mm"}, 3574 "name": "PA_SC_VPORT_SCISSOR_5_BR", 3575 "type_ref": "PA_SC_WINDOW_SCISSOR_BR" 3576 }, 3577 { 3578 "chips": ["gfx9"], 3579 "map": {"at": 164480, "to": "mm"}, 3580 "name": "PA_SC_VPORT_SCISSOR_6_TL", 3581 "type_ref": "PA_SC_WINDOW_SCISSOR_TL" 3582 }, 3583 { 3584 "chips": ["gfx9"], 3585 "map": {"at": 164484, "to": "mm"}, 3586 "name": "PA_SC_VPORT_SCISSOR_6_BR", 3587 "type_ref": "PA_SC_WINDOW_SCISSOR_BR" 3588 }, 3589 { 3590 "chips": ["gfx9"], 3591 "map": {"at": 164488, "to": "mm"}, 3592 "name": "PA_SC_VPORT_SCISSOR_7_TL", 3593 "type_ref": "PA_SC_WINDOW_SCISSOR_TL" 3594 }, 3595 { 3596 "chips": ["gfx9"], 3597 "map": {"at": 164492, "to": "mm"}, 3598 "name": "PA_SC_VPORT_SCISSOR_7_BR", 3599 "type_ref": "PA_SC_WINDOW_SCISSOR_BR" 3600 }, 3601 { 3602 "chips": ["gfx9"], 3603 "map": {"at": 164496, "to": "mm"}, 3604 "name": "PA_SC_VPORT_SCISSOR_8_TL", 3605 "type_ref": "PA_SC_WINDOW_SCISSOR_TL" 3606 }, 3607 { 3608 "chips": ["gfx9"], 3609 "map": {"at": 164500, "to": "mm"}, 3610 "name": "PA_SC_VPORT_SCISSOR_8_BR", 3611 "type_ref": "PA_SC_WINDOW_SCISSOR_BR" 3612 }, 3613 { 3614 "chips": ["gfx9"], 3615 "map": {"at": 164504, "to": "mm"}, 3616 "name": "PA_SC_VPORT_SCISSOR_9_TL", 3617 "type_ref": "PA_SC_WINDOW_SCISSOR_TL" 3618 }, 3619 { 3620 "chips": ["gfx9"], 3621 "map": {"at": 164508, "to": "mm"}, 3622 "name": "PA_SC_VPORT_SCISSOR_9_BR", 3623 "type_ref": "PA_SC_WINDOW_SCISSOR_BR" 3624 }, 3625 { 3626 "chips": ["gfx9"], 3627 "map": {"at": 164512, "to": "mm"}, 3628 "name": "PA_SC_VPORT_SCISSOR_10_TL", 3629 "type_ref": "PA_SC_WINDOW_SCISSOR_TL" 3630 }, 3631 { 3632 "chips": ["gfx9"], 3633 "map": {"at": 164516, "to": "mm"}, 3634 "name": "PA_SC_VPORT_SCISSOR_10_BR", 3635 "type_ref": "PA_SC_WINDOW_SCISSOR_BR" 3636 }, 3637 { 3638 "chips": ["gfx9"], 3639 "map": {"at": 164520, "to": "mm"}, 3640 "name": "PA_SC_VPORT_SCISSOR_11_TL", 3641 "type_ref": "PA_SC_WINDOW_SCISSOR_TL" 3642 }, 3643 { 3644 "chips": ["gfx9"], 3645 "map": {"at": 164524, "to": "mm"}, 3646 "name": "PA_SC_VPORT_SCISSOR_11_BR", 3647 "type_ref": "PA_SC_WINDOW_SCISSOR_BR" 3648 }, 3649 { 3650 "chips": ["gfx9"], 3651 "map": {"at": 164528, "to": "mm"}, 3652 "name": "PA_SC_VPORT_SCISSOR_12_TL", 3653 "type_ref": "PA_SC_WINDOW_SCISSOR_TL" 3654 }, 3655 { 3656 "chips": ["gfx9"], 3657 "map": {"at": 164532, "to": "mm"}, 3658 "name": "PA_SC_VPORT_SCISSOR_12_BR", 3659 "type_ref": "PA_SC_WINDOW_SCISSOR_BR" 3660 }, 3661 { 3662 "chips": ["gfx9"], 3663 "map": {"at": 164536, "to": "mm"}, 3664 "name": "PA_SC_VPORT_SCISSOR_13_TL", 3665 "type_ref": "PA_SC_WINDOW_SCISSOR_TL" 3666 }, 3667 { 3668 "chips": ["gfx9"], 3669 "map": {"at": 164540, "to": "mm"}, 3670 "name": "PA_SC_VPORT_SCISSOR_13_BR", 3671 "type_ref": "PA_SC_WINDOW_SCISSOR_BR" 3672 }, 3673 { 3674 "chips": ["gfx9"], 3675 "map": {"at": 164544, "to": "mm"}, 3676 "name": "PA_SC_VPORT_SCISSOR_14_TL", 3677 "type_ref": "PA_SC_WINDOW_SCISSOR_TL" 3678 }, 3679 { 3680 "chips": ["gfx9"], 3681 "map": {"at": 164548, "to": "mm"}, 3682 "name": "PA_SC_VPORT_SCISSOR_14_BR", 3683 "type_ref": "PA_SC_WINDOW_SCISSOR_BR" 3684 }, 3685 { 3686 "chips": ["gfx9"], 3687 "map": {"at": 164552, "to": "mm"}, 3688 "name": "PA_SC_VPORT_SCISSOR_15_TL", 3689 "type_ref": "PA_SC_WINDOW_SCISSOR_TL" 3690 }, 3691 { 3692 "chips": ["gfx9"], 3693 "map": {"at": 164556, "to": "mm"}, 3694 "name": "PA_SC_VPORT_SCISSOR_15_BR", 3695 "type_ref": "PA_SC_WINDOW_SCISSOR_BR" 3696 }, 3697 { 3698 "chips": ["gfx9"], 3699 "map": {"at": 164560, "to": "mm"}, 3700 "name": "PA_SC_VPORT_ZMIN_0" 3701 }, 3702 { 3703 "chips": ["gfx9"], 3704 "map": {"at": 164564, "to": "mm"}, 3705 "name": "PA_SC_VPORT_ZMAX_0" 3706 }, 3707 { 3708 "chips": ["gfx9"], 3709 "map": {"at": 164568, "to": "mm"}, 3710 "name": "PA_SC_VPORT_ZMIN_1" 3711 }, 3712 { 3713 "chips": ["gfx9"], 3714 "map": {"at": 164572, "to": "mm"}, 3715 "name": "PA_SC_VPORT_ZMAX_1" 3716 }, 3717 { 3718 "chips": ["gfx9"], 3719 "map": {"at": 164576, "to": "mm"}, 3720 "name": "PA_SC_VPORT_ZMIN_2" 3721 }, 3722 { 3723 "chips": ["gfx9"], 3724 "map": {"at": 164580, "to": "mm"}, 3725 "name": "PA_SC_VPORT_ZMAX_2" 3726 }, 3727 { 3728 "chips": ["gfx9"], 3729 "map": {"at": 164584, "to": "mm"}, 3730 "name": "PA_SC_VPORT_ZMIN_3" 3731 }, 3732 { 3733 "chips": ["gfx9"], 3734 "map": {"at": 164588, "to": "mm"}, 3735 "name": "PA_SC_VPORT_ZMAX_3" 3736 }, 3737 { 3738 "chips": ["gfx9"], 3739 "map": {"at": 164592, "to": "mm"}, 3740 "name": "PA_SC_VPORT_ZMIN_4" 3741 }, 3742 { 3743 "chips": ["gfx9"], 3744 "map": {"at": 164596, "to": "mm"}, 3745 "name": "PA_SC_VPORT_ZMAX_4" 3746 }, 3747 { 3748 "chips": ["gfx9"], 3749 "map": {"at": 164600, "to": "mm"}, 3750 "name": "PA_SC_VPORT_ZMIN_5" 3751 }, 3752 { 3753 "chips": ["gfx9"], 3754 "map": {"at": 164604, "to": "mm"}, 3755 "name": "PA_SC_VPORT_ZMAX_5" 3756 }, 3757 { 3758 "chips": ["gfx9"], 3759 "map": {"at": 164608, "to": "mm"}, 3760 "name": "PA_SC_VPORT_ZMIN_6" 3761 }, 3762 { 3763 "chips": ["gfx9"], 3764 "map": {"at": 164612, "to": "mm"}, 3765 "name": "PA_SC_VPORT_ZMAX_6" 3766 }, 3767 { 3768 "chips": ["gfx9"], 3769 "map": {"at": 164616, "to": "mm"}, 3770 "name": "PA_SC_VPORT_ZMIN_7" 3771 }, 3772 { 3773 "chips": ["gfx9"], 3774 "map": {"at": 164620, "to": "mm"}, 3775 "name": "PA_SC_VPORT_ZMAX_7" 3776 }, 3777 { 3778 "chips": ["gfx9"], 3779 "map": {"at": 164624, "to": "mm"}, 3780 "name": "PA_SC_VPORT_ZMIN_8" 3781 }, 3782 { 3783 "chips": ["gfx9"], 3784 "map": {"at": 164628, "to": "mm"}, 3785 "name": "PA_SC_VPORT_ZMAX_8" 3786 }, 3787 { 3788 "chips": ["gfx9"], 3789 "map": {"at": 164632, "to": "mm"}, 3790 "name": "PA_SC_VPORT_ZMIN_9" 3791 }, 3792 { 3793 "chips": ["gfx9"], 3794 "map": {"at": 164636, "to": "mm"}, 3795 "name": "PA_SC_VPORT_ZMAX_9" 3796 }, 3797 { 3798 "chips": ["gfx9"], 3799 "map": {"at": 164640, "to": "mm"}, 3800 "name": "PA_SC_VPORT_ZMIN_10" 3801 }, 3802 { 3803 "chips": ["gfx9"], 3804 "map": {"at": 164644, "to": "mm"}, 3805 "name": "PA_SC_VPORT_ZMAX_10" 3806 }, 3807 { 3808 "chips": ["gfx9"], 3809 "map": {"at": 164648, "to": "mm"}, 3810 "name": "PA_SC_VPORT_ZMIN_11" 3811 }, 3812 { 3813 "chips": ["gfx9"], 3814 "map": {"at": 164652, "to": "mm"}, 3815 "name": "PA_SC_VPORT_ZMAX_11" 3816 }, 3817 { 3818 "chips": ["gfx9"], 3819 "map": {"at": 164656, "to": "mm"}, 3820 "name": "PA_SC_VPORT_ZMIN_12" 3821 }, 3822 { 3823 "chips": ["gfx9"], 3824 "map": {"at": 164660, "to": "mm"}, 3825 "name": "PA_SC_VPORT_ZMAX_12" 3826 }, 3827 { 3828 "chips": ["gfx9"], 3829 "map": {"at": 164664, "to": "mm"}, 3830 "name": "PA_SC_VPORT_ZMIN_13" 3831 }, 3832 { 3833 "chips": ["gfx9"], 3834 "map": {"at": 164668, "to": "mm"}, 3835 "name": "PA_SC_VPORT_ZMAX_13" 3836 }, 3837 { 3838 "chips": ["gfx9"], 3839 "map": {"at": 164672, "to": "mm"}, 3840 "name": "PA_SC_VPORT_ZMIN_14" 3841 }, 3842 { 3843 "chips": ["gfx9"], 3844 "map": {"at": 164676, "to": "mm"}, 3845 "name": "PA_SC_VPORT_ZMAX_14" 3846 }, 3847 { 3848 "chips": ["gfx9"], 3849 "map": {"at": 164680, "to": "mm"}, 3850 "name": "PA_SC_VPORT_ZMIN_15" 3851 }, 3852 { 3853 "chips": ["gfx9"], 3854 "map": {"at": 164684, "to": "mm"}, 3855 "name": "PA_SC_VPORT_ZMAX_15" 3856 }, 3857 { 3858 "chips": ["gfx9"], 3859 "map": {"at": 164688, "to": "mm"}, 3860 "name": "PA_SC_RASTER_CONFIG", 3861 "type_ref": "PA_SC_RASTER_CONFIG" 3862 }, 3863 { 3864 "chips": ["gfx9"], 3865 "map": {"at": 164692, "to": "mm"}, 3866 "name": "PA_SC_RASTER_CONFIG_1", 3867 "type_ref": "PA_SC_RASTER_CONFIG_1" 3868 }, 3869 { 3870 "chips": ["gfx9"], 3871 "map": {"at": 164696, "to": "mm"}, 3872 "name": "PA_SC_SCREEN_EXTENT_CONTROL", 3873 "type_ref": "PA_SC_SCREEN_EXTENT_CONTROL" 3874 }, 3875 { 3876 "chips": ["gfx9"], 3877 "map": {"at": 164700, "to": "mm"}, 3878 "name": "PA_SC_TILE_STEERING_OVERRIDE", 3879 "type_ref": "PA_SC_TILE_STEERING_OVERRIDE" 3880 }, 3881 { 3882 "chips": ["gfx9"], 3883 "map": {"at": 164704, "to": "mm"}, 3884 "name": "CP_PERFMON_CNTX_CNTL", 3885 "type_ref": "CP_PERFMON_CNTX_CNTL" 3886 }, 3887 { 3888 "chips": ["gfx9"], 3889 "map": {"at": 164708, "to": "mm"}, 3890 "name": "CP_PIPEID", 3891 "type_ref": "CP_PIPEID" 3892 }, 3893 { 3894 "chips": ["gfx9"], 3895 "map": {"at": 164712, "to": "mm"}, 3896 "name": "CP_VMID", 3897 "type_ref": "CP_VMID" 3898 }, 3899 { 3900 "chips": ["gfx9"], 3901 "map": {"at": 164768, "to": "mm"}, 3902 "name": "PA_SC_RIGHT_VERT_GRID", 3903 "type_ref": "PA_SC_RIGHT_VERT_GRID" 3904 }, 3905 { 3906 "chips": ["gfx9"], 3907 "map": {"at": 164772, "to": "mm"}, 3908 "name": "PA_SC_LEFT_VERT_GRID", 3909 "type_ref": "PA_SC_RIGHT_VERT_GRID" 3910 }, 3911 { 3912 "chips": ["gfx9"], 3913 "map": {"at": 164776, "to": "mm"}, 3914 "name": "PA_SC_HORIZ_GRID", 3915 "type_ref": "PA_SC_HORIZ_GRID" 3916 }, 3917 { 3918 "chips": ["gfx9"], 3919 "map": {"at": 164876, "to": "mm"}, 3920 "name": "VGT_MULTI_PRIM_IB_RESET_INDX" 3921 }, 3922 { 3923 "chips": ["gfx9"], 3924 "map": {"at": 164884, "to": "mm"}, 3925 "name": "CB_BLEND_RED" 3926 }, 3927 { 3928 "chips": ["gfx9"], 3929 "map": {"at": 164888, "to": "mm"}, 3930 "name": "CB_BLEND_GREEN" 3931 }, 3932 { 3933 "chips": ["gfx9"], 3934 "map": {"at": 164892, "to": "mm"}, 3935 "name": "CB_BLEND_BLUE" 3936 }, 3937 { 3938 "chips": ["gfx9"], 3939 "map": {"at": 164896, "to": "mm"}, 3940 "name": "CB_BLEND_ALPHA" 3941 }, 3942 { 3943 "chips": ["gfx9"], 3944 "map": {"at": 164900, "to": "mm"}, 3945 "name": "CB_DCC_CONTROL", 3946 "type_ref": "CB_DCC_CONTROL" 3947 }, 3948 { 3949 "chips": ["gfx9"], 3950 "map": {"at": 164908, "to": "mm"}, 3951 "name": "DB_STENCIL_CONTROL", 3952 "type_ref": "DB_STENCIL_CONTROL" 3953 }, 3954 { 3955 "chips": ["gfx9"], 3956 "map": {"at": 164912, "to": "mm"}, 3957 "name": "DB_STENCILREFMASK", 3958 "type_ref": "DB_STENCILREFMASK" 3959 }, 3960 { 3961 "chips": ["gfx9"], 3962 "map": {"at": 164916, "to": "mm"}, 3963 "name": "DB_STENCILREFMASK_BF", 3964 "type_ref": "DB_STENCILREFMASK_BF" 3965 }, 3966 { 3967 "chips": ["gfx9"], 3968 "map": {"at": 164924, "to": "mm"}, 3969 "name": "PA_CL_VPORT_XSCALE" 3970 }, 3971 { 3972 "chips": ["gfx9"], 3973 "map": {"at": 164928, "to": "mm"}, 3974 "name": "PA_CL_VPORT_XOFFSET" 3975 }, 3976 { 3977 "chips": ["gfx9"], 3978 "map": {"at": 164932, "to": "mm"}, 3979 "name": "PA_CL_VPORT_YSCALE" 3980 }, 3981 { 3982 "chips": ["gfx9"], 3983 "map": {"at": 164936, "to": "mm"}, 3984 "name": "PA_CL_VPORT_YOFFSET" 3985 }, 3986 { 3987 "chips": ["gfx9"], 3988 "map": {"at": 164940, "to": "mm"}, 3989 "name": "PA_CL_VPORT_ZSCALE" 3990 }, 3991 { 3992 "chips": ["gfx9"], 3993 "map": {"at": 164944, "to": "mm"}, 3994 "name": "PA_CL_VPORT_ZOFFSET" 3995 }, 3996 { 3997 "chips": ["gfx9"], 3998 "map": {"at": 164948, "to": "mm"}, 3999 "name": "PA_CL_VPORT_XSCALE_1" 4000 }, 4001 { 4002 "chips": ["gfx9"], 4003 "map": {"at": 164952, "to": "mm"}, 4004 "name": "PA_CL_VPORT_XOFFSET_1" 4005 }, 4006 { 4007 "chips": ["gfx9"], 4008 "map": {"at": 164956, "to": "mm"}, 4009 "name": "PA_CL_VPORT_YSCALE_1" 4010 }, 4011 { 4012 "chips": ["gfx9"], 4013 "map": {"at": 164960, "to": "mm"}, 4014 "name": "PA_CL_VPORT_YOFFSET_1" 4015 }, 4016 { 4017 "chips": ["gfx9"], 4018 "map": {"at": 164964, "to": "mm"}, 4019 "name": "PA_CL_VPORT_ZSCALE_1" 4020 }, 4021 { 4022 "chips": ["gfx9"], 4023 "map": {"at": 164968, "to": "mm"}, 4024 "name": "PA_CL_VPORT_ZOFFSET_1" 4025 }, 4026 { 4027 "chips": ["gfx9"], 4028 "map": {"at": 164972, "to": "mm"}, 4029 "name": "PA_CL_VPORT_XSCALE_2" 4030 }, 4031 { 4032 "chips": ["gfx9"], 4033 "map": {"at": 164976, "to": "mm"}, 4034 "name": "PA_CL_VPORT_XOFFSET_2" 4035 }, 4036 { 4037 "chips": ["gfx9"], 4038 "map": {"at": 164980, "to": "mm"}, 4039 "name": "PA_CL_VPORT_YSCALE_2" 4040 }, 4041 { 4042 "chips": ["gfx9"], 4043 "map": {"at": 164984, "to": "mm"}, 4044 "name": "PA_CL_VPORT_YOFFSET_2" 4045 }, 4046 { 4047 "chips": ["gfx9"], 4048 "map": {"at": 164988, "to": "mm"}, 4049 "name": "PA_CL_VPORT_ZSCALE_2" 4050 }, 4051 { 4052 "chips": ["gfx9"], 4053 "map": {"at": 164992, "to": "mm"}, 4054 "name": "PA_CL_VPORT_ZOFFSET_2" 4055 }, 4056 { 4057 "chips": ["gfx9"], 4058 "map": {"at": 164996, "to": "mm"}, 4059 "name": "PA_CL_VPORT_XSCALE_3" 4060 }, 4061 { 4062 "chips": ["gfx9"], 4063 "map": {"at": 165000, "to": "mm"}, 4064 "name": "PA_CL_VPORT_XOFFSET_3" 4065 }, 4066 { 4067 "chips": ["gfx9"], 4068 "map": {"at": 165004, "to": "mm"}, 4069 "name": "PA_CL_VPORT_YSCALE_3" 4070 }, 4071 { 4072 "chips": ["gfx9"], 4073 "map": {"at": 165008, "to": "mm"}, 4074 "name": "PA_CL_VPORT_YOFFSET_3" 4075 }, 4076 { 4077 "chips": ["gfx9"], 4078 "map": {"at": 165012, "to": "mm"}, 4079 "name": "PA_CL_VPORT_ZSCALE_3" 4080 }, 4081 { 4082 "chips": ["gfx9"], 4083 "map": {"at": 165016, "to": "mm"}, 4084 "name": "PA_CL_VPORT_ZOFFSET_3" 4085 }, 4086 { 4087 "chips": ["gfx9"], 4088 "map": {"at": 165020, "to": "mm"}, 4089 "name": "PA_CL_VPORT_XSCALE_4" 4090 }, 4091 { 4092 "chips": ["gfx9"], 4093 "map": {"at": 165024, "to": "mm"}, 4094 "name": "PA_CL_VPORT_XOFFSET_4" 4095 }, 4096 { 4097 "chips": ["gfx9"], 4098 "map": {"at": 165028, "to": "mm"}, 4099 "name": "PA_CL_VPORT_YSCALE_4" 4100 }, 4101 { 4102 "chips": ["gfx9"], 4103 "map": {"at": 165032, "to": "mm"}, 4104 "name": "PA_CL_VPORT_YOFFSET_4" 4105 }, 4106 { 4107 "chips": ["gfx9"], 4108 "map": {"at": 165036, "to": "mm"}, 4109 "name": "PA_CL_VPORT_ZSCALE_4" 4110 }, 4111 { 4112 "chips": ["gfx9"], 4113 "map": {"at": 165040, "to": "mm"}, 4114 "name": "PA_CL_VPORT_ZOFFSET_4" 4115 }, 4116 { 4117 "chips": ["gfx9"], 4118 "map": {"at": 165044, "to": "mm"}, 4119 "name": "PA_CL_VPORT_XSCALE_5" 4120 }, 4121 { 4122 "chips": ["gfx9"], 4123 "map": {"at": 165048, "to": "mm"}, 4124 "name": "PA_CL_VPORT_XOFFSET_5" 4125 }, 4126 { 4127 "chips": ["gfx9"], 4128 "map": {"at": 165052, "to": "mm"}, 4129 "name": "PA_CL_VPORT_YSCALE_5" 4130 }, 4131 { 4132 "chips": ["gfx9"], 4133 "map": {"at": 165056, "to": "mm"}, 4134 "name": "PA_CL_VPORT_YOFFSET_5" 4135 }, 4136 { 4137 "chips": ["gfx9"], 4138 "map": {"at": 165060, "to": "mm"}, 4139 "name": "PA_CL_VPORT_ZSCALE_5" 4140 }, 4141 { 4142 "chips": ["gfx9"], 4143 "map": {"at": 165064, "to": "mm"}, 4144 "name": "PA_CL_VPORT_ZOFFSET_5" 4145 }, 4146 { 4147 "chips": ["gfx9"], 4148 "map": {"at": 165068, "to": "mm"}, 4149 "name": "PA_CL_VPORT_XSCALE_6" 4150 }, 4151 { 4152 "chips": ["gfx9"], 4153 "map": {"at": 165072, "to": "mm"}, 4154 "name": "PA_CL_VPORT_XOFFSET_6" 4155 }, 4156 { 4157 "chips": ["gfx9"], 4158 "map": {"at": 165076, "to": "mm"}, 4159 "name": "PA_CL_VPORT_YSCALE_6" 4160 }, 4161 { 4162 "chips": ["gfx9"], 4163 "map": {"at": 165080, "to": "mm"}, 4164 "name": "PA_CL_VPORT_YOFFSET_6" 4165 }, 4166 { 4167 "chips": ["gfx9"], 4168 "map": {"at": 165084, "to": "mm"}, 4169 "name": "PA_CL_VPORT_ZSCALE_6" 4170 }, 4171 { 4172 "chips": ["gfx9"], 4173 "map": {"at": 165088, "to": "mm"}, 4174 "name": "PA_CL_VPORT_ZOFFSET_6" 4175 }, 4176 { 4177 "chips": ["gfx9"], 4178 "map": {"at": 165092, "to": "mm"}, 4179 "name": "PA_CL_VPORT_XSCALE_7" 4180 }, 4181 { 4182 "chips": ["gfx9"], 4183 "map": {"at": 165096, "to": "mm"}, 4184 "name": "PA_CL_VPORT_XOFFSET_7" 4185 }, 4186 { 4187 "chips": ["gfx9"], 4188 "map": {"at": 165100, "to": "mm"}, 4189 "name": "PA_CL_VPORT_YSCALE_7" 4190 }, 4191 { 4192 "chips": ["gfx9"], 4193 "map": {"at": 165104, "to": "mm"}, 4194 "name": "PA_CL_VPORT_YOFFSET_7" 4195 }, 4196 { 4197 "chips": ["gfx9"], 4198 "map": {"at": 165108, "to": "mm"}, 4199 "name": "PA_CL_VPORT_ZSCALE_7" 4200 }, 4201 { 4202 "chips": ["gfx9"], 4203 "map": {"at": 165112, "to": "mm"}, 4204 "name": "PA_CL_VPORT_ZOFFSET_7" 4205 }, 4206 { 4207 "chips": ["gfx9"], 4208 "map": {"at": 165116, "to": "mm"}, 4209 "name": "PA_CL_VPORT_XSCALE_8" 4210 }, 4211 { 4212 "chips": ["gfx9"], 4213 "map": {"at": 165120, "to": "mm"}, 4214 "name": "PA_CL_VPORT_XOFFSET_8" 4215 }, 4216 { 4217 "chips": ["gfx9"], 4218 "map": {"at": 165124, "to": "mm"}, 4219 "name": "PA_CL_VPORT_YSCALE_8" 4220 }, 4221 { 4222 "chips": ["gfx9"], 4223 "map": {"at": 165128, "to": "mm"}, 4224 "name": "PA_CL_VPORT_YOFFSET_8" 4225 }, 4226 { 4227 "chips": ["gfx9"], 4228 "map": {"at": 165132, "to": "mm"}, 4229 "name": "PA_CL_VPORT_ZSCALE_8" 4230 }, 4231 { 4232 "chips": ["gfx9"], 4233 "map": {"at": 165136, "to": "mm"}, 4234 "name": "PA_CL_VPORT_ZOFFSET_8" 4235 }, 4236 { 4237 "chips": ["gfx9"], 4238 "map": {"at": 165140, "to": "mm"}, 4239 "name": "PA_CL_VPORT_XSCALE_9" 4240 }, 4241 { 4242 "chips": ["gfx9"], 4243 "map": {"at": 165144, "to": "mm"}, 4244 "name": "PA_CL_VPORT_XOFFSET_9" 4245 }, 4246 { 4247 "chips": ["gfx9"], 4248 "map": {"at": 165148, "to": "mm"}, 4249 "name": "PA_CL_VPORT_YSCALE_9" 4250 }, 4251 { 4252 "chips": ["gfx9"], 4253 "map": {"at": 165152, "to": "mm"}, 4254 "name": "PA_CL_VPORT_YOFFSET_9" 4255 }, 4256 { 4257 "chips": ["gfx9"], 4258 "map": {"at": 165156, "to": "mm"}, 4259 "name": "PA_CL_VPORT_ZSCALE_9" 4260 }, 4261 { 4262 "chips": ["gfx9"], 4263 "map": {"at": 165160, "to": "mm"}, 4264 "name": "PA_CL_VPORT_ZOFFSET_9" 4265 }, 4266 { 4267 "chips": ["gfx9"], 4268 "map": {"at": 165164, "to": "mm"}, 4269 "name": "PA_CL_VPORT_XSCALE_10" 4270 }, 4271 { 4272 "chips": ["gfx9"], 4273 "map": {"at": 165168, "to": "mm"}, 4274 "name": "PA_CL_VPORT_XOFFSET_10" 4275 }, 4276 { 4277 "chips": ["gfx9"], 4278 "map": {"at": 165172, "to": "mm"}, 4279 "name": "PA_CL_VPORT_YSCALE_10" 4280 }, 4281 { 4282 "chips": ["gfx9"], 4283 "map": {"at": 165176, "to": "mm"}, 4284 "name": "PA_CL_VPORT_YOFFSET_10" 4285 }, 4286 { 4287 "chips": ["gfx9"], 4288 "map": {"at": 165180, "to": "mm"}, 4289 "name": "PA_CL_VPORT_ZSCALE_10" 4290 }, 4291 { 4292 "chips": ["gfx9"], 4293 "map": {"at": 165184, "to": "mm"}, 4294 "name": "PA_CL_VPORT_ZOFFSET_10" 4295 }, 4296 { 4297 "chips": ["gfx9"], 4298 "map": {"at": 165188, "to": "mm"}, 4299 "name": "PA_CL_VPORT_XSCALE_11" 4300 }, 4301 { 4302 "chips": ["gfx9"], 4303 "map": {"at": 165192, "to": "mm"}, 4304 "name": "PA_CL_VPORT_XOFFSET_11" 4305 }, 4306 { 4307 "chips": ["gfx9"], 4308 "map": {"at": 165196, "to": "mm"}, 4309 "name": "PA_CL_VPORT_YSCALE_11" 4310 }, 4311 { 4312 "chips": ["gfx9"], 4313 "map": {"at": 165200, "to": "mm"}, 4314 "name": "PA_CL_VPORT_YOFFSET_11" 4315 }, 4316 { 4317 "chips": ["gfx9"], 4318 "map": {"at": 165204, "to": "mm"}, 4319 "name": "PA_CL_VPORT_ZSCALE_11" 4320 }, 4321 { 4322 "chips": ["gfx9"], 4323 "map": {"at": 165208, "to": "mm"}, 4324 "name": "PA_CL_VPORT_ZOFFSET_11" 4325 }, 4326 { 4327 "chips": ["gfx9"], 4328 "map": {"at": 165212, "to": "mm"}, 4329 "name": "PA_CL_VPORT_XSCALE_12" 4330 }, 4331 { 4332 "chips": ["gfx9"], 4333 "map": {"at": 165216, "to": "mm"}, 4334 "name": "PA_CL_VPORT_XOFFSET_12" 4335 }, 4336 { 4337 "chips": ["gfx9"], 4338 "map": {"at": 165220, "to": "mm"}, 4339 "name": "PA_CL_VPORT_YSCALE_12" 4340 }, 4341 { 4342 "chips": ["gfx9"], 4343 "map": {"at": 165224, "to": "mm"}, 4344 "name": "PA_CL_VPORT_YOFFSET_12" 4345 }, 4346 { 4347 "chips": ["gfx9"], 4348 "map": {"at": 165228, "to": "mm"}, 4349 "name": "PA_CL_VPORT_ZSCALE_12" 4350 }, 4351 { 4352 "chips": ["gfx9"], 4353 "map": {"at": 165232, "to": "mm"}, 4354 "name": "PA_CL_VPORT_ZOFFSET_12" 4355 }, 4356 { 4357 "chips": ["gfx9"], 4358 "map": {"at": 165236, "to": "mm"}, 4359 "name": "PA_CL_VPORT_XSCALE_13" 4360 }, 4361 { 4362 "chips": ["gfx9"], 4363 "map": {"at": 165240, "to": "mm"}, 4364 "name": "PA_CL_VPORT_XOFFSET_13" 4365 }, 4366 { 4367 "chips": ["gfx9"], 4368 "map": {"at": 165244, "to": "mm"}, 4369 "name": "PA_CL_VPORT_YSCALE_13" 4370 }, 4371 { 4372 "chips": ["gfx9"], 4373 "map": {"at": 165248, "to": "mm"}, 4374 "name": "PA_CL_VPORT_YOFFSET_13" 4375 }, 4376 { 4377 "chips": ["gfx9"], 4378 "map": {"at": 165252, "to": "mm"}, 4379 "name": "PA_CL_VPORT_ZSCALE_13" 4380 }, 4381 { 4382 "chips": ["gfx9"], 4383 "map": {"at": 165256, "to": "mm"}, 4384 "name": "PA_CL_VPORT_ZOFFSET_13" 4385 }, 4386 { 4387 "chips": ["gfx9"], 4388 "map": {"at": 165260, "to": "mm"}, 4389 "name": "PA_CL_VPORT_XSCALE_14" 4390 }, 4391 { 4392 "chips": ["gfx9"], 4393 "map": {"at": 165264, "to": "mm"}, 4394 "name": "PA_CL_VPORT_XOFFSET_14" 4395 }, 4396 { 4397 "chips": ["gfx9"], 4398 "map": {"at": 165268, "to": "mm"}, 4399 "name": "PA_CL_VPORT_YSCALE_14" 4400 }, 4401 { 4402 "chips": ["gfx9"], 4403 "map": {"at": 165272, "to": "mm"}, 4404 "name": "PA_CL_VPORT_YOFFSET_14" 4405 }, 4406 { 4407 "chips": ["gfx9"], 4408 "map": {"at": 165276, "to": "mm"}, 4409 "name": "PA_CL_VPORT_ZSCALE_14" 4410 }, 4411 { 4412 "chips": ["gfx9"], 4413 "map": {"at": 165280, "to": "mm"}, 4414 "name": "PA_CL_VPORT_ZOFFSET_14" 4415 }, 4416 { 4417 "chips": ["gfx9"], 4418 "map": {"at": 165284, "to": "mm"}, 4419 "name": "PA_CL_VPORT_XSCALE_15" 4420 }, 4421 { 4422 "chips": ["gfx9"], 4423 "map": {"at": 165288, "to": "mm"}, 4424 "name": "PA_CL_VPORT_XOFFSET_15" 4425 }, 4426 { 4427 "chips": ["gfx9"], 4428 "map": {"at": 165292, "to": "mm"}, 4429 "name": "PA_CL_VPORT_YSCALE_15" 4430 }, 4431 { 4432 "chips": ["gfx9"], 4433 "map": {"at": 165296, "to": "mm"}, 4434 "name": "PA_CL_VPORT_YOFFSET_15" 4435 }, 4436 { 4437 "chips": ["gfx9"], 4438 "map": {"at": 165300, "to": "mm"}, 4439 "name": "PA_CL_VPORT_ZSCALE_15" 4440 }, 4441 { 4442 "chips": ["gfx9"], 4443 "map": {"at": 165304, "to": "mm"}, 4444 "name": "PA_CL_VPORT_ZOFFSET_15" 4445 }, 4446 { 4447 "chips": ["gfx9"], 4448 "map": {"at": 165308, "to": "mm"}, 4449 "name": "PA_CL_UCP_0_X" 4450 }, 4451 { 4452 "chips": ["gfx9"], 4453 "map": {"at": 165312, "to": "mm"}, 4454 "name": "PA_CL_UCP_0_Y" 4455 }, 4456 { 4457 "chips": ["gfx9"], 4458 "map": {"at": 165316, "to": "mm"}, 4459 "name": "PA_CL_UCP_0_Z" 4460 }, 4461 { 4462 "chips": ["gfx9"], 4463 "map": {"at": 165320, "to": "mm"}, 4464 "name": "PA_CL_UCP_0_W" 4465 }, 4466 { 4467 "chips": ["gfx9"], 4468 "map": {"at": 165324, "to": "mm"}, 4469 "name": "PA_CL_UCP_1_X" 4470 }, 4471 { 4472 "chips": ["gfx9"], 4473 "map": {"at": 165328, "to": "mm"}, 4474 "name": "PA_CL_UCP_1_Y" 4475 }, 4476 { 4477 "chips": ["gfx9"], 4478 "map": {"at": 165332, "to": "mm"}, 4479 "name": "PA_CL_UCP_1_Z" 4480 }, 4481 { 4482 "chips": ["gfx9"], 4483 "map": {"at": 165336, "to": "mm"}, 4484 "name": "PA_CL_UCP_1_W" 4485 }, 4486 { 4487 "chips": ["gfx9"], 4488 "map": {"at": 165340, "to": "mm"}, 4489 "name": "PA_CL_UCP_2_X" 4490 }, 4491 { 4492 "chips": ["gfx9"], 4493 "map": {"at": 165344, "to": "mm"}, 4494 "name": "PA_CL_UCP_2_Y" 4495 }, 4496 { 4497 "chips": ["gfx9"], 4498 "map": {"at": 165348, "to": "mm"}, 4499 "name": "PA_CL_UCP_2_Z" 4500 }, 4501 { 4502 "chips": ["gfx9"], 4503 "map": {"at": 165352, "to": "mm"}, 4504 "name": "PA_CL_UCP_2_W" 4505 }, 4506 { 4507 "chips": ["gfx9"], 4508 "map": {"at": 165356, "to": "mm"}, 4509 "name": "PA_CL_UCP_3_X" 4510 }, 4511 { 4512 "chips": ["gfx9"], 4513 "map": {"at": 165360, "to": "mm"}, 4514 "name": "PA_CL_UCP_3_Y" 4515 }, 4516 { 4517 "chips": ["gfx9"], 4518 "map": {"at": 165364, "to": "mm"}, 4519 "name": "PA_CL_UCP_3_Z" 4520 }, 4521 { 4522 "chips": ["gfx9"], 4523 "map": {"at": 165368, "to": "mm"}, 4524 "name": "PA_CL_UCP_3_W" 4525 }, 4526 { 4527 "chips": ["gfx9"], 4528 "map": {"at": 165372, "to": "mm"}, 4529 "name": "PA_CL_UCP_4_X" 4530 }, 4531 { 4532 "chips": ["gfx9"], 4533 "map": {"at": 165376, "to": "mm"}, 4534 "name": "PA_CL_UCP_4_Y" 4535 }, 4536 { 4537 "chips": ["gfx9"], 4538 "map": {"at": 165380, "to": "mm"}, 4539 "name": "PA_CL_UCP_4_Z" 4540 }, 4541 { 4542 "chips": ["gfx9"], 4543 "map": {"at": 165384, "to": "mm"}, 4544 "name": "PA_CL_UCP_4_W" 4545 }, 4546 { 4547 "chips": ["gfx9"], 4548 "map": {"at": 165388, "to": "mm"}, 4549 "name": "PA_CL_UCP_5_X" 4550 }, 4551 { 4552 "chips": ["gfx9"], 4553 "map": {"at": 165392, "to": "mm"}, 4554 "name": "PA_CL_UCP_5_Y" 4555 }, 4556 { 4557 "chips": ["gfx9"], 4558 "map": {"at": 165396, "to": "mm"}, 4559 "name": "PA_CL_UCP_5_Z" 4560 }, 4561 { 4562 "chips": ["gfx9"], 4563 "map": {"at": 165400, "to": "mm"}, 4564 "name": "PA_CL_UCP_5_W" 4565 }, 4566 { 4567 "chips": ["gfx9"], 4568 "map": {"at": 165404, "to": "mm"}, 4569 "name": "PA_CL_PROG_NEAR_CLIP_Z" 4570 }, 4571 { 4572 "chips": ["gfx9"], 4573 "map": {"at": 165444, "to": "mm"}, 4574 "name": "SPI_PS_INPUT_CNTL_0", 4575 "type_ref": "SPI_PS_INPUT_CNTL_0" 4576 }, 4577 { 4578 "chips": ["gfx9"], 4579 "map": {"at": 165448, "to": "mm"}, 4580 "name": "SPI_PS_INPUT_CNTL_1", 4581 "type_ref": "SPI_PS_INPUT_CNTL_0" 4582 }, 4583 { 4584 "chips": ["gfx9"], 4585 "map": {"at": 165452, "to": "mm"}, 4586 "name": "SPI_PS_INPUT_CNTL_2", 4587 "type_ref": "SPI_PS_INPUT_CNTL_0" 4588 }, 4589 { 4590 "chips": ["gfx9"], 4591 "map": {"at": 165456, "to": "mm"}, 4592 "name": "SPI_PS_INPUT_CNTL_3", 4593 "type_ref": "SPI_PS_INPUT_CNTL_0" 4594 }, 4595 { 4596 "chips": ["gfx9"], 4597 "map": {"at": 165460, "to": "mm"}, 4598 "name": "SPI_PS_INPUT_CNTL_4", 4599 "type_ref": "SPI_PS_INPUT_CNTL_0" 4600 }, 4601 { 4602 "chips": ["gfx9"], 4603 "map": {"at": 165464, "to": "mm"}, 4604 "name": "SPI_PS_INPUT_CNTL_5", 4605 "type_ref": "SPI_PS_INPUT_CNTL_0" 4606 }, 4607 { 4608 "chips": ["gfx9"], 4609 "map": {"at": 165468, "to": "mm"}, 4610 "name": "SPI_PS_INPUT_CNTL_6", 4611 "type_ref": "SPI_PS_INPUT_CNTL_0" 4612 }, 4613 { 4614 "chips": ["gfx9"], 4615 "map": {"at": 165472, "to": "mm"}, 4616 "name": "SPI_PS_INPUT_CNTL_7", 4617 "type_ref": "SPI_PS_INPUT_CNTL_0" 4618 }, 4619 { 4620 "chips": ["gfx9"], 4621 "map": {"at": 165476, "to": "mm"}, 4622 "name": "SPI_PS_INPUT_CNTL_8", 4623 "type_ref": "SPI_PS_INPUT_CNTL_0" 4624 }, 4625 { 4626 "chips": ["gfx9"], 4627 "map": {"at": 165480, "to": "mm"}, 4628 "name": "SPI_PS_INPUT_CNTL_9", 4629 "type_ref": "SPI_PS_INPUT_CNTL_0" 4630 }, 4631 { 4632 "chips": ["gfx9"], 4633 "map": {"at": 165484, "to": "mm"}, 4634 "name": "SPI_PS_INPUT_CNTL_10", 4635 "type_ref": "SPI_PS_INPUT_CNTL_0" 4636 }, 4637 { 4638 "chips": ["gfx9"], 4639 "map": {"at": 165488, "to": "mm"}, 4640 "name": "SPI_PS_INPUT_CNTL_11", 4641 "type_ref": "SPI_PS_INPUT_CNTL_0" 4642 }, 4643 { 4644 "chips": ["gfx9"], 4645 "map": {"at": 165492, "to": "mm"}, 4646 "name": "SPI_PS_INPUT_CNTL_12", 4647 "type_ref": "SPI_PS_INPUT_CNTL_0" 4648 }, 4649 { 4650 "chips": ["gfx9"], 4651 "map": {"at": 165496, "to": "mm"}, 4652 "name": "SPI_PS_INPUT_CNTL_13", 4653 "type_ref": "SPI_PS_INPUT_CNTL_0" 4654 }, 4655 { 4656 "chips": ["gfx9"], 4657 "map": {"at": 165500, "to": "mm"}, 4658 "name": "SPI_PS_INPUT_CNTL_14", 4659 "type_ref": "SPI_PS_INPUT_CNTL_0" 4660 }, 4661 { 4662 "chips": ["gfx9"], 4663 "map": {"at": 165504, "to": "mm"}, 4664 "name": "SPI_PS_INPUT_CNTL_15", 4665 "type_ref": "SPI_PS_INPUT_CNTL_0" 4666 }, 4667 { 4668 "chips": ["gfx9"], 4669 "map": {"at": 165508, "to": "mm"}, 4670 "name": "SPI_PS_INPUT_CNTL_16", 4671 "type_ref": "SPI_PS_INPUT_CNTL_0" 4672 }, 4673 { 4674 "chips": ["gfx9"], 4675 "map": {"at": 165512, "to": "mm"}, 4676 "name": "SPI_PS_INPUT_CNTL_17", 4677 "type_ref": "SPI_PS_INPUT_CNTL_0" 4678 }, 4679 { 4680 "chips": ["gfx9"], 4681 "map": {"at": 165516, "to": "mm"}, 4682 "name": "SPI_PS_INPUT_CNTL_18", 4683 "type_ref": "SPI_PS_INPUT_CNTL_0" 4684 }, 4685 { 4686 "chips": ["gfx9"], 4687 "map": {"at": 165520, "to": "mm"}, 4688 "name": "SPI_PS_INPUT_CNTL_19", 4689 "type_ref": "SPI_PS_INPUT_CNTL_0" 4690 }, 4691 { 4692 "chips": ["gfx9"], 4693 "map": {"at": 165524, "to": "mm"}, 4694 "name": "SPI_PS_INPUT_CNTL_20", 4695 "type_ref": "SPI_PS_INPUT_CNTL_20" 4696 }, 4697 { 4698 "chips": ["gfx9"], 4699 "map": {"at": 165528, "to": "mm"}, 4700 "name": "SPI_PS_INPUT_CNTL_21", 4701 "type_ref": "SPI_PS_INPUT_CNTL_20" 4702 }, 4703 { 4704 "chips": ["gfx9"], 4705 "map": {"at": 165532, "to": "mm"}, 4706 "name": "SPI_PS_INPUT_CNTL_22", 4707 "type_ref": "SPI_PS_INPUT_CNTL_20" 4708 }, 4709 { 4710 "chips": ["gfx9"], 4711 "map": {"at": 165536, "to": "mm"}, 4712 "name": "SPI_PS_INPUT_CNTL_23", 4713 "type_ref": "SPI_PS_INPUT_CNTL_20" 4714 }, 4715 { 4716 "chips": ["gfx9"], 4717 "map": {"at": 165540, "to": "mm"}, 4718 "name": "SPI_PS_INPUT_CNTL_24", 4719 "type_ref": "SPI_PS_INPUT_CNTL_20" 4720 }, 4721 { 4722 "chips": ["gfx9"], 4723 "map": {"at": 165544, "to": "mm"}, 4724 "name": "SPI_PS_INPUT_CNTL_25", 4725 "type_ref": "SPI_PS_INPUT_CNTL_20" 4726 }, 4727 { 4728 "chips": ["gfx9"], 4729 "map": {"at": 165548, "to": "mm"}, 4730 "name": "SPI_PS_INPUT_CNTL_26", 4731 "type_ref": "SPI_PS_INPUT_CNTL_20" 4732 }, 4733 { 4734 "chips": ["gfx9"], 4735 "map": {"at": 165552, "to": "mm"}, 4736 "name": "SPI_PS_INPUT_CNTL_27", 4737 "type_ref": "SPI_PS_INPUT_CNTL_20" 4738 }, 4739 { 4740 "chips": ["gfx9"], 4741 "map": {"at": 165556, "to": "mm"}, 4742 "name": "SPI_PS_INPUT_CNTL_28", 4743 "type_ref": "SPI_PS_INPUT_CNTL_20" 4744 }, 4745 { 4746 "chips": ["gfx9"], 4747 "map": {"at": 165560, "to": "mm"}, 4748 "name": "SPI_PS_INPUT_CNTL_29", 4749 "type_ref": "SPI_PS_INPUT_CNTL_20" 4750 }, 4751 { 4752 "chips": ["gfx9"], 4753 "map": {"at": 165564, "to": "mm"}, 4754 "name": "SPI_PS_INPUT_CNTL_30", 4755 "type_ref": "SPI_PS_INPUT_CNTL_20" 4756 }, 4757 { 4758 "chips": ["gfx9"], 4759 "map": {"at": 165568, "to": "mm"}, 4760 "name": "SPI_PS_INPUT_CNTL_31", 4761 "type_ref": "SPI_PS_INPUT_CNTL_20" 4762 }, 4763 { 4764 "chips": ["gfx9"], 4765 "map": {"at": 165572, "to": "mm"}, 4766 "name": "SPI_VS_OUT_CONFIG", 4767 "type_ref": "SPI_VS_OUT_CONFIG" 4768 }, 4769 { 4770 "chips": ["gfx9"], 4771 "map": {"at": 165580, "to": "mm"}, 4772 "name": "SPI_PS_INPUT_ENA", 4773 "type_ref": "SPI_PS_INPUT_ENA" 4774 }, 4775 { 4776 "chips": ["gfx9"], 4777 "map": {"at": 165584, "to": "mm"}, 4778 "name": "SPI_PS_INPUT_ADDR", 4779 "type_ref": "SPI_PS_INPUT_ENA" 4780 }, 4781 { 4782 "chips": ["gfx9"], 4783 "map": {"at": 165588, "to": "mm"}, 4784 "name": "SPI_INTERP_CONTROL_0", 4785 "type_ref": "SPI_INTERP_CONTROL_0" 4786 }, 4787 { 4788 "chips": ["gfx9"], 4789 "map": {"at": 165592, "to": "mm"}, 4790 "name": "SPI_PS_IN_CONTROL", 4791 "type_ref": "SPI_PS_IN_CONTROL" 4792 }, 4793 { 4794 "chips": ["gfx9"], 4795 "map": {"at": 165600, "to": "mm"}, 4796 "name": "SPI_BARYC_CNTL", 4797 "type_ref": "SPI_BARYC_CNTL" 4798 }, 4799 { 4800 "chips": ["gfx9"], 4801 "map": {"at": 165608, "to": "mm"}, 4802 "name": "SPI_TMPRING_SIZE", 4803 "type_ref": "COMPUTE_TMPRING_SIZE" 4804 }, 4805 { 4806 "chips": ["gfx9"], 4807 "map": {"at": 165644, "to": "mm"}, 4808 "name": "SPI_SHADER_POS_FORMAT", 4809 "type_ref": "SPI_SHADER_POS_FORMAT" 4810 }, 4811 { 4812 "chips": ["gfx9"], 4813 "map": {"at": 165648, "to": "mm"}, 4814 "name": "SPI_SHADER_Z_FORMAT", 4815 "type_ref": "SPI_SHADER_Z_FORMAT" 4816 }, 4817 { 4818 "chips": ["gfx9"], 4819 "map": {"at": 165652, "to": "mm"}, 4820 "name": "SPI_SHADER_COL_FORMAT", 4821 "type_ref": "SPI_SHADER_COL_FORMAT" 4822 }, 4823 { 4824 "chips": ["gfx9"], 4825 "map": {"at": 165716, "to": "mm"}, 4826 "name": "SX_PS_DOWNCONVERT", 4827 "type_ref": "SX_PS_DOWNCONVERT" 4828 }, 4829 { 4830 "chips": ["gfx9"], 4831 "map": {"at": 165720, "to": "mm"}, 4832 "name": "SX_BLEND_OPT_EPSILON", 4833 "type_ref": "SX_BLEND_OPT_EPSILON" 4834 }, 4835 { 4836 "chips": ["gfx9"], 4837 "map": {"at": 165724, "to": "mm"}, 4838 "name": "SX_BLEND_OPT_CONTROL", 4839 "type_ref": "SX_BLEND_OPT_CONTROL" 4840 }, 4841 { 4842 "chips": ["gfx9"], 4843 "map": {"at": 165728, "to": "mm"}, 4844 "name": "SX_MRT0_BLEND_OPT", 4845 "type_ref": "SX_MRT0_BLEND_OPT" 4846 }, 4847 { 4848 "chips": ["gfx9"], 4849 "map": {"at": 165732, "to": "mm"}, 4850 "name": "SX_MRT1_BLEND_OPT", 4851 "type_ref": "SX_MRT0_BLEND_OPT" 4852 }, 4853 { 4854 "chips": ["gfx9"], 4855 "map": {"at": 165736, "to": "mm"}, 4856 "name": "SX_MRT2_BLEND_OPT", 4857 "type_ref": "SX_MRT0_BLEND_OPT" 4858 }, 4859 { 4860 "chips": ["gfx9"], 4861 "map": {"at": 165740, "to": "mm"}, 4862 "name": "SX_MRT3_BLEND_OPT", 4863 "type_ref": "SX_MRT0_BLEND_OPT" 4864 }, 4865 { 4866 "chips": ["gfx9"], 4867 "map": {"at": 165744, "to": "mm"}, 4868 "name": "SX_MRT4_BLEND_OPT", 4869 "type_ref": "SX_MRT0_BLEND_OPT" 4870 }, 4871 { 4872 "chips": ["gfx9"], 4873 "map": {"at": 165748, "to": "mm"}, 4874 "name": "SX_MRT5_BLEND_OPT", 4875 "type_ref": "SX_MRT0_BLEND_OPT" 4876 }, 4877 { 4878 "chips": ["gfx9"], 4879 "map": {"at": 165752, "to": "mm"}, 4880 "name": "SX_MRT6_BLEND_OPT", 4881 "type_ref": "SX_MRT0_BLEND_OPT" 4882 }, 4883 { 4884 "chips": ["gfx9"], 4885 "map": {"at": 165756, "to": "mm"}, 4886 "name": "SX_MRT7_BLEND_OPT", 4887 "type_ref": "SX_MRT0_BLEND_OPT" 4888 }, 4889 { 4890 "chips": ["gfx9"], 4891 "map": {"at": 165760, "to": "mm"}, 4892 "name": "CB_BLEND0_CONTROL", 4893 "type_ref": "CB_BLEND0_CONTROL" 4894 }, 4895 { 4896 "chips": ["gfx9"], 4897 "map": {"at": 165764, "to": "mm"}, 4898 "name": "CB_BLEND1_CONTROL", 4899 "type_ref": "CB_BLEND0_CONTROL" 4900 }, 4901 { 4902 "chips": ["gfx9"], 4903 "map": {"at": 165768, "to": "mm"}, 4904 "name": "CB_BLEND2_CONTROL", 4905 "type_ref": "CB_BLEND0_CONTROL" 4906 }, 4907 { 4908 "chips": ["gfx9"], 4909 "map": {"at": 165772, "to": "mm"}, 4910 "name": "CB_BLEND3_CONTROL", 4911 "type_ref": "CB_BLEND0_CONTROL" 4912 }, 4913 { 4914 "chips": ["gfx9"], 4915 "map": {"at": 165776, "to": "mm"}, 4916 "name": "CB_BLEND4_CONTROL", 4917 "type_ref": "CB_BLEND0_CONTROL" 4918 }, 4919 { 4920 "chips": ["gfx9"], 4921 "map": {"at": 165780, "to": "mm"}, 4922 "name": "CB_BLEND5_CONTROL", 4923 "type_ref": "CB_BLEND0_CONTROL" 4924 }, 4925 { 4926 "chips": ["gfx9"], 4927 "map": {"at": 165784, "to": "mm"}, 4928 "name": "CB_BLEND6_CONTROL", 4929 "type_ref": "CB_BLEND0_CONTROL" 4930 }, 4931 { 4932 "chips": ["gfx9"], 4933 "map": {"at": 165788, "to": "mm"}, 4934 "name": "CB_BLEND7_CONTROL", 4935 "type_ref": "CB_BLEND0_CONTROL" 4936 }, 4937 { 4938 "chips": ["gfx9"], 4939 "map": {"at": 165792, "to": "mm"}, 4940 "name": "CB_MRT0_EPITCH", 4941 "type_ref": "DB_Z_INFO2" 4942 }, 4943 { 4944 "chips": ["gfx9"], 4945 "map": {"at": 165796, "to": "mm"}, 4946 "name": "CB_MRT1_EPITCH", 4947 "type_ref": "DB_Z_INFO2" 4948 }, 4949 { 4950 "chips": ["gfx9"], 4951 "map": {"at": 165800, "to": "mm"}, 4952 "name": "CB_MRT2_EPITCH", 4953 "type_ref": "DB_Z_INFO2" 4954 }, 4955 { 4956 "chips": ["gfx9"], 4957 "map": {"at": 165804, "to": "mm"}, 4958 "name": "CB_MRT3_EPITCH", 4959 "type_ref": "DB_Z_INFO2" 4960 }, 4961 { 4962 "chips": ["gfx9"], 4963 "map": {"at": 165808, "to": "mm"}, 4964 "name": "CB_MRT4_EPITCH", 4965 "type_ref": "DB_Z_INFO2" 4966 }, 4967 { 4968 "chips": ["gfx9"], 4969 "map": {"at": 165812, "to": "mm"}, 4970 "name": "CB_MRT5_EPITCH", 4971 "type_ref": "DB_Z_INFO2" 4972 }, 4973 { 4974 "chips": ["gfx9"], 4975 "map": {"at": 165816, "to": "mm"}, 4976 "name": "CB_MRT6_EPITCH", 4977 "type_ref": "DB_Z_INFO2" 4978 }, 4979 { 4980 "chips": ["gfx9"], 4981 "map": {"at": 165820, "to": "mm"}, 4982 "name": "CB_MRT7_EPITCH", 4983 "type_ref": "DB_Z_INFO2" 4984 }, 4985 { 4986 "chips": ["gfx9"], 4987 "map": {"at": 165836, "to": "mm"}, 4988 "name": "CS_COPY_STATE", 4989 "type_ref": "CS_COPY_STATE" 4990 }, 4991 { 4992 "chips": ["gfx9"], 4993 "map": {"at": 165840, "to": "mm"}, 4994 "name": "GFX_COPY_STATE", 4995 "type_ref": "CS_COPY_STATE" 4996 }, 4997 { 4998 "chips": ["gfx9"], 4999 "map": {"at": 165844, "to": "mm"}, 5000 "name": "PA_CL_POINT_X_RAD" 5001 }, 5002 { 5003 "chips": ["gfx9"], 5004 "map": {"at": 165848, "to": "mm"}, 5005 "name": "PA_CL_POINT_Y_RAD" 5006 }, 5007 { 5008 "chips": ["gfx9"], 5009 "map": {"at": 165852, "to": "mm"}, 5010 "name": "PA_CL_POINT_SIZE" 5011 }, 5012 { 5013 "chips": ["gfx9"], 5014 "map": {"at": 165856, "to": "mm"}, 5015 "name": "PA_CL_POINT_CULL_RAD" 5016 }, 5017 { 5018 "chips": ["gfx9"], 5019 "map": {"at": 165860, "to": "mm"}, 5020 "name": "VGT_DMA_BASE_HI", 5021 "type_ref": "VGT_DMA_BASE_HI" 5022 }, 5023 { 5024 "chips": ["gfx9"], 5025 "map": {"at": 165864, "to": "mm"}, 5026 "name": "VGT_DMA_BASE" 5027 }, 5028 { 5029 "chips": ["gfx9"], 5030 "map": {"at": 165872, "to": "mm"}, 5031 "name": "VGT_DRAW_INITIATOR", 5032 "type_ref": "VGT_DRAW_INITIATOR" 5033 }, 5034 { 5035 "chips": ["gfx9"], 5036 "map": {"at": 165876, "to": "mm"}, 5037 "name": "VGT_IMMED_DATA" 5038 }, 5039 { 5040 "chips": ["gfx9"], 5041 "map": {"at": 165880, "to": "mm"}, 5042 "name": "VGT_EVENT_ADDRESS_REG", 5043 "type_ref": "VGT_EVENT_ADDRESS_REG" 5044 }, 5045 { 5046 "chips": ["gfx9"], 5047 "map": {"at": 165888, "to": "mm"}, 5048 "name": "DB_DEPTH_CONTROL", 5049 "type_ref": "DB_DEPTH_CONTROL" 5050 }, 5051 { 5052 "chips": ["gfx9"], 5053 "map": {"at": 165892, "to": "mm"}, 5054 "name": "DB_EQAA", 5055 "type_ref": "DB_EQAA" 5056 }, 5057 { 5058 "chips": ["gfx9"], 5059 "map": {"at": 165896, "to": "mm"}, 5060 "name": "CB_COLOR_CONTROL", 5061 "type_ref": "CB_COLOR_CONTROL" 5062 }, 5063 { 5064 "chips": ["gfx9"], 5065 "map": {"at": 165900, "to": "mm"}, 5066 "name": "DB_SHADER_CONTROL", 5067 "type_ref": "DB_SHADER_CONTROL" 5068 }, 5069 { 5070 "chips": ["gfx9"], 5071 "map": {"at": 165904, "to": "mm"}, 5072 "name": "PA_CL_CLIP_CNTL", 5073 "type_ref": "PA_CL_CLIP_CNTL" 5074 }, 5075 { 5076 "chips": ["gfx9"], 5077 "map": {"at": 165908, "to": "mm"}, 5078 "name": "PA_SU_SC_MODE_CNTL", 5079 "type_ref": "PA_SU_SC_MODE_CNTL" 5080 }, 5081 { 5082 "chips": ["gfx9"], 5083 "map": {"at": 165912, "to": "mm"}, 5084 "name": "PA_CL_VTE_CNTL", 5085 "type_ref": "PA_CL_VTE_CNTL" 5086 }, 5087 { 5088 "chips": ["gfx9"], 5089 "map": {"at": 165916, "to": "mm"}, 5090 "name": "PA_CL_VS_OUT_CNTL", 5091 "type_ref": "PA_CL_VS_OUT_CNTL" 5092 }, 5093 { 5094 "chips": ["gfx9"], 5095 "map": {"at": 165920, "to": "mm"}, 5096 "name": "PA_CL_NANINF_CNTL", 5097 "type_ref": "PA_CL_NANINF_CNTL" 5098 }, 5099 { 5100 "chips": ["gfx9"], 5101 "map": {"at": 165924, "to": "mm"}, 5102 "name": "PA_SU_LINE_STIPPLE_CNTL", 5103 "type_ref": "PA_SU_LINE_STIPPLE_CNTL" 5104 }, 5105 { 5106 "chips": ["gfx9"], 5107 "map": {"at": 165928, "to": "mm"}, 5108 "name": "PA_SU_LINE_STIPPLE_SCALE" 5109 }, 5110 { 5111 "chips": ["gfx9"], 5112 "map": {"at": 165932, "to": "mm"}, 5113 "name": "PA_SU_PRIM_FILTER_CNTL", 5114 "type_ref": "PA_SU_PRIM_FILTER_CNTL" 5115 }, 5116 { 5117 "chips": ["gfx9"], 5118 "map": {"at": 165936, "to": "mm"}, 5119 "name": "PA_SU_SMALL_PRIM_FILTER_CNTL", 5120 "type_ref": "PA_SU_SMALL_PRIM_FILTER_CNTL" 5121 }, 5122 { 5123 "chips": ["gfx9"], 5124 "map": {"at": 165940, "to": "mm"}, 5125 "name": "PA_CL_OBJPRIM_ID_CNTL", 5126 "type_ref": "PA_CL_OBJPRIM_ID_CNTL" 5127 }, 5128 { 5129 "chips": ["gfx9"], 5130 "map": {"at": 165944, "to": "mm"}, 5131 "name": "PA_CL_NGG_CNTL", 5132 "type_ref": "PA_CL_NGG_CNTL" 5133 }, 5134 { 5135 "chips": ["gfx9"], 5136 "map": {"at": 165948, "to": "mm"}, 5137 "name": "PA_SU_OVER_RASTERIZATION_CNTL", 5138 "type_ref": "PA_SU_OVER_RASTERIZATION_CNTL" 5139 }, 5140 { 5141 "chips": ["gfx9"], 5142 "map": {"at": 165952, "to": "mm"}, 5143 "name": "PA_STEREO_CNTL", 5144 "type_ref": "PA_STEREO_CNTL" 5145 }, 5146 { 5147 "chips": ["gfx9"], 5148 "map": {"at": 166400, "to": "mm"}, 5149 "name": "PA_SU_POINT_SIZE", 5150 "type_ref": "PA_SU_POINT_SIZE" 5151 }, 5152 { 5153 "chips": ["gfx9"], 5154 "map": {"at": 166404, "to": "mm"}, 5155 "name": "PA_SU_POINT_MINMAX", 5156 "type_ref": "PA_SU_POINT_MINMAX" 5157 }, 5158 { 5159 "chips": ["gfx9"], 5160 "map": {"at": 166408, "to": "mm"}, 5161 "name": "PA_SU_LINE_CNTL", 5162 "type_ref": "PA_SU_LINE_CNTL" 5163 }, 5164 { 5165 "chips": ["gfx9"], 5166 "map": {"at": 166412, "to": "mm"}, 5167 "name": "PA_SC_LINE_STIPPLE", 5168 "type_ref": "PA_SC_LINE_STIPPLE" 5169 }, 5170 { 5171 "chips": ["gfx9"], 5172 "map": {"at": 166416, "to": "mm"}, 5173 "name": "VGT_OUTPUT_PATH_CNTL", 5174 "type_ref": "VGT_OUTPUT_PATH_CNTL" 5175 }, 5176 { 5177 "chips": ["gfx9"], 5178 "map": {"at": 166420, "to": "mm"}, 5179 "name": "VGT_HOS_CNTL", 5180 "type_ref": "VGT_HOS_CNTL" 5181 }, 5182 { 5183 "chips": ["gfx9"], 5184 "map": {"at": 166424, "to": "mm"}, 5185 "name": "VGT_HOS_MAX_TESS_LEVEL" 5186 }, 5187 { 5188 "chips": ["gfx9"], 5189 "map": {"at": 166428, "to": "mm"}, 5190 "name": "VGT_HOS_MIN_TESS_LEVEL" 5191 }, 5192 { 5193 "chips": ["gfx9"], 5194 "map": {"at": 166432, "to": "mm"}, 5195 "name": "VGT_HOS_REUSE_DEPTH", 5196 "type_ref": "VGT_HOS_REUSE_DEPTH" 5197 }, 5198 { 5199 "chips": ["gfx9"], 5200 "map": {"at": 166436, "to": "mm"}, 5201 "name": "VGT_GROUP_PRIM_TYPE", 5202 "type_ref": "VGT_GROUP_PRIM_TYPE" 5203 }, 5204 { 5205 "chips": ["gfx9"], 5206 "map": {"at": 166440, "to": "mm"}, 5207 "name": "VGT_GROUP_FIRST_DECR", 5208 "type_ref": "VGT_GROUP_FIRST_DECR" 5209 }, 5210 { 5211 "chips": ["gfx9"], 5212 "map": {"at": 166444, "to": "mm"}, 5213 "name": "VGT_GROUP_DECR", 5214 "type_ref": "VGT_GROUP_DECR" 5215 }, 5216 { 5217 "chips": ["gfx9"], 5218 "map": {"at": 166448, "to": "mm"}, 5219 "name": "VGT_GROUP_VECT_0_CNTL", 5220 "type_ref": "VGT_GROUP_VECT_0_CNTL" 5221 }, 5222 { 5223 "chips": ["gfx9"], 5224 "map": {"at": 166452, "to": "mm"}, 5225 "name": "VGT_GROUP_VECT_1_CNTL", 5226 "type_ref": "VGT_GROUP_VECT_0_CNTL" 5227 }, 5228 { 5229 "chips": ["gfx9"], 5230 "map": {"at": 166456, "to": "mm"}, 5231 "name": "VGT_GROUP_VECT_0_FMT_CNTL", 5232 "type_ref": "VGT_GROUP_VECT_0_FMT_CNTL" 5233 }, 5234 { 5235 "chips": ["gfx9"], 5236 "map": {"at": 166460, "to": "mm"}, 5237 "name": "VGT_GROUP_VECT_1_FMT_CNTL", 5238 "type_ref": "VGT_GROUP_VECT_0_FMT_CNTL" 5239 }, 5240 { 5241 "chips": ["gfx9"], 5242 "map": {"at": 166464, "to": "mm"}, 5243 "name": "VGT_GS_MODE", 5244 "type_ref": "VGT_GS_MODE" 5245 }, 5246 { 5247 "chips": ["gfx9"], 5248 "map": {"at": 166468, "to": "mm"}, 5249 "name": "VGT_GS_ONCHIP_CNTL", 5250 "type_ref": "VGT_GS_ONCHIP_CNTL" 5251 }, 5252 { 5253 "chips": ["gfx9"], 5254 "map": {"at": 166472, "to": "mm"}, 5255 "name": "PA_SC_MODE_CNTL_0", 5256 "type_ref": "PA_SC_MODE_CNTL_0" 5257 }, 5258 { 5259 "chips": ["gfx9"], 5260 "map": {"at": 166476, "to": "mm"}, 5261 "name": "PA_SC_MODE_CNTL_1", 5262 "type_ref": "PA_SC_MODE_CNTL_1" 5263 }, 5264 { 5265 "chips": ["gfx9"], 5266 "map": {"at": 166480, "to": "mm"}, 5267 "name": "VGT_ENHANCE" 5268 }, 5269 { 5270 "chips": ["gfx9"], 5271 "map": {"at": 166484, "to": "mm"}, 5272 "name": "VGT_GS_PER_ES", 5273 "type_ref": "VGT_GS_PER_ES" 5274 }, 5275 { 5276 "chips": ["gfx9"], 5277 "map": {"at": 166488, "to": "mm"}, 5278 "name": "VGT_ES_PER_GS", 5279 "type_ref": "VGT_ES_PER_GS" 5280 }, 5281 { 5282 "chips": ["gfx9"], 5283 "map": {"at": 166492, "to": "mm"}, 5284 "name": "VGT_GS_PER_VS", 5285 "type_ref": "VGT_GS_PER_VS" 5286 }, 5287 { 5288 "chips": ["gfx9"], 5289 "map": {"at": 166496, "to": "mm"}, 5290 "name": "VGT_GSVS_RING_OFFSET_1", 5291 "type_ref": "VGT_GSVS_RING_OFFSET_1" 5292 }, 5293 { 5294 "chips": ["gfx9"], 5295 "map": {"at": 166500, "to": "mm"}, 5296 "name": "VGT_GSVS_RING_OFFSET_2", 5297 "type_ref": "VGT_GSVS_RING_OFFSET_1" 5298 }, 5299 { 5300 "chips": ["gfx9"], 5301 "map": {"at": 166504, "to": "mm"}, 5302 "name": "VGT_GSVS_RING_OFFSET_3", 5303 "type_ref": "VGT_GSVS_RING_OFFSET_1" 5304 }, 5305 { 5306 "chips": ["gfx9"], 5307 "map": {"at": 166508, "to": "mm"}, 5308 "name": "VGT_GS_OUT_PRIM_TYPE", 5309 "type_ref": "VGT_GS_OUT_PRIM_TYPE" 5310 }, 5311 { 5312 "chips": ["gfx9"], 5313 "map": {"at": 166512, "to": "mm"}, 5314 "name": "IA_ENHANCE" 5315 }, 5316 { 5317 "chips": ["gfx9"], 5318 "map": {"at": 166516, "to": "mm"}, 5319 "name": "VGT_DMA_SIZE" 5320 }, 5321 { 5322 "chips": ["gfx9"], 5323 "map": {"at": 166520, "to": "mm"}, 5324 "name": "VGT_DMA_MAX_SIZE" 5325 }, 5326 { 5327 "chips": ["gfx9"], 5328 "map": {"at": 166524, "to": "mm"}, 5329 "name": "VGT_DMA_INDEX_TYPE", 5330 "type_ref": "VGT_DMA_INDEX_TYPE" 5331 }, 5332 { 5333 "chips": ["gfx9"], 5334 "map": {"at": 166528, "to": "mm"}, 5335 "name": "WD_ENHANCE" 5336 }, 5337 { 5338 "chips": ["gfx9"], 5339 "map": {"at": 166532, "to": "mm"}, 5340 "name": "VGT_PRIMITIVEID_EN", 5341 "type_ref": "VGT_PRIMITIVEID_EN" 5342 }, 5343 { 5344 "chips": ["gfx9"], 5345 "map": {"at": 166536, "to": "mm"}, 5346 "name": "VGT_DMA_NUM_INSTANCES" 5347 }, 5348 { 5349 "chips": ["gfx9"], 5350 "map": {"at": 166540, "to": "mm"}, 5351 "name": "VGT_PRIMITIVEID_RESET" 5352 }, 5353 { 5354 "chips": ["gfx9"], 5355 "map": {"at": 166544, "to": "mm"}, 5356 "name": "VGT_EVENT_INITIATOR", 5357 "type_ref": "VGT_EVENT_INITIATOR" 5358 }, 5359 { 5360 "chips": ["gfx9"], 5361 "map": {"at": 166548, "to": "mm"}, 5362 "name": "VGT_GS_MAX_PRIMS_PER_SUBGROUP", 5363 "type_ref": "VGT_GS_MAX_PRIMS_PER_SUBGROUP" 5364 }, 5365 { 5366 "chips": ["gfx9"], 5367 "map": {"at": 166552, "to": "mm"}, 5368 "name": "VGT_DRAW_PAYLOAD_CNTL", 5369 "type_ref": "VGT_DRAW_PAYLOAD_CNTL" 5370 }, 5371 { 5372 "chips": ["gfx9"], 5373 "map": {"at": 166560, "to": "mm"}, 5374 "name": "VGT_INSTANCE_STEP_RATE_0" 5375 }, 5376 { 5377 "chips": ["gfx9"], 5378 "map": {"at": 166564, "to": "mm"}, 5379 "name": "VGT_INSTANCE_STEP_RATE_1" 5380 }, 5381 { 5382 "chips": ["gfx9"], 5383 "map": {"at": 166572, "to": "mm"}, 5384 "name": "VGT_ESGS_RING_ITEMSIZE", 5385 "type_ref": "VGT_ESGS_RING_ITEMSIZE" 5386 }, 5387 { 5388 "chips": ["gfx9"], 5389 "map": {"at": 166576, "to": "mm"}, 5390 "name": "VGT_GSVS_RING_ITEMSIZE", 5391 "type_ref": "VGT_ESGS_RING_ITEMSIZE" 5392 }, 5393 { 5394 "chips": ["gfx9"], 5395 "map": {"at": 166580, "to": "mm"}, 5396 "name": "VGT_REUSE_OFF", 5397 "type_ref": "VGT_REUSE_OFF" 5398 }, 5399 { 5400 "chips": ["gfx9"], 5401 "map": {"at": 166584, "to": "mm"}, 5402 "name": "VGT_VTX_CNT_EN", 5403 "type_ref": "VGT_VTX_CNT_EN" 5404 }, 5405 { 5406 "chips": ["gfx9"], 5407 "map": {"at": 166588, "to": "mm"}, 5408 "name": "DB_HTILE_SURFACE", 5409 "type_ref": "DB_HTILE_SURFACE" 5410 }, 5411 { 5412 "chips": ["gfx9"], 5413 "map": {"at": 166592, "to": "mm"}, 5414 "name": "DB_SRESULTS_COMPARE_STATE0", 5415 "type_ref": "DB_SRESULTS_COMPARE_STATE0" 5416 }, 5417 { 5418 "chips": ["gfx9"], 5419 "map": {"at": 166596, "to": "mm"}, 5420 "name": "DB_SRESULTS_COMPARE_STATE1", 5421 "type_ref": "DB_SRESULTS_COMPARE_STATE1" 5422 }, 5423 { 5424 "chips": ["gfx9"], 5425 "map": {"at": 166600, "to": "mm"}, 5426 "name": "DB_PRELOAD_CONTROL", 5427 "type_ref": "DB_PRELOAD_CONTROL" 5428 }, 5429 { 5430 "chips": ["gfx9"], 5431 "map": {"at": 166608, "to": "mm"}, 5432 "name": "VGT_STRMOUT_BUFFER_SIZE_0" 5433 }, 5434 { 5435 "chips": ["gfx9"], 5436 "map": {"at": 166612, "to": "mm"}, 5437 "name": "VGT_STRMOUT_VTX_STRIDE_0", 5438 "type_ref": "VGT_STRMOUT_VTX_STRIDE_0" 5439 }, 5440 { 5441 "chips": ["gfx9"], 5442 "map": {"at": 166620, "to": "mm"}, 5443 "name": "VGT_STRMOUT_BUFFER_OFFSET_0" 5444 }, 5445 { 5446 "chips": ["gfx9"], 5447 "map": {"at": 166624, "to": "mm"}, 5448 "name": "VGT_STRMOUT_BUFFER_SIZE_1" 5449 }, 5450 { 5451 "chips": ["gfx9"], 5452 "map": {"at": 166628, "to": "mm"}, 5453 "name": "VGT_STRMOUT_VTX_STRIDE_1", 5454 "type_ref": "VGT_STRMOUT_VTX_STRIDE_0" 5455 }, 5456 { 5457 "chips": ["gfx9"], 5458 "map": {"at": 166636, "to": "mm"}, 5459 "name": "VGT_STRMOUT_BUFFER_OFFSET_1" 5460 }, 5461 { 5462 "chips": ["gfx9"], 5463 "map": {"at": 166640, "to": "mm"}, 5464 "name": "VGT_STRMOUT_BUFFER_SIZE_2" 5465 }, 5466 { 5467 "chips": ["gfx9"], 5468 "map": {"at": 166644, "to": "mm"}, 5469 "name": "VGT_STRMOUT_VTX_STRIDE_2", 5470 "type_ref": "VGT_STRMOUT_VTX_STRIDE_0" 5471 }, 5472 { 5473 "chips": ["gfx9"], 5474 "map": {"at": 166652, "to": "mm"}, 5475 "name": "VGT_STRMOUT_BUFFER_OFFSET_2" 5476 }, 5477 { 5478 "chips": ["gfx9"], 5479 "map": {"at": 166656, "to": "mm"}, 5480 "name": "VGT_STRMOUT_BUFFER_SIZE_3" 5481 }, 5482 { 5483 "chips": ["gfx9"], 5484 "map": {"at": 166660, "to": "mm"}, 5485 "name": "VGT_STRMOUT_VTX_STRIDE_3", 5486 "type_ref": "VGT_STRMOUT_VTX_STRIDE_0" 5487 }, 5488 { 5489 "chips": ["gfx9"], 5490 "map": {"at": 166668, "to": "mm"}, 5491 "name": "VGT_STRMOUT_BUFFER_OFFSET_3" 5492 }, 5493 { 5494 "chips": ["gfx9"], 5495 "map": {"at": 166696, "to": "mm"}, 5496 "name": "VGT_STRMOUT_DRAW_OPAQUE_OFFSET" 5497 }, 5498 { 5499 "chips": ["gfx9"], 5500 "map": {"at": 166700, "to": "mm"}, 5501 "name": "VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE" 5502 }, 5503 { 5504 "chips": ["gfx9"], 5505 "map": {"at": 166704, "to": "mm"}, 5506 "name": "VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE", 5507 "type_ref": "VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE" 5508 }, 5509 { 5510 "chips": ["gfx9"], 5511 "map": {"at": 166712, "to": "mm"}, 5512 "name": "VGT_GS_MAX_VERT_OUT", 5513 "type_ref": "VGT_GS_MAX_VERT_OUT" 5514 }, 5515 { 5516 "chips": ["gfx9"], 5517 "map": {"at": 166736, "to": "mm"}, 5518 "name": "VGT_TESS_DISTRIBUTION", 5519 "type_ref": "VGT_TESS_DISTRIBUTION" 5520 }, 5521 { 5522 "chips": ["gfx9"], 5523 "map": {"at": 166740, "to": "mm"}, 5524 "name": "VGT_SHADER_STAGES_EN", 5525 "type_ref": "VGT_SHADER_STAGES_EN" 5526 }, 5527 { 5528 "chips": ["gfx9"], 5529 "map": {"at": 166744, "to": "mm"}, 5530 "name": "VGT_LS_HS_CONFIG", 5531 "type_ref": "VGT_LS_HS_CONFIG" 5532 }, 5533 { 5534 "chips": ["gfx9"], 5535 "map": {"at": 166748, "to": "mm"}, 5536 "name": "VGT_GS_VERT_ITEMSIZE", 5537 "type_ref": "VGT_ESGS_RING_ITEMSIZE" 5538 }, 5539 { 5540 "chips": ["gfx9"], 5541 "map": {"at": 166752, "to": "mm"}, 5542 "name": "VGT_GS_VERT_ITEMSIZE_1", 5543 "type_ref": "VGT_ESGS_RING_ITEMSIZE" 5544 }, 5545 { 5546 "chips": ["gfx9"], 5547 "map": {"at": 166756, "to": "mm"}, 5548 "name": "VGT_GS_VERT_ITEMSIZE_2", 5549 "type_ref": "VGT_ESGS_RING_ITEMSIZE" 5550 }, 5551 { 5552 "chips": ["gfx9"], 5553 "map": {"at": 166760, "to": "mm"}, 5554 "name": "VGT_GS_VERT_ITEMSIZE_3", 5555 "type_ref": "VGT_ESGS_RING_ITEMSIZE" 5556 }, 5557 { 5558 "chips": ["gfx9"], 5559 "map": {"at": 166764, "to": "mm"}, 5560 "name": "VGT_TF_PARAM", 5561 "type_ref": "VGT_TF_PARAM" 5562 }, 5563 { 5564 "chips": ["gfx9"], 5565 "map": {"at": 166768, "to": "mm"}, 5566 "name": "DB_ALPHA_TO_MASK", 5567 "type_ref": "DB_ALPHA_TO_MASK" 5568 }, 5569 { 5570 "chips": ["gfx9"], 5571 "map": {"at": 166772, "to": "mm"}, 5572 "name": "VGT_DISPATCH_DRAW_INDEX" 5573 }, 5574 { 5575 "chips": ["gfx9"], 5576 "map": {"at": 166776, "to": "mm"}, 5577 "name": "PA_SU_POLY_OFFSET_DB_FMT_CNTL", 5578 "type_ref": "PA_SU_POLY_OFFSET_DB_FMT_CNTL" 5579 }, 5580 { 5581 "chips": ["gfx9"], 5582 "map": {"at": 166780, "to": "mm"}, 5583 "name": "PA_SU_POLY_OFFSET_CLAMP" 5584 }, 5585 { 5586 "chips": ["gfx9"], 5587 "map": {"at": 166784, "to": "mm"}, 5588 "name": "PA_SU_POLY_OFFSET_FRONT_SCALE" 5589 }, 5590 { 5591 "chips": ["gfx9"], 5592 "map": {"at": 166788, "to": "mm"}, 5593 "name": "PA_SU_POLY_OFFSET_FRONT_OFFSET" 5594 }, 5595 { 5596 "chips": ["gfx9"], 5597 "map": {"at": 166792, "to": "mm"}, 5598 "name": "PA_SU_POLY_OFFSET_BACK_SCALE" 5599 }, 5600 { 5601 "chips": ["gfx9"], 5602 "map": {"at": 166796, "to": "mm"}, 5603 "name": "PA_SU_POLY_OFFSET_BACK_OFFSET" 5604 }, 5605 { 5606 "chips": ["gfx9"], 5607 "map": {"at": 166800, "to": "mm"}, 5608 "name": "VGT_GS_INSTANCE_CNT", 5609 "type_ref": "VGT_GS_INSTANCE_CNT" 5610 }, 5611 { 5612 "chips": ["gfx9"], 5613 "map": {"at": 166804, "to": "mm"}, 5614 "name": "VGT_STRMOUT_CONFIG", 5615 "type_ref": "VGT_STRMOUT_CONFIG" 5616 }, 5617 { 5618 "chips": ["gfx9"], 5619 "map": {"at": 166808, "to": "mm"}, 5620 "name": "VGT_STRMOUT_BUFFER_CONFIG", 5621 "type_ref": "VGT_STRMOUT_BUFFER_CONFIG" 5622 }, 5623 { 5624 "chips": ["gfx9"], 5625 "map": {"at": 166812, "to": "mm"}, 5626 "name": "VGT_DMA_EVENT_INITIATOR", 5627 "type_ref": "VGT_EVENT_INITIATOR" 5628 }, 5629 { 5630 "chips": ["gfx9"], 5631 "map": {"at": 166868, "to": "mm"}, 5632 "name": "PA_SC_CENTROID_PRIORITY_0", 5633 "type_ref": "PA_SC_CENTROID_PRIORITY_0" 5634 }, 5635 { 5636 "chips": ["gfx9"], 5637 "map": {"at": 166872, "to": "mm"}, 5638 "name": "PA_SC_CENTROID_PRIORITY_1", 5639 "type_ref": "PA_SC_CENTROID_PRIORITY_1" 5640 }, 5641 { 5642 "chips": ["gfx9"], 5643 "map": {"at": 166876, "to": "mm"}, 5644 "name": "PA_SC_LINE_CNTL", 5645 "type_ref": "PA_SC_LINE_CNTL" 5646 }, 5647 { 5648 "chips": ["gfx9"], 5649 "map": {"at": 166880, "to": "mm"}, 5650 "name": "PA_SC_AA_CONFIG", 5651 "type_ref": "PA_SC_AA_CONFIG" 5652 }, 5653 { 5654 "chips": ["gfx9"], 5655 "map": {"at": 166884, "to": "mm"}, 5656 "name": "PA_SU_VTX_CNTL", 5657 "type_ref": "PA_SU_VTX_CNTL" 5658 }, 5659 { 5660 "chips": ["gfx9"], 5661 "map": {"at": 166888, "to": "mm"}, 5662 "name": "PA_CL_GB_VERT_CLIP_ADJ" 5663 }, 5664 { 5665 "chips": ["gfx9"], 5666 "map": {"at": 166892, "to": "mm"}, 5667 "name": "PA_CL_GB_VERT_DISC_ADJ" 5668 }, 5669 { 5670 "chips": ["gfx9"], 5671 "map": {"at": 166896, "to": "mm"}, 5672 "name": "PA_CL_GB_HORZ_CLIP_ADJ" 5673 }, 5674 { 5675 "chips": ["gfx9"], 5676 "map": {"at": 166900, "to": "mm"}, 5677 "name": "PA_CL_GB_HORZ_DISC_ADJ" 5678 }, 5679 { 5680 "chips": ["gfx9"], 5681 "map": {"at": 166904, "to": "mm"}, 5682 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0", 5683 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0" 5684 }, 5685 { 5686 "chips": ["gfx9"], 5687 "map": {"at": 166908, "to": "mm"}, 5688 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1", 5689 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1" 5690 }, 5691 { 5692 "chips": ["gfx9"], 5693 "map": {"at": 166912, "to": "mm"}, 5694 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2", 5695 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2" 5696 }, 5697 { 5698 "chips": ["gfx9"], 5699 "map": {"at": 166916, "to": "mm"}, 5700 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3", 5701 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3" 5702 }, 5703 { 5704 "chips": ["gfx9"], 5705 "map": {"at": 166920, "to": "mm"}, 5706 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0", 5707 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0" 5708 }, 5709 { 5710 "chips": ["gfx9"], 5711 "map": {"at": 166924, "to": "mm"}, 5712 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1", 5713 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1" 5714 }, 5715 { 5716 "chips": ["gfx9"], 5717 "map": {"at": 166928, "to": "mm"}, 5718 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2", 5719 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2" 5720 }, 5721 { 5722 "chips": ["gfx9"], 5723 "map": {"at": 166932, "to": "mm"}, 5724 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3", 5725 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3" 5726 }, 5727 { 5728 "chips": ["gfx9"], 5729 "map": {"at": 166936, "to": "mm"}, 5730 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0", 5731 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0" 5732 }, 5733 { 5734 "chips": ["gfx9"], 5735 "map": {"at": 166940, "to": "mm"}, 5736 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1", 5737 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1" 5738 }, 5739 { 5740 "chips": ["gfx9"], 5741 "map": {"at": 166944, "to": "mm"}, 5742 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2", 5743 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2" 5744 }, 5745 { 5746 "chips": ["gfx9"], 5747 "map": {"at": 166948, "to": "mm"}, 5748 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3", 5749 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3" 5750 }, 5751 { 5752 "chips": ["gfx9"], 5753 "map": {"at": 166952, "to": "mm"}, 5754 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0", 5755 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0" 5756 }, 5757 { 5758 "chips": ["gfx9"], 5759 "map": {"at": 166956, "to": "mm"}, 5760 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1", 5761 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1" 5762 }, 5763 { 5764 "chips": ["gfx9"], 5765 "map": {"at": 166960, "to": "mm"}, 5766 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2", 5767 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2" 5768 }, 5769 { 5770 "chips": ["gfx9"], 5771 "map": {"at": 166964, "to": "mm"}, 5772 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3", 5773 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3" 5774 }, 5775 { 5776 "chips": ["gfx9"], 5777 "map": {"at": 166968, "to": "mm"}, 5778 "name": "PA_SC_AA_MASK_X0Y0_X1Y0", 5779 "type_ref": "PA_SC_AA_MASK_X0Y0_X1Y0" 5780 }, 5781 { 5782 "chips": ["gfx9"], 5783 "map": {"at": 166972, "to": "mm"}, 5784 "name": "PA_SC_AA_MASK_X0Y1_X1Y1", 5785 "type_ref": "PA_SC_AA_MASK_X0Y1_X1Y1" 5786 }, 5787 { 5788 "chips": ["gfx9"], 5789 "map": {"at": 166976, "to": "mm"}, 5790 "name": "PA_SC_SHADER_CONTROL", 5791 "type_ref": "PA_SC_SHADER_CONTROL" 5792 }, 5793 { 5794 "chips": ["gfx9"], 5795 "map": {"at": 166980, "to": "mm"}, 5796 "name": "PA_SC_BINNER_CNTL_0", 5797 "type_ref": "PA_SC_BINNER_CNTL_0" 5798 }, 5799 { 5800 "chips": ["gfx9"], 5801 "map": {"at": 166984, "to": "mm"}, 5802 "name": "PA_SC_BINNER_CNTL_1", 5803 "type_ref": "PA_SC_BINNER_CNTL_1" 5804 }, 5805 { 5806 "chips": ["gfx9"], 5807 "map": {"at": 166988, "to": "mm"}, 5808 "name": "PA_SC_CONSERVATIVE_RASTERIZATION_CNTL", 5809 "type_ref": "PA_SC_CONSERVATIVE_RASTERIZATION_CNTL" 5810 }, 5811 { 5812 "chips": ["gfx9"], 5813 "map": {"at": 166992, "to": "mm"}, 5814 "name": "PA_SC_NGG_MODE_CNTL", 5815 "type_ref": "PA_SC_NGG_MODE_CNTL" 5816 }, 5817 { 5818 "chips": ["gfx9"], 5819 "map": {"at": 167000, "to": "mm"}, 5820 "name": "VGT_VERTEX_REUSE_BLOCK_CNTL", 5821 "type_ref": "VGT_VERTEX_REUSE_BLOCK_CNTL" 5822 }, 5823 { 5824 "chips": ["gfx9"], 5825 "map": {"at": 167004, "to": "mm"}, 5826 "name": "VGT_OUT_DEALLOC_CNTL", 5827 "type_ref": "VGT_OUT_DEALLOC_CNTL" 5828 }, 5829 { 5830 "chips": ["gfx9"], 5831 "map": {"at": 167008, "to": "mm"}, 5832 "name": "CB_COLOR0_BASE" 5833 }, 5834 { 5835 "chips": ["gfx9"], 5836 "map": {"at": 167012, "to": "mm"}, 5837 "name": "CB_COLOR0_BASE_EXT", 5838 "type_ref": "CB_COLOR0_BASE_EXT" 5839 }, 5840 { 5841 "chips": ["gfx9"], 5842 "map": {"at": 167016, "to": "mm"}, 5843 "name": "CB_COLOR0_ATTRIB2", 5844 "type_ref": "CB_COLOR0_ATTRIB2" 5845 }, 5846 { 5847 "chips": ["gfx9"], 5848 "map": {"at": 167020, "to": "mm"}, 5849 "name": "CB_COLOR0_VIEW", 5850 "type_ref": "CB_COLOR0_VIEW" 5851 }, 5852 { 5853 "chips": ["gfx9"], 5854 "map": {"at": 167024, "to": "mm"}, 5855 "name": "CB_COLOR0_INFO", 5856 "type_ref": "CB_COLOR0_INFO" 5857 }, 5858 { 5859 "chips": ["gfx9"], 5860 "map": {"at": 167028, "to": "mm"}, 5861 "name": "CB_COLOR0_ATTRIB", 5862 "type_ref": "CB_COLOR0_ATTRIB" 5863 }, 5864 { 5865 "chips": ["gfx9"], 5866 "map": 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{ 5908 "chips": ["gfx9"], 5909 "map": {"at": 167064, "to": "mm"}, 5910 "name": "CB_COLOR0_DCC_BASE_EXT", 5911 "type_ref": "CB_COLOR0_BASE_EXT" 5912 }, 5913 { 5914 "chips": ["gfx9"], 5915 "map": {"at": 167068, "to": "mm"}, 5916 "name": "CB_COLOR1_BASE" 5917 }, 5918 { 5919 "chips": ["gfx9"], 5920 "map": {"at": 167072, "to": "mm"}, 5921 "name": "CB_COLOR1_BASE_EXT", 5922 "type_ref": "CB_COLOR0_BASE_EXT" 5923 }, 5924 { 5925 "chips": ["gfx9"], 5926 "map": {"at": 167076, "to": "mm"}, 5927 "name": "CB_COLOR1_ATTRIB2", 5928 "type_ref": "CB_COLOR0_ATTRIB2" 5929 }, 5930 { 5931 "chips": ["gfx9"], 5932 "map": {"at": 167080, "to": "mm"}, 5933 "name": "CB_COLOR1_VIEW", 5934 "type_ref": "CB_COLOR0_VIEW" 5935 }, 5936 { 5937 "chips": ["gfx9"], 5938 "map": {"at": 167084, "to": "mm"}, 5939 "name": "CB_COLOR1_INFO", 5940 "type_ref": "CB_COLOR0_INFO" 5941 }, 5942 { 5943 "chips": ["gfx9"], 5944 "map": {"at": 167088, "to": "mm"}, 5945 "name": "CB_COLOR1_ATTRIB", 5946 "type_ref": "CB_COLOR0_ATTRIB" 5947 }, 5948 { 5949 "chips": ["gfx9"], 5950 "map": {"at": 167092, "to": "mm"}, 5951 "name": "CB_COLOR1_DCC_CONTROL", 5952 "type_ref": "CB_COLOR0_DCC_CONTROL" 5953 }, 5954 { 5955 "chips": ["gfx9"], 5956 "map": {"at": 167096, "to": "mm"}, 5957 "name": "CB_COLOR1_CMASK" 5958 }, 5959 { 5960 "chips": ["gfx9"], 5961 "map": {"at": 167100, "to": "mm"}, 5962 "name": "CB_COLOR1_CMASK_BASE_EXT", 5963 "type_ref": "CB_COLOR0_BASE_EXT" 5964 }, 5965 { 5966 "chips": ["gfx9"], 5967 "map": {"at": 167104, "to": "mm"}, 5968 "name": "CB_COLOR1_FMASK" 5969 }, 5970 { 5971 "chips": ["gfx9"], 5972 "map": {"at": 167108, "to": "mm"}, 5973 "name": "CB_COLOR1_FMASK_BASE_EXT", 5974 "type_ref": "CB_COLOR0_BASE_EXT" 5975 }, 5976 { 5977 "chips": ["gfx9"], 5978 "map": {"at": 167112, "to": "mm"}, 5979 "name": "CB_COLOR1_CLEAR_WORD0" 5980 }, 5981 { 5982 "chips": ["gfx9"], 5983 "map": {"at": 167116, "to": "mm"}, 5984 "name": "CB_COLOR1_CLEAR_WORD1" 5985 }, 5986 { 5987 "chips": ["gfx9"], 5988 "map": {"at": 167120, "to": "mm"}, 5989 "name": "CB_COLOR1_DCC_BASE" 5990 }, 5991 { 5992 "chips": ["gfx9"], 5993 "map": {"at": 167124, "to": "mm"}, 5994 "name": "CB_COLOR1_DCC_BASE_EXT", 5995 "type_ref": "CB_COLOR0_BASE_EXT" 5996 }, 5997 { 5998 "chips": ["gfx9"], 5999 "map": {"at": 167128, "to": "mm"}, 6000 "name": "CB_COLOR2_BASE" 6001 }, 6002 { 6003 "chips": ["gfx9"], 6004 "map": {"at": 167132, "to": "mm"}, 6005 "name": "CB_COLOR2_BASE_EXT", 6006 "type_ref": "CB_COLOR0_BASE_EXT" 6007 }, 6008 { 6009 "chips": ["gfx9"], 6010 "map": {"at": 167136, "to": "mm"}, 6011 "name": "CB_COLOR2_ATTRIB2", 6012 "type_ref": "CB_COLOR0_ATTRIB2" 6013 }, 6014 { 6015 "chips": ["gfx9"], 6016 "map": {"at": 167140, "to": "mm"}, 6017 "name": "CB_COLOR2_VIEW", 6018 "type_ref": "CB_COLOR0_VIEW" 6019 }, 6020 { 6021 "chips": ["gfx9"], 6022 "map": {"at": 167144, "to": "mm"}, 6023 "name": "CB_COLOR2_INFO", 6024 "type_ref": "CB_COLOR0_INFO" 6025 }, 6026 { 6027 "chips": ["gfx9"], 6028 "map": {"at": 167148, "to": "mm"}, 6029 "name": "CB_COLOR2_ATTRIB", 6030 "type_ref": "CB_COLOR0_ATTRIB" 6031 }, 6032 { 6033 "chips": ["gfx9"], 6034 "map": {"at": 167152, "to": "mm"}, 6035 "name": "CB_COLOR2_DCC_CONTROL", 6036 "type_ref": "CB_COLOR0_DCC_CONTROL" 6037 }, 6038 { 6039 "chips": ["gfx9"], 6040 "map": {"at": 167156, "to": "mm"}, 6041 "name": "CB_COLOR2_CMASK" 6042 }, 6043 { 6044 "chips": ["gfx9"], 6045 "map": {"at": 167160, "to": "mm"}, 6046 "name": "CB_COLOR2_CMASK_BASE_EXT", 6047 "type_ref": "CB_COLOR0_BASE_EXT" 6048 }, 6049 { 6050 "chips": ["gfx9"], 6051 "map": {"at": 167164, "to": "mm"}, 6052 "name": "CB_COLOR2_FMASK" 6053 }, 6054 { 6055 "chips": ["gfx9"], 6056 "map": {"at": 167168, "to": "mm"}, 6057 "name": "CB_COLOR2_FMASK_BASE_EXT", 6058 "type_ref": "CB_COLOR0_BASE_EXT" 6059 }, 6060 { 6061 "chips": ["gfx9"], 6062 "map": {"at": 167172, "to": "mm"}, 6063 "name": "CB_COLOR2_CLEAR_WORD0" 6064 }, 6065 { 6066 "chips": ["gfx9"], 6067 "map": {"at": 167176, "to": "mm"}, 6068 "name": "CB_COLOR2_CLEAR_WORD1" 6069 }, 6070 { 6071 "chips": ["gfx9"], 6072 "map": {"at": 167180, "to": "mm"}, 6073 "name": "CB_COLOR2_DCC_BASE" 6074 }, 6075 { 6076 "chips": ["gfx9"], 6077 "map": {"at": 167184, "to": "mm"}, 6078 "name": "CB_COLOR2_DCC_BASE_EXT", 6079 "type_ref": "CB_COLOR0_BASE_EXT" 6080 }, 6081 { 6082 "chips": ["gfx9"], 6083 "map": {"at": 167188, "to": "mm"}, 6084 "name": "CB_COLOR3_BASE" 6085 }, 6086 { 6087 "chips": ["gfx9"], 6088 "map": {"at": 167192, "to": "mm"}, 6089 "name": "CB_COLOR3_BASE_EXT", 6090 "type_ref": "CB_COLOR0_BASE_EXT" 6091 }, 6092 { 6093 "chips": ["gfx9"], 6094 "map": {"at": 167196, "to": "mm"}, 6095 "name": "CB_COLOR3_ATTRIB2", 6096 "type_ref": "CB_COLOR0_ATTRIB2" 6097 }, 6098 { 6099 "chips": ["gfx9"], 6100 "map": {"at": 167200, "to": "mm"}, 6101 "name": "CB_COLOR3_VIEW", 6102 "type_ref": "CB_COLOR0_VIEW" 6103 }, 6104 { 6105 "chips": ["gfx9"], 6106 "map": {"at": 167204, "to": "mm"}, 6107 "name": "CB_COLOR3_INFO", 6108 "type_ref": "CB_COLOR0_INFO" 6109 }, 6110 { 6111 "chips": ["gfx9"], 6112 "map": {"at": 167208, "to": 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6194 { 6195 "chips": ["gfx9"], 6196 "map": {"at": 167268, "to": "mm"}, 6197 "name": "CB_COLOR4_ATTRIB", 6198 "type_ref": "CB_COLOR0_ATTRIB" 6199 }, 6200 { 6201 "chips": ["gfx9"], 6202 "map": {"at": 167272, "to": "mm"}, 6203 "name": "CB_COLOR4_DCC_CONTROL", 6204 "type_ref": "CB_COLOR0_DCC_CONTROL" 6205 }, 6206 { 6207 "chips": ["gfx9"], 6208 "map": {"at": 167276, "to": "mm"}, 6209 "name": "CB_COLOR4_CMASK" 6210 }, 6211 { 6212 "chips": ["gfx9"], 6213 "map": {"at": 167280, "to": "mm"}, 6214 "name": "CB_COLOR4_CMASK_BASE_EXT", 6215 "type_ref": "CB_COLOR0_BASE_EXT" 6216 }, 6217 { 6218 "chips": ["gfx9"], 6219 "map": {"at": 167284, "to": "mm"}, 6220 "name": "CB_COLOR4_FMASK" 6221 }, 6222 { 6223 "chips": ["gfx9"], 6224 "map": {"at": 167288, "to": "mm"}, 6225 "name": "CB_COLOR4_FMASK_BASE_EXT", 6226 "type_ref": "CB_COLOR0_BASE_EXT" 6227 }, 6228 { 6229 "chips": ["gfx9"], 6230 "map": {"at": 167292, "to": "mm"}, 6231 "name": "CB_COLOR4_CLEAR_WORD0" 6232 }, 6233 { 6234 "chips": ["gfx9"], 6235 "map": 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6276 "type_ref": "CB_COLOR0_INFO" 6277 }, 6278 { 6279 "chips": ["gfx9"], 6280 "map": {"at": 167328, "to": "mm"}, 6281 "name": "CB_COLOR5_ATTRIB", 6282 "type_ref": "CB_COLOR0_ATTRIB" 6283 }, 6284 { 6285 "chips": ["gfx9"], 6286 "map": {"at": 167332, "to": "mm"}, 6287 "name": "CB_COLOR5_DCC_CONTROL", 6288 "type_ref": "CB_COLOR0_DCC_CONTROL" 6289 }, 6290 { 6291 "chips": ["gfx9"], 6292 "map": {"at": 167336, "to": "mm"}, 6293 "name": "CB_COLOR5_CMASK" 6294 }, 6295 { 6296 "chips": ["gfx9"], 6297 "map": {"at": 167340, "to": "mm"}, 6298 "name": "CB_COLOR5_CMASK_BASE_EXT", 6299 "type_ref": "CB_COLOR0_BASE_EXT" 6300 }, 6301 { 6302 "chips": ["gfx9"], 6303 "map": {"at": 167344, "to": "mm"}, 6304 "name": "CB_COLOR5_FMASK" 6305 }, 6306 { 6307 "chips": ["gfx9"], 6308 "map": {"at": 167348, "to": "mm"}, 6309 "name": "CB_COLOR5_FMASK_BASE_EXT", 6310 "type_ref": "CB_COLOR0_BASE_EXT" 6311 }, 6312 { 6313 "chips": ["gfx9"], 6314 "map": {"at": 167352, "to": "mm"}, 6315 "name": "CB_COLOR5_CLEAR_WORD0" 6316 }, 6317 { 6318 "chips": ["gfx9"], 6319 "map": {"at": 167356, "to": "mm"}, 6320 "name": "CB_COLOR5_CLEAR_WORD1" 6321 }, 6322 { 6323 "chips": ["gfx9"], 6324 "map": {"at": 167360, "to": "mm"}, 6325 "name": "CB_COLOR5_DCC_BASE" 6326 }, 6327 { 6328 "chips": ["gfx9"], 6329 "map": {"at": 167364, "to": "mm"}, 6330 "name": "CB_COLOR5_DCC_BASE_EXT", 6331 "type_ref": "CB_COLOR0_BASE_EXT" 6332 }, 6333 { 6334 "chips": ["gfx9"], 6335 "map": {"at": 167368, "to": "mm"}, 6336 "name": "CB_COLOR6_BASE" 6337 }, 6338 { 6339 "chips": ["gfx9"], 6340 "map": {"at": 167372, "to": "mm"}, 6341 "name": "CB_COLOR6_BASE_EXT", 6342 "type_ref": "CB_COLOR0_BASE_EXT" 6343 }, 6344 { 6345 "chips": ["gfx9"], 6346 "map": {"at": 167376, "to": "mm"}, 6347 "name": "CB_COLOR6_ATTRIB2", 6348 "type_ref": "CB_COLOR0_ATTRIB2" 6349 }, 6350 { 6351 "chips": ["gfx9"], 6352 "map": {"at": 167380, "to": "mm"}, 6353 "name": "CB_COLOR6_VIEW", 6354 "type_ref": "CB_COLOR0_VIEW" 6355 }, 6356 { 6357 "chips": ["gfx9"], 6358 "map": {"at": 167384, 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6399 "name": "CB_COLOR6_CLEAR_WORD0" 6400 }, 6401 { 6402 "chips": ["gfx9"], 6403 "map": {"at": 167416, "to": "mm"}, 6404 "name": "CB_COLOR6_CLEAR_WORD1" 6405 }, 6406 { 6407 "chips": ["gfx9"], 6408 "map": {"at": 167420, "to": "mm"}, 6409 "name": "CB_COLOR6_DCC_BASE" 6410 }, 6411 { 6412 "chips": ["gfx9"], 6413 "map": {"at": 167424, "to": "mm"}, 6414 "name": "CB_COLOR6_DCC_BASE_EXT", 6415 "type_ref": "CB_COLOR0_BASE_EXT" 6416 }, 6417 { 6418 "chips": ["gfx9"], 6419 "map": {"at": 167428, "to": "mm"}, 6420 "name": "CB_COLOR7_BASE" 6421 }, 6422 { 6423 "chips": ["gfx9"], 6424 "map": {"at": 167432, "to": "mm"}, 6425 "name": "CB_COLOR7_BASE_EXT", 6426 "type_ref": "CB_COLOR0_BASE_EXT" 6427 }, 6428 { 6429 "chips": ["gfx9"], 6430 "map": {"at": 167436, "to": "mm"}, 6431 "name": "CB_COLOR7_ATTRIB2", 6432 "type_ref": "CB_COLOR0_ATTRIB2" 6433 }, 6434 { 6435 "chips": ["gfx9"], 6436 "map": {"at": 167440, "to": "mm"}, 6437 "name": "CB_COLOR7_VIEW", 6438 "type_ref": "CB_COLOR0_VIEW" 6439 }, 6440 { 6441 "chips": ["gfx9"], 6442 "map": {"at": 167444, "to": "mm"}, 6443 "name": "CB_COLOR7_INFO", 6444 "type_ref": "CB_COLOR0_INFO" 6445 }, 6446 { 6447 "chips": ["gfx9"], 6448 "map": {"at": 167448, "to": "mm"}, 6449 "name": "CB_COLOR7_ATTRIB", 6450 "type_ref": "CB_COLOR0_ATTRIB" 6451 }, 6452 { 6453 "chips": ["gfx9"], 6454 "map": {"at": 167452, "to": "mm"}, 6455 "name": "CB_COLOR7_DCC_CONTROL", 6456 "type_ref": "CB_COLOR0_DCC_CONTROL" 6457 }, 6458 { 6459 "chips": ["gfx9"], 6460 "map": {"at": 167456, "to": "mm"}, 6461 "name": "CB_COLOR7_CMASK" 6462 }, 6463 { 6464 "chips": ["gfx9"], 6465 "map": {"at": 167460, "to": "mm"}, 6466 "name": "CB_COLOR7_CMASK_BASE_EXT", 6467 "type_ref": "CB_COLOR0_BASE_EXT" 6468 }, 6469 { 6470 "chips": ["gfx9"], 6471 "map": {"at": 167464, "to": "mm"}, 6472 "name": "CB_COLOR7_FMASK" 6473 }, 6474 { 6475 "chips": ["gfx9"], 6476 "map": {"at": 167468, "to": "mm"}, 6477 "name": "CB_COLOR7_FMASK_BASE_EXT", 6478 "type_ref": "CB_COLOR0_BASE_EXT" 6479 }, 6480 { 6481 "chips": ["gfx9"], 6482 "map": {"at": 167472, "to": "mm"}, 6483 "name": "CB_COLOR7_CLEAR_WORD0" 6484 }, 6485 { 6486 "chips": ["gfx9"], 6487 "map": {"at": 167476, "to": "mm"}, 6488 "name": "CB_COLOR7_CLEAR_WORD1" 6489 }, 6490 { 6491 "chips": ["gfx9"], 6492 "map": {"at": 167480, "to": "mm"}, 6493 "name": "CB_COLOR7_DCC_BASE" 6494 }, 6495 { 6496 "chips": ["gfx9"], 6497 "map": {"at": 167484, "to": "mm"}, 6498 "name": "CB_COLOR7_DCC_BASE_EXT", 6499 "type_ref": "CB_COLOR0_BASE_EXT" 6500 }, 6501 { 6502 "chips": ["gfx9"], 6503 "map": {"at": 196608, "to": "mm"}, 6504 "name": "CP_EOP_DONE_ADDR_LO", 6505 "type_ref": "CP_EOP_DONE_ADDR_LO" 6506 }, 6507 { 6508 "chips": ["gfx9"], 6509 "map": {"at": 196612, "to": "mm"}, 6510 "name": "CP_EOP_DONE_ADDR_HI", 6511 "type_ref": "CP_EOP_DONE_ADDR_HI" 6512 }, 6513 { 6514 "chips": ["gfx9"], 6515 "map": {"at": 196616, "to": "mm"}, 6516 "name": "CP_EOP_DONE_DATA_LO" 6517 }, 6518 { 6519 "chips": ["gfx9"], 6520 "map": {"at": 196620, "to": "mm"}, 6521 "name": "CP_EOP_DONE_DATA_HI" 6522 }, 6523 { 6524 "chips": ["gfx9"], 6525 "map": {"at": 196624, "to": "mm"}, 6526 "name": "CP_EOP_LAST_FENCE_LO" 6527 }, 6528 { 6529 "chips": ["gfx9"], 6530 "map": {"at": 196628, "to": "mm"}, 6531 "name": "CP_EOP_LAST_FENCE_HI" 6532 }, 6533 { 6534 "chips": ["gfx9"], 6535 "map": {"at": 196632, "to": "mm"}, 6536 "name": "CP_STREAM_OUT_ADDR_LO", 6537 "type_ref": "CP_STREAM_OUT_ADDR_LO" 6538 }, 6539 { 6540 "chips": ["gfx9"], 6541 "map": {"at": 196636, "to": "mm"}, 6542 "name": "CP_STREAM_OUT_ADDR_HI", 6543 "type_ref": "CP_STREAM_OUT_ADDR_HI" 6544 }, 6545 { 6546 "chips": ["gfx9"], 6547 "map": {"at": 196640, "to": "mm"}, 6548 "name": "CP_NUM_PRIM_WRITTEN_COUNT0_LO" 6549 }, 6550 { 6551 "chips": ["gfx9"], 6552 "map": {"at": 196644, "to": "mm"}, 6553 "name": "CP_NUM_PRIM_WRITTEN_COUNT0_HI" 6554 }, 6555 { 6556 "chips": ["gfx9"], 6557 "map": {"at": 196648, "to": "mm"}, 6558 "name": "CP_NUM_PRIM_NEEDED_COUNT0_LO" 6559 }, 6560 { 6561 "chips": ["gfx9"], 6562 "map": {"at": 196652, "to": "mm"}, 6563 "name": "CP_NUM_PRIM_NEEDED_COUNT0_HI" 6564 }, 6565 { 6566 "chips": ["gfx9"], 6567 "map": {"at": 196656, "to": "mm"}, 6568 "name": "CP_NUM_PRIM_WRITTEN_COUNT1_LO" 6569 }, 6570 { 6571 "chips": ["gfx9"], 6572 "map": {"at": 196660, "to": "mm"}, 6573 "name": "CP_NUM_PRIM_WRITTEN_COUNT1_HI" 6574 }, 6575 { 6576 "chips": ["gfx9"], 6577 "map": {"at": 196664, "to": "mm"}, 6578 "name": "CP_NUM_PRIM_NEEDED_COUNT1_LO" 6579 }, 6580 { 6581 "chips": ["gfx9"], 6582 "map": {"at": 196668, "to": "mm"}, 6583 "name": "CP_NUM_PRIM_NEEDED_COUNT1_HI" 6584 }, 6585 { 6586 "chips": ["gfx9"], 6587 "map": {"at": 196672, "to": "mm"}, 6588 "name": "CP_NUM_PRIM_WRITTEN_COUNT2_LO" 6589 }, 6590 { 6591 "chips": ["gfx9"], 6592 "map": {"at": 196676, "to": "mm"}, 6593 "name": "CP_NUM_PRIM_WRITTEN_COUNT2_HI" 6594 }, 6595 { 6596 "chips": ["gfx9"], 6597 "map": {"at": 196680, "to": "mm"}, 6598 "name": "CP_NUM_PRIM_NEEDED_COUNT2_LO" 6599 }, 6600 { 6601 "chips": ["gfx9"], 6602 "map": {"at": 196684, "to": "mm"}, 6603 "name": "CP_NUM_PRIM_NEEDED_COUNT2_HI" 6604 }, 6605 { 6606 "chips": ["gfx9"], 6607 "map": {"at": 196688, "to": "mm"}, 6608 "name": "CP_NUM_PRIM_WRITTEN_COUNT3_LO" 6609 }, 6610 { 6611 "chips": ["gfx9"], 6612 "map": {"at": 196692, "to": "mm"}, 6613 "name": "CP_NUM_PRIM_WRITTEN_COUNT3_HI" 6614 }, 6615 { 6616 "chips": ["gfx9"], 6617 "map": {"at": 196696, "to": "mm"}, 6618 "name": "CP_NUM_PRIM_NEEDED_COUNT3_LO" 6619 }, 6620 { 6621 "chips": ["gfx9"], 6622 "map": {"at": 196700, "to": "mm"}, 6623 "name": "CP_NUM_PRIM_NEEDED_COUNT3_HI" 6624 }, 6625 { 6626 "chips": ["gfx9"], 6627 "map": {"at": 196704, "to": "mm"}, 6628 "name": "CP_PIPE_STATS_ADDR_LO", 6629 "type_ref": "CP_PIPE_STATS_ADDR_LO" 6630 }, 6631 { 6632 "chips": ["gfx9"], 6633 "map": {"at": 196708, "to": "mm"}, 6634 "name": "CP_PIPE_STATS_ADDR_HI", 6635 "type_ref": "CP_PIPE_STATS_ADDR_HI" 6636 }, 6637 { 6638 "chips": ["gfx9"], 6639 "map": {"at": 196712, "to": "mm"}, 6640 "name": "CP_VGT_IAVERT_COUNT_LO" 6641 }, 6642 { 6643 "chips": ["gfx9"], 6644 "map": {"at": 196716, "to": "mm"}, 6645 "name": "CP_VGT_IAVERT_COUNT_HI" 6646 }, 6647 { 6648 "chips": ["gfx9"], 6649 "map": {"at": 196720, "to": "mm"}, 6650 "name": "CP_VGT_IAPRIM_COUNT_LO" 6651 }, 6652 { 6653 "chips": ["gfx9"], 6654 "map": {"at": 196724, "to": "mm"}, 6655 "name": "CP_VGT_IAPRIM_COUNT_HI" 6656 }, 6657 { 6658 "chips": ["gfx9"], 6659 "map": {"at": 196728, "to": "mm"}, 6660 "name": "CP_VGT_GSPRIM_COUNT_LO" 6661 }, 6662 { 6663 "chips": ["gfx9"], 6664 "map": {"at": 196732, "to": "mm"}, 6665 "name": "CP_VGT_GSPRIM_COUNT_HI" 6666 }, 6667 { 6668 "chips": ["gfx9"], 6669 "map": {"at": 196736, "to": "mm"}, 6670 "name": "CP_VGT_VSINVOC_COUNT_LO" 6671 }, 6672 { 6673 "chips": ["gfx9"], 6674 "map": {"at": 196740, "to": "mm"}, 6675 "name": "CP_VGT_VSINVOC_COUNT_HI" 6676 }, 6677 { 6678 "chips": ["gfx9"], 6679 "map": {"at": 196744, "to": "mm"}, 6680 "name": "CP_VGT_GSINVOC_COUNT_LO" 6681 }, 6682 { 6683 "chips": ["gfx9"], 6684 "map": {"at": 196748, "to": "mm"}, 6685 "name": "CP_VGT_GSINVOC_COUNT_HI" 6686 }, 6687 { 6688 "chips": ["gfx9"], 6689 "map": {"at": 196752, "to": "mm"}, 6690 "name": "CP_VGT_HSINVOC_COUNT_LO" 6691 }, 6692 { 6693 "chips": ["gfx9"], 6694 "map": {"at": 196756, "to": "mm"}, 6695 "name": "CP_VGT_HSINVOC_COUNT_HI" 6696 }, 6697 { 6698 "chips": ["gfx9"], 6699 "map": {"at": 196760, "to": "mm"}, 6700 "name": "CP_VGT_DSINVOC_COUNT_LO" 6701 }, 6702 { 6703 "chips": ["gfx9"], 6704 "map": {"at": 196764, "to": "mm"}, 6705 "name": "CP_VGT_DSINVOC_COUNT_HI" 6706 }, 6707 { 6708 "chips": ["gfx9"], 6709 "map": {"at": 196768, "to": "mm"}, 6710 "name": "CP_PA_CINVOC_COUNT_LO" 6711 }, 6712 { 6713 "chips": ["gfx9"], 6714 "map": {"at": 196772, "to": "mm"}, 6715 "name": "CP_PA_CINVOC_COUNT_HI" 6716 }, 6717 { 6718 "chips": ["gfx9"], 6719 "map": {"at": 196776, "to": "mm"}, 6720 "name": "CP_PA_CPRIM_COUNT_LO" 6721 }, 6722 { 6723 "chips": ["gfx9"], 6724 "map": {"at": 196780, "to": "mm"}, 6725 "name": "CP_PA_CPRIM_COUNT_HI" 6726 }, 6727 { 6728 "chips": ["gfx9"], 6729 "map": {"at": 196784, "to": "mm"}, 6730 "name": "CP_SC_PSINVOC_COUNT0_LO" 6731 }, 6732 { 6733 "chips": ["gfx9"], 6734 "map": {"at": 196788, "to": "mm"}, 6735 "name": "CP_SC_PSINVOC_COUNT0_HI" 6736 }, 6737 { 6738 "chips": ["gfx9"], 6739 "map": {"at": 196792, "to": "mm"}, 6740 "name": "CP_SC_PSINVOC_COUNT1_LO" 6741 }, 6742 { 6743 "chips": ["gfx9"], 6744 "map": {"at": 196796, "to": "mm"}, 6745 "name": "CP_SC_PSINVOC_COUNT1_HI" 6746 }, 6747 { 6748 "chips": ["gfx9"], 6749 "map": {"at": 196800, "to": "mm"}, 6750 "name": "CP_VGT_CSINVOC_COUNT_LO" 6751 }, 6752 { 6753 "chips": ["gfx9"], 6754 "map": {"at": 196804, "to": "mm"}, 6755 "name": "CP_VGT_CSINVOC_COUNT_HI" 6756 }, 6757 { 6758 "chips": ["gfx9"], 6759 "map": {"at": 196852, "to": "mm"}, 6760 "name": "CP_PIPE_STATS_CONTROL", 6761 "type_ref": "CP_PIPE_STATS_CONTROL" 6762 }, 6763 { 6764 "chips": ["gfx9"], 6765 "map": {"at": 196856, "to": "mm"}, 6766 "name": "CP_STREAM_OUT_CONTROL", 6767 "type_ref": "CP_PIPE_STATS_CONTROL" 6768 }, 6769 { 6770 "chips": ["gfx9"], 6771 "map": {"at": 196860, "to": "mm"}, 6772 "name": "CP_STRMOUT_CNTL", 6773 "type_ref": "CP_STRMOUT_CNTL" 6774 }, 6775 { 6776 "chips": ["gfx9"], 6777 "map": {"at": 196864, "to": "mm"}, 6778 "name": "SCRATCH_REG0" 6779 }, 6780 { 6781 "chips": ["gfx9"], 6782 "map": {"at": 196868, "to": "mm"}, 6783 "name": "SCRATCH_REG1" 6784 }, 6785 { 6786 "chips": ["gfx9"], 6787 "map": {"at": 196872, "to": "mm"}, 6788 "name": "SCRATCH_REG2" 6789 }, 6790 { 6791 "chips": ["gfx9"], 6792 "map": {"at": 196876, "to": "mm"}, 6793 "name": "SCRATCH_REG3" 6794 }, 6795 { 6796 "chips": ["gfx9"], 6797 "map": {"at": 196880, "to": "mm"}, 6798 "name": "SCRATCH_REG4" 6799 }, 6800 { 6801 "chips": ["gfx9"], 6802 "map": {"at": 196884, "to": "mm"}, 6803 "name": "SCRATCH_REG5" 6804 }, 6805 { 6806 "chips": ["gfx9"], 6807 "map": {"at": 196888, "to": "mm"}, 6808 "name": "SCRATCH_REG6" 6809 }, 6810 { 6811 "chips": ["gfx9"], 6812 "map": {"at": 196892, "to": "mm"}, 6813 "name": "SCRATCH_REG7" 6814 }, 6815 { 6816 "chips": ["gfx9"], 6817 "map": {"at": 196912, "to": "mm"}, 6818 "name": "CP_APPEND_DATA_HI" 6819 }, 6820 { 6821 "chips": ["gfx9"], 6822 "map": {"at": 196916, "to": "mm"}, 6823 "name": "CP_APPEND_LAST_CS_FENCE_HI" 6824 }, 6825 { 6826 "chips": ["gfx9"], 6827 "map": {"at": 196920, "to": "mm"}, 6828 "name": "CP_APPEND_LAST_PS_FENCE_HI" 6829 }, 6830 { 6831 "chips": ["gfx9"], 6832 "map": {"at": 196928, "to": "mm"}, 6833 "name": "SCRATCH_UMSK", 6834 "type_ref": "SCRATCH_UMSK" 6835 }, 6836 { 6837 "chips": ["gfx9"], 6838 "map": {"at": 196932, "to": "mm"}, 6839 "name": "SCRATCH_ADDR" 6840 }, 6841 { 6842 "chips": ["gfx9"], 6843 "map": {"at": 196936, "to": "mm"}, 6844 "name": "CP_PFP_ATOMIC_PREOP_LO" 6845 }, 6846 { 6847 "chips": ["gfx9"], 6848 "map": {"at": 196940, "to": "mm"}, 6849 "name": "CP_PFP_ATOMIC_PREOP_HI" 6850 }, 6851 { 6852 "chips": ["gfx9"], 6853 "map": {"at": 196944, "to": "mm"}, 6854 "name": "CP_PFP_GDS_ATOMIC0_PREOP_LO" 6855 }, 6856 { 6857 "chips": ["gfx9"], 6858 "map": {"at": 196948, "to": "mm"}, 6859 "name": "CP_PFP_GDS_ATOMIC0_PREOP_HI" 6860 }, 6861 { 6862 "chips": ["gfx9"], 6863 "map": {"at": 196952, "to": "mm"}, 6864 "name": "CP_PFP_GDS_ATOMIC1_PREOP_LO" 6865 }, 6866 { 6867 "chips": ["gfx9"], 6868 "map": {"at": 196956, "to": "mm"}, 6869 "name": "CP_PFP_GDS_ATOMIC1_PREOP_HI" 6870 }, 6871 { 6872 "chips": ["gfx9"], 6873 "map": {"at": 196960, "to": "mm"}, 6874 "name": "CP_APPEND_ADDR_LO", 6875 "type_ref": "CP_APPEND_ADDR_LO" 6876 }, 6877 { 6878 "chips": ["gfx9"], 6879 "map": {"at": 196964, "to": "mm"}, 6880 "name": "CP_APPEND_ADDR_HI", 6881 "type_ref": "CP_APPEND_ADDR_HI" 6882 }, 6883 { 6884 "chips": ["gfx9"], 6885 "map": {"at": 196968, "to": "mm"}, 6886 "name": "CP_APPEND_DATA_LO" 6887 }, 6888 { 6889 "chips": ["gfx9"], 6890 "map": {"at": 196972, "to": "mm"}, 6891 "name": "CP_APPEND_LAST_CS_FENCE_LO" 6892 }, 6893 { 6894 "chips": ["gfx9"], 6895 "map": {"at": 196976, "to": "mm"}, 6896 "name": "CP_APPEND_LAST_PS_FENCE_LO" 6897 }, 6898 { 6899 "chips": ["gfx9"], 6900 "map": {"at": 196980, "to": "mm"}, 6901 "name": "CP_ATOMIC_PREOP_LO" 6902 }, 6903 { 6904 "chips": ["gfx9"], 6905 "map": {"at": 196984, "to": "mm"}, 6906 "name": "CP_ATOMIC_PREOP_HI" 6907 }, 6908 { 6909 "chips": ["gfx9"], 6910 "map": {"at": 196988, "to": "mm"}, 6911 "name": "CP_GDS_ATOMIC0_PREOP_LO" 6912 }, 6913 { 6914 "chips": ["gfx9"], 6915 "map": {"at": 196992, "to": "mm"}, 6916 "name": "CP_GDS_ATOMIC0_PREOP_HI" 6917 }, 6918 { 6919 "chips": ["gfx9"], 6920 "map": {"at": 196996, "to": "mm"}, 6921 "name": "CP_GDS_ATOMIC1_PREOP_LO" 6922 }, 6923 { 6924 "chips": ["gfx9"], 6925 "map": {"at": 197000, "to": "mm"}, 6926 "name": "CP_GDS_ATOMIC1_PREOP_HI" 6927 }, 6928 { 6929 "chips": ["gfx9"], 6930 "map": {"at": 197028, "to": "mm"}, 6931 "name": "CP_ME_MC_WADDR_LO", 6932 "type_ref": "CP_ME_MC_WADDR_LO" 6933 }, 6934 { 6935 "chips": ["gfx9"], 6936 "map": {"at": 197032, "to": "mm"}, 6937 "name": "CP_ME_MC_WADDR_HI", 6938 "type_ref": "CP_ME_MC_WADDR_HI" 6939 }, 6940 { 6941 "chips": ["gfx9"], 6942 "map": {"at": 197036, "to": "mm"}, 6943 "name": "CP_ME_MC_WDATA_LO" 6944 }, 6945 { 6946 "chips": ["gfx9"], 6947 "map": {"at": 197040, "to": "mm"}, 6948 "name": "CP_ME_MC_WDATA_HI" 6949 }, 6950 { 6951 "chips": ["gfx9"], 6952 "map": {"at": 197044, "to": "mm"}, 6953 "name": "CP_ME_MC_RADDR_LO", 6954 "type_ref": "CP_ME_MC_RADDR_LO" 6955 }, 6956 { 6957 "chips": ["gfx9"], 6958 "map": {"at": 197048, "to": "mm"}, 6959 "name": "CP_ME_MC_RADDR_HI", 6960 "type_ref": "CP_ME_MC_RADDR_HI" 6961 }, 6962 { 6963 "chips": ["gfx9"], 6964 "map": {"at": 197052, "to": "mm"}, 6965 "name": "CP_SEM_WAIT_TIMER" 6966 }, 6967 { 6968 "chips": ["gfx9"], 6969 "map": {"at": 197056, "to": "mm"}, 6970 "name": "CP_SIG_SEM_ADDR_LO", 6971 "type_ref": "CP_SIG_SEM_ADDR_LO" 6972 }, 6973 { 6974 "chips": ["gfx9"], 6975 "map": {"at": 197060, "to": "mm"}, 6976 "name": "CP_SIG_SEM_ADDR_HI", 6977 "type_ref": "CP_SIG_SEM_ADDR_HI" 6978 }, 6979 { 6980 "chips": ["gfx9"], 6981 "map": {"at": 197072, "to": "mm"}, 6982 "name": "CP_WAIT_REG_MEM_TIMEOUT" 6983 }, 6984 { 6985 "chips": ["gfx9"], 6986 "map": {"at": 197076, "to": "mm"}, 6987 "name": "CP_WAIT_SEM_ADDR_LO", 6988 "type_ref": "CP_SIG_SEM_ADDR_LO" 6989 }, 6990 { 6991 "chips": ["gfx9"], 6992 "map": {"at": 197080, "to": "mm"}, 6993 "name": "CP_WAIT_SEM_ADDR_HI", 6994 "type_ref": "CP_SIG_SEM_ADDR_HI" 6995 }, 6996 { 6997 "chips": ["gfx9"], 6998 "map": {"at": 197084, "to": "mm"}, 6999 "name": "CP_DMA_PFP_CONTROL", 7000 "type_ref": "CP_DMA_PFP_CONTROL" 7001 }, 7002 { 7003 "chips": ["gfx9"], 7004 "map": {"at": 197088, "to": "mm"}, 7005 "name": "CP_DMA_ME_CONTROL", 7006 "type_ref": "CP_DMA_PFP_CONTROL" 7007 }, 7008 { 7009 "chips": ["gfx9"], 7010 "map": {"at": 197092, "to": "mm"}, 7011 "name": "CP_COHER_BASE_HI", 7012 "type_ref": "CP_COHER_BASE_HI" 7013 }, 7014 { 7015 "chips": ["gfx9"], 7016 "map": {"at": 197100, "to": "mm"}, 7017 "name": "CP_COHER_START_DELAY", 7018 "type_ref": "CP_COHER_START_DELAY" 7019 }, 7020 { 7021 "chips": ["gfx9"], 7022 "map": {"at": 197104, "to": "mm"}, 7023 "name": "CP_COHER_CNTL", 7024 "type_ref": "CP_COHER_CNTL" 7025 }, 7026 { 7027 "chips": ["gfx9"], 7028 "map": {"at": 197108, "to": "mm"}, 7029 "name": "CP_COHER_SIZE" 7030 }, 7031 { 7032 "chips": ["gfx9"], 7033 "map": {"at": 197112, "to": "mm"}, 7034 "name": "CP_COHER_BASE" 7035 }, 7036 { 7037 "chips": ["gfx9"], 7038 "map": {"at": 197116, "to": "mm"}, 7039 "name": "CP_COHER_STATUS", 7040 "type_ref": "CP_COHER_STATUS" 7041 }, 7042 { 7043 "chips": ["gfx9"], 7044 "map": {"at": 197120, "to": "mm"}, 7045 "name": "CP_DMA_ME_SRC_ADDR" 7046 }, 7047 { 7048 "chips": ["gfx9"], 7049 "map": {"at": 197124, "to": "mm"}, 7050 "name": "CP_DMA_ME_SRC_ADDR_HI", 7051 "type_ref": "CP_DMA_ME_SRC_ADDR_HI" 7052 }, 7053 { 7054 "chips": ["gfx9"], 7055 "map": {"at": 197128, "to": "mm"}, 7056 "name": "CP_DMA_ME_DST_ADDR" 7057 }, 7058 { 7059 "chips": ["gfx9"], 7060 "map": {"at": 197132, "to": "mm"}, 7061 "name": "CP_DMA_ME_DST_ADDR_HI", 7062 "type_ref": "CP_DMA_ME_DST_ADDR_HI" 7063 }, 7064 { 7065 "chips": ["gfx9"], 7066 "map": {"at": 197136, "to": "mm"}, 7067 "name": "CP_DMA_ME_COMMAND", 7068 "type_ref": "CP_DMA_ME_COMMAND" 7069 }, 7070 { 7071 "chips": ["gfx9"], 7072 "map": {"at": 197140, "to": "mm"}, 7073 "name": "CP_DMA_PFP_SRC_ADDR" 7074 }, 7075 { 7076 "chips": ["gfx9"], 7077 "map": {"at": 197144, "to": "mm"}, 7078 "name": "CP_DMA_PFP_SRC_ADDR_HI", 7079 "type_ref": "CP_DMA_ME_SRC_ADDR_HI" 7080 }, 7081 { 7082 "chips": ["gfx9"], 7083 "map": {"at": 197148, "to": "mm"}, 7084 "name": "CP_DMA_PFP_DST_ADDR" 7085 }, 7086 { 7087 "chips": ["gfx9"], 7088 "map": {"at": 197152, "to": "mm"}, 7089 "name": "CP_DMA_PFP_DST_ADDR_HI", 7090 "type_ref": "CP_DMA_ME_DST_ADDR_HI" 7091 }, 7092 { 7093 "chips": ["gfx9"], 7094 "map": {"at": 197156, "to": "mm"}, 7095 "name": "CP_DMA_PFP_COMMAND", 7096 "type_ref": "CP_DMA_ME_COMMAND" 7097 }, 7098 { 7099 "chips": ["gfx9"], 7100 "map": {"at": 197160, "to": "mm"}, 7101 "name": "CP_DMA_CNTL", 7102 "type_ref": "CP_DMA_CNTL" 7103 }, 7104 { 7105 "chips": ["gfx9"], 7106 "map": {"at": 197164, "to": "mm"}, 7107 "name": "CP_DMA_READ_TAGS", 7108 "type_ref": "CP_DMA_READ_TAGS" 7109 }, 7110 { 7111 "chips": ["gfx9"], 7112 "map": {"at": 197168, "to": "mm"}, 7113 "name": "CP_COHER_SIZE_HI", 7114 "type_ref": "CP_COHER_SIZE_HI" 7115 }, 7116 { 7117 "chips": ["gfx9"], 7118 "map": {"at": 197172, "to": "mm"}, 7119 "name": "CP_PFP_IB_CONTROL", 7120 "type_ref": "CP_PFP_IB_CONTROL" 7121 }, 7122 { 7123 "chips": ["gfx9"], 7124 "map": {"at": 197176, "to": "mm"}, 7125 "name": "CP_PFP_LOAD_CONTROL", 7126 "type_ref": "CP_PFP_LOAD_CONTROL" 7127 }, 7128 { 7129 "chips": ["gfx9"], 7130 "map": {"at": 197180, "to": "mm"}, 7131 "name": "CP_SCRATCH_INDEX", 7132 "type_ref": "CP_SCRATCH_INDEX" 7133 }, 7134 { 7135 "chips": ["gfx9"], 7136 "map": {"at": 197184, "to": "mm"}, 7137 "name": "CP_SCRATCH_DATA" 7138 }, 7139 { 7140 "chips": ["gfx9"], 7141 "map": {"at": 197188, "to": "mm"}, 7142 "name": "CP_RB_OFFSET", 7143 "type_ref": "CP_RB_OFFSET" 7144 }, 7145 { 7146 "chips": ["gfx9"], 7147 "map": {"at": 197192, "to": "mm"}, 7148 "name": "CP_IB1_OFFSET", 7149 "type_ref": "CP_IB1_OFFSET" 7150 }, 7151 { 7152 "chips": ["gfx9"], 7153 "map": {"at": 197196, "to": "mm"}, 7154 "name": "CP_IB2_OFFSET", 7155 "type_ref": "CP_IB2_OFFSET" 7156 }, 7157 { 7158 "chips": ["gfx9"], 7159 "map": {"at": 197200, "to": "mm"}, 7160 "name": "CP_IB1_PREAMBLE_BEGIN", 7161 "type_ref": "CP_IB1_PREAMBLE_BEGIN" 7162 }, 7163 { 7164 "chips": ["gfx9"], 7165 "map": {"at": 197204, "to": "mm"}, 7166 "name": "CP_IB1_PREAMBLE_END", 7167 "type_ref": "CP_IB1_PREAMBLE_END" 7168 }, 7169 { 7170 "chips": ["gfx9"], 7171 "map": {"at": 197208, "to": "mm"}, 7172 "name": "CP_IB2_PREAMBLE_BEGIN", 7173 "type_ref": "CP_IB2_PREAMBLE_BEGIN" 7174 }, 7175 { 7176 "chips": ["gfx9"], 7177 "map": {"at": 197212, "to": "mm"}, 7178 "name": "CP_IB2_PREAMBLE_END", 7179 "type_ref": "CP_IB2_PREAMBLE_END" 7180 }, 7181 { 7182 "chips": ["gfx9"], 7183 "map": {"at": 197216, "to": "mm"}, 7184 "name": "CP_CE_IB1_OFFSET", 7185 "type_ref": "CP_IB1_OFFSET" 7186 }, 7187 { 7188 "chips": ["gfx9"], 7189 "map": {"at": 197220, "to": "mm"}, 7190 "name": "CP_CE_IB2_OFFSET", 7191 "type_ref": "CP_IB2_OFFSET" 7192 }, 7193 { 7194 "chips": ["gfx9"], 7195 "map": {"at": 197224, "to": "mm"}, 7196 "name": "CP_CE_COUNTER" 7197 }, 7198 { 7199 "chips": ["gfx9"], 7200 "map": {"at": 197228, "to": "mm"}, 7201 "name": "CP_CE_RB_OFFSET", 7202 "type_ref": "CP_RB_OFFSET" 7203 }, 7204 { 7205 "chips": ["gfx9"], 7206 "map": {"at": 197364, "to": "mm"}, 7207 "name": "CP_CE_INIT_CMD_BUFSZ", 7208 "type_ref": "CP_CE_INIT_CMD_BUFSZ" 7209 }, 7210 { 7211 "chips": ["gfx9"], 7212 "map": {"at": 197368, "to": "mm"}, 7213 "name": "CP_CE_IB1_CMD_BUFSZ", 7214 "type_ref": "CP_CE_IB1_CMD_BUFSZ" 7215 }, 7216 { 7217 "chips": ["gfx9"], 7218 "map": {"at": 197372, "to": "mm"}, 7219 "name": "CP_CE_IB2_CMD_BUFSZ", 7220 "type_ref": "CP_CE_IB2_CMD_BUFSZ" 7221 }, 7222 { 7223 "chips": ["gfx9"], 7224 "map": {"at": 197376, "to": "mm"}, 7225 "name": "CP_IB1_CMD_BUFSZ", 7226 "type_ref": "CP_CE_IB1_CMD_BUFSZ" 7227 }, 7228 { 7229 "chips": ["gfx9"], 7230 "map": {"at": 197380, "to": "mm"}, 7231 "name": "CP_IB2_CMD_BUFSZ", 7232 "type_ref": "CP_CE_IB2_CMD_BUFSZ" 7233 }, 7234 { 7235 "chips": ["gfx9"], 7236 "map": {"at": 197384, "to": "mm"}, 7237 "name": "CP_ST_CMD_BUFSZ", 7238 "type_ref": "CP_ST_CMD_BUFSZ" 7239 }, 7240 { 7241 "chips": ["gfx9"], 7242 "map": {"at": 197388, "to": "mm"}, 7243 "name": "CP_CE_INIT_BASE_LO", 7244 "type_ref": "CP_CE_INIT_BASE_LO" 7245 }, 7246 { 7247 "chips": ["gfx9"], 7248 "map": {"at": 197392, "to": "mm"}, 7249 "name": "CP_CE_INIT_BASE_HI", 7250 "type_ref": "CP_CE_INIT_BASE_HI" 7251 }, 7252 { 7253 "chips": ["gfx9"], 7254 "map": {"at": 197396, "to": "mm"}, 7255 "name": "CP_CE_INIT_BUFSZ", 7256 "type_ref": "CP_CE_INIT_BUFSZ" 7257 }, 7258 { 7259 "chips": ["gfx9"], 7260 "map": {"at": 197400, "to": "mm"}, 7261 "name": "CP_CE_IB1_BASE_LO", 7262 "type_ref": "CP_CE_IB1_BASE_LO" 7263 }, 7264 { 7265 "chips": ["gfx9"], 7266 "map": {"at": 197404, "to": "mm"}, 7267 "name": "CP_CE_IB1_BASE_HI", 7268 "type_ref": "CP_CE_IB1_BASE_HI" 7269 }, 7270 { 7271 "chips": ["gfx9"], 7272 "map": {"at": 197408, "to": "mm"}, 7273 "name": "CP_CE_IB1_BUFSZ", 7274 "type_ref": "CP_CE_IB1_BUFSZ" 7275 }, 7276 { 7277 "chips": ["gfx9"], 7278 "map": {"at": 197412, "to": "mm"}, 7279 "name": "CP_CE_IB2_BASE_LO", 7280 "type_ref": "CP_CE_IB2_BASE_LO" 7281 }, 7282 { 7283 "chips": ["gfx9"], 7284 "map": {"at": 197416, "to": "mm"}, 7285 "name": "CP_CE_IB2_BASE_HI", 7286 "type_ref": "CP_CE_IB2_BASE_HI" 7287 }, 7288 { 7289 "chips": ["gfx9"], 7290 "map": {"at": 197420, "to": "mm"}, 7291 "name": "CP_CE_IB2_BUFSZ", 7292 "type_ref": "CP_CE_IB2_BUFSZ" 7293 }, 7294 { 7295 "chips": ["gfx9"], 7296 "map": {"at": 197424, "to": "mm"}, 7297 "name": "CP_IB1_BASE_LO", 7298 "type_ref": "CP_CE_IB1_BASE_LO" 7299 }, 7300 { 7301 "chips": ["gfx9"], 7302 "map": {"at": 197428, "to": "mm"}, 7303 "name": "CP_IB1_BASE_HI", 7304 "type_ref": "CP_CE_IB1_BASE_HI" 7305 }, 7306 { 7307 "chips": ["gfx9"], 7308 "map": {"at": 197432, "to": "mm"}, 7309 "name": "CP_IB1_BUFSZ", 7310 "type_ref": "CP_CE_IB1_BUFSZ" 7311 }, 7312 { 7313 "chips": ["gfx9"], 7314 "map": {"at": 197436, "to": "mm"}, 7315 "name": "CP_IB2_BASE_LO", 7316 "type_ref": "CP_CE_IB2_BASE_LO" 7317 }, 7318 { 7319 "chips": ["gfx9"], 7320 "map": {"at": 197440, "to": "mm"}, 7321 "name": "CP_IB2_BASE_HI", 7322 "type_ref": "CP_CE_IB2_BASE_HI" 7323 }, 7324 { 7325 "chips": ["gfx9"], 7326 "map": {"at": 197444, "to": "mm"}, 7327 "name": "CP_IB2_BUFSZ", 7328 "type_ref": "CP_CE_IB2_BUFSZ" 7329 }, 7330 { 7331 "chips": ["gfx9"], 7332 "map": {"at": 197448, "to": "mm"}, 7333 "name": "CP_ST_BASE_LO", 7334 "type_ref": "CP_ST_BASE_LO" 7335 }, 7336 { 7337 "chips": ["gfx9"], 7338 "map": {"at": 197452, "to": "mm"}, 7339 "name": "CP_ST_BASE_HI", 7340 "type_ref": "CP_ST_BASE_HI" 7341 }, 7342 { 7343 "chips": ["gfx9"], 7344 "map": {"at": 197456, "to": "mm"}, 7345 "name": "CP_ST_BUFSZ", 7346 "type_ref": "CP_ST_BUFSZ" 7347 }, 7348 { 7349 "chips": ["gfx9"], 7350 "map": {"at": 197460, "to": "mm"}, 7351 "name": "CP_EOP_DONE_EVENT_CNTL", 7352 "type_ref": "CP_EOP_DONE_EVENT_CNTL" 7353 }, 7354 { 7355 "chips": ["gfx9"], 7356 "map": {"at": 197464, "to": "mm"}, 7357 "name": "CP_EOP_DONE_DATA_CNTL", 7358 "type_ref": "CP_EOP_DONE_DATA_CNTL" 7359 }, 7360 { 7361 "chips": ["gfx9"], 7362 "map": {"at": 197468, "to": "mm"}, 7363 "name": "CP_EOP_DONE_CNTX_ID" 7364 }, 7365 { 7366 "chips": ["gfx9"], 7367 "map": {"at": 197552, "to": "mm"}, 7368 "name": "CP_PFP_COMPLETION_STATUS", 7369 "type_ref": "CP_PFP_COMPLETION_STATUS" 7370 }, 7371 { 7372 "chips": ["gfx9"], 7373 "map": {"at": 197556, "to": "mm"}, 7374 "name": "CP_CE_COMPLETION_STATUS", 7375 "type_ref": "CP_PFP_COMPLETION_STATUS" 7376 }, 7377 { 7378 "chips": ["gfx9"], 7379 "map": {"at": 197560, "to": "mm"}, 7380 "name": "CP_PRED_NOT_VISIBLE", 7381 "type_ref": "CP_PRED_NOT_VISIBLE" 7382 }, 7383 { 7384 "chips": ["gfx9"], 7385 "map": {"at": 197568, "to": "mm"}, 7386 "name": "CP_PFP_METADATA_BASE_ADDR" 7387 }, 7388 { 7389 "chips": ["gfx9"], 7390 "map": {"at": 197572, "to": "mm"}, 7391 "name": "CP_PFP_METADATA_BASE_ADDR_HI", 7392 "type_ref": "CP_EOP_DONE_ADDR_HI" 7393 }, 7394 { 7395 "chips": ["gfx9"], 7396 "map": {"at": 197576, "to": "mm"}, 7397 "name": "CP_CE_METADATA_BASE_ADDR" 7398 }, 7399 { 7400 "chips": ["gfx9"], 7401 "map": {"at": 197580, "to": "mm"}, 7402 "name": "CP_CE_METADATA_BASE_ADDR_HI", 7403 "type_ref": "CP_EOP_DONE_ADDR_HI" 7404 }, 7405 { 7406 "chips": ["gfx9"], 7407 "map": {"at": 197584, "to": "mm"}, 7408 "name": "CP_DRAW_INDX_INDR_ADDR" 7409 }, 7410 { 7411 "chips": ["gfx9"], 7412 "map": {"at": 197588, "to": "mm"}, 7413 "name": "CP_DRAW_INDX_INDR_ADDR_HI", 7414 "type_ref": "CP_EOP_DONE_ADDR_HI" 7415 }, 7416 { 7417 "chips": ["gfx9"], 7418 "map": {"at": 197592, "to": "mm"}, 7419 "name": "CP_DISPATCH_INDR_ADDR" 7420 }, 7421 { 7422 "chips": ["gfx9"], 7423 "map": {"at": 197596, "to": "mm"}, 7424 "name": "CP_DISPATCH_INDR_ADDR_HI", 7425 "type_ref": "CP_EOP_DONE_ADDR_HI" 7426 }, 7427 { 7428 "chips": ["gfx9"], 7429 "map": {"at": 197600, "to": "mm"}, 7430 "name": "CP_INDEX_BASE_ADDR" 7431 }, 7432 { 7433 "chips": ["gfx9"], 7434 "map": {"at": 197604, "to": "mm"}, 7435 "name": "CP_INDEX_BASE_ADDR_HI", 7436 "type_ref": "CP_EOP_DONE_ADDR_HI" 7437 }, 7438 { 7439 "chips": ["gfx9"], 7440 "map": {"at": 197608, "to": "mm"}, 7441 "name": "CP_INDEX_TYPE", 7442 "type_ref": "CP_INDEX_TYPE" 7443 }, 7444 { 7445 "chips": ["gfx9"], 7446 "map": {"at": 197612, "to": "mm"}, 7447 "name": "CP_GDS_BKUP_ADDR" 7448 }, 7449 { 7450 "chips": ["gfx9"], 7451 "map": {"at": 197616, "to": "mm"}, 7452 "name": "CP_GDS_BKUP_ADDR_HI", 7453 "type_ref": "CP_EOP_DONE_ADDR_HI" 7454 }, 7455 { 7456 "chips": ["gfx9"], 7457 "map": {"at": 197620, "to": "mm"}, 7458 "name": "CP_SAMPLE_STATUS", 7459 "type_ref": "CP_SAMPLE_STATUS" 7460 }, 7461 { 7462 "chips": ["gfx9"], 7463 "map": {"at": 197624, "to": "mm"}, 7464 "name": "CP_ME_COHER_CNTL", 7465 "type_ref": "CP_ME_COHER_CNTL" 7466 }, 7467 { 7468 "chips": ["gfx9"], 7469 "map": {"at": 197628, "to": "mm"}, 7470 "name": "CP_ME_COHER_SIZE" 7471 }, 7472 { 7473 "chips": ["gfx9"], 7474 "map": {"at": 197632, "to": "mm"}, 7475 "name": "CP_ME_COHER_SIZE_HI", 7476 "type_ref": "CP_COHER_SIZE_HI" 7477 }, 7478 { 7479 "chips": ["gfx9"], 7480 "map": {"at": 197636, "to": "mm"}, 7481 "name": "CP_ME_COHER_BASE" 7482 }, 7483 { 7484 "chips": ["gfx9"], 7485 "map": {"at": 197640, "to": "mm"}, 7486 "name": "CP_ME_COHER_BASE_HI", 7487 "type_ref": "CP_COHER_BASE_HI" 7488 }, 7489 { 7490 "chips": ["gfx9"], 7491 "map": {"at": 197644, "to": "mm"}, 7492 "name": "CP_ME_COHER_STATUS", 7493 "type_ref": "CP_ME_COHER_STATUS" 7494 }, 7495 { 7496 "chips": ["gfx9"], 7497 "map": {"at": 197888, "to": "mm"}, 7498 "name": "RLC_GPM_PERF_COUNT_0", 7499 "type_ref": "RLC_GPM_PERF_COUNT_0" 7500 }, 7501 { 7502 "chips": ["gfx9"], 7503 "map": {"at": 197892, "to": "mm"}, 7504 "name": "RLC_GPM_PERF_COUNT_1", 7505 "type_ref": "RLC_GPM_PERF_COUNT_0" 7506 }, 7507 { 7508 "chips": ["gfx9"], 7509 "map": {"at": 198656, "to": "mm"}, 7510 "name": "GRBM_GFX_INDEX", 7511 "type_ref": "GRBM_GFX_INDEX" 7512 }, 7513 { 7514 "chips": ["gfx9"], 7515 "map": {"at": 198916, "to": "mm"}, 7516 "name": "VGT_GSVS_RING_SIZE" 7517 }, 7518 { 7519 "chips": ["gfx9"], 7520 "map": {"at": 198920, "to": "mm"}, 7521 "name": "VGT_PRIMITIVE_TYPE", 7522 "type_ref": "VGT_PRIMITIVE_TYPE" 7523 }, 7524 { 7525 "chips": ["gfx9"], 7526 "map": {"at": 198924, "to": "mm"}, 7527 "name": "VGT_INDEX_TYPE", 7528 "type_ref": "VGT_INDEX_TYPE" 7529 }, 7530 { 7531 "chips": ["gfx9"], 7532 "map": {"at": 198928, "to": "mm"}, 7533 "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_0" 7534 }, 7535 { 7536 "chips": ["gfx9"], 7537 "map": {"at": 198932, "to": "mm"}, 7538 "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_1" 7539 }, 7540 { 7541 "chips": ["gfx9"], 7542 "map": {"at": 198936, "to": "mm"}, 7543 "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_2" 7544 }, 7545 { 7546 "chips": ["gfx9"], 7547 "map": {"at": 198940, "to": "mm"}, 7548 "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_3" 7549 }, 7550 { 7551 "chips": ["gfx9"], 7552 "map": {"at": 198944, "to": "mm"}, 7553 "name": "VGT_MAX_VTX_INDX" 7554 }, 7555 { 7556 "chips": ["gfx9"], 7557 "map": {"at": 198948, "to": "mm"}, 7558 "name": "VGT_MIN_VTX_INDX" 7559 }, 7560 { 7561 "chips": ["gfx9"], 7562 "map": {"at": 198952, "to": "mm"}, 7563 "name": "VGT_INDX_OFFSET" 7564 }, 7565 { 7566 "chips": ["gfx9"], 7567 "map": {"at": 198956, "to": "mm"}, 7568 "name": "VGT_MULTI_PRIM_IB_RESET_EN", 7569 "type_ref": "VGT_MULTI_PRIM_IB_RESET_EN" 7570 }, 7571 { 7572 "chips": ["gfx9"], 7573 "map": {"at": 198960, "to": "mm"}, 7574 "name": "VGT_NUM_INDICES" 7575 }, 7576 { 7577 "chips": ["gfx9"], 7578 "map": {"at": 198964, "to": "mm"}, 7579 "name": "VGT_NUM_INSTANCES" 7580 }, 7581 { 7582 "chips": ["gfx9"], 7583 "map": {"at": 198968, "to": "mm"}, 7584 "name": "VGT_TF_RING_SIZE", 7585 "type_ref": "VGT_TF_RING_SIZE" 7586 }, 7587 { 7588 "chips": ["gfx9"], 7589 "map": {"at": 198972, "to": "mm"}, 7590 "name": "VGT_HS_OFFCHIP_PARAM", 7591 "type_ref": "VGT_HS_OFFCHIP_PARAM" 7592 }, 7593 { 7594 "chips": ["gfx9"], 7595 "map": {"at": 198976, "to": "mm"}, 7596 "name": "VGT_TF_MEMORY_BASE" 7597 }, 7598 { 7599 "chips": ["gfx9"], 7600 "map": {"at": 198980, "to": "mm"}, 7601 "name": "VGT_TF_MEMORY_BASE_HI", 7602 "type_ref": "DB_HTILE_DATA_BASE_HI" 7603 }, 7604 { 7605 "chips": ["gfx9"], 7606 "map": {"at": 198984, "to": "mm"}, 7607 "name": "WD_POS_BUF_BASE" 7608 }, 7609 { 7610 "chips": ["gfx9"], 7611 "map": {"at": 198988, "to": "mm"}, 7612 "name": "WD_POS_BUF_BASE_HI", 7613 "type_ref": "DB_HTILE_DATA_BASE_HI" 7614 }, 7615 { 7616 "chips": ["gfx9"], 7617 "map": {"at": 198992, "to": "mm"}, 7618 "name": "WD_CNTL_SB_BUF_BASE" 7619 }, 7620 { 7621 "chips": ["gfx9"], 7622 "map": {"at": 198996, "to": "mm"}, 7623 "name": "WD_CNTL_SB_BUF_BASE_HI", 7624 "type_ref": "DB_HTILE_DATA_BASE_HI" 7625 }, 7626 { 7627 "chips": ["gfx9"], 7628 "map": {"at": 199000, "to": "mm"}, 7629 "name": "WD_INDEX_BUF_BASE" 7630 }, 7631 { 7632 "chips": ["gfx9"], 7633 "map": {"at": 199004, "to": "mm"}, 7634 "name": "WD_INDEX_BUF_BASE_HI", 7635 "type_ref": "DB_HTILE_DATA_BASE_HI" 7636 }, 7637 { 7638 "chips": ["gfx9"], 7639 "map": {"at": 199008, "to": "mm"}, 7640 "name": "IA_MULTI_VGT_PARAM", 7641 "type_ref": "IA_MULTI_VGT_PARAM" 7642 }, 7643 { 7644 "chips": ["gfx9"], 7645 "map": {"at": 199016, "to": "mm"}, 7646 "name": "VGT_INSTANCE_BASE_ID" 7647 }, 7648 { 7649 "chips": ["gfx9"], 7650 "map": {"at": 199168, "to": "mm"}, 7651 "name": "PA_SU_LINE_STIPPLE_VALUE", 7652 "type_ref": "PA_SU_LINE_STIPPLE_VALUE" 7653 }, 7654 { 7655 "chips": ["gfx9"], 7656 "map": {"at": 199172, "to": "mm"}, 7657 "name": "PA_SC_LINE_STIPPLE_STATE", 7658 "type_ref": "PA_SC_LINE_STIPPLE_STATE" 7659 }, 7660 { 7661 "chips": ["gfx9"], 7662 "map": {"at": 199184, "to": "mm"}, 7663 "name": "PA_SC_SCREEN_EXTENT_MIN_0", 7664 "type_ref": "PA_SC_SCREEN_EXTENT_MIN_0" 7665 }, 7666 { 7667 "chips": ["gfx9"], 7668 "map": {"at": 199188, "to": "mm"}, 7669 "name": "PA_SC_SCREEN_EXTENT_MAX_0", 7670 "type_ref": "PA_SC_SCREEN_EXTENT_MIN_0" 7671 }, 7672 { 7673 "chips": ["gfx9"], 7674 "map": {"at": 199192, "to": "mm"}, 7675 "name": "PA_SC_SCREEN_EXTENT_MIN_1", 7676 "type_ref": "PA_SC_SCREEN_EXTENT_MIN_0" 7677 }, 7678 { 7679 "chips": ["gfx9"], 7680 "map": {"at": 199212, "to": "mm"}, 7681 "name": "PA_SC_SCREEN_EXTENT_MAX_1", 7682 "type_ref": "PA_SC_SCREEN_EXTENT_MIN_0" 7683 }, 7684 { 7685 "chips": ["gfx9"], 7686 "map": {"at": 199296, "to": "mm"}, 7687 "name": "PA_SC_P3D_TRAP_SCREEN_HV_EN", 7688 "type_ref": "PA_SC_P3D_TRAP_SCREEN_HV_EN" 7689 }, 7690 { 7691 "chips": ["gfx9"], 7692 "map": {"at": 199300, "to": "mm"}, 7693 "name": "PA_SC_P3D_TRAP_SCREEN_H", 7694 "type_ref": "PA_SC_P3D_TRAP_SCREEN_H" 7695 }, 7696 { 7697 "chips": ["gfx9"], 7698 "map": {"at": 199304, "to": "mm"}, 7699 "name": "PA_SC_P3D_TRAP_SCREEN_V", 7700 "type_ref": "PA_SC_P3D_TRAP_SCREEN_V" 7701 }, 7702 { 7703 "chips": ["gfx9"], 7704 "map": {"at": 199308, "to": "mm"}, 7705 "name": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE", 7706 "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE" 7707 }, 7708 { 7709 "chips": ["gfx9"], 7710 "map": {"at": 199312, "to": "mm"}, 7711 "name": "PA_SC_P3D_TRAP_SCREEN_COUNT", 7712 "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE" 7713 }, 7714 { 7715 "chips": ["gfx9"], 7716 "map": {"at": 199328, "to": "mm"}, 7717 "name": "PA_SC_HP3D_TRAP_SCREEN_HV_EN", 7718 "type_ref": "PA_SC_P3D_TRAP_SCREEN_HV_EN" 7719 }, 7720 { 7721 "chips": ["gfx9"], 7722 "map": {"at": 199332, "to": "mm"}, 7723 "name": "PA_SC_HP3D_TRAP_SCREEN_H", 7724 "type_ref": "PA_SC_P3D_TRAP_SCREEN_H" 7725 }, 7726 { 7727 "chips": ["gfx9"], 7728 "map": {"at": 199336, "to": "mm"}, 7729 "name": "PA_SC_HP3D_TRAP_SCREEN_V", 7730 "type_ref": "PA_SC_P3D_TRAP_SCREEN_V" 7731 }, 7732 { 7733 "chips": ["gfx9"], 7734 "map": {"at": 199340, "to": "mm"}, 7735 "name": "PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE", 7736 "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE" 7737 }, 7738 { 7739 "chips": ["gfx9"], 7740 "map": {"at": 199344, "to": "mm"}, 7741 "name": "PA_SC_HP3D_TRAP_SCREEN_COUNT", 7742 "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE" 7743 }, 7744 { 7745 "chips": ["gfx9"], 7746 "map": {"at": 199360, "to": "mm"}, 7747 "name": "PA_SC_TRAP_SCREEN_HV_EN", 7748 "type_ref": "PA_SC_P3D_TRAP_SCREEN_HV_EN" 7749 }, 7750 { 7751 "chips": ["gfx9"], 7752 "map": {"at": 199364, "to": "mm"}, 7753 "name": "PA_SC_TRAP_SCREEN_H", 7754 "type_ref": "PA_SC_P3D_TRAP_SCREEN_H" 7755 }, 7756 { 7757 "chips": ["gfx9"], 7758 "map": {"at": 199368, "to": "mm"}, 7759 "name": "PA_SC_TRAP_SCREEN_V", 7760 "type_ref": "PA_SC_P3D_TRAP_SCREEN_V" 7761 }, 7762 { 7763 "chips": ["gfx9"], 7764 "map": {"at": 199372, "to": "mm"}, 7765 "name": "PA_SC_TRAP_SCREEN_OCCURRENCE", 7766 "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE" 7767 }, 7768 { 7769 "chips": ["gfx9"], 7770 "map": {"at": 199376, "to": "mm"}, 7771 "name": "PA_SC_TRAP_SCREEN_COUNT", 7772 "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE" 7773 }, 7774 { 7775 "chips": ["gfx9"], 7776 "map": {"at": 199380, "to": "mm"}, 7777 "name": "PA_STATE_STEREO_X" 7778 }, 7779 { 7780 "chips": ["gfx9"], 7781 "map": {"at": 199872, "to": "mm"}, 7782 "name": "SQ_THREAD_TRACE_BASE" 7783 }, 7784 { 7785 "chips": ["gfx9"], 7786 "map": {"at": 199876, "to": "mm"}, 7787 "name": "SQ_THREAD_TRACE_SIZE", 7788 "type_ref": "SQ_THREAD_TRACE_SIZE" 7789 }, 7790 { 7791 "chips": ["gfx9"], 7792 "map": {"at": 199880, "to": "mm"}, 7793 "name": "SQ_THREAD_TRACE_MASK", 7794 "type_ref": "SQ_THREAD_TRACE_MASK" 7795 }, 7796 { 7797 "chips": ["gfx9"], 7798 "map": {"at": 199884, "to": "mm"}, 7799 "name": "SQ_THREAD_TRACE_TOKEN_MASK", 7800 "type_ref": "SQ_THREAD_TRACE_TOKEN_MASK" 7801 }, 7802 { 7803 "chips": ["gfx9"], 7804 "map": {"at": 199888, "to": "mm"}, 7805 "name": "SQ_THREAD_TRACE_PERF_MASK", 7806 "type_ref": "SQ_THREAD_TRACE_PERF_MASK" 7807 }, 7808 { 7809 "chips": ["gfx9"], 7810 "map": {"at": 199892, "to": "mm"}, 7811 "name": "SQ_THREAD_TRACE_CTRL", 7812 "type_ref": "SQ_THREAD_TRACE_CTRL" 7813 }, 7814 { 7815 "chips": ["gfx9"], 7816 "map": {"at": 199896, "to": "mm"}, 7817 "name": "SQ_THREAD_TRACE_MODE", 7818 "type_ref": "SQ_THREAD_TRACE_MODE" 7819 }, 7820 { 7821 "chips": ["gfx9"], 7822 "map": {"at": 199900, "to": "mm"}, 7823 "name": "SQ_THREAD_TRACE_BASE2", 7824 "type_ref": "SQ_THREAD_TRACE_BASE2" 7825 }, 7826 { 7827 "chips": ["gfx9"], 7828 "map": {"at": 199904, "to": "mm"}, 7829 "name": "SQ_THREAD_TRACE_TOKEN_MASK2" 7830 }, 7831 { 7832 "chips": ["gfx9"], 7833 "map": {"at": 199908, "to": "mm"}, 7834 "name": "SQ_THREAD_TRACE_WPTR", 7835 "type_ref": "SQ_THREAD_TRACE_WPTR" 7836 }, 7837 { 7838 "chips": ["gfx9"], 7839 "map": {"at": 199912, "to": "mm"}, 7840 "name": "SQ_THREAD_TRACE_STATUS", 7841 "type_ref": "SQ_THREAD_TRACE_STATUS" 7842 }, 7843 { 7844 "chips": ["gfx9"], 7845 "map": {"at": 199916, "to": "mm"}, 7846 "name": "SQ_THREAD_TRACE_HIWATER", 7847 "type_ref": "SQ_THREAD_TRACE_HIWATER" 7848 }, 7849 { 7850 "chips": ["gfx9"], 7851 "map": {"at": 199920, "to": "mm"}, 7852 "name": "SQ_THREAD_TRACE_CNTR" 7853 }, 7854 { 7855 "chips": ["gfx9"], 7856 "map": {"at": 199936, "to": "mm"}, 7857 "name": "SQ_THREAD_TRACE_USERDATA_0" 7858 }, 7859 { 7860 "chips": ["gfx9"], 7861 "map": {"at": 199940, "to": "mm"}, 7862 "name": "SQ_THREAD_TRACE_USERDATA_1" 7863 }, 7864 { 7865 "chips": ["gfx9"], 7866 "map": {"at": 199944, "to": "mm"}, 7867 "name": "SQ_THREAD_TRACE_USERDATA_2" 7868 }, 7869 { 7870 "chips": ["gfx9"], 7871 "map": {"at": 199948, "to": "mm"}, 7872 "name": "SQ_THREAD_TRACE_USERDATA_3" 7873 }, 7874 { 7875 "chips": ["gfx9"], 7876 "map": {"at": 199968, "to": "mm"}, 7877 "name": "SQC_CACHES", 7878 "type_ref": "SQC_CACHES" 7879 }, 7880 { 7881 "chips": ["gfx9"], 7882 "map": {"at": 199972, "to": "mm"}, 7883 "name": "SQC_WRITEBACK", 7884 "type_ref": "SQC_WRITEBACK" 7885 }, 7886 { 7887 "chips": ["gfx9"], 7888 "map": {"at": 200192, "to": "mm"}, 7889 "name": "TA_CS_BC_BASE_ADDR" 7890 }, 7891 { 7892 "chips": ["gfx9"], 7893 "map": {"at": 200196, "to": "mm"}, 7894 "name": "TA_CS_BC_BASE_ADDR_HI", 7895 "type_ref": "TA_BC_BASE_ADDR_HI" 7896 }, 7897 { 7898 "chips": ["gfx9"], 7899 "map": {"at": 200448, "to": "mm"}, 7900 "name": "DB_OCCLUSION_COUNT0_LOW" 7901 }, 7902 { 7903 "chips": ["gfx9"], 7904 "map": {"at": 200452, "to": "mm"}, 7905 "name": "DB_OCCLUSION_COUNT0_HI", 7906 "type_ref": "DB_OCCLUSION_COUNT0_HI" 7907 }, 7908 { 7909 "chips": ["gfx9"], 7910 "map": {"at": 200456, "to": "mm"}, 7911 "name": "DB_OCCLUSION_COUNT1_LOW" 7912 }, 7913 { 7914 "chips": ["gfx9"], 7915 "map": {"at": 200460, "to": "mm"}, 7916 "name": "DB_OCCLUSION_COUNT1_HI", 7917 "type_ref": "DB_OCCLUSION_COUNT0_HI" 7918 }, 7919 { 7920 "chips": ["gfx9"], 7921 "map": {"at": 200464, "to": "mm"}, 7922 "name": "DB_OCCLUSION_COUNT2_LOW" 7923 }, 7924 { 7925 "chips": ["gfx9"], 7926 "map": {"at": 200468, "to": "mm"}, 7927 "name": "DB_OCCLUSION_COUNT2_HI", 7928 "type_ref": "DB_OCCLUSION_COUNT0_HI" 7929 }, 7930 { 7931 "chips": ["gfx9"], 7932 "map": {"at": 200472, "to": "mm"}, 7933 "name": "DB_OCCLUSION_COUNT3_LOW" 7934 }, 7935 { 7936 "chips": ["gfx9"], 7937 "map": {"at": 200476, "to": "mm"}, 7938 "name": "DB_OCCLUSION_COUNT3_HI", 7939 "type_ref": "DB_OCCLUSION_COUNT0_HI" 7940 }, 7941 { 7942 "chips": ["gfx9"], 7943 "map": {"at": 200696, "to": "mm"}, 7944 "name": "DB_ZPASS_COUNT_LOW" 7945 }, 7946 { 7947 "chips": ["gfx9"], 7948 "map": {"at": 200700, "to": "mm"}, 7949 "name": "DB_ZPASS_COUNT_HI", 7950 "type_ref": "DB_OCCLUSION_COUNT0_HI" 7951 }, 7952 { 7953 "chips": ["gfx9"], 7954 "map": {"at": 200704, "to": "mm"}, 7955 "name": "GDS_RD_ADDR" 7956 }, 7957 { 7958 "chips": ["gfx9"], 7959 "map": {"at": 200708, "to": "mm"}, 7960 "name": "GDS_RD_DATA" 7961 }, 7962 { 7963 "chips": ["gfx9"], 7964 "map": {"at": 200712, "to": "mm"}, 7965 "name": "GDS_RD_BURST_ADDR" 7966 }, 7967 { 7968 "chips": ["gfx9"], 7969 "map": {"at": 200716, "to": "mm"}, 7970 "name": "GDS_RD_BURST_COUNT" 7971 }, 7972 { 7973 "chips": ["gfx9"], 7974 "map": {"at": 200720, "to": "mm"}, 7975 "name": "GDS_RD_BURST_DATA" 7976 }, 7977 { 7978 "chips": ["gfx9"], 7979 "map": {"at": 200724, "to": "mm"}, 7980 "name": "GDS_WR_ADDR" 7981 }, 7982 { 7983 "chips": ["gfx9"], 7984 "map": {"at": 200728, "to": "mm"}, 7985 "name": "GDS_WR_DATA" 7986 }, 7987 { 7988 "chips": ["gfx9"], 7989 "map": {"at": 200732, "to": "mm"}, 7990 "name": "GDS_WR_BURST_ADDR" 7991 }, 7992 { 7993 "chips": ["gfx9"], 7994 "map": {"at": 200736, "to": "mm"}, 7995 "name": "GDS_WR_BURST_DATA" 7996 }, 7997 { 7998 "chips": ["gfx9"], 7999 "map": {"at": 200740, "to": "mm"}, 8000 "name": "GDS_WRITE_COMPLETE" 8001 }, 8002 { 8003 "chips": ["gfx9"], 8004 "map": {"at": 200744, "to": "mm"}, 8005 "name": "GDS_ATOM_CNTL", 8006 "type_ref": "GDS_ATOM_CNTL" 8007 }, 8008 { 8009 "chips": ["gfx9"], 8010 "map": {"at": 200748, "to": "mm"}, 8011 "name": "GDS_ATOM_COMPLETE", 8012 "type_ref": "GDS_ATOM_COMPLETE" 8013 }, 8014 { 8015 "chips": ["gfx9"], 8016 "map": {"at": 200752, "to": "mm"}, 8017 "name": "GDS_ATOM_BASE", 8018 "type_ref": "GDS_ATOM_BASE" 8019 }, 8020 { 8021 "chips": ["gfx9"], 8022 "map": {"at": 200756, "to": "mm"}, 8023 "name": "GDS_ATOM_SIZE", 8024 "type_ref": "GDS_ATOM_SIZE" 8025 }, 8026 { 8027 "chips": ["gfx9"], 8028 "map": {"at": 200760, "to": "mm"}, 8029 "name": "GDS_ATOM_OFFSET0", 8030 "type_ref": "GDS_ATOM_OFFSET0" 8031 }, 8032 { 8033 "chips": ["gfx9"], 8034 "map": {"at": 200764, "to": "mm"}, 8035 "name": "GDS_ATOM_OFFSET1", 8036 "type_ref": "GDS_ATOM_OFFSET1" 8037 }, 8038 { 8039 "chips": ["gfx9"], 8040 "map": {"at": 200768, "to": "mm"}, 8041 "name": "GDS_ATOM_DST" 8042 }, 8043 { 8044 "chips": ["gfx9"], 8045 "map": {"at": 200772, "to": "mm"}, 8046 "name": "GDS_ATOM_OP", 8047 "type_ref": "GDS_ATOM_OP" 8048 }, 8049 { 8050 "chips": ["gfx9"], 8051 "map": {"at": 200776, "to": "mm"}, 8052 "name": "GDS_ATOM_SRC0" 8053 }, 8054 { 8055 "chips": ["gfx9"], 8056 "map": {"at": 200780, "to": "mm"}, 8057 "name": "GDS_ATOM_SRC0_U" 8058 }, 8059 { 8060 "chips": ["gfx9"], 8061 "map": {"at": 200784, "to": "mm"}, 8062 "name": "GDS_ATOM_SRC1" 8063 }, 8064 { 8065 "chips": ["gfx9"], 8066 "map": {"at": 200788, "to": "mm"}, 8067 "name": "GDS_ATOM_SRC1_U" 8068 }, 8069 { 8070 "chips": ["gfx9"], 8071 "map": {"at": 200792, "to": "mm"}, 8072 "name": "GDS_ATOM_READ0" 8073 }, 8074 { 8075 "chips": ["gfx9"], 8076 "map": {"at": 200796, "to": "mm"}, 8077 "name": "GDS_ATOM_READ0_U" 8078 }, 8079 { 8080 "chips": ["gfx9"], 8081 "map": {"at": 200800, "to": "mm"}, 8082 "name": "GDS_ATOM_READ1" 8083 }, 8084 { 8085 "chips": ["gfx9"], 8086 "map": {"at": 200804, "to": "mm"}, 8087 "name": "GDS_ATOM_READ1_U" 8088 }, 8089 { 8090 "chips": ["gfx9"], 8091 "map": {"at": 200808, "to": "mm"}, 8092 "name": "GDS_GWS_RESOURCE_CNTL", 8093 "type_ref": "GDS_GWS_RESOURCE_CNTL" 8094 }, 8095 { 8096 "chips": ["gfx9"], 8097 "map": {"at": 200812, "to": "mm"}, 8098 "name": "GDS_GWS_RESOURCE", 8099 "type_ref": "GDS_GWS_RESOURCE" 8100 }, 8101 { 8102 "chips": ["gfx9"], 8103 "map": {"at": 200816, "to": "mm"}, 8104 "name": "GDS_GWS_RESOURCE_CNT", 8105 "type_ref": "GDS_GWS_RESOURCE_CNT" 8106 }, 8107 { 8108 "chips": ["gfx9"], 8109 "map": {"at": 200820, "to": "mm"}, 8110 "name": "GDS_OA_CNTL", 8111 "type_ref": "GDS_OA_CNTL" 8112 }, 8113 { 8114 "chips": ["gfx9"], 8115 "map": {"at": 200824, "to": "mm"}, 8116 "name": "GDS_OA_COUNTER" 8117 }, 8118 { 8119 "chips": ["gfx9"], 8120 "map": {"at": 200828, "to": "mm"}, 8121 "name": "GDS_OA_ADDRESS", 8122 "type_ref": "GDS_OA_ADDRESS" 8123 }, 8124 { 8125 "chips": ["gfx9"], 8126 "map": {"at": 200832, "to": "mm"}, 8127 "name": "GDS_OA_INCDEC", 8128 "type_ref": "GDS_OA_INCDEC" 8129 }, 8130 { 8131 "chips": ["gfx9"], 8132 "map": {"at": 200836, "to": "mm"}, 8133 "name": "GDS_OA_RING_SIZE" 8134 }, 8135 { 8136 "chips": ["gfx9"], 8137 "map": {"at": 200960, "to": "mm"}, 8138 "name": "SPI_CONFIG_CNTL", 8139 "type_ref": "SPI_CONFIG_CNTL" 8140 }, 8141 { 8142 "chips": ["gfx9"], 8143 "map": {"at": 200964, "to": "mm"}, 8144 "name": "SPI_CONFIG_CNTL_1", 8145 "type_ref": "SPI_CONFIG_CNTL_1" 8146 }, 8147 { 8148 "chips": ["gfx9"], 8149 "map": {"at": 200968, "to": "mm"}, 8150 "name": "SPI_CONFIG_CNTL_2", 8151 "type_ref": "SPI_CONFIG_CNTL_2" 8152 }, 8153 { 8154 "chips": ["gfx9"], 8155 "map": {"at": 200972, "to": "mm"}, 8156 "name": "SPI_WAVE_LIMIT_CNTL", 8157 "type_ref": "SPI_WAVE_LIMIT_CNTL" 8158 }, 8159 { 8160 "chips": ["gfx9"], 8161 "map": {"at": 212992, "to": "mm"}, 8162 "name": "CPG_PERFCOUNTER1_LO" 8163 }, 8164 { 8165 "chips": ["gfx9"], 8166 "map": {"at": 212996, "to": "mm"}, 8167 "name": "CPG_PERFCOUNTER1_HI" 8168 }, 8169 { 8170 "chips": ["gfx9"], 8171 "map": {"at": 213000, "to": "mm"}, 8172 "name": "CPG_PERFCOUNTER0_LO" 8173 }, 8174 { 8175 "chips": ["gfx9"], 8176 "map": {"at": 213004, "to": "mm"}, 8177 "name": "CPG_PERFCOUNTER0_HI" 8178 }, 8179 { 8180 "chips": ["gfx9"], 8181 "map": {"at": 213008, "to": "mm"}, 8182 "name": "CPC_PERFCOUNTER1_LO" 8183 }, 8184 { 8185 "chips": ["gfx9"], 8186 "map": {"at": 213012, "to": "mm"}, 8187 "name": "CPC_PERFCOUNTER1_HI" 8188 }, 8189 { 8190 "chips": ["gfx9"], 8191 "map": {"at": 213016, "to": "mm"}, 8192 "name": "CPC_PERFCOUNTER0_LO" 8193 }, 8194 { 8195 "chips": ["gfx9"], 8196 "map": {"at": 213020, "to": "mm"}, 8197 "name": "CPC_PERFCOUNTER0_HI" 8198 }, 8199 { 8200 "chips": ["gfx9"], 8201 "map": {"at": 213024, "to": "mm"}, 8202 "name": "CPF_PERFCOUNTER1_LO" 8203 }, 8204 { 8205 "chips": ["gfx9"], 8206 "map": {"at": 213028, "to": "mm"}, 8207 "name": "CPF_PERFCOUNTER1_HI" 8208 }, 8209 { 8210 "chips": ["gfx9"], 8211 "map": {"at": 213032, "to": "mm"}, 8212 "name": "CPF_PERFCOUNTER0_LO" 8213 }, 8214 { 8215 "chips": ["gfx9"], 8216 "map": {"at": 213036, "to": "mm"}, 8217 "name": "CPF_PERFCOUNTER0_HI" 8218 }, 8219 { 8220 "chips": ["gfx9"], 8221 "map": {"at": 213040, "to": "mm"}, 8222 "name": "CPF_LATENCY_STATS_DATA" 8223 }, 8224 { 8225 "chips": ["gfx9"], 8226 "map": {"at": 213044, "to": "mm"}, 8227 "name": "CPG_LATENCY_STATS_DATA" 8228 }, 8229 { 8230 "chips": ["gfx9"], 8231 "map": {"at": 213048, "to": "mm"}, 8232 "name": "CPC_LATENCY_STATS_DATA" 8233 }, 8234 { 8235 "chips": ["gfx9"], 8236 "map": {"at": 213248, "to": "mm"}, 8237 "name": "GRBM_PERFCOUNTER0_LO" 8238 }, 8239 { 8240 "chips": ["gfx9"], 8241 "map": {"at": 213252, "to": "mm"}, 8242 "name": "GRBM_PERFCOUNTER0_HI" 8243 }, 8244 { 8245 "chips": ["gfx9"], 8246 "map": {"at": 213260, "to": "mm"}, 8247 "name": "GRBM_PERFCOUNTER1_LO" 8248 }, 8249 { 8250 "chips": ["gfx9"], 8251 "map": {"at": 213264, "to": "mm"}, 8252 "name": "GRBM_PERFCOUNTER1_HI" 8253 }, 8254 { 8255 "chips": ["gfx9"], 8256 "map": {"at": 213268, "to": "mm"}, 8257 "name": "GRBM_SE0_PERFCOUNTER_LO" 8258 }, 8259 { 8260 "chips": ["gfx9"], 8261 "map": {"at": 213272, "to": "mm"}, 8262 "name": "GRBM_SE0_PERFCOUNTER_HI" 8263 }, 8264 { 8265 "chips": ["gfx9"], 8266 "map": {"at": 213276, "to": "mm"}, 8267 "name": "GRBM_SE1_PERFCOUNTER_LO" 8268 }, 8269 { 8270 "chips": ["gfx9"], 8271 "map": {"at": 213280, "to": "mm"}, 8272 "name": "GRBM_SE1_PERFCOUNTER_HI" 8273 }, 8274 { 8275 "chips": ["gfx9"], 8276 "map": {"at": 213284, "to": "mm"}, 8277 "name": "GRBM_SE2_PERFCOUNTER_LO" 8278 }, 8279 { 8280 "chips": ["gfx9"], 8281 "map": {"at": 213288, "to": "mm"}, 8282 "name": "GRBM_SE2_PERFCOUNTER_HI" 8283 }, 8284 { 8285 "chips": ["gfx9"], 8286 "map": {"at": 213292, "to": "mm"}, 8287 "name": "GRBM_SE3_PERFCOUNTER_LO" 8288 }, 8289 { 8290 "chips": ["gfx9"], 8291 "map": {"at": 213296, "to": "mm"}, 8292 "name": "GRBM_SE3_PERFCOUNTER_HI" 8293 }, 8294 { 8295 "chips": ["gfx9"], 8296 "map": {"at": 213504, "to": "mm"}, 8297 "name": "WD_PERFCOUNTER0_LO" 8298 }, 8299 { 8300 "chips": ["gfx9"], 8301 "map": {"at": 213508, "to": "mm"}, 8302 "name": "WD_PERFCOUNTER0_HI" 8303 }, 8304 { 8305 "chips": ["gfx9"], 8306 "map": {"at": 213512, "to": "mm"}, 8307 "name": "WD_PERFCOUNTER1_LO" 8308 }, 8309 { 8310 "chips": ["gfx9"], 8311 "map": {"at": 213516, "to": "mm"}, 8312 "name": "WD_PERFCOUNTER1_HI" 8313 }, 8314 { 8315 "chips": ["gfx9"], 8316 "map": {"at": 213520, "to": "mm"}, 8317 "name": "WD_PERFCOUNTER2_LO" 8318 }, 8319 { 8320 "chips": ["gfx9"], 8321 "map": {"at": 213524, "to": "mm"}, 8322 "name": "WD_PERFCOUNTER2_HI" 8323 }, 8324 { 8325 "chips": ["gfx9"], 8326 "map": {"at": 213528, "to": "mm"}, 8327 "name": "WD_PERFCOUNTER3_LO" 8328 }, 8329 { 8330 "chips": ["gfx9"], 8331 "map": {"at": 213532, "to": "mm"}, 8332 "name": "WD_PERFCOUNTER3_HI" 8333 }, 8334 { 8335 "chips": ["gfx9"], 8336 "map": {"at": 213536, "to": "mm"}, 8337 "name": "IA_PERFCOUNTER0_LO" 8338 }, 8339 { 8340 "chips": ["gfx9"], 8341 "map": {"at": 213540, "to": "mm"}, 8342 "name": "IA_PERFCOUNTER0_HI" 8343 }, 8344 { 8345 "chips": ["gfx9"], 8346 "map": {"at": 213544, "to": "mm"}, 8347 "name": "IA_PERFCOUNTER1_LO" 8348 }, 8349 { 8350 "chips": ["gfx9"], 8351 "map": {"at": 213548, "to": "mm"}, 8352 "name": "IA_PERFCOUNTER1_HI" 8353 }, 8354 { 8355 "chips": ["gfx9"], 8356 "map": {"at": 213552, "to": "mm"}, 8357 "name": "IA_PERFCOUNTER2_LO" 8358 }, 8359 { 8360 "chips": ["gfx9"], 8361 "map": {"at": 213556, "to": "mm"}, 8362 "name": "IA_PERFCOUNTER2_HI" 8363 }, 8364 { 8365 "chips": ["gfx9"], 8366 "map": {"at": 213560, "to": "mm"}, 8367 "name": "IA_PERFCOUNTER3_LO" 8368 }, 8369 { 8370 "chips": ["gfx9"], 8371 "map": {"at": 213564, "to": "mm"}, 8372 "name": "IA_PERFCOUNTER3_HI" 8373 }, 8374 { 8375 "chips": ["gfx9"], 8376 "map": {"at": 213568, "to": "mm"}, 8377 "name": "VGT_PERFCOUNTER0_LO" 8378 }, 8379 { 8380 "chips": ["gfx9"], 8381 "map": {"at": 213572, "to": "mm"}, 8382 "name": "VGT_PERFCOUNTER0_HI" 8383 }, 8384 { 8385 "chips": ["gfx9"], 8386 "map": {"at": 213576, "to": "mm"}, 8387 "name": "VGT_PERFCOUNTER1_LO" 8388 }, 8389 { 8390 "chips": ["gfx9"], 8391 "map": {"at": 213580, "to": "mm"}, 8392 "name": "VGT_PERFCOUNTER1_HI" 8393 }, 8394 { 8395 "chips": ["gfx9"], 8396 "map": {"at": 213584, "to": "mm"}, 8397 "name": "VGT_PERFCOUNTER2_LO" 8398 }, 8399 { 8400 "chips": ["gfx9"], 8401 "map": {"at": 213588, "to": "mm"}, 8402 "name": "VGT_PERFCOUNTER2_HI" 8403 }, 8404 { 8405 "chips": ["gfx9"], 8406 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8969 "chips": ["gfx9"], 8970 "map": {"at": 216648, "to": "mm"}, 8971 "name": "TCA_PERFCOUNTER1_LO" 8972 }, 8973 { 8974 "chips": ["gfx9"], 8975 "map": {"at": 216652, "to": "mm"}, 8976 "name": "TCA_PERFCOUNTER1_HI" 8977 }, 8978 { 8979 "chips": ["gfx9"], 8980 "map": {"at": 216656, "to": "mm"}, 8981 "name": "TCA_PERFCOUNTER2_LO" 8982 }, 8983 { 8984 "chips": ["gfx9"], 8985 "map": {"at": 216660, "to": "mm"}, 8986 "name": "TCA_PERFCOUNTER2_HI" 8987 }, 8988 { 8989 "chips": ["gfx9"], 8990 "map": {"at": 216664, "to": "mm"}, 8991 "name": "TCA_PERFCOUNTER3_LO" 8992 }, 8993 { 8994 "chips": ["gfx9"], 8995 "map": {"at": 216668, "to": "mm"}, 8996 "name": "TCA_PERFCOUNTER3_HI" 8997 }, 8998 { 8999 "chips": ["gfx9"], 9000 "map": {"at": 217112, "to": "mm"}, 9001 "name": "CB_PERFCOUNTER0_LO" 9002 }, 9003 { 9004 "chips": ["gfx9"], 9005 "map": {"at": 217116, "to": "mm"}, 9006 "name": "CB_PERFCOUNTER0_HI" 9007 }, 9008 { 9009 "chips": ["gfx9"], 9010 "map": {"at": 217120, "to": "mm"}, 9011 "name": "CB_PERFCOUNTER1_LO" 9012 }, 9013 { 9014 "chips": ["gfx9"], 9015 "map": {"at": 217124, "to": "mm"}, 9016 "name": "CB_PERFCOUNTER1_HI" 9017 }, 9018 { 9019 "chips": ["gfx9"], 9020 "map": {"at": 217128, "to": "mm"}, 9021 "name": "CB_PERFCOUNTER2_LO" 9022 }, 9023 { 9024 "chips": ["gfx9"], 9025 "map": {"at": 217132, "to": "mm"}, 9026 "name": "CB_PERFCOUNTER2_HI" 9027 }, 9028 { 9029 "chips": ["gfx9"], 9030 "map": {"at": 217136, "to": "mm"}, 9031 "name": "CB_PERFCOUNTER3_LO" 9032 }, 9033 { 9034 "chips": ["gfx9"], 9035 "map": {"at": 217140, "to": "mm"}, 9036 "name": "CB_PERFCOUNTER3_HI" 9037 }, 9038 { 9039 "chips": ["gfx9"], 9040 "map": {"at": 217344, "to": "mm"}, 9041 "name": "DB_PERFCOUNTER0_LO" 9042 }, 9043 { 9044 "chips": ["gfx9"], 9045 "map": {"at": 217348, "to": "mm"}, 9046 "name": "DB_PERFCOUNTER0_HI" 9047 }, 9048 { 9049 "chips": ["gfx9"], 9050 "map": {"at": 217352, "to": "mm"}, 9051 "name": "DB_PERFCOUNTER1_LO" 9052 }, 9053 { 9054 "chips": ["gfx9"], 9055 "map": {"at": 217356, "to": "mm"}, 9056 "name": "DB_PERFCOUNTER1_HI" 9057 }, 9058 { 9059 "chips": ["gfx9"], 9060 "map": {"at": 217360, "to": "mm"}, 9061 "name": "DB_PERFCOUNTER2_LO" 9062 }, 9063 { 9064 "chips": ["gfx9"], 9065 "map": {"at": 217364, "to": "mm"}, 9066 "name": "DB_PERFCOUNTER2_HI" 9067 }, 9068 { 9069 "chips": ["gfx9"], 9070 "map": {"at": 217368, "to": "mm"}, 9071 "name": "DB_PERFCOUNTER3_LO" 9072 }, 9073 { 9074 "chips": ["gfx9"], 9075 "map": {"at": 217372, "to": "mm"}, 9076 "name": "DB_PERFCOUNTER3_HI" 9077 }, 9078 { 9079 "chips": ["gfx9"], 9080 "map": {"at": 217600, "to": "mm"}, 9081 "name": "RLC_PERFCOUNTER0_LO" 9082 }, 9083 { 9084 "chips": ["gfx9"], 9085 "map": {"at": 217604, "to": "mm"}, 9086 "name": "RLC_PERFCOUNTER0_HI" 9087 }, 9088 { 9089 "chips": ["gfx9"], 9090 "map": {"at": 217608, "to": "mm"}, 9091 "name": "RLC_PERFCOUNTER1_LO" 9092 }, 9093 { 9094 "chips": ["gfx9"], 9095 "map": {"at": 217612, "to": "mm"}, 9096 "name": "RLC_PERFCOUNTER1_HI" 9097 }, 9098 { 9099 "chips": ["gfx9"], 9100 "map": {"at": 217856, "to": "mm"}, 9101 "name": "RMI_PERFCOUNTER0_LO" 9102 }, 9103 { 9104 "chips": ["gfx9"], 9105 "map": {"at": 217860, "to": "mm"}, 9106 "name": "RMI_PERFCOUNTER0_HI" 9107 }, 9108 { 9109 "chips": ["gfx9"], 9110 "map": {"at": 217864, "to": "mm"}, 9111 "name": "RMI_PERFCOUNTER1_LO" 9112 }, 9113 { 9114 "chips": ["gfx9"], 9115 "map": {"at": 217868, "to": "mm"}, 9116 "name": "RMI_PERFCOUNTER1_HI" 9117 }, 9118 { 9119 "chips": ["gfx9"], 9120 "map": {"at": 217872, "to": "mm"}, 9121 "name": "RMI_PERFCOUNTER2_LO" 9122 }, 9123 { 9124 "chips": ["gfx9"], 9125 "map": {"at": 217876, "to": "mm"}, 9126 "name": "RMI_PERFCOUNTER2_HI" 9127 }, 9128 { 9129 "chips": ["gfx9"], 9130 "map": {"at": 217880, "to": "mm"}, 9131 "name": "RMI_PERFCOUNTER3_LO" 9132 }, 9133 { 9134 "chips": ["gfx9"], 9135 "map": {"at": 217884, "to": "mm"}, 9136 "name": "RMI_PERFCOUNTER3_HI" 9137 }, 9138 { 9139 "chips": ["gfx9"], 9140 "map": {"at": 218112, "to": "mm"}, 9141 "name": "ATC_L2_PERFCOUNTER_LO" 9142 }, 9143 { 9144 "chips": ["gfx9"], 9145 "map": {"at": 218116, "to": "mm"}, 9146 "name": "ATC_L2_PERFCOUNTER_HI", 9147 "type_ref": "ATC_L2_PERFCOUNTER_HI" 9148 }, 9149 { 9150 "chips": ["gfx9"], 9151 "map": {"at": 218144, "to": "mm"}, 9152 "name": "MC_VM_L2_PERFCOUNTER_LO" 9153 }, 9154 { 9155 "chips": ["gfx9"], 9156 "map": {"at": 218148, "to": "mm"}, 9157 "name": "MC_VM_L2_PERFCOUNTER_HI", 9158 "type_ref": "ATC_L2_PERFCOUNTER_HI" 9159 }, 9160 { 9161 "chips": ["gfx9"], 9162 "map": {"at": 221184, "to": "mm"}, 9163 "name": "CPG_PERFCOUNTER1_SELECT", 9164 "type_ref": "CPG_PERFCOUNTER1_SELECT" 9165 }, 9166 { 9167 "chips": ["gfx9"], 9168 "map": {"at": 221188, "to": "mm"}, 9169 "name": "CPG_PERFCOUNTER0_SELECT1", 9170 "type_ref": "CPG_PERFCOUNTER0_SELECT1" 9171 }, 9172 { 9173 "chips": ["gfx9"], 9174 "map": {"at": 221192, "to": "mm"}, 9175 "name": "CPG_PERFCOUNTER0_SELECT", 9176 "type_ref": "CPG_PERFCOUNTER1_SELECT" 9177 }, 9178 { 9179 "chips": ["gfx9"], 9180 "map": {"at": 221196, "to": "mm"}, 9181 "name": "CPC_PERFCOUNTER1_SELECT", 9182 "type_ref": "CPG_PERFCOUNTER1_SELECT" 9183 }, 9184 { 9185 "chips": ["gfx9"], 9186 "map": {"at": 221200, "to": "mm"}, 9187 "name": "CPC_PERFCOUNTER0_SELECT1", 9188 "type_ref": "CPG_PERFCOUNTER0_SELECT1" 9189 }, 9190 { 9191 "chips": ["gfx9"], 9192 "map": {"at": 221204, "to": "mm"}, 9193 "name": "CPF_PERFCOUNTER1_SELECT", 9194 "type_ref": "CPG_PERFCOUNTER1_SELECT" 9195 }, 9196 { 9197 "chips": ["gfx9"], 9198 "map": {"at": 221208, "to": "mm"}, 9199 "name": "CPF_PERFCOUNTER0_SELECT1", 9200 "type_ref": "CPG_PERFCOUNTER0_SELECT1" 9201 }, 9202 { 9203 "chips": ["gfx9"], 9204 "map": {"at": 221212, "to": "mm"}, 9205 "name": "CPF_PERFCOUNTER0_SELECT", 9206 "type_ref": "CPG_PERFCOUNTER1_SELECT" 9207 }, 9208 { 9209 "chips": ["gfx9"], 9210 "map": {"at": 221216, "to": "mm"}, 9211 "name": "CP_PERFMON_CNTL", 9212 "type_ref": "CP_PERFMON_CNTL" 9213 }, 9214 { 9215 "chips": ["gfx9"], 9216 "map": {"at": 221220, "to": "mm"}, 9217 "name": "CPC_PERFCOUNTER0_SELECT", 9218 "type_ref": "CPG_PERFCOUNTER1_SELECT" 9219 }, 9220 { 9221 "chips": ["gfx9"], 9222 "map": {"at": 221224, "to": "mm"}, 9223 "name": "CPF_TC_PERF_COUNTER_WINDOW_SELECT", 9224 "type_ref": "CPF_TC_PERF_COUNTER_WINDOW_SELECT" 9225 }, 9226 { 9227 "chips": ["gfx9"], 9228 "map": {"at": 221228, "to": "mm"}, 9229 "name": "CPG_TC_PERF_COUNTER_WINDOW_SELECT", 9230 "type_ref": "CPG_TC_PERF_COUNTER_WINDOW_SELECT" 9231 }, 9232 { 9233 "chips": ["gfx9"], 9234 "map": {"at": 221232, "to": "mm"}, 9235 "name": "CPF_LATENCY_STATS_SELECT", 9236 "type_ref": "CPF_LATENCY_STATS_SELECT" 9237 }, 9238 { 9239 "chips": ["gfx9"], 9240 "map": {"at": 221236, "to": "mm"}, 9241 "name": "CPG_LATENCY_STATS_SELECT", 9242 "type_ref": "CPG_LATENCY_STATS_SELECT" 9243 }, 9244 { 9245 "chips": ["gfx9"], 9246 "map": {"at": 221240, "to": "mm"}, 9247 "name": "CPC_LATENCY_STATS_SELECT", 9248 "type_ref": "CPC_LATENCY_STATS_SELECT" 9249 }, 9250 { 9251 "chips": ["gfx9"], 9252 "map": {"at": 221248, "to": "mm"}, 9253 "name": "CP_DRAW_OBJECT" 9254 }, 9255 { 9256 "chips": ["gfx9"], 9257 "map": {"at": 221252, "to": "mm"}, 9258 "name": "CP_DRAW_OBJECT_COUNTER", 9259 "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE" 9260 }, 9261 { 9262 "chips": ["gfx9"], 9263 "map": {"at": 221256, "to": "mm"}, 9264 "name": "CP_DRAW_WINDOW_MASK_HI" 9265 }, 9266 { 9267 "chips": ["gfx9"], 9268 "map": {"at": 221260, "to": "mm"}, 9269 "name": "CP_DRAW_WINDOW_HI" 9270 }, 9271 { 9272 "chips": ["gfx9"], 9273 "map": {"at": 221264, "to": "mm"}, 9274 "name": "CP_DRAW_WINDOW_LO", 9275 "type_ref": "CP_DRAW_WINDOW_LO" 9276 }, 9277 { 9278 "chips": ["gfx9"], 9279 "map": {"at": 221268, "to": "mm"}, 9280 "name": "CP_DRAW_WINDOW_CNTL", 9281 "type_ref": "CP_DRAW_WINDOW_CNTL" 9282 }, 9283 { 9284 "chips": ["gfx9"], 9285 "map": {"at": 221440, "to": "mm"}, 9286 "name": "GRBM_PERFCOUNTER0_SELECT", 9287 "type_ref": "GRBM_PERFCOUNTER0_SELECT" 9288 }, 9289 { 9290 "chips": ["gfx9"], 9291 "map": {"at": 221444, "to": "mm"}, 9292 "name": "GRBM_PERFCOUNTER1_SELECT", 9293 "type_ref": "GRBM_PERFCOUNTER0_SELECT" 9294 }, 9295 { 9296 "chips": ["gfx9"], 9297 "map": {"at": 221448, "to": "mm"}, 9298 "name": "GRBM_SE0_PERFCOUNTER_SELECT", 9299 "type_ref": "GRBM_SE0_PERFCOUNTER_SELECT" 9300 }, 9301 { 9302 "chips": ["gfx9"], 9303 "map": {"at": 221452, "to": "mm"}, 9304 "name": "GRBM_SE1_PERFCOUNTER_SELECT", 9305 "type_ref": "GRBM_SE0_PERFCOUNTER_SELECT" 9306 }, 9307 { 9308 "chips": ["gfx9"], 9309 "map": {"at": 221456, "to": "mm"}, 9310 "name": "GRBM_SE2_PERFCOUNTER_SELECT", 9311 "type_ref": "GRBM_SE0_PERFCOUNTER_SELECT" 9312 }, 9313 { 9314 "chips": ["gfx9"], 9315 "map": {"at": 221460, "to": "mm"}, 9316 "name": "GRBM_SE3_PERFCOUNTER_SELECT", 9317 "type_ref": "GRBM_SE0_PERFCOUNTER_SELECT" 9318 }, 9319 { 9320 "chips": ["gfx9"], 9321 "map": {"at": 221696, "to": "mm"}, 9322 "name": "WD_PERFCOUNTER0_SELECT", 9323 "type_ref": "WD_PERFCOUNTER0_SELECT" 9324 }, 9325 { 9326 "chips": ["gfx9"], 9327 "map": {"at": 221700, "to": "mm"}, 9328 "name": "WD_PERFCOUNTER1_SELECT", 9329 "type_ref": "WD_PERFCOUNTER0_SELECT" 9330 }, 9331 { 9332 "chips": ["gfx9"], 9333 "map": {"at": 221704, "to": "mm"}, 9334 "name": "WD_PERFCOUNTER2_SELECT", 9335 "type_ref": "WD_PERFCOUNTER0_SELECT" 9336 }, 9337 { 9338 "chips": ["gfx9"], 9339 "map": {"at": 221708, "to": "mm"}, 9340 "name": "WD_PERFCOUNTER3_SELECT", 9341 "type_ref": "WD_PERFCOUNTER0_SELECT" 9342 }, 9343 { 9344 "chips": ["gfx9"], 9345 "map": {"at": 221712, "to": "mm"}, 9346 "name": "IA_PERFCOUNTER0_SELECT", 9347 "type_ref": "IA_PERFCOUNTER0_SELECT" 9348 }, 9349 { 9350 "chips": ["gfx9"], 9351 "map": {"at": 221716, "to": "mm"}, 9352 "name": "IA_PERFCOUNTER1_SELECT", 9353 "type_ref": "WD_PERFCOUNTER0_SELECT" 9354 }, 9355 { 9356 "chips": ["gfx9"], 9357 "map": {"at": 221720, "to": "mm"}, 9358 "name": "IA_PERFCOUNTER2_SELECT", 9359 "type_ref": "WD_PERFCOUNTER0_SELECT" 9360 }, 9361 { 9362 "chips": ["gfx9"], 9363 "map": {"at": 221724, "to": "mm"}, 9364 "name": "IA_PERFCOUNTER3_SELECT", 9365 "type_ref": "WD_PERFCOUNTER0_SELECT" 9366 }, 9367 { 9368 "chips": ["gfx9"], 9369 "map": {"at": 221728, "to": "mm"}, 9370 "name": "IA_PERFCOUNTER0_SELECT1", 9371 "type_ref": "IA_PERFCOUNTER0_SELECT1" 9372 }, 9373 { 9374 "chips": ["gfx9"], 9375 "map": {"at": 221744, "to": "mm"}, 9376 "name": "VGT_PERFCOUNTER0_SELECT", 9377 "type_ref": "IA_PERFCOUNTER0_SELECT" 9378 }, 9379 { 9380 "chips": ["gfx9"], 9381 "map": {"at": 221748, "to": "mm"}, 9382 "name": "VGT_PERFCOUNTER1_SELECT", 9383 "type_ref": "IA_PERFCOUNTER0_SELECT" 9384 }, 9385 { 9386 "chips": ["gfx9"], 9387 "map": {"at": 221752, "to": "mm"}, 9388 "name": "VGT_PERFCOUNTER2_SELECT", 9389 "type_ref": "WD_PERFCOUNTER0_SELECT" 9390 }, 9391 { 9392 "chips": ["gfx9"], 9393 "map": {"at": 221756, "to": "mm"}, 9394 "name": "VGT_PERFCOUNTER3_SELECT", 9395 "type_ref": "WD_PERFCOUNTER0_SELECT" 9396 }, 9397 { 9398 "chips": ["gfx9"], 9399 "map": {"at": 221760, "to": "mm"}, 9400 "name": "VGT_PERFCOUNTER0_SELECT1", 9401 "type_ref": "IA_PERFCOUNTER0_SELECT1" 9402 }, 9403 { 9404 "chips": ["gfx9"], 9405 "map": {"at": 221764, "to": "mm"}, 9406 "name": "VGT_PERFCOUNTER1_SELECT1", 9407 "type_ref": "IA_PERFCOUNTER0_SELECT1" 9408 }, 9409 { 9410 "chips": ["gfx9"], 9411 "map": {"at": 221776, "to": "mm"}, 9412 "name": "VGT_PERFCOUNTER_SEID_MASK", 9413 "type_ref": "VGT_PERFCOUNTER_SEID_MASK" 9414 }, 9415 { 9416 "chips": ["gfx9"], 9417 "map": {"at": 222208, "to": "mm"}, 9418 "name": "PA_SU_PERFCOUNTER0_SELECT", 9419 "type_ref": "IA_PERFCOUNTER0_SELECT" 9420 }, 9421 { 9422 "chips": ["gfx9"], 9423 "map": {"at": 222212, "to": "mm"}, 9424 "name": "PA_SU_PERFCOUNTER0_SELECT1", 9425 "type_ref": "IA_PERFCOUNTER0_SELECT1" 9426 }, 9427 { 9428 "chips": ["gfx9"], 9429 "map": {"at": 222216, "to": "mm"}, 9430 "name": "PA_SU_PERFCOUNTER1_SELECT", 9431 "type_ref": "IA_PERFCOUNTER0_SELECT" 9432 }, 9433 { 9434 "chips": ["gfx9"], 9435 "map": {"at": 222220, "to": "mm"}, 9436 "name": "PA_SU_PERFCOUNTER1_SELECT1", 9437 "type_ref": "IA_PERFCOUNTER0_SELECT1" 9438 }, 9439 { 9440 "chips": ["gfx9"], 9441 "map": {"at": 222224, "to": "mm"}, 9442 "name": "PA_SU_PERFCOUNTER2_SELECT", 9443 "type_ref": "PA_SU_PERFCOUNTER2_SELECT" 9444 }, 9445 { 9446 "chips": ["gfx9"], 9447 "map": {"at": 222228, "to": "mm"}, 9448 "name": "PA_SU_PERFCOUNTER3_SELECT", 9449 "type_ref": "PA_SU_PERFCOUNTER2_SELECT" 9450 }, 9451 { 9452 "chips": ["gfx9"], 9453 "map": {"at": 222464, "to": "mm"}, 9454 "name": "PA_SC_PERFCOUNTER0_SELECT", 9455 "type_ref": "IA_PERFCOUNTER0_SELECT" 9456 }, 9457 { 9458 "chips": ["gfx9"], 9459 "map": {"at": 222468, "to": "mm"}, 9460 "name": "PA_SC_PERFCOUNTER0_SELECT1", 9461 "type_ref": "IA_PERFCOUNTER0_SELECT1" 9462 }, 9463 { 9464 "chips": ["gfx9"], 9465 "map": {"at": 222472, "to": "mm"}, 9466 "name": "PA_SC_PERFCOUNTER1_SELECT", 9467 "type_ref": "PA_SC_PERFCOUNTER1_SELECT" 9468 }, 9469 { 9470 "chips": ["gfx9"], 9471 "map": {"at": 222476, "to": "mm"}, 9472 "name": "PA_SC_PERFCOUNTER2_SELECT", 9473 "type_ref": "PA_SC_PERFCOUNTER1_SELECT" 9474 }, 9475 { 9476 "chips": ["gfx9"], 9477 "map": {"at": 222480, "to": "mm"}, 9478 "name": "PA_SC_PERFCOUNTER3_SELECT", 9479 "type_ref": "PA_SC_PERFCOUNTER1_SELECT" 9480 }, 9481 { 9482 "chips": ["gfx9"], 9483 "map": {"at": 222484, "to": "mm"}, 9484 "name": "PA_SC_PERFCOUNTER4_SELECT", 9485 "type_ref": "PA_SC_PERFCOUNTER1_SELECT" 9486 }, 9487 { 9488 "chips": ["gfx9"], 9489 "map": {"at": 222488, "to": "mm"}, 9490 "name": "PA_SC_PERFCOUNTER5_SELECT", 9491 "type_ref": "PA_SC_PERFCOUNTER1_SELECT" 9492 }, 9493 { 9494 "chips": ["gfx9"], 9495 "map": {"at": 222492, "to": "mm"}, 9496 "name": "PA_SC_PERFCOUNTER6_SELECT", 9497 "type_ref": "PA_SC_PERFCOUNTER1_SELECT" 9498 }, 9499 { 9500 "chips": ["gfx9"], 9501 "map": {"at": 222496, "to": "mm"}, 9502 "name": "PA_SC_PERFCOUNTER7_SELECT", 9503 "type_ref": "PA_SC_PERFCOUNTER1_SELECT" 9504 }, 9505 { 9506 "chips": ["gfx9"], 9507 "map": {"at": 222720, "to": "mm"}, 9508 "name": "SPI_PERFCOUNTER0_SELECT", 9509 "type_ref": "IA_PERFCOUNTER0_SELECT" 9510 }, 9511 { 9512 "chips": ["gfx9"], 9513 "map": {"at": 222724, "to": "mm"}, 9514 "name": "SPI_PERFCOUNTER1_SELECT", 9515 "type_ref": "IA_PERFCOUNTER0_SELECT" 9516 }, 9517 { 9518 "chips": ["gfx9"], 9519 "map": {"at": 222728, "to": "mm"}, 9520 "name": "SPI_PERFCOUNTER2_SELECT", 9521 "type_ref": "IA_PERFCOUNTER0_SELECT" 9522 }, 9523 { 9524 "chips": ["gfx9"], 9525 "map": {"at": 222732, "to": "mm"}, 9526 "name": "SPI_PERFCOUNTER3_SELECT", 9527 "type_ref": "IA_PERFCOUNTER0_SELECT" 9528 }, 9529 { 9530 "chips": ["gfx9"], 9531 "map": {"at": 222736, "to": "mm"}, 9532 "name": "SPI_PERFCOUNTER0_SELECT1", 9533 "type_ref": "IA_PERFCOUNTER0_SELECT1" 9534 }, 9535 { 9536 "chips": ["gfx9"], 9537 "map": {"at": 222740, "to": "mm"}, 9538 "name": "SPI_PERFCOUNTER1_SELECT1", 9539 "type_ref": "IA_PERFCOUNTER0_SELECT1" 9540 }, 9541 { 9542 "chips": ["gfx9"], 9543 "map": {"at": 222744, "to": "mm"}, 9544 "name": "SPI_PERFCOUNTER2_SELECT1", 9545 "type_ref": "IA_PERFCOUNTER0_SELECT1" 9546 }, 9547 { 9548 "chips": ["gfx9"], 9549 "map": {"at": 222748, "to": "mm"}, 9550 "name": "SPI_PERFCOUNTER3_SELECT1", 9551 "type_ref": "IA_PERFCOUNTER0_SELECT1" 9552 }, 9553 { 9554 "chips": ["gfx9"], 9555 "map": {"at": 222752, "to": "mm"}, 9556 "name": "SPI_PERFCOUNTER4_SELECT", 9557 "type_ref": "SPI_PERFCOUNTER4_SELECT" 9558 }, 9559 { 9560 "chips": ["gfx9"], 9561 "map": {"at": 222756, "to": "mm"}, 9562 "name": "SPI_PERFCOUNTER5_SELECT", 9563 "type_ref": "SPI_PERFCOUNTER4_SELECT" 9564 }, 9565 { 9566 "chips": ["gfx9"], 9567 "map": {"at": 222760, "to": "mm"}, 9568 "name": "SPI_PERFCOUNTER_BINS", 9569 "type_ref": "SPI_PERFCOUNTER_BINS" 9570 }, 9571 { 9572 "chips": ["gfx9"], 9573 "map": {"at": 222976, "to": "mm"}, 9574 "name": "SQ_PERFCOUNTER0_SELECT", 9575 "type_ref": "SQ_PERFCOUNTER0_SELECT" 9576 }, 9577 { 9578 "chips": ["gfx9"], 9579 "map": {"at": 222980, "to": "mm"}, 9580 "name": "SQ_PERFCOUNTER1_SELECT", 9581 "type_ref": "SQ_PERFCOUNTER0_SELECT" 9582 }, 9583 { 9584 "chips": ["gfx9"], 9585 "map": {"at": 222984, "to": "mm"}, 9586 "name": "SQ_PERFCOUNTER2_SELECT", 9587 "type_ref": "SQ_PERFCOUNTER0_SELECT" 9588 }, 9589 { 9590 "chips": ["gfx9"], 9591 "map": {"at": 222988, "to": "mm"}, 9592 "name": "SQ_PERFCOUNTER3_SELECT", 9593 "type_ref": "SQ_PERFCOUNTER0_SELECT" 9594 }, 9595 { 9596 "chips": ["gfx9"], 9597 "map": {"at": 222992, "to": "mm"}, 9598 "name": "SQ_PERFCOUNTER4_SELECT", 9599 "type_ref": "SQ_PERFCOUNTER0_SELECT" 9600 }, 9601 { 9602 "chips": ["gfx9"], 9603 "map": {"at": 222996, "to": "mm"}, 9604 "name": "SQ_PERFCOUNTER5_SELECT", 9605 "type_ref": "SQ_PERFCOUNTER0_SELECT" 9606 }, 9607 { 9608 "chips": ["gfx9"], 9609 "map": {"at": 223000, "to": "mm"}, 9610 "name": "SQ_PERFCOUNTER6_SELECT", 9611 "type_ref": "SQ_PERFCOUNTER0_SELECT" 9612 }, 9613 { 9614 "chips": ["gfx9"], 9615 "map": {"at": 223004, "to": "mm"}, 9616 "name": "SQ_PERFCOUNTER7_SELECT", 9617 "type_ref": "SQ_PERFCOUNTER0_SELECT" 9618 }, 9619 { 9620 "chips": ["gfx9"], 9621 "map": {"at": 223008, "to": "mm"}, 9622 "name": "SQ_PERFCOUNTER8_SELECT", 9623 "type_ref": "SQ_PERFCOUNTER0_SELECT" 9624 }, 9625 { 9626 "chips": ["gfx9"], 9627 "map": {"at": 223012, "to": "mm"}, 9628 "name": "SQ_PERFCOUNTER9_SELECT", 9629 "type_ref": "SQ_PERFCOUNTER0_SELECT" 9630 }, 9631 { 9632 "chips": ["gfx9"], 9633 "map": {"at": 223016, "to": "mm"}, 9634 "name": "SQ_PERFCOUNTER10_SELECT", 9635 "type_ref": "SQ_PERFCOUNTER0_SELECT" 9636 }, 9637 { 9638 "chips": ["gfx9"], 9639 "map": {"at": 223020, "to": "mm"}, 9640 "name": "SQ_PERFCOUNTER11_SELECT", 9641 "type_ref": "SQ_PERFCOUNTER0_SELECT" 9642 }, 9643 { 9644 "chips": ["gfx9"], 9645 "map": {"at": 223024, "to": "mm"}, 9646 "name": "SQ_PERFCOUNTER12_SELECT", 9647 "type_ref": "SQ_PERFCOUNTER0_SELECT" 9648 }, 9649 { 9650 "chips": ["gfx9"], 9651 "map": {"at": 223028, "to": "mm"}, 9652 "name": "SQ_PERFCOUNTER13_SELECT", 9653 "type_ref": "SQ_PERFCOUNTER0_SELECT" 9654 }, 9655 { 9656 "chips": ["gfx9"], 9657 "map": {"at": 223032, "to": "mm"}, 9658 "name": "SQ_PERFCOUNTER14_SELECT", 9659 "type_ref": "SQ_PERFCOUNTER0_SELECT" 9660 }, 9661 { 9662 "chips": ["gfx9"], 9663 "map": {"at": 223036, "to": "mm"}, 9664 "name": "SQ_PERFCOUNTER15_SELECT", 9665 "type_ref": "SQ_PERFCOUNTER0_SELECT" 9666 }, 9667 { 9668 "chips": ["gfx9"], 9669 "map": {"at": 223104, "to": "mm"}, 9670 "name": "SQ_PERFCOUNTER_CTRL", 9671 "type_ref": "SQ_PERFCOUNTER_CTRL" 9672 }, 9673 { 9674 "chips": ["gfx9"], 9675 "map": {"at": 223108, "to": "mm"}, 9676 "name": "SQ_PERFCOUNTER_MASK", 9677 "type_ref": "SQ_THREAD_TRACE_PERF_MASK" 9678 }, 9679 { 9680 "chips": ["gfx9"], 9681 "map": {"at": 223112, "to": "mm"}, 9682 "name": "SQ_PERFCOUNTER_CTRL2", 9683 "type_ref": "SQ_PERFCOUNTER_CTRL2" 9684 }, 9685 { 9686 "chips": ["gfx9"], 9687 "map": {"at": 223488, "to": "mm"}, 9688 "name": "SX_PERFCOUNTER0_SELECT", 9689 "type_ref": "IA_PERFCOUNTER0_SELECT" 9690 }, 9691 { 9692 "chips": ["gfx9"], 9693 "map": {"at": 223492, "to": "mm"}, 9694 "name": "SX_PERFCOUNTER1_SELECT", 9695 "type_ref": "IA_PERFCOUNTER0_SELECT" 9696 }, 9697 { 9698 "chips": ["gfx9"], 9699 "map": {"at": 223496, "to": "mm"}, 9700 "name": "SX_PERFCOUNTER2_SELECT", 9701 "type_ref": "PA_SU_PERFCOUNTER2_SELECT" 9702 }, 9703 { 9704 "chips": ["gfx9"], 9705 "map": {"at": 223500, "to": "mm"}, 9706 "name": "SX_PERFCOUNTER3_SELECT", 9707 "type_ref": "PA_SU_PERFCOUNTER2_SELECT" 9708 }, 9709 { 9710 "chips": ["gfx9"], 9711 "map": {"at": 223504, "to": "mm"}, 9712 "name": "SX_PERFCOUNTER0_SELECT1", 9713 "type_ref": "IA_PERFCOUNTER0_SELECT1" 9714 }, 9715 { 9716 "chips": ["gfx9"], 9717 "map": {"at": 223508, "to": "mm"}, 9718 "name": "SX_PERFCOUNTER1_SELECT1", 9719 "type_ref": "IA_PERFCOUNTER0_SELECT1" 9720 }, 9721 { 9722 "chips": ["gfx9"], 9723 "map": {"at": 223744, "to": "mm"}, 9724 "name": "GDS_PERFCOUNTER0_SELECT", 9725 "type_ref": "IA_PERFCOUNTER0_SELECT" 9726 }, 9727 { 9728 "chips": ["gfx9"], 9729 "map": {"at": 223748, "to": "mm"}, 9730 "name": "GDS_PERFCOUNTER1_SELECT", 9731 "type_ref": "IA_PERFCOUNTER0_SELECT" 9732 }, 9733 { 9734 "chips": ["gfx9"], 9735 "map": {"at": 223752, "to": "mm"}, 9736 "name": "GDS_PERFCOUNTER2_SELECT", 9737 "type_ref": "IA_PERFCOUNTER0_SELECT" 9738 }, 9739 { 9740 "chips": ["gfx9"], 9741 "map": {"at": 223756, "to": "mm"}, 9742 "name": "GDS_PERFCOUNTER3_SELECT", 9743 "type_ref": "IA_PERFCOUNTER0_SELECT" 9744 }, 9745 { 9746 "chips": ["gfx9"], 9747 "map": {"at": 223760, "to": "mm"}, 9748 "name": "GDS_PERFCOUNTER0_SELECT1", 9749 "type_ref": "IA_PERFCOUNTER0_SELECT1" 9750 }, 9751 { 9752 "chips": ["gfx9"], 9753 "map": {"at": 224000, "to": "mm"}, 9754 "name": "TA_PERFCOUNTER0_SELECT", 9755 "type_ref": "TA_PERFCOUNTER0_SELECT" 9756 }, 9757 { 9758 "chips": ["gfx9"], 9759 "map": {"at": 224004, "to": "mm"}, 9760 "name": "TA_PERFCOUNTER0_SELECT1", 9761 "type_ref": "TA_PERFCOUNTER0_SELECT1" 9762 }, 9763 { 9764 "chips": ["gfx9"], 9765 "map": {"at": 224008, "to": "mm"}, 9766 "name": "TA_PERFCOUNTER1_SELECT", 9767 "type_ref": "TA_PERFCOUNTER1_SELECT" 9768 }, 9769 { 9770 "chips": ["gfx9"], 9771 "map": {"at": 224256, "to": "mm"}, 9772 "name": "TD_PERFCOUNTER0_SELECT", 9773 "type_ref": "TA_PERFCOUNTER0_SELECT" 9774 }, 9775 { 9776 "chips": ["gfx9"], 9777 "map": {"at": 224260, "to": "mm"}, 9778 "name": "TD_PERFCOUNTER0_SELECT1", 9779 "type_ref": "TA_PERFCOUNTER0_SELECT1" 9780 }, 9781 { 9782 "chips": ["gfx9"], 9783 "map": {"at": 224264, "to": "mm"}, 9784 "name": "TD_PERFCOUNTER1_SELECT", 9785 "type_ref": "TA_PERFCOUNTER1_SELECT" 9786 }, 9787 { 9788 "chips": ["gfx9"], 9789 "map": {"at": 224512, "to": "mm"}, 9790 "name": "TCP_PERFCOUNTER0_SELECT", 9791 "type_ref": "IA_PERFCOUNTER0_SELECT" 9792 }, 9793 { 9794 "chips": ["gfx9"], 9795 "map": {"at": 224516, "to": "mm"}, 9796 "name": "TCP_PERFCOUNTER0_SELECT1", 9797 "type_ref": "IA_PERFCOUNTER0_SELECT1" 9798 }, 9799 { 9800 "chips": ["gfx9"], 9801 "map": {"at": 224520, "to": "mm"}, 9802 "name": "TCP_PERFCOUNTER1_SELECT", 9803 "type_ref": "IA_PERFCOUNTER0_SELECT" 9804 }, 9805 { 9806 "chips": ["gfx9"], 9807 "map": {"at": 224524, "to": "mm"}, 9808 "name": "TCP_PERFCOUNTER1_SELECT1", 9809 "type_ref": "IA_PERFCOUNTER0_SELECT1" 9810 }, 9811 { 9812 "chips": ["gfx9"], 9813 "map": {"at": 224528, "to": "mm"}, 9814 "name": "TCP_PERFCOUNTER2_SELECT", 9815 "type_ref": "PA_SU_PERFCOUNTER2_SELECT" 9816 }, 9817 { 9818 "chips": ["gfx9"], 9819 "map": {"at": 224532, "to": "mm"}, 9820 "name": "TCP_PERFCOUNTER3_SELECT", 9821 "type_ref": "PA_SU_PERFCOUNTER2_SELECT" 9822 }, 9823 { 9824 "chips": ["gfx9"], 9825 "map": {"at": 224768, "to": "mm"}, 9826 "name": "TCC_PERFCOUNTER0_SELECT", 9827 "type_ref": "IA_PERFCOUNTER0_SELECT" 9828 }, 9829 { 9830 "chips": ["gfx9"], 9831 "map": {"at": 224772, "to": "mm"}, 9832 "name": "TCC_PERFCOUNTER0_SELECT1", 9833 "type_ref": "TCC_PERFCOUNTER0_SELECT1" 9834 }, 9835 { 9836 "chips": ["gfx9"], 9837 "map": {"at": 224776, "to": "mm"}, 9838 "name": "TCC_PERFCOUNTER1_SELECT", 9839 "type_ref": "IA_PERFCOUNTER0_SELECT" 9840 }, 9841 { 9842 "chips": ["gfx9"], 9843 "map": {"at": 224780, "to": "mm"}, 9844 "name": "TCC_PERFCOUNTER1_SELECT1", 9845 "type_ref": "TCC_PERFCOUNTER0_SELECT1" 9846 }, 9847 { 9848 "chips": ["gfx9"], 9849 "map": {"at": 224784, "to": "mm"}, 9850 "name": "TCC_PERFCOUNTER2_SELECT", 9851 "type_ref": "PA_SU_PERFCOUNTER2_SELECT" 9852 }, 9853 { 9854 "chips": ["gfx9"], 9855 "map": {"at": 224788, "to": "mm"}, 9856 "name": "TCC_PERFCOUNTER3_SELECT", 9857 "type_ref": "PA_SU_PERFCOUNTER2_SELECT" 9858 }, 9859 { 9860 "chips": ["gfx9"], 9861 "map": {"at": 224832, "to": "mm"}, 9862 "name": "TCA_PERFCOUNTER0_SELECT", 9863 "type_ref": "IA_PERFCOUNTER0_SELECT" 9864 }, 9865 { 9866 "chips": ["gfx9"], 9867 "map": {"at": 224836, "to": "mm"}, 9868 "name": "TCA_PERFCOUNTER0_SELECT1", 9869 "type_ref": "TCC_PERFCOUNTER0_SELECT1" 9870 }, 9871 { 9872 "chips": ["gfx9"], 9873 "map": {"at": 224840, "to": "mm"}, 9874 "name": "TCA_PERFCOUNTER1_SELECT", 9875 "type_ref": "IA_PERFCOUNTER0_SELECT" 9876 }, 9877 { 9878 "chips": ["gfx9"], 9879 "map": {"at": 224844, "to": "mm"}, 9880 "name": "TCA_PERFCOUNTER1_SELECT1", 9881 "type_ref": "TCC_PERFCOUNTER0_SELECT1" 9882 }, 9883 { 9884 "chips": ["gfx9"], 9885 "map": {"at": 224848, "to": "mm"}, 9886 "name": "TCA_PERFCOUNTER2_SELECT", 9887 "type_ref": "PA_SU_PERFCOUNTER2_SELECT" 9888 }, 9889 { 9890 "chips": ["gfx9"], 9891 "map": {"at": 224852, "to": "mm"}, 9892 "name": "TCA_PERFCOUNTER3_SELECT", 9893 "type_ref": "PA_SU_PERFCOUNTER2_SELECT" 9894 }, 9895 { 9896 "chips": ["gfx9"], 9897 "map": {"at": 225280, "to": "mm"}, 9898 "name": "CB_PERFCOUNTER_FILTER", 9899 "type_ref": "CB_PERFCOUNTER_FILTER" 9900 }, 9901 { 9902 "chips": ["gfx9"], 9903 "map": {"at": 225284, "to": "mm"}, 9904 "name": "CB_PERFCOUNTER0_SELECT", 9905 "type_ref": "CB_PERFCOUNTER0_SELECT" 9906 }, 9907 { 9908 "chips": ["gfx9"], 9909 "map": {"at": 225288, "to": "mm"}, 9910 "name": "CB_PERFCOUNTER0_SELECT1", 9911 "type_ref": "CB_PERFCOUNTER0_SELECT1" 9912 }, 9913 { 9914 "chips": ["gfx9"], 9915 "map": {"at": 225292, "to": "mm"}, 9916 "name": "CB_PERFCOUNTER1_SELECT", 9917 "type_ref": "CB_PERFCOUNTER1_SELECT" 9918 }, 9919 { 9920 "chips": ["gfx9"], 9921 "map": {"at": 225296, "to": "mm"}, 9922 "name": "CB_PERFCOUNTER2_SELECT", 9923 "type_ref": "CB_PERFCOUNTER1_SELECT" 9924 }, 9925 { 9926 "chips": ["gfx9"], 9927 "map": {"at": 225300, "to": "mm"}, 9928 "name": "CB_PERFCOUNTER3_SELECT", 9929 "type_ref": "CB_PERFCOUNTER1_SELECT" 9930 }, 9931 { 9932 "chips": ["gfx9"], 9933 "map": {"at": 225536, "to": "mm"}, 9934 "name": "DB_PERFCOUNTER0_SELECT", 9935 "type_ref": "IA_PERFCOUNTER0_SELECT" 9936 }, 9937 { 9938 "chips": ["gfx9"], 9939 "map": {"at": 225540, "to": "mm"}, 9940 "name": "DB_PERFCOUNTER0_SELECT1", 9941 "type_ref": "IA_PERFCOUNTER0_SELECT1" 9942 }, 9943 { 9944 "chips": ["gfx9"], 9945 "map": {"at": 225544, "to": "mm"}, 9946 "name": "DB_PERFCOUNTER1_SELECT", 9947 "type_ref": "IA_PERFCOUNTER0_SELECT" 9948 }, 9949 { 9950 "chips": ["gfx9"], 9951 "map": {"at": 225548, "to": "mm"}, 9952 "name": "DB_PERFCOUNTER1_SELECT1", 9953 "type_ref": "IA_PERFCOUNTER0_SELECT1" 9954 }, 9955 { 9956 "chips": ["gfx9"], 9957 "map": {"at": 225552, "to": "mm"}, 9958 "name": "DB_PERFCOUNTER2_SELECT", 9959 "type_ref": "IA_PERFCOUNTER0_SELECT" 9960 }, 9961 { 9962 "chips": ["gfx9"], 9963 "map": {"at": 225560, "to": "mm"}, 9964 "name": "DB_PERFCOUNTER3_SELECT", 9965 "type_ref": "IA_PERFCOUNTER0_SELECT" 9966 }, 9967 { 9968 "chips": ["gfx9"], 9969 "map": {"at": 225792, "to": "mm"}, 9970 "name": "RLC_SPM_PERFMON_CNTL", 9971 "type_ref": "RLC_SPM_PERFMON_CNTL" 9972 }, 9973 { 9974 "chips": ["gfx9"], 9975 "map": {"at": 225796, "to": "mm"}, 9976 "name": "RLC_SPM_PERFMON_RING_BASE_LO" 9977 }, 9978 { 9979 "chips": ["gfx9"], 9980 "map": {"at": 225800, "to": "mm"}, 9981 "name": "RLC_SPM_PERFMON_RING_BASE_HI", 9982 "type_ref": "RLC_SPM_PERFMON_RING_BASE_HI" 9983 }, 9984 { 9985 "chips": ["gfx9"], 9986 "map": {"at": 225804, "to": "mm"}, 9987 "name": "RLC_SPM_PERFMON_RING_SIZE" 9988 }, 9989 { 9990 "chips": ["gfx9"], 9991 "map": {"at": 225808, "to": "mm"}, 9992 "name": "RLC_SPM_PERFMON_SEGMENT_SIZE", 9993 "type_ref": "RLC_SPM_PERFMON_SEGMENT_SIZE" 9994 }, 9995 { 9996 "chips": ["gfx9"], 9997 "map": {"at": 225812, "to": "mm"}, 9998 "name": "RLC_SPM_SE_MUXSEL_ADDR" 9999 }, 10000 { 10001 "chips": ["gfx9"], 10002 "map": {"at": 225816, "to": "mm"}, 10003 "name": "RLC_SPM_SE_MUXSEL_DATA" 10004 }, 10005 { 10006 "chips": ["gfx9"], 10007 "map": {"at": 225820, "to": "mm"}, 10008 "name": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY", 10009 "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY" 10010 }, 10011 { 10012 "chips": ["gfx9"], 10013 "map": {"at": 225824, "to": "mm"}, 10014 "name": "RLC_SPM_CPC_PERFMON_SAMPLE_DELAY", 10015 "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY" 10016 }, 10017 { 10018 "chips": ["gfx9"], 10019 "map": {"at": 225828, "to": "mm"}, 10020 "name": "RLC_SPM_CPF_PERFMON_SAMPLE_DELAY", 10021 "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY" 10022 }, 10023 { 10024 "chips": ["gfx9"], 10025 "map": {"at": 225832, "to": "mm"}, 10026 "name": "RLC_SPM_CB_PERFMON_SAMPLE_DELAY", 10027 "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY" 10028 }, 10029 { 10030 "chips": ["gfx9"], 10031 "map": {"at": 225836, "to": "mm"}, 10032 "name": "RLC_SPM_DB_PERFMON_SAMPLE_DELAY", 10033 "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY" 10034 }, 10035 { 10036 "chips": ["gfx9"], 10037 "map": {"at": 225840, "to": "mm"}, 10038 "name": "RLC_SPM_PA_PERFMON_SAMPLE_DELAY", 10039 "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY" 10040 }, 10041 { 10042 "chips": ["gfx9"], 10043 "map": {"at": 225844, "to": "mm"}, 10044 "name": "RLC_SPM_GDS_PERFMON_SAMPLE_DELAY", 10045 "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY" 10046 }, 10047 { 10048 "chips": ["gfx9"], 10049 "map": {"at": 225848, "to": "mm"}, 10050 "name": "RLC_SPM_IA_PERFMON_SAMPLE_DELAY", 10051 "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY" 10052 }, 10053 { 10054 "chips": ["gfx9"], 10055 "map": {"at": 225856, "to": "mm"}, 10056 "name": "RLC_SPM_SC_PERFMON_SAMPLE_DELAY", 10057 "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY" 10058 }, 10059 { 10060 "chips": ["gfx9"], 10061 "map": {"at": 225860, "to": "mm"}, 10062 "name": "RLC_SPM_TCC_PERFMON_SAMPLE_DELAY", 10063 "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY" 10064 }, 10065 { 10066 "chips": ["gfx9"], 10067 "map": {"at": 225864, "to": "mm"}, 10068 "name": "RLC_SPM_TCA_PERFMON_SAMPLE_DELAY", 10069 "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY" 10070 }, 10071 { 10072 "chips": ["gfx9"], 10073 "map": {"at": 225868, "to": "mm"}, 10074 "name": "RLC_SPM_TCP_PERFMON_SAMPLE_DELAY", 10075 "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY" 10076 }, 10077 { 10078 "chips": ["gfx9"], 10079 "map": {"at": 225872, "to": "mm"}, 10080 "name": "RLC_SPM_TA_PERFMON_SAMPLE_DELAY", 10081 "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY" 10082 }, 10083 { 10084 "chips": ["gfx9"], 10085 "map": {"at": 225876, "to": "mm"}, 10086 "name": "RLC_SPM_TD_PERFMON_SAMPLE_DELAY", 10087 "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY" 10088 }, 10089 { 10090 "chips": ["gfx9"], 10091 "map": {"at": 225880, "to": "mm"}, 10092 "name": "RLC_SPM_VGT_PERFMON_SAMPLE_DELAY", 10093 "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY" 10094 }, 10095 { 10096 "chips": ["gfx9"], 10097 "map": {"at": 225884, "to": "mm"}, 10098 "name": "RLC_SPM_SPI_PERFMON_SAMPLE_DELAY", 10099 "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY" 10100 }, 10101 { 10102 "chips": ["gfx9"], 10103 "map": {"at": 225888, "to": "mm"}, 10104 "name": "RLC_SPM_SQG_PERFMON_SAMPLE_DELAY", 10105 "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY" 10106 }, 10107 { 10108 "chips": ["gfx9"], 10109 "map": {"at": 225896, "to": "mm"}, 10110 "name": "RLC_SPM_SX_PERFMON_SAMPLE_DELAY", 10111 "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY" 10112 }, 10113 { 10114 "chips": ["gfx9"], 10115 "map": {"at": 225900, "to": "mm"}, 10116 "name": "RLC_SPM_GLOBAL_MUXSEL_ADDR" 10117 }, 10118 { 10119 "chips": ["gfx9"], 10120 "map": {"at": 225904, "to": "mm"}, 10121 "name": "RLC_SPM_GLOBAL_MUXSEL_DATA" 10122 }, 10123 { 10124 "chips": ["gfx9"], 10125 "map": {"at": 225908, "to": "mm"}, 10126 "name": "RLC_SPM_RING_RDPTR" 10127 }, 10128 { 10129 "chips": ["gfx9"], 10130 "map": {"at": 225912, "to": "mm"}, 10131 "name": "RLC_SPM_SEGMENT_THRESHOLD" 10132 }, 10133 { 10134 "chips": ["gfx9"], 10135 "map": {"at": 225932, "to": "mm"}, 10136 "name": "RLC_SPM_RMI_PERFMON_SAMPLE_DELAY", 10137 "type_ref": "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY" 10138 }, 10139 { 10140 "chips": ["gfx9"], 10141 "map": {"at": 225936, "to": "mm"}, 10142 "name": "RLC_SPM_PERFMON_SAMPLE_DELAY_MAX", 10143 "type_ref": "RLC_SPM_PERFMON_SAMPLE_DELAY_MAX" 10144 }, 10145 { 10146 "chips": ["gfx9"], 10147 "map": {"at": 226040, "to": "mm"}, 10148 "name": "RLC_PERFMON_CLK_CNTL_UCODE", 10149 "type_ref": "RLC_PERFMON_CLK_CNTL_UCODE" 10150 }, 10151 { 10152 "chips": ["gfx9"], 10153 "map": {"at": 226044, "to": "mm"}, 10154 "name": "RLC_PERFMON_CLK_CNTL", 10155 "type_ref": "RLC_PERFMON_CLK_CNTL_UCODE" 10156 }, 10157 { 10158 "chips": ["gfx9"], 10159 "map": {"at": 226048, "to": "mm"}, 10160 "name": "RLC_PERFMON_CNTL", 10161 "type_ref": "RLC_PERFMON_CNTL" 10162 }, 10163 { 10164 "chips": ["gfx9"], 10165 "map": {"at": 226052, "to": "mm"}, 10166 "name": "RLC_PERFCOUNTER0_SELECT", 10167 "type_ref": "RLC_PERFCOUNTER0_SELECT" 10168 }, 10169 { 10170 "chips": ["gfx9"], 10171 "map": {"at": 226056, "to": "mm"}, 10172 "name": "RLC_PERFCOUNTER1_SELECT", 10173 "type_ref": "RLC_PERFCOUNTER0_SELECT" 10174 }, 10175 { 10176 "chips": ["gfx9"], 10177 "map": {"at": 226060, "to": "mm"}, 10178 "name": "RLC_GPU_IOV_PERF_CNT_CNTL", 10179 "type_ref": "RLC_GPU_IOV_PERF_CNT_CNTL" 10180 }, 10181 { 10182 "chips": ["gfx9"], 10183 "map": {"at": 226064, "to": "mm"}, 10184 "name": "RLC_GPU_IOV_PERF_CNT_WR_ADDR", 10185 "type_ref": "RLC_GPU_IOV_PERF_CNT_WR_ADDR" 10186 }, 10187 { 10188 "chips": ["gfx9"], 10189 "map": {"at": 226068, "to": "mm"}, 10190 "name": "RLC_GPU_IOV_PERF_CNT_WR_DATA", 10191 "type_ref": "COMPUTE_VMID" 10192 }, 10193 { 10194 "chips": ["gfx9"], 10195 "map": {"at": 226072, "to": "mm"}, 10196 "name": "RLC_GPU_IOV_PERF_CNT_RD_ADDR", 10197 "type_ref": "RLC_GPU_IOV_PERF_CNT_WR_ADDR" 10198 }, 10199 { 10200 "chips": ["gfx9"], 10201 "map": {"at": 226076, "to": "mm"}, 10202 "name": "RLC_GPU_IOV_PERF_CNT_RD_DATA", 10203 "type_ref": "COMPUTE_VMID" 10204 }, 10205 { 10206 "chips": ["gfx9"], 10207 "map": {"at": 226304, "to": "mm"}, 10208 "name": "RMI_PERFCOUNTER0_SELECT", 10209 "type_ref": "CB_PERFCOUNTER0_SELECT" 10210 }, 10211 { 10212 "chips": ["gfx9"], 10213 "map": {"at": 226308, "to": "mm"}, 10214 "name": "RMI_PERFCOUNTER0_SELECT1", 10215 "type_ref": "CB_PERFCOUNTER0_SELECT1" 10216 }, 10217 { 10218 "chips": ["gfx9"], 10219 "map": {"at": 226312, "to": "mm"}, 10220 "name": "RMI_PERFCOUNTER1_SELECT", 10221 "type_ref": "CB_PERFCOUNTER1_SELECT" 10222 }, 10223 { 10224 "chips": ["gfx9"], 10225 "map": {"at": 226316, "to": "mm"}, 10226 "name": "RMI_PERFCOUNTER2_SELECT", 10227 "type_ref": "CB_PERFCOUNTER0_SELECT" 10228 }, 10229 { 10230 "chips": ["gfx9"], 10231 "map": {"at": 226320, "to": "mm"}, 10232 "name": "RMI_PERFCOUNTER2_SELECT1", 10233 "type_ref": "CB_PERFCOUNTER0_SELECT1" 10234 }, 10235 { 10236 "chips": ["gfx9"], 10237 "map": {"at": 226324, "to": "mm"}, 10238 "name": "RMI_PERFCOUNTER3_SELECT", 10239 "type_ref": "CB_PERFCOUNTER1_SELECT" 10240 }, 10241 { 10242 "chips": ["gfx9"], 10243 "map": {"at": 226328, "to": "mm"}, 10244 "name": "RMI_PERF_COUNTER_CNTL", 10245 "type_ref": "RMI_PERF_COUNTER_CNTL" 10246 }, 10247 { 10248 "chips": ["gfx9"], 10249 "map": {"at": 226560, "to": "mm"}, 10250 "name": "ATC_L2_PERFCOUNTER0_CFG", 10251 "type_ref": "ATC_L2_PERFCOUNTER0_CFG" 10252 }, 10253 { 10254 "chips": ["gfx9"], 10255 "map": {"at": 226564, "to": "mm"}, 10256 "name": "ATC_L2_PERFCOUNTER1_CFG", 10257 "type_ref": "ATC_L2_PERFCOUNTER0_CFG" 10258 }, 10259 { 10260 "chips": ["gfx9"], 10261 "map": {"at": 226568, "to": "mm"}, 10262 "name": "ATC_L2_PERFCOUNTER_RSLT_CNTL", 10263 "type_ref": "ATC_L2_PERFCOUNTER_RSLT_CNTL" 10264 }, 10265 { 10266 "chips": ["gfx9"], 10267 "map": {"at": 226608, "to": "mm"}, 10268 "name": "MC_VM_L2_PERFCOUNTER0_CFG", 10269 "type_ref": "ATC_L2_PERFCOUNTER0_CFG" 10270 }, 10271 { 10272 "chips": ["gfx9"], 10273 "map": {"at": 226612, "to": "mm"}, 10274 "name": "MC_VM_L2_PERFCOUNTER1_CFG", 10275 "type_ref": "ATC_L2_PERFCOUNTER0_CFG" 10276 }, 10277 { 10278 "chips": ["gfx9"], 10279 "map": {"at": 226616, "to": "mm"}, 10280 "name": "MC_VM_L2_PERFCOUNTER2_CFG", 10281 "type_ref": "ATC_L2_PERFCOUNTER0_CFG" 10282 }, 10283 { 10284 "chips": ["gfx9"], 10285 "map": {"at": 226620, "to": "mm"}, 10286 "name": "MC_VM_L2_PERFCOUNTER3_CFG", 10287 "type_ref": "ATC_L2_PERFCOUNTER0_CFG" 10288 }, 10289 { 10290 "chips": ["gfx9"], 10291 "map": {"at": 226624, "to": "mm"}, 10292 "name": "MC_VM_L2_PERFCOUNTER4_CFG", 10293 "type_ref": "ATC_L2_PERFCOUNTER0_CFG" 10294 }, 10295 { 10296 "chips": ["gfx9"], 10297 "map": {"at": 226628, "to": "mm"}, 10298 "name": "MC_VM_L2_PERFCOUNTER5_CFG", 10299 "type_ref": "ATC_L2_PERFCOUNTER0_CFG" 10300 }, 10301 { 10302 "chips": ["gfx9"], 10303 "map": {"at": 226632, "to": "mm"}, 10304 "name": "MC_VM_L2_PERFCOUNTER6_CFG", 10305 "type_ref": "ATC_L2_PERFCOUNTER0_CFG" 10306 }, 10307 { 10308 "chips": ["gfx9"], 10309 "map": {"at": 226636, "to": "mm"}, 10310 "name": "MC_VM_L2_PERFCOUNTER7_CFG", 10311 "type_ref": "ATC_L2_PERFCOUNTER0_CFG" 10312 }, 10313 { 10314 "chips": ["gfx9"], 10315 "map": {"at": 226640, "to": "mm"}, 10316 "name": "MC_VM_L2_PERFCOUNTER_RSLT_CNTL", 10317 "type_ref": "ATC_L2_PERFCOUNTER_RSLT_CNTL" 10318 } 10319 ], 10320 "register_types": { 10321 "ATC_L2_PERFCOUNTER0_CFG": { 10322 "fields": [ 10323 {"bits": [0, 7], "name": "PERF_SEL"}, 10324 {"bits": [8, 15], "name": "PERF_SEL_END"}, 10325 {"bits": [24, 27], "name": "PERF_MODE"}, 10326 {"bits": [28, 28], "name": "ENABLE"}, 10327 {"bits": [29, 29], "name": "CLEAR"} 10328 ] 10329 }, 10330 "ATC_L2_PERFCOUNTER_HI": { 10331 "fields": [ 10332 {"bits": [0, 15], "name": "COUNTER_HI"}, 10333 {"bits": [16, 31], "name": "COMPARE_VALUE"} 10334 ] 10335 }, 10336 "ATC_L2_PERFCOUNTER_RSLT_CNTL": { 10337 "fields": [ 10338 {"bits": [0, 3], "name": "PERF_COUNTER_SELECT"}, 10339 {"bits": [8, 15], "name": "START_TRIGGER"}, 10340 {"bits": [16, 23], "name": "STOP_TRIGGER"}, 10341 {"bits": [24, 24], "name": "ENABLE_ANY"}, 10342 {"bits": [25, 25], "name": "CLEAR_ALL"}, 10343 {"bits": [26, 26], "name": "STOP_ALL_ON_SATURATE"} 10344 ] 10345 }, 10346 "CB_BLEND0_CONTROL": { 10347 "fields": [ 10348 {"bits": [0, 4], "enum_ref": "BlendOp", "name": "COLOR_SRCBLEND"}, 10349 {"bits": [5, 7], "enum_ref": "CombFunc", "name": "COLOR_COMB_FCN"}, 10350 {"bits": [8, 12], "enum_ref": "BlendOp", "name": "COLOR_DESTBLEND"}, 10351 {"bits": [16, 20], "enum_ref": "BlendOp", "name": "ALPHA_SRCBLEND"}, 10352 {"bits": [21, 23], "enum_ref": "CombFunc", "name": "ALPHA_COMB_FCN"}, 10353 {"bits": [24, 28], "enum_ref": "BlendOp", "name": "ALPHA_DESTBLEND"}, 10354 {"bits": [29, 29], "name": "SEPARATE_ALPHA_BLEND"}, 10355 {"bits": [30, 30], "name": "ENABLE"}, 10356 {"bits": [31, 31], "name": "DISABLE_ROP3"} 10357 ] 10358 }, 10359 "CB_COLOR0_ATTRIB": { 10360 "fields": [ 10361 {"bits": [0, 10], "name": "MIP0_DEPTH"}, 10362 {"bits": [11, 11], "name": "META_LINEAR"}, 10363 {"bits": [12, 14], "name": "NUM_SAMPLES"}, 10364 {"bits": [15, 16], "name": "NUM_FRAGMENTS"}, 10365 {"bits": [17, 17], "name": "FORCE_DST_ALPHA_1"}, 10366 {"bits": [18, 22], "name": "COLOR_SW_MODE"}, 10367 {"bits": [23, 27], "name": "FMASK_SW_MODE"}, 10368 {"bits": [28, 29], "name": "RESOURCE_TYPE"}, 10369 {"bits": [30, 30], "name": "RB_ALIGNED"}, 10370 {"bits": [31, 31], "name": "PIPE_ALIGNED"} 10371 ] 10372 }, 10373 "CB_COLOR0_ATTRIB2": { 10374 "fields": [ 10375 {"bits": [0, 13], "name": "MIP0_HEIGHT"}, 10376 {"bits": [14, 27], "name": "MIP0_WIDTH"}, 10377 {"bits": [28, 31], "name": "MAX_MIP"} 10378 ] 10379 }, 10380 "CB_COLOR0_BASE_EXT": { 10381 "fields": [ 10382 {"bits": [0, 7], "name": "BASE_256B"} 10383 ] 10384 }, 10385 "CB_COLOR0_DCC_CONTROL": { 10386 "fields": [ 10387 {"bits": [0, 0], "name": "OVERWRITE_COMBINER_DISABLE"}, 10388 {"bits": [1, 1], "name": "KEY_CLEAR_ENABLE"}, 10389 {"bits": [2, 3], "enum_ref": "CB_COLOR_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE", "name": "MAX_UNCOMPRESSED_BLOCK_SIZE"}, 10390 {"bits": [4, 4], "enum_ref": "CB_COLOR_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE", "name": "MIN_COMPRESSED_BLOCK_SIZE"}, 10391 {"bits": [5, 6], "name": "MAX_COMPRESSED_BLOCK_SIZE"}, 10392 {"bits": [7, 8], "name": "COLOR_TRANSFORM"}, 10393 {"bits": [9, 9], "name": "INDEPENDENT_64B_BLOCKS"}, 10394 {"bits": [10, 13], "name": "LOSSY_RGB_PRECISION"}, 10395 {"bits": [14, 17], "name": "LOSSY_ALPHA_PRECISION"}, 10396 {"bits": [18, 18], "name": "DISABLE_CONSTANT_ENCODE_REG"}, 10397 {"bits": [19, 19], "name": "ENABLE_CONSTANT_ENCODE_REG_WRITE"} 10398 ] 10399 }, 10400 "CB_COLOR0_INFO": { 10401 "fields": [ 10402 {"bits": [0, 1], "enum_ref": "SurfaceEndian", "name": "ENDIAN"}, 10403 {"bits": [2, 6], "enum_ref": "ColorFormat", "name": "FORMAT"}, 10404 {"bits": [8, 10], "enum_ref": "SurfaceNumber", "name": "NUMBER_TYPE"}, 10405 {"bits": [11, 12], "enum_ref": "SurfaceSwap", "name": "COMP_SWAP"}, 10406 {"bits": [13, 13], "name": "FAST_CLEAR"}, 10407 {"bits": [14, 14], "name": "COMPRESSION"}, 10408 {"bits": [15, 15], "name": "BLEND_CLAMP"}, 10409 {"bits": [16, 16], "name": "BLEND_BYPASS"}, 10410 {"bits": [17, 17], "name": "SIMPLE_FLOAT"}, 10411 {"bits": [18, 18], "name": "ROUND_MODE"}, 10412 {"bits": [20, 22], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DONT_RD_DST"}, 10413 {"bits": [23, 25], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DISCARD_PIXEL"}, 10414 {"bits": [26, 26], "name": "FMASK_COMPRESSION_DISABLE"}, 10415 {"bits": [27, 27], "name": "FMASK_COMPRESS_1FRAG_ONLY"}, 10416 {"bits": [28, 28], "name": "DCC_ENABLE"}, 10417 {"bits": [29, 30], "enum_ref": "CmaskAddr", "name": "CMASK_ADDR_TYPE"} 10418 ] 10419 }, 10420 "CB_COLOR0_VIEW": { 10421 "fields": [ 10422 {"bits": [0, 10], "name": "SLICE_START"}, 10423 {"bits": [13, 23], "name": "SLICE_MAX"}, 10424 {"bits": [24, 27], "name": "MIP_LEVEL"} 10425 ] 10426 }, 10427 "CB_COLOR_CONTROL": { 10428 "fields": [ 10429 {"bits": [0, 0], "name": "DISABLE_DUAL_QUAD"}, 10430 {"bits": [3, 3], "name": "DEGAMMA_ENABLE"}, 10431 {"bits": [4, 6], "enum_ref": "CBMode", "name": "MODE"}, 10432 {"bits": [16, 23], "enum_ref": "ROP3", "name": "ROP3"} 10433 ] 10434 }, 10435 "CB_DCC_CONTROL": { 10436 "fields": [ 10437 {"bits": [0, 0], "name": "OVERWRITE_COMBINER_DISABLE"}, 10438 {"bits": [1, 1], "name": "OVERWRITE_COMBINER_MRT_SHARING_DISABLE"}, 10439 {"bits": [2, 6], "name": "OVERWRITE_COMBINER_WATERMARK"}, 10440 {"bits": [8, 8], "name": "DISABLE_CONSTANT_ENCODE_AC01"}, 10441 {"bits": [9, 9], "name": "DISABLE_CONSTANT_ENCODE_SINGLE"}, 10442 {"bits": [10, 10], "name": "DISABLE_CONSTANT_ENCODE_REG"}, 10443 {"bits": [12, 12], "name": "DISABLE_ELIMFC_SKIP_OF_AC01"}, 10444 {"bits": [13, 13], "name": "DISABLE_ELIMFC_SKIP_OF_SINGLE"}, 10445 {"bits": [14, 14], "name": "ENABLE_ELIMFC_SKIP_OF_REG"} 10446 ] 10447 }, 10448 "CB_PERFCOUNTER0_SELECT": { 10449 "fields": [ 10450 {"bits": [0, 8], "name": "PERF_SEL"}, 10451 {"bits": [10, 18], "name": "PERF_SEL1"}, 10452 {"bits": [20, 23], "name": "CNTR_MODE"}, 10453 {"bits": [24, 27], "name": "PERF_MODE1"}, 10454 {"bits": [28, 31], "name": "PERF_MODE"} 10455 ] 10456 }, 10457 "CB_PERFCOUNTER0_SELECT1": { 10458 "fields": [ 10459 {"bits": [0, 8], "name": "PERF_SEL2"}, 10460 {"bits": [10, 18], "name": "PERF_SEL3"}, 10461 {"bits": [24, 27], "name": "PERF_MODE3"}, 10462 {"bits": [28, 31], "name": "PERF_MODE2"} 10463 ] 10464 }, 10465 "CB_PERFCOUNTER1_SELECT": { 10466 "fields": [ 10467 {"bits": [0, 8], "name": "PERF_SEL"}, 10468 {"bits": [28, 31], "name": "PERF_MODE"} 10469 ] 10470 }, 10471 "CB_PERFCOUNTER_FILTER": { 10472 "fields": [ 10473 {"bits": [0, 0], "name": "OP_FILTER_ENABLE"}, 10474 {"bits": [1, 3], "enum_ref": "CBPerfOpFilterSel", "name": "OP_FILTER_SEL"}, 10475 {"bits": [4, 4], "name": "FORMAT_FILTER_ENABLE"}, 10476 {"bits": [5, 9], "name": "FORMAT_FILTER_SEL"}, 10477 {"bits": [10, 10], "name": "CLEAR_FILTER_ENABLE"}, 10478 {"bits": [11, 11], "enum_ref": "CBPerfClearFilterSel", "name": "CLEAR_FILTER_SEL"}, 10479 {"bits": [12, 12], "name": "MRT_FILTER_ENABLE"}, 10480 {"bits": [13, 15], "name": "MRT_FILTER_SEL"}, 10481 {"bits": [17, 17], "name": "NUM_SAMPLES_FILTER_ENABLE"}, 10482 {"bits": [18, 20], "name": "NUM_SAMPLES_FILTER_SEL"}, 10483 {"bits": [21, 21], "name": "NUM_FRAGMENTS_FILTER_ENABLE"}, 10484 {"bits": [22, 23], "name": "NUM_FRAGMENTS_FILTER_SEL"} 10485 ] 10486 }, 10487 "CB_SHADER_MASK": { 10488 "fields": [ 10489 {"bits": [0, 3], "name": "OUTPUT0_ENABLE"}, 10490 {"bits": [4, 7], "name": "OUTPUT1_ENABLE"}, 10491 {"bits": [8, 11], "name": "OUTPUT2_ENABLE"}, 10492 {"bits": [12, 15], "name": "OUTPUT3_ENABLE"}, 10493 {"bits": [16, 19], "name": "OUTPUT4_ENABLE"}, 10494 {"bits": [20, 23], "name": "OUTPUT5_ENABLE"}, 10495 {"bits": [24, 27], "name": "OUTPUT6_ENABLE"}, 10496 {"bits": [28, 31], "name": "OUTPUT7_ENABLE"} 10497 ] 10498 }, 10499 "CB_TARGET_MASK": { 10500 "fields": [ 10501 {"bits": [0, 3], "name": "TARGET0_ENABLE"}, 10502 {"bits": [4, 7], "name": "TARGET1_ENABLE"}, 10503 {"bits": [8, 11], "name": "TARGET2_ENABLE"}, 10504 {"bits": [12, 15], "name": "TARGET3_ENABLE"}, 10505 {"bits": [16, 19], "name": "TARGET4_ENABLE"}, 10506 {"bits": [20, 23], "name": "TARGET5_ENABLE"}, 10507 {"bits": [24, 27], "name": "TARGET6_ENABLE"}, 10508 {"bits": [28, 31], "name": "TARGET7_ENABLE"} 10509 ] 10510 }, 10511 "COHER_DEST_BASE_HI_0": { 10512 "fields": [ 10513 {"bits": [0, 7], "name": "DEST_BASE_HI_256B"} 10514 ] 10515 }, 10516 "COMPUTE_DISPATCH_INITIATOR": { 10517 "fields": [ 10518 {"bits": [0, 0], "name": "COMPUTE_SHADER_EN"}, 10519 {"bits": [1, 1], "name": "PARTIAL_TG_EN"}, 10520 {"bits": [2, 2], "name": "FORCE_START_AT_000"}, 10521 {"bits": [3, 3], "name": "ORDERED_APPEND_ENBL"}, 10522 {"bits": [4, 4], "name": "ORDERED_APPEND_MODE"}, 10523 {"bits": [5, 5], "name": "USE_THREAD_DIMENSIONS"}, 10524 {"bits": [6, 6], "name": "ORDER_MODE"}, 10525 {"bits": [10, 10], "name": "SCALAR_L1_INV_VOL"}, 10526 {"bits": [11, 11], "name": "VECTOR_L1_INV_VOL"}, 10527 {"bits": [12, 12], "name": "RESERVED"}, 10528 {"bits": [14, 14], "name": "RESTORE"} 10529 ] 10530 }, 10531 "COMPUTE_MISC_RESERVED": { 10532 "fields": [ 10533 {"bits": [0, 1], "name": "SEND_SEID"}, 10534 {"bits": [2, 2], "name": "RESERVED2"}, 10535 {"bits": [3, 3], "name": "RESERVED3"}, 10536 {"bits": [4, 4], "name": "RESERVED4"}, 10537 {"bits": [5, 16], "name": "WAVE_ID_BASE"} 10538 ] 10539 }, 10540 "COMPUTE_NUM_THREAD_X": { 10541 "fields": [ 10542 {"bits": [0, 15], "name": "NUM_THREAD_FULL"}, 10543 {"bits": [16, 31], "name": "NUM_THREAD_PARTIAL"} 10544 ] 10545 }, 10546 "COMPUTE_PERFCOUNT_ENABLE": { 10547 "fields": [ 10548 {"bits": [0, 0], "name": "PERFCOUNT_ENABLE"} 10549 ] 10550 }, 10551 "COMPUTE_PGM_HI": { 10552 "fields": [ 10553 {"bits": [0, 7], "name": "DATA"} 10554 ] 10555 }, 10556 "COMPUTE_PGM_RSRC1": { 10557 "fields": [ 10558 {"bits": [0, 5], "name": "VGPRS"}, 10559 {"bits": [6, 9], "name": "SGPRS"}, 10560 {"bits": [10, 11], "name": "PRIORITY"}, 10561 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, 10562 {"bits": [20, 20], "name": "PRIV"}, 10563 {"bits": [21, 21], "name": "DX10_CLAMP"}, 10564 {"bits": [22, 22], "name": "DEBUG_MODE"}, 10565 {"bits": [23, 23], "name": "IEEE_MODE"}, 10566 {"bits": [24, 24], "name": "BULKY"}, 10567 {"bits": [25, 25], "name": "CDBG_USER"}, 10568 {"bits": [26, 26], "name": "FP16_OVFL"} 10569 ] 10570 }, 10571 "COMPUTE_PGM_RSRC2": { 10572 "fields": [ 10573 {"bits": [0, 0], "name": "SCRATCH_EN"}, 10574 {"bits": [1, 5], "name": "USER_SGPR"}, 10575 {"bits": [6, 6], "name": "TRAP_PRESENT"}, 10576 {"bits": [7, 7], "name": "TGID_X_EN"}, 10577 {"bits": [8, 8], "name": "TGID_Y_EN"}, 10578 {"bits": [9, 9], "name": "TGID_Z_EN"}, 10579 {"bits": [10, 10], "name": "TG_SIZE_EN"}, 10580 {"bits": [11, 12], "name": "TIDIG_COMP_CNT"}, 10581 {"bits": [13, 14], "name": "EXCP_EN_MSB"}, 10582 {"bits": [15, 23], "name": "LDS_SIZE"}, 10583 {"bits": [24, 30], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, 10584 {"bits": [31, 31], "name": "SKIP_USGPR0"} 10585 ] 10586 }, 10587 "COMPUTE_PIPELINESTAT_ENABLE": { 10588 "fields": [ 10589 {"bits": [0, 0], "name": "PIPELINESTAT_ENABLE"} 10590 ] 10591 }, 10592 "COMPUTE_RELAUNCH": { 10593 "fields": [ 10594 {"bits": [0, 29], "name": "PAYLOAD"}, 10595 {"bits": [30, 30], "name": "IS_EVENT"}, 10596 {"bits": [31, 31], "name": "IS_STATE"} 10597 ] 10598 }, 10599 "COMPUTE_RESOURCE_LIMITS": { 10600 "fields": [ 10601 {"bits": [0, 9], "name": "WAVES_PER_SH"}, 10602 {"bits": [12, 15], "name": "TG_PER_CU"}, 10603 {"bits": [16, 21], "name": "LOCK_THRESHOLD"}, 10604 {"bits": [22, 22], "name": "SIMD_DEST_CNTL"}, 10605 {"bits": [23, 23], "name": "FORCE_SIMD_DIST"}, 10606 {"bits": [24, 26], "name": "CU_GROUP_COUNT"}, 10607 {"bits": [27, 30], "name": "SIMD_DISABLE"} 10608 ] 10609 }, 10610 "COMPUTE_STATIC_THREAD_MGMT_SE0": { 10611 "fields": [ 10612 {"bits": [0, 15], "name": "SH0_CU_EN"}, 10613 {"bits": [16, 31], "name": "SH1_CU_EN"} 10614 ] 10615 }, 10616 "COMPUTE_THREAD_TRACE_ENABLE": { 10617 "fields": [ 10618 {"bits": [0, 0], "name": "THREAD_TRACE_ENABLE"} 10619 ] 10620 }, 10621 "COMPUTE_TMPRING_SIZE": { 10622 "fields": [ 10623 {"bits": [0, 11], "name": "WAVES"}, 10624 {"bits": [12, 24], "name": "WAVESIZE"} 10625 ] 10626 }, 10627 "COMPUTE_VMID": { 10628 "fields": [ 10629 {"bits": [0, 3], "name": "DATA"} 10630 ] 10631 }, 10632 "COMPUTE_WAVE_RESTORE_ADDR_HI": { 10633 "fields": [ 10634 {"bits": [0, 15], "name": "ADDR"} 10635 ] 10636 }, 10637 "CPC_LATENCY_STATS_SELECT": { 10638 "fields": [ 10639 {"bits": [0, 2], "name": "INDEX"}, 10640 {"bits": [30, 30], "name": "CLEAR"}, 10641 {"bits": [31, 31], "name": "ENABLE"} 10642 ] 10643 }, 10644 "CPF_LATENCY_STATS_SELECT": { 10645 "fields": [ 10646 {"bits": [0, 3], "name": "INDEX"}, 10647 {"bits": [30, 30], "name": "CLEAR"}, 10648 {"bits": [31, 31], "name": "ENABLE"} 10649 ] 10650 }, 10651 "CPF_TC_PERF_COUNTER_WINDOW_SELECT": { 10652 "fields": [ 10653 {"bits": [0, 2], "name": "INDEX"}, 10654 {"bits": [30, 30], "name": "ALWAYS"}, 10655 {"bits": [31, 31], "name": "ENABLE"} 10656 ] 10657 }, 10658 "CPG_LATENCY_STATS_SELECT": { 10659 "fields": [ 10660 {"bits": [0, 4], "name": "INDEX"}, 10661 {"bits": [30, 30], "name": "CLEAR"}, 10662 {"bits": [31, 31], "name": "ENABLE"} 10663 ] 10664 }, 10665 "CPG_PERFCOUNTER0_SELECT1": { 10666 "fields": [ 10667 {"bits": [0, 9], "name": "CNTR_SEL2"}, 10668 {"bits": [10, 19], "name": "CNTR_SEL3"}, 10669 {"bits": [24, 27], "name": "CNTR_MODE3"}, 10670 {"bits": [28, 31], "name": "CNTR_MODE2"} 10671 ] 10672 }, 10673 "CPG_PERFCOUNTER1_SELECT": { 10674 "fields": [ 10675 {"bits": [0, 9], "name": "CNTR_SEL0"}, 10676 {"bits": [10, 19], "name": "CNTR_SEL1"}, 10677 {"bits": [20, 23], "name": "SPM_MODE"}, 10678 {"bits": [24, 27], "name": "CNTR_MODE1"}, 10679 {"bits": [28, 31], "name": "CNTR_MODE0"} 10680 ] 10681 }, 10682 "CPG_TC_PERF_COUNTER_WINDOW_SELECT": { 10683 "fields": [ 10684 {"bits": [0, 4], "name": "INDEX"}, 10685 {"bits": [30, 30], "name": "ALWAYS"}, 10686 {"bits": [31, 31], "name": "ENABLE"} 10687 ] 10688 }, 10689 "CP_APPEND_ADDR_HI": { 10690 "fields": [ 10691 {"bits": [0, 15], "name": "MEM_ADDR_HI"}, 10692 {"bits": [16, 16], "name": "CS_PS_SEL"}, 10693 {"bits": [25, 25], "name": "CACHE_POLICY"}, 10694 {"bits": [29, 31], "name": "COMMAND"} 10695 ] 10696 }, 10697 "CP_APPEND_ADDR_LO": { 10698 "fields": [ 10699 {"bits": [2, 31], "name": "MEM_ADDR_LO"} 10700 ] 10701 }, 10702 "CP_CE_IB1_BASE_HI": { 10703 "fields": [ 10704 {"bits": [0, 15], "name": "IB1_BASE_HI"} 10705 ] 10706 }, 10707 "CP_CE_IB1_BASE_LO": { 10708 "fields": [ 10709 {"bits": [2, 31], "name": "IB1_BASE_LO"} 10710 ] 10711 }, 10712 "CP_CE_IB1_BUFSZ": { 10713 "fields": [ 10714 {"bits": [0, 19], "name": "IB1_BUFSZ"} 10715 ] 10716 }, 10717 "CP_CE_IB1_CMD_BUFSZ": { 10718 "fields": [ 10719 {"bits": [0, 19], "name": "IB1_CMD_REQSZ"} 10720 ] 10721 }, 10722 "CP_CE_IB2_BASE_HI": { 10723 "fields": [ 10724 {"bits": [0, 15], "name": "IB2_BASE_HI"} 10725 ] 10726 }, 10727 "CP_CE_IB2_BASE_LO": { 10728 "fields": [ 10729 {"bits": [2, 31], "name": "IB2_BASE_LO"} 10730 ] 10731 }, 10732 "CP_CE_IB2_BUFSZ": { 10733 "fields": [ 10734 {"bits": [0, 19], "name": "IB2_BUFSZ"} 10735 ] 10736 }, 10737 "CP_CE_IB2_CMD_BUFSZ": { 10738 "fields": [ 10739 {"bits": [0, 19], "name": "IB2_CMD_REQSZ"} 10740 ] 10741 }, 10742 "CP_CE_INIT_BASE_HI": { 10743 "fields": [ 10744 {"bits": [0, 15], "name": "INIT_BASE_HI"} 10745 ] 10746 }, 10747 "CP_CE_INIT_BASE_LO": { 10748 "fields": [ 10749 {"bits": [5, 31], "name": "INIT_BASE_LO"} 10750 ] 10751 }, 10752 "CP_CE_INIT_BUFSZ": { 10753 "fields": [ 10754 {"bits": [0, 11], "name": "INIT_BUFSZ"} 10755 ] 10756 }, 10757 "CP_CE_INIT_CMD_BUFSZ": { 10758 "fields": [ 10759 {"bits": [0, 11], "name": "INIT_CMD_REQSZ"} 10760 ] 10761 }, 10762 "CP_COHER_BASE_HI": { 10763 "fields": [ 10764 {"bits": [0, 7], "name": "COHER_BASE_HI_256B"} 10765 ] 10766 }, 10767 "CP_COHER_CNTL": { 10768 "fields": [ 10769 {"bits": [3, 3], "name": "TC_NC_ACTION_ENA"}, 10770 {"bits": [4, 4], "name": "TC_WC_ACTION_ENA"}, 10771 {"bits": [5, 5], "name": "TC_INV_METADATA_ACTION_ENA"}, 10772 {"bits": [15, 15], "name": "TCL1_VOL_ACTION_ENA"}, 10773 {"bits": [18, 18], "name": "TC_WB_ACTION_ENA"}, 10774 {"bits": [22, 22], "name": "TCL1_ACTION_ENA"}, 10775 {"bits": [23, 23], "name": "TC_ACTION_ENA"}, 10776 {"bits": [25, 25], "name": "CB_ACTION_ENA"}, 10777 {"bits": [26, 26], "name": "DB_ACTION_ENA"}, 10778 {"bits": [27, 27], "name": "SH_KCACHE_ACTION_ENA"}, 10779 {"bits": [28, 28], "name": "SH_KCACHE_VOL_ACTION_ENA"}, 10780 {"bits": [29, 29], "name": "SH_ICACHE_ACTION_ENA"}, 10781 {"bits": [30, 30], "name": "SH_KCACHE_WB_ACTION_ENA"} 10782 ] 10783 }, 10784 "CP_COHER_SIZE_HI": { 10785 "fields": [ 10786 {"bits": [0, 7], "name": "COHER_SIZE_HI_256B"} 10787 ] 10788 }, 10789 "CP_COHER_START_DELAY": { 10790 "fields": [ 10791 {"bits": [0, 5], "name": "START_DELAY_COUNT"} 10792 ] 10793 }, 10794 "CP_COHER_STATUS": { 10795 "fields": [ 10796 {"bits": [24, 25], "name": "MEID"}, 10797 {"bits": [31, 31], "name": "STATUS"} 10798 ] 10799 }, 10800 "CP_CPC_BUSY_STAT": { 10801 "fields": [ 10802 {"bits": [0, 0], "name": "MEC1_LOAD_BUSY"}, 10803 {"bits": [1, 1], "name": "MEC1_SEMAPOHRE_BUSY"}, 10804 {"bits": [2, 2], "name": "MEC1_MUTEX_BUSY"}, 10805 {"bits": [3, 3], "name": "MEC1_MESSAGE_BUSY"}, 10806 {"bits": [4, 4], "name": "MEC1_EOP_QUEUE_BUSY"}, 10807 {"bits": [5, 5], "name": "MEC1_IQ_QUEUE_BUSY"}, 10808 {"bits": [6, 6], "name": "MEC1_IB_QUEUE_BUSY"}, 10809 {"bits": [7, 7], "name": "MEC1_TC_BUSY"}, 10810 {"bits": [8, 8], "name": "MEC1_DMA_BUSY"}, 10811 {"bits": [9, 9], "name": "MEC1_PARTIAL_FLUSH_BUSY"}, 10812 {"bits": [10, 10], "name": "MEC1_PIPE0_BUSY"}, 10813 {"bits": [11, 11], "name": "MEC1_PIPE1_BUSY"}, 10814 {"bits": [12, 12], "name": "MEC1_PIPE2_BUSY"}, 10815 {"bits": [13, 13], "name": "MEC1_PIPE3_BUSY"}, 10816 {"bits": [16, 16], "name": "MEC2_LOAD_BUSY"}, 10817 {"bits": [17, 17], "name": "MEC2_SEMAPOHRE_BUSY"}, 10818 {"bits": [18, 18], "name": "MEC2_MUTEX_BUSY"}, 10819 {"bits": [19, 19], "name": "MEC2_MESSAGE_BUSY"}, 10820 {"bits": [20, 20], "name": "MEC2_EOP_QUEUE_BUSY"}, 10821 {"bits": [21, 21], "name": "MEC2_IQ_QUEUE_BUSY"}, 10822 {"bits": [22, 22], "name": "MEC2_IB_QUEUE_BUSY"}, 10823 {"bits": [23, 23], "name": "MEC2_TC_BUSY"}, 10824 {"bits": [24, 24], "name": "MEC2_DMA_BUSY"}, 10825 {"bits": [25, 25], "name": "MEC2_PARTIAL_FLUSH_BUSY"}, 10826 {"bits": [26, 26], "name": "MEC2_PIPE0_BUSY"}, 10827 {"bits": [27, 27], "name": "MEC2_PIPE1_BUSY"}, 10828 {"bits": [28, 28], "name": "MEC2_PIPE2_BUSY"}, 10829 {"bits": [29, 29], "name": "MEC2_PIPE3_BUSY"} 10830 ] 10831 }, 10832 "CP_CPC_GRBM_FREE_COUNT": { 10833 "fields": [ 10834 {"bits": [0, 5], "name": "FREE_COUNT"} 10835 ] 10836 }, 10837 "CP_CPC_HALT_HYST_COUNT": { 10838 "fields": [ 10839 {"bits": [0, 3], "name": "COUNT"} 10840 ] 10841 }, 10842 "CP_CPC_SCRATCH_INDEX": { 10843 "fields": [ 10844 {"bits": [0, 8], "name": "SCRATCH_INDEX"} 10845 ] 10846 }, 10847 "CP_CPC_STALLED_STAT1": { 10848 "fields": [ 10849 {"bits": [3, 3], "name": "RCIU_TX_FREE_STALL"}, 10850 {"bits": [4, 4], "name": "RCIU_PRIV_VIOLATION"}, 10851 {"bits": [6, 6], "name": "TCIU_TX_FREE_STALL"}, 10852 {"bits": [8, 8], "name": "MEC1_DECODING_PACKET"}, 10853 {"bits": [9, 9], "name": "MEC1_WAIT_ON_RCIU"}, 10854 {"bits": [10, 10], "name": "MEC1_WAIT_ON_RCIU_READ"}, 10855 {"bits": [13, 13], "name": "MEC1_WAIT_ON_ROQ_DATA"}, 10856 {"bits": [16, 16], "name": "MEC2_DECODING_PACKET"}, 10857 {"bits": [17, 17], "name": "MEC2_WAIT_ON_RCIU"}, 10858 {"bits": [18, 18], "name": "MEC2_WAIT_ON_RCIU_READ"}, 10859 {"bits": [21, 21], "name": "MEC2_WAIT_ON_ROQ_DATA"}, 10860 {"bits": [22, 22], "name": "UTCL2IU_WAITING_ON_FREE"}, 10861 {"bits": [23, 23], "name": "UTCL2IU_WAITING_ON_TAGS"}, 10862 {"bits": [24, 24], "name": "UTCL1_WAITING_ON_TRANS"} 10863 ] 10864 }, 10865 "CP_CPC_STATUS": { 10866 "fields": [ 10867 {"bits": [0, 0], "name": "MEC1_BUSY"}, 10868 {"bits": [1, 1], "name": "MEC2_BUSY"}, 10869 {"bits": [2, 2], "name": "DC0_BUSY"}, 10870 {"bits": [3, 3], "name": "DC1_BUSY"}, 10871 {"bits": [4, 4], "name": "RCIU1_BUSY"}, 10872 {"bits": [5, 5], "name": "RCIU2_BUSY"}, 10873 {"bits": [6, 6], "name": "ROQ1_BUSY"}, 10874 {"bits": [7, 7], "name": "ROQ2_BUSY"}, 10875 {"bits": [10, 10], "name": "TCIU_BUSY"}, 10876 {"bits": [11, 11], "name": "SCRATCH_RAM_BUSY"}, 10877 {"bits": [12, 12], "name": "QU_BUSY"}, 10878 {"bits": [13, 13], "name": "UTCL2IU_BUSY"}, 10879 {"bits": [14, 14], "name": "SAVE_RESTORE_BUSY"}, 10880 {"bits": [29, 29], "name": "CPG_CPC_BUSY"}, 10881 {"bits": [30, 30], "name": "CPF_CPC_BUSY"}, 10882 {"bits": [31, 31], "name": "CPC_BUSY"} 10883 ] 10884 }, 10885 "CP_CPF_BUSY_STAT": { 10886 "fields": [ 10887 {"bits": [0, 0], "name": "REG_BUS_FIFO_BUSY"}, 10888 {"bits": [1, 1], "name": "CSF_RING_BUSY"}, 10889 {"bits": [2, 2], "name": "CSF_INDIRECT1_BUSY"}, 10890 {"bits": [3, 3], "name": "CSF_INDIRECT2_BUSY"}, 10891 {"bits": [4, 4], "name": "CSF_STATE_BUSY"}, 10892 {"bits": [5, 5], "name": "CSF_CE_INDR1_BUSY"}, 10893 {"bits": [6, 6], "name": "CSF_CE_INDR2_BUSY"}, 10894 {"bits": [7, 7], "name": "CSF_ARBITER_BUSY"}, 10895 {"bits": [8, 8], "name": "CSF_INPUT_BUSY"}, 10896 {"bits": [9, 9], "name": "OUTSTANDING_READ_TAGS"}, 10897 {"bits": [11, 11], "name": "HPD_PROCESSING_EOP_BUSY"}, 10898 {"bits": [12, 12], "name": "HQD_DISPATCH_BUSY"}, 10899 {"bits": [13, 13], "name": "HQD_IQ_TIMER_BUSY"}, 10900 {"bits": [14, 14], "name": "HQD_DMA_OFFLOAD_BUSY"}, 10901 {"bits": [15, 15], "name": "HQD_WAIT_SEMAPHORE_BUSY"}, 10902 {"bits": [16, 16], "name": "HQD_SIGNAL_SEMAPHORE_BUSY"}, 10903 {"bits": [17, 17], "name": "HQD_MESSAGE_BUSY"}, 10904 {"bits": [18, 18], "name": "HQD_PQ_FETCHER_BUSY"}, 10905 {"bits": [19, 19], "name": "HQD_IB_FETCHER_BUSY"}, 10906 {"bits": [20, 20], "name": "HQD_IQ_FETCHER_BUSY"}, 10907 {"bits": [21, 21], "name": "HQD_EOP_FETCHER_BUSY"}, 10908 {"bits": [22, 22], "name": "HQD_CONSUMED_RPTR_BUSY"}, 10909 {"bits": [23, 23], "name": "HQD_FETCHER_ARB_BUSY"}, 10910 {"bits": [24, 24], "name": "HQD_ROQ_ALIGN_BUSY"}, 10911 {"bits": [25, 25], "name": "HQD_ROQ_EOP_BUSY"}, 10912 {"bits": [26, 26], "name": "HQD_ROQ_IQ_BUSY"}, 10913 {"bits": [27, 27], "name": "HQD_ROQ_PQ_BUSY"}, 10914 {"bits": [28, 28], "name": "HQD_ROQ_IB_BUSY"}, 10915 {"bits": [29, 29], "name": "HQD_WPTR_POLL_BUSY"}, 10916 {"bits": [30, 30], "name": "HQD_PQ_BUSY"}, 10917 {"bits": [31, 31], "name": "HQD_IB_BUSY"} 10918 ] 10919 }, 10920 "CP_CPF_GRBM_FREE_COUNT": { 10921 "fields": [ 10922 {"bits": [0, 2], "name": "FREE_COUNT"} 10923 ] 10924 }, 10925 "CP_CPF_STALLED_STAT1": { 10926 "fields": [ 10927 {"bits": [0, 0], "name": "RING_FETCHING_DATA"}, 10928 {"bits": [1, 1], "name": "INDR1_FETCHING_DATA"}, 10929 {"bits": [2, 2], "name": "INDR2_FETCHING_DATA"}, 10930 {"bits": [3, 3], "name": "STATE_FETCHING_DATA"}, 10931 {"bits": [5, 5], "name": "TCIU_WAITING_ON_FREE"}, 10932 {"bits": [6, 6], "name": "TCIU_WAITING_ON_TAGS"}, 10933 {"bits": [7, 7], "name": "UTCL2IU_WAITING_ON_FREE"}, 10934 {"bits": [8, 8], "name": "UTCL2IU_WAITING_ON_TAGS"}, 10935 {"bits": [9, 9], "name": "GFX_UTCL1_WAITING_ON_TRANS"}, 10936 {"bits": [10, 10], "name": "CMP_UTCL1_WAITING_ON_TRANS"}, 10937 {"bits": [11, 11], "name": "RCIU_WAITING_ON_FREE"} 10938 ] 10939 }, 10940 "CP_CPF_STATUS": { 10941 "fields": [ 10942 {"bits": [0, 0], "name": "POST_WPTR_GFX_BUSY"}, 10943 {"bits": [1, 1], "name": "CSF_BUSY"}, 10944 {"bits": [4, 4], "name": "ROQ_ALIGN_BUSY"}, 10945 {"bits": [5, 5], "name": "ROQ_RING_BUSY"}, 10946 {"bits": [6, 6], "name": "ROQ_INDIRECT1_BUSY"}, 10947 {"bits": [7, 7], "name": "ROQ_INDIRECT2_BUSY"}, 10948 {"bits": [8, 8], "name": "ROQ_STATE_BUSY"}, 10949 {"bits": [9, 9], "name": "ROQ_CE_RING_BUSY"}, 10950 {"bits": [10, 10], "name": "ROQ_CE_INDIRECT1_BUSY"}, 10951 {"bits": [11, 11], "name": "ROQ_CE_INDIRECT2_BUSY"}, 10952 {"bits": [12, 12], "name": "SEMAPHORE_BUSY"}, 10953 {"bits": [13, 13], "name": "INTERRUPT_BUSY"}, 10954 {"bits": [14, 14], "name": "TCIU_BUSY"}, 10955 {"bits": [15, 15], "name": "HQD_BUSY"}, 10956 {"bits": [16, 16], "name": "PRT_BUSY"}, 10957 {"bits": [17, 17], "name": "UTCL2IU_BUSY"}, 10958 {"bits": [26, 26], "name": "CPF_GFX_BUSY"}, 10959 {"bits": [27, 27], "name": "CPF_CMP_BUSY"}, 10960 {"bits": [28, 29], "name": "GRBM_CPF_STAT_BUSY"}, 10961 {"bits": [30, 30], "name": "CPC_CPF_BUSY"}, 10962 {"bits": [31, 31], "name": "CPF_BUSY"} 10963 ] 10964 }, 10965 "CP_DMA_CNTL": { 10966 "fields": [ 10967 {"bits": [0, 0], "name": "UTCL1_FAULT_CONTROL"}, 10968 {"bits": [4, 5], "name": "MIN_AVAILSZ"}, 10969 {"bits": [16, 19], "name": "BUFFER_DEPTH"}, 10970 {"bits": [28, 28], "name": "PIO_FIFO_EMPTY"}, 10971 {"bits": [29, 29], "name": "PIO_FIFO_FULL"}, 10972 {"bits": [30, 31], "name": "PIO_COUNT"} 10973 ] 10974 }, 10975 "CP_DMA_ME_COMMAND": { 10976 "fields": [ 10977 {"bits": [0, 25], "name": "BYTE_COUNT"}, 10978 {"bits": [26, 26], "name": "SAS"}, 10979 {"bits": [27, 27], "name": "DAS"}, 10980 {"bits": [28, 28], "name": "SAIC"}, 10981 {"bits": [29, 29], "name": "DAIC"}, 10982 {"bits": [30, 30], "name": "RAW_WAIT"}, 10983 {"bits": [31, 31], "name": "DIS_WC"} 10984 ] 10985 }, 10986 "CP_DMA_ME_DST_ADDR_HI": { 10987 "fields": [ 10988 {"bits": [0, 15], "name": "DST_ADDR_HI"} 10989 ] 10990 }, 10991 "CP_DMA_ME_SRC_ADDR_HI": { 10992 "fields": [ 10993 {"bits": [0, 15], "name": "SRC_ADDR_HI"} 10994 ] 10995 }, 10996 "CP_DMA_PFP_CONTROL": { 10997 "fields": [ 10998 {"bits": [10, 10], "name": "MEMLOG_CLEAR"}, 10999 {"bits": [13, 13], "name": "SRC_CACHE_POLICY"}, 11000 {"bits": [20, 21], "name": "DST_SELECT"}, 11001 {"bits": [25, 25], "name": "DST_CACHE_POLICY"}, 11002 {"bits": [29, 30], "name": "SRC_SELECT"} 11003 ] 11004 }, 11005 "CP_DMA_READ_TAGS": { 11006 "fields": [ 11007 {"bits": [0, 25], "name": "DMA_READ_TAG"}, 11008 {"bits": [28, 28], "name": "DMA_READ_TAG_VALID"} 11009 ] 11010 }, 11011 "CP_DRAW_WINDOW_CNTL": { 11012 "fields": [ 11013 {"bits": [0, 0], "name": "DISABLE_DRAW_WINDOW_LO_MAX"}, 11014 {"bits": [1, 1], "name": "DISABLE_DRAW_WINDOW_LO_MIN"}, 11015 {"bits": [2, 2], "name": "DISABLE_DRAW_WINDOW_HI"}, 11016 {"bits": [8, 8], "name": "MODE"} 11017 ] 11018 }, 11019 "CP_DRAW_WINDOW_LO": { 11020 "fields": [ 11021 {"bits": [0, 15], "name": "MIN"}, 11022 {"bits": [16, 31], "name": "MAX"} 11023 ] 11024 }, 11025 "CP_EOP_DONE_ADDR_HI": { 11026 "fields": [ 11027 {"bits": [0, 15], "name": "ADDR_HI"} 11028 ] 11029 }, 11030 "CP_EOP_DONE_ADDR_LO": { 11031 "fields": [ 11032 {"bits": [2, 31], "name": "ADDR_LO"} 11033 ] 11034 }, 11035 "CP_EOP_DONE_DATA_CNTL": { 11036 "fields": [ 11037 {"bits": [16, 17], "name": "DST_SEL"}, 11038 {"bits": [24, 26], "name": "INT_SEL"}, 11039 {"bits": [29, 31], "name": "DATA_SEL"} 11040 ] 11041 }, 11042 "CP_EOP_DONE_EVENT_CNTL": { 11043 "fields": [ 11044 {"bits": [0, 6], "name": "WBINV_TC_OP"}, 11045 {"bits": [12, 17], "name": "WBINV_ACTION_ENA"}, 11046 {"bits": [25, 25], "name": "CACHE_POLICY"}, 11047 {"bits": [28, 28], "name": "EXECUTE"} 11048 ] 11049 }, 11050 "CP_IB1_OFFSET": { 11051 "fields": [ 11052 {"bits": [0, 19], "name": "IB1_OFFSET"} 11053 ] 11054 }, 11055 "CP_IB1_PREAMBLE_BEGIN": { 11056 "fields": [ 11057 {"bits": [0, 19], "name": "IB1_PREAMBLE_BEGIN"} 11058 ] 11059 }, 11060 "CP_IB1_PREAMBLE_END": { 11061 "fields": [ 11062 {"bits": [0, 19], "name": "IB1_PREAMBLE_END"} 11063 ] 11064 }, 11065 "CP_IB2_OFFSET": { 11066 "fields": [ 11067 {"bits": [0, 19], "name": "IB2_OFFSET"} 11068 ] 11069 }, 11070 "CP_IB2_PREAMBLE_BEGIN": { 11071 "fields": [ 11072 {"bits": [0, 19], "name": "IB2_PREAMBLE_BEGIN"} 11073 ] 11074 }, 11075 "CP_IB2_PREAMBLE_END": { 11076 "fields": [ 11077 {"bits": [0, 19], "name": "IB2_PREAMBLE_END"} 11078 ] 11079 }, 11080 "CP_INDEX_TYPE": { 11081 "fields": [ 11082 {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"} 11083 ] 11084 }, 11085 "CP_ME_COHER_CNTL": { 11086 "fields": [ 11087 {"bits": [0, 0], "name": "DEST_BASE_0_ENA"}, 11088 {"bits": [1, 1], "name": "DEST_BASE_1_ENA"}, 11089 {"bits": [6, 6], "name": "CB0_DEST_BASE_ENA"}, 11090 {"bits": [7, 7], "name": "CB1_DEST_BASE_ENA"}, 11091 {"bits": [8, 8], "name": "CB2_DEST_BASE_ENA"}, 11092 {"bits": [9, 9], "name": "CB3_DEST_BASE_ENA"}, 11093 {"bits": [10, 10], "name": "CB4_DEST_BASE_ENA"}, 11094 {"bits": [11, 11], "name": "CB5_DEST_BASE_ENA"}, 11095 {"bits": [12, 12], "name": "CB6_DEST_BASE_ENA"}, 11096 {"bits": [13, 13], "name": "CB7_DEST_BASE_ENA"}, 11097 {"bits": [14, 14], "name": "DB_DEST_BASE_ENA"}, 11098 {"bits": [19, 19], "name": "DEST_BASE_2_ENA"}, 11099 {"bits": [21, 21], "name": "DEST_BASE_3_ENA"} 11100 ] 11101 }, 11102 "CP_ME_COHER_STATUS": { 11103 "fields": [ 11104 {"bits": [0, 7], "name": "MATCHING_GFX_CNTX"}, 11105 {"bits": [31, 31], "name": "STATUS"} 11106 ] 11107 }, 11108 "CP_ME_MC_RADDR_HI": { 11109 "fields": [ 11110 {"bits": [0, 15], "name": "ME_MC_RADDR_HI"}, 11111 {"bits": [22, 22], "name": "CACHE_POLICY"} 11112 ] 11113 }, 11114 "CP_ME_MC_RADDR_LO": { 11115 "fields": [ 11116 {"bits": [2, 31], "name": "ME_MC_RADDR_LO"} 11117 ] 11118 }, 11119 "CP_ME_MC_WADDR_HI": { 11120 "fields": [ 11121 {"bits": [0, 15], "name": "ME_MC_WADDR_HI"}, 11122 {"bits": [22, 22], "name": "CACHE_POLICY"} 11123 ] 11124 }, 11125 "CP_ME_MC_WADDR_LO": { 11126 "fields": [ 11127 {"bits": [2, 31], "name": "ME_MC_WADDR_LO"} 11128 ] 11129 }, 11130 "CP_PERFMON_CNTL": { 11131 "fields": [ 11132 {"bits": [0, 3], "enum_ref": "CP_PERFMON_STATE", "name": "PERFMON_STATE"}, 11133 {"bits": [4, 7], "enum_ref": "SPM_PERFMON_STATE", "name": "SPM_PERFMON_STATE"}, 11134 {"bits": [8, 9], "enum_ref": "CP_PERFMON_ENABLE_MODE", "name": "PERFMON_ENABLE_MODE"}, 11135 {"bits": [10, 10], "name": "PERFMON_SAMPLE_ENABLE"} 11136 ] 11137 }, 11138 "CP_PERFMON_CNTX_CNTL": { 11139 "fields": [ 11140 {"bits": [31, 31], "name": "PERFMON_ENABLE"} 11141 ] 11142 }, 11143 "CP_PFP_COMPLETION_STATUS": { 11144 "fields": [ 11145 {"bits": [0, 1], "name": "STATUS"} 11146 ] 11147 }, 11148 "CP_PFP_IB_CONTROL": { 11149 "fields": [ 11150 {"bits": [0, 7], "name": "IB_EN"} 11151 ] 11152 }, 11153 "CP_PFP_LOAD_CONTROL": { 11154 "fields": [ 11155 {"bits": [0, 0], "name": "CONFIG_REG_EN"}, 11156 {"bits": [1, 1], "name": "CNTX_REG_EN"}, 11157 {"bits": [16, 16], "name": "SH_GFX_REG_EN"}, 11158 {"bits": [24, 24], "name": "SH_CS_REG_EN"} 11159 ] 11160 }, 11161 "CP_PIPEID": { 11162 "fields": [ 11163 {"bits": [0, 1], "name": "PIPE_ID"} 11164 ] 11165 }, 11166 "CP_PIPE_STATS_ADDR_HI": { 11167 "fields": [ 11168 {"bits": [0, 15], "name": "PIPE_STATS_ADDR_HI"} 11169 ] 11170 }, 11171 "CP_PIPE_STATS_ADDR_LO": { 11172 "fields": [ 11173 {"bits": [2, 31], "name": "PIPE_STATS_ADDR_LO"} 11174 ] 11175 }, 11176 "CP_PIPE_STATS_CONTROL": { 11177 "fields": [ 11178 {"bits": [25, 25], "name": "CACHE_POLICY"} 11179 ] 11180 }, 11181 "CP_PRED_NOT_VISIBLE": { 11182 "fields": [ 11183 {"bits": [0, 0], "name": "NOT_VISIBLE"} 11184 ] 11185 }, 11186 "CP_RB_OFFSET": { 11187 "fields": [ 11188 {"bits": [0, 19], "name": "RB_OFFSET"} 11189 ] 11190 }, 11191 "CP_SAMPLE_STATUS": { 11192 "fields": [ 11193 {"bits": [0, 0], "name": "Z_PASS_ACITVE"}, 11194 {"bits": [1, 1], "name": "STREAMOUT_ACTIVE"}, 11195 {"bits": [2, 2], "name": "PIPELINE_ACTIVE"}, 11196 {"bits": [3, 3], "name": "STIPPLE_ACTIVE"}, 11197 {"bits": [4, 4], "name": "VGT_BUFFERS_ACTIVE"}, 11198 {"bits": [5, 5], "name": "SCREEN_EXT_ACTIVE"}, 11199 {"bits": [6, 6], "name": "DRAW_INDIRECT_ACTIVE"}, 11200 {"bits": [7, 7], "name": "DISP_INDIRECT_ACTIVE"} 11201 ] 11202 }, 11203 "CP_SCRATCH_INDEX": { 11204 "fields": [ 11205 {"bits": [0, 7], "name": "SCRATCH_INDEX"} 11206 ] 11207 }, 11208 "CP_SIG_SEM_ADDR_HI": { 11209 "fields": [ 11210 {"bits": [0, 15], "name": "SEM_ADDR_HI"}, 11211 {"bits": [16, 16], "name": "SEM_USE_MAILBOX"}, 11212 {"bits": [20, 20], "name": "SEM_SIGNAL_TYPE"}, 11213 {"bits": [24, 25], "name": "SEM_CLIENT_CODE"}, 11214 {"bits": [29, 31], "name": "SEM_SELECT"} 11215 ] 11216 }, 11217 "CP_SIG_SEM_ADDR_LO": { 11218 "fields": [ 11219 {"bits": [0, 1], "name": "SEM_ADDR_SWAP"}, 11220 {"bits": [3, 31], "name": "SEM_ADDR_LO"} 11221 ] 11222 }, 11223 "CP_STREAM_OUT_ADDR_HI": { 11224 "fields": [ 11225 {"bits": [0, 15], "name": "STREAM_OUT_ADDR_HI"} 11226 ] 11227 }, 11228 "CP_STREAM_OUT_ADDR_LO": { 11229 "fields": [ 11230 {"bits": [2, 31], "name": "STREAM_OUT_ADDR_LO"} 11231 ] 11232 }, 11233 "CP_STRMOUT_CNTL": { 11234 "fields": [ 11235 {"bits": [0, 0], "name": "OFFSET_UPDATE_DONE"} 11236 ] 11237 }, 11238 "CP_ST_BASE_HI": { 11239 "fields": [ 11240 {"bits": [0, 15], "name": "ST_BASE_HI"} 11241 ] 11242 }, 11243 "CP_ST_BASE_LO": { 11244 "fields": [ 11245 {"bits": [2, 31], "name": "ST_BASE_LO"} 11246 ] 11247 }, 11248 "CP_ST_BUFSZ": { 11249 "fields": [ 11250 {"bits": [0, 19], "name": "ST_BUFSZ"} 11251 ] 11252 }, 11253 "CP_ST_CMD_BUFSZ": { 11254 "fields": [ 11255 {"bits": [0, 19], "name": "ST_CMD_REQSZ"} 11256 ] 11257 }, 11258 "CP_VMID": { 11259 "fields": [ 11260 {"bits": [0, 3], "name": "VMID"} 11261 ] 11262 }, 11263 "CS_COPY_STATE": { 11264 "fields": [ 11265 {"bits": [0, 2], "name": "SRC_STATE_ID"} 11266 ] 11267 }, 11268 "DB_ALPHA_TO_MASK": { 11269 "fields": [ 11270 {"bits": [0, 0], "name": "ALPHA_TO_MASK_ENABLE"}, 11271 {"bits": [8, 9], "name": "ALPHA_TO_MASK_OFFSET0"}, 11272 {"bits": [10, 11], "name": "ALPHA_TO_MASK_OFFSET1"}, 11273 {"bits": [12, 13], "name": "ALPHA_TO_MASK_OFFSET2"}, 11274 {"bits": [14, 15], "name": "ALPHA_TO_MASK_OFFSET3"}, 11275 {"bits": [16, 16], "name": "OFFSET_ROUND"} 11276 ] 11277 }, 11278 "DB_COUNT_CONTROL": { 11279 "fields": [ 11280 {"bits": [0, 0], "name": "ZPASS_INCREMENT_DISABLE"}, 11281 {"bits": [1, 1], "name": "PERFECT_ZPASS_COUNTS"}, 11282 {"bits": [4, 6], "name": "SAMPLE_RATE"}, 11283 {"bits": [8, 11], "name": "ZPASS_ENABLE"}, 11284 {"bits": [12, 15], "name": "ZFAIL_ENABLE"}, 11285 {"bits": [16, 19], "name": "SFAIL_ENABLE"}, 11286 {"bits": [20, 23], "name": "DBFAIL_ENABLE"}, 11287 {"bits": [24, 27], "name": "SLICE_EVEN_ENABLE"}, 11288 {"bits": [28, 31], "name": "SLICE_ODD_ENABLE"} 11289 ] 11290 }, 11291 "DB_DEPTH_CONTROL": { 11292 "fields": [ 11293 {"bits": [0, 0], "name": "STENCIL_ENABLE"}, 11294 {"bits": [1, 1], "name": "Z_ENABLE"}, 11295 {"bits": [2, 2], "name": "Z_WRITE_ENABLE"}, 11296 {"bits": [3, 3], "name": "DEPTH_BOUNDS_ENABLE"}, 11297 {"bits": [4, 6], "enum_ref": "CompareFrag", "name": "ZFUNC"}, 11298 {"bits": [7, 7], "name": "BACKFACE_ENABLE"}, 11299 {"bits": [8, 10], "enum_ref": "CompareFrag", "name": "STENCILFUNC"}, 11300 {"bits": [20, 22], "enum_ref": "CompareFrag", "name": "STENCILFUNC_BF"}, 11301 {"bits": [30, 30], "name": "ENABLE_COLOR_WRITES_ON_DEPTH_FAIL"}, 11302 {"bits": [31, 31], "name": "DISABLE_COLOR_WRITES_ON_DEPTH_PASS"} 11303 ] 11304 }, 11305 "DB_DEPTH_SIZE": { 11306 "fields": [ 11307 {"bits": [0, 13], "name": "X_MAX"}, 11308 {"bits": [16, 29], "name": "Y_MAX"} 11309 ] 11310 }, 11311 "DB_DEPTH_VIEW": { 11312 "fields": [ 11313 {"bits": [0, 10], "name": "SLICE_START"}, 11314 {"bits": [13, 23], "name": "SLICE_MAX"}, 11315 {"bits": [24, 24], "name": "Z_READ_ONLY"}, 11316 {"bits": [25, 25], "name": "STENCIL_READ_ONLY"}, 11317 {"bits": [26, 29], "name": "MIPID"} 11318 ] 11319 }, 11320 "DB_DFSM_CONTROL": { 11321 "fields": [ 11322 {"bits": [0, 1], "enum_ref": "DB_DFSM_CONTROL__PUNCHOUT_MODE", "name": "PUNCHOUT_MODE"}, 11323 {"bits": [2, 2], "name": "POPS_DRAIN_PS_ON_OVERLAP"}, 11324 {"bits": [3, 3], "name": "DISALLOW_OVERFLOW"} 11325 ] 11326 }, 11327 "DB_EQAA": { 11328 "fields": [ 11329 {"bits": [0, 2], "name": "MAX_ANCHOR_SAMPLES"}, 11330 {"bits": [4, 6], "name": "PS_ITER_SAMPLES"}, 11331 {"bits": [8, 10], "name": "MASK_EXPORT_NUM_SAMPLES"}, 11332 {"bits": [12, 14], "name": "ALPHA_TO_MASK_NUM_SAMPLES"}, 11333 {"bits": [16, 16], "name": "HIGH_QUALITY_INTERSECTIONS"}, 11334 {"bits": [17, 17], "name": "INCOHERENT_EQAA_READS"}, 11335 {"bits": [18, 18], "name": "INTERPOLATE_COMP_Z"}, 11336 {"bits": [19, 19], "name": "INTERPOLATE_SRC_Z"}, 11337 {"bits": [20, 20], "name": "STATIC_ANCHOR_ASSOCIATIONS"}, 11338 {"bits": [21, 21], "name": "ALPHA_TO_MASK_EQAA_DISABLE"}, 11339 {"bits": [24, 26], "name": "OVERRASTERIZATION_AMOUNT"}, 11340 {"bits": [27, 27], "name": "ENABLE_POSTZ_OVERRASTERIZATION"} 11341 ] 11342 }, 11343 "DB_HTILE_DATA_BASE_HI": { 11344 "fields": [ 11345 {"bits": [0, 7], "name": "BASE_HI"} 11346 ] 11347 }, 11348 "DB_HTILE_SURFACE": { 11349 "fields": [ 11350 {"bits": [1, 1], "name": "FULL_CACHE"}, 11351 {"bits": [2, 2], "name": "HTILE_USES_PRELOAD_WIN"}, 11352 {"bits": [3, 3], "name": "PRELOAD"}, 11353 {"bits": [4, 9], "name": "PREFETCH_WIDTH"}, 11354 {"bits": [10, 15], "name": "PREFETCH_HEIGHT"}, 11355 {"bits": [16, 16], "name": "DST_OUTSIDE_ZERO_TO_ONE"}, 11356 {"bits": [18, 18], "name": "PIPE_ALIGNED"}, 11357 {"bits": [19, 19], "name": "RB_ALIGNED"} 11358 ] 11359 }, 11360 "DB_OCCLUSION_COUNT0_HI": { 11361 "fields": [ 11362 {"bits": [0, 30], "name": "COUNT_HI"} 11363 ] 11364 }, 11365 "DB_PRELOAD_CONTROL": { 11366 "fields": [ 11367 {"bits": [0, 7], "name": "START_X"}, 11368 {"bits": [8, 15], "name": "START_Y"}, 11369 {"bits": [16, 23], "name": "MAX_X"}, 11370 {"bits": [24, 31], "name": "MAX_Y"} 11371 ] 11372 }, 11373 "DB_RENDER_CONTROL": { 11374 "fields": [ 11375 {"bits": [0, 0], "name": "DEPTH_CLEAR_ENABLE"}, 11376 {"bits": [1, 1], "name": "STENCIL_CLEAR_ENABLE"}, 11377 {"bits": [2, 2], "name": "DEPTH_COPY"}, 11378 {"bits": [3, 3], "name": "STENCIL_COPY"}, 11379 {"bits": [4, 4], "name": "RESUMMARIZE_ENABLE"}, 11380 {"bits": [5, 5], "name": "STENCIL_COMPRESS_DISABLE"}, 11381 {"bits": [6, 6], "name": "DEPTH_COMPRESS_DISABLE"}, 11382 {"bits": [7, 7], "name": "COPY_CENTROID"}, 11383 {"bits": [8, 11], "name": "COPY_SAMPLE"}, 11384 {"bits": [12, 12], "name": "DECOMPRESS_ENABLE"} 11385 ] 11386 }, 11387 "DB_RENDER_OVERRIDE": { 11388 "fields": [ 11389 {"bits": [0, 1], "enum_ref": "ForceControl", "name": "FORCE_HIZ_ENABLE"}, 11390 {"bits": [2, 3], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE0"}, 11391 {"bits": [4, 5], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE1"}, 11392 {"bits": [6, 6], "name": "FORCE_SHADER_Z_ORDER"}, 11393 {"bits": [7, 7], "name": "FAST_Z_DISABLE"}, 11394 {"bits": [8, 8], "name": "FAST_STENCIL_DISABLE"}, 11395 {"bits": [9, 9], "name": "NOOP_CULL_DISABLE"}, 11396 {"bits": [10, 10], "name": "FORCE_COLOR_KILL"}, 11397 {"bits": [11, 11], "name": "FORCE_Z_READ"}, 11398 {"bits": [12, 12], "name": "FORCE_STENCIL_READ"}, 11399 {"bits": [13, 14], "enum_ref": "ForceControl", "name": "FORCE_FULL_Z_RANGE"}, 11400 {"bits": [15, 15], "name": "FORCE_QC_SMASK_CONFLICT"}, 11401 {"bits": [16, 16], "name": "DISABLE_VIEWPORT_CLAMP"}, 11402 {"bits": [17, 17], "name": "IGNORE_SC_ZRANGE"}, 11403 {"bits": [18, 18], "name": "DISABLE_FULLY_COVERED"}, 11404 {"bits": [19, 20], "enum_ref": "ZLimitSumm", "name": "FORCE_Z_LIMIT_SUMM"}, 11405 {"bits": [21, 25], "name": "MAX_TILES_IN_DTT"}, 11406 {"bits": [26, 26], "name": "DISABLE_TILE_RATE_TILES"}, 11407 {"bits": [27, 27], "name": "FORCE_Z_DIRTY"}, 11408 {"bits": [28, 28], "name": "FORCE_STENCIL_DIRTY"}, 11409 {"bits": [29, 29], "name": "FORCE_Z_VALID"}, 11410 {"bits": [30, 30], "name": "FORCE_STENCIL_VALID"}, 11411 {"bits": [31, 31], "name": "PRESERVE_COMPRESSION"} 11412 ] 11413 }, 11414 "DB_RENDER_OVERRIDE2": { 11415 "fields": [ 11416 {"bits": [0, 1], "enum_ref": "DbPSLControl", "name": "PARTIAL_SQUAD_LAUNCH_CONTROL"}, 11417 {"bits": [2, 4], "name": "PARTIAL_SQUAD_LAUNCH_COUNTDOWN"}, 11418 {"bits": [5, 5], "name": "DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION"}, 11419 {"bits": [6, 6], "name": "DISABLE_SMEM_EXPCLEAR_OPTIMIZATION"}, 11420 {"bits": [7, 7], "name": "DISABLE_COLOR_ON_VALIDATION"}, 11421 {"bits": [8, 8], "name": "DECOMPRESS_Z_ON_FLUSH"}, 11422 {"bits": [9, 9], "name": "DISABLE_REG_SNOOP"}, 11423 {"bits": [10, 10], "name": "DEPTH_BOUNDS_HIER_DEPTH_DISABLE"}, 11424 {"bits": [11, 11], "name": "SEPARATE_HIZS_FUNC_ENABLE"}, 11425 {"bits": [12, 14], "enum_ref": "CompareFrag", "name": "HIZ_ZFUNC"}, 11426 {"bits": [15, 17], "name": "HIS_SFUNC_FF"}, 11427 {"bits": [18, 20], "name": "HIS_SFUNC_BF"}, 11428 {"bits": [21, 21], "name": "PRESERVE_ZRANGE"}, 11429 {"bits": [22, 22], "name": "PRESERVE_SRESULTS"}, 11430 {"bits": [23, 23], "name": "DISABLE_FAST_PASS"}, 11431 {"bits": [25, 25], "name": "ALLOW_PARTIAL_RES_HIER_KILL"} 11432 ] 11433 }, 11434 "DB_SHADER_CONTROL": { 11435 "fields": [ 11436 {"bits": [0, 0], "name": "Z_EXPORT_ENABLE"}, 11437 {"bits": [1, 1], "name": "STENCIL_TEST_VAL_EXPORT_ENABLE"}, 11438 {"bits": [2, 2], "name": "STENCIL_OP_VAL_EXPORT_ENABLE"}, 11439 {"bits": [4, 5], "enum_ref": "ZOrder", "name": "Z_ORDER"}, 11440 {"bits": [6, 6], "name": "KILL_ENABLE"}, 11441 {"bits": [7, 7], "name": "COVERAGE_TO_MASK_ENABLE"}, 11442 {"bits": [8, 8], "name": "MASK_EXPORT_ENABLE"}, 11443 {"bits": [9, 9], "name": "EXEC_ON_HIER_FAIL"}, 11444 {"bits": [10, 10], "name": "EXEC_ON_NOOP"}, 11445 {"bits": [11, 11], "name": "ALPHA_TO_MASK_DISABLE"}, 11446 {"bits": [12, 12], "name": "DEPTH_BEFORE_SHADER"}, 11447 {"bits": [13, 14], "enum_ref": "ConservativeZExport", "name": "CONSERVATIVE_Z_EXPORT"}, 11448 {"bits": [15, 15], "name": "DUAL_QUAD_DISABLE"}, 11449 {"bits": [16, 16], "name": "PRIMITIVE_ORDERED_PIXEL_SHADER"}, 11450 {"bits": [17, 17], "name": "EXEC_IF_OVERLAPPED"}, 11451 {"bits": [20, 22], "name": "POPS_OVERLAP_NUM_SAMPLES"} 11452 ] 11453 }, 11454 "DB_SRESULTS_COMPARE_STATE0": { 11455 "fields": [ 11456 {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC0"}, 11457 {"bits": [4, 11], "name": "COMPAREVALUE0"}, 11458 {"bits": [12, 19], "name": "COMPAREMASK0"}, 11459 {"bits": [24, 24], "name": "ENABLE0"} 11460 ] 11461 }, 11462 "DB_SRESULTS_COMPARE_STATE1": { 11463 "fields": [ 11464 {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC1"}, 11465 {"bits": [4, 11], "name": "COMPAREVALUE1"}, 11466 {"bits": [12, 19], "name": "COMPAREMASK1"}, 11467 {"bits": [24, 24], "name": "ENABLE1"} 11468 ] 11469 }, 11470 "DB_STENCILREFMASK": { 11471 "fields": [ 11472 {"bits": [0, 7], "name": "STENCILTESTVAL"}, 11473 {"bits": [8, 15], "name": "STENCILMASK"}, 11474 {"bits": [16, 23], "name": "STENCILWRITEMASK"}, 11475 {"bits": [24, 31], "name": "STENCILOPVAL"} 11476 ] 11477 }, 11478 "DB_STENCILREFMASK_BF": { 11479 "fields": [ 11480 {"bits": [0, 7], "name": "STENCILTESTVAL_BF"}, 11481 {"bits": [8, 15], "name": "STENCILMASK_BF"}, 11482 {"bits": [16, 23], "name": "STENCILWRITEMASK_BF"}, 11483 {"bits": [24, 31], "name": "STENCILOPVAL_BF"} 11484 ] 11485 }, 11486 "DB_STENCIL_CLEAR": { 11487 "fields": [ 11488 {"bits": [0, 7], "name": "CLEAR"} 11489 ] 11490 }, 11491 "DB_STENCIL_CONTROL": { 11492 "fields": [ 11493 {"bits": [0, 3], "enum_ref": "StencilOp", "name": "STENCILFAIL"}, 11494 {"bits": [4, 7], "enum_ref": "StencilOp", "name": "STENCILZPASS"}, 11495 {"bits": [8, 11], "enum_ref": "StencilOp", "name": "STENCILZFAIL"}, 11496 {"bits": [12, 15], "enum_ref": "StencilOp", "name": "STENCILFAIL_BF"}, 11497 {"bits": [16, 19], "enum_ref": "StencilOp", "name": "STENCILZPASS_BF"}, 11498 {"bits": [20, 23], "enum_ref": "StencilOp", "name": "STENCILZFAIL_BF"} 11499 ] 11500 }, 11501 "DB_STENCIL_INFO": { 11502 "fields": [ 11503 {"bits": [0, 0], "enum_ref": "StencilFormat", "name": "FORMAT"}, 11504 {"bits": [4, 8], "name": "SW_MODE"}, 11505 {"bits": [12, 12], "name": "PARTIALLY_RESIDENT"}, 11506 {"bits": [13, 14], "enum_ref": "DbPRTFaultBehavior", "name": "FAULT_BEHAVIOR"}, 11507 {"bits": [15, 15], "name": "ITERATE_FLUSH"}, 11508 {"bits": [27, 27], "name": "ALLOW_EXPCLEAR"}, 11509 {"bits": [29, 29], "name": "TILE_STENCIL_DISABLE"}, 11510 {"bits": [30, 30], "name": "CLEAR_DISALLOWED"} 11511 ] 11512 }, 11513 "DB_Z_INFO": { 11514 "fields": [ 11515 {"bits": [0, 1], "enum_ref": "ZFormat", "name": "FORMAT"}, 11516 {"bits": [2, 3], "name": "NUM_SAMPLES"}, 11517 {"bits": [4, 8], "name": "SW_MODE"}, 11518 {"bits": [12, 12], "name": "PARTIALLY_RESIDENT"}, 11519 {"bits": [13, 14], "enum_ref": "DbPRTFaultBehavior", "name": "FAULT_BEHAVIOR"}, 11520 {"bits": [15, 15], "name": "ITERATE_FLUSH"}, 11521 {"bits": [16, 19], "name": "MAXMIP"}, 11522 {"bits": [23, 26], "name": "DECOMPRESS_ON_N_ZPLANES"}, 11523 {"bits": [27, 27], "name": "ALLOW_EXPCLEAR"}, 11524 {"bits": [28, 28], "name": "READ_SIZE"}, 11525 {"bits": [29, 29], "name": "TILE_SURFACE_ENABLE"}, 11526 {"bits": [30, 30], "name": "CLEAR_DISALLOWED"}, 11527 {"bits": [31, 31], "name": "ZRANGE_PRECISION"} 11528 ] 11529 }, 11530 "DB_Z_INFO2": { 11531 "fields": [ 11532 {"bits": [0, 15], "name": "EPITCH"} 11533 ] 11534 }, 11535 "GB_ADDR_CONFIG": { 11536 "fields": [ 11537 {"bits": [0, 2], "name": "NUM_PIPES"}, 11538 {"bits": [3, 5], "name": "PIPE_INTERLEAVE_SIZE"}, 11539 {"bits": [6, 7], "name": "MAX_COMPRESSED_FRAGS"}, 11540 {"bits": [8, 10], "name": "BANK_INTERLEAVE_SIZE"}, 11541 {"bits": [12, 14], "enum_ref": "NumBanks", "name": "NUM_BANKS"}, 11542 {"bits": [16, 18], "name": "SHADER_ENGINE_TILE_SIZE"}, 11543 {"bits": [19, 20], "name": "NUM_SHADER_ENGINES"}, 11544 {"bits": [21, 23], "name": "NUM_GPUS"}, 11545 {"bits": [24, 25], "name": "MULTI_GPU_TILE_SIZE"}, 11546 {"bits": [26, 27], "name": "NUM_RB_PER_SE"}, 11547 {"bits": [28, 29], "name": "ROW_SIZE"}, 11548 {"bits": [30, 30], "name": "NUM_LOWER_PIPES"}, 11549 {"bits": [31, 31], "name": "SE_ENABLE"} 11550 ] 11551 }, 11552 "GB_MACROTILE_MODE0": { 11553 "fields": [ 11554 {"bits": [0, 1], "enum_ref": "BankWidth", "name": "BANK_WIDTH"}, 11555 {"bits": [2, 3], "enum_ref": "BankHeight", "name": "BANK_HEIGHT"}, 11556 {"bits": [4, 5], "enum_ref": "MacroTileAspect", "name": "MACRO_TILE_ASPECT"}, 11557 {"bits": [6, 7], "enum_ref": "NumBanks", "name": "NUM_BANKS"} 11558 ] 11559 }, 11560 "GB_TILE_MODE0": { 11561 "fields": [ 11562 {"bits": [2, 5], "enum_ref": "ArrayMode", "name": "ARRAY_MODE"}, 11563 {"bits": [6, 10], "enum_ref": "PipeConfig", "name": "PIPE_CONFIG"}, 11564 {"bits": [11, 13], "enum_ref": "TileSplit", "name": "TILE_SPLIT"}, 11565 {"bits": [22, 24], "enum_ref": "MicroTileMode", "name": "MICRO_TILE_MODE_NEW"}, 11566 {"bits": [25, 26], "name": "SAMPLE_SPLIT"} 11567 ] 11568 }, 11569 "GDS_ATOM_BASE": { 11570 "fields": [ 11571 {"bits": [0, 15], "name": "BASE"}, 11572 {"bits": [16, 31], "name": "UNUSED"} 11573 ] 11574 }, 11575 "GDS_ATOM_CNTL": { 11576 "fields": [ 11577 {"bits": [0, 5], "name": "AINC"}, 11578 {"bits": [6, 7], "name": "UNUSED1"}, 11579 {"bits": [8, 9], "name": "DMODE"}, 11580 {"bits": [10, 31], "name": "UNUSED2"} 11581 ] 11582 }, 11583 "GDS_ATOM_COMPLETE": { 11584 "fields": [ 11585 {"bits": [0, 0], "name": "COMPLETE"}, 11586 {"bits": [1, 31], "name": "UNUSED"} 11587 ] 11588 }, 11589 "GDS_ATOM_OFFSET0": { 11590 "fields": [ 11591 {"bits": [0, 7], "name": "OFFSET0"}, 11592 {"bits": [8, 31], "name": "UNUSED"} 11593 ] 11594 }, 11595 "GDS_ATOM_OFFSET1": { 11596 "fields": [ 11597 {"bits": [0, 7], "name": "OFFSET1"}, 11598 {"bits": [8, 31], "name": "UNUSED"} 11599 ] 11600 }, 11601 "GDS_ATOM_OP": { 11602 "fields": [ 11603 {"bits": [0, 7], "name": "OP"}, 11604 {"bits": [8, 31], "name": "UNUSED"} 11605 ] 11606 }, 11607 "GDS_ATOM_SIZE": { 11608 "fields": [ 11609 {"bits": [0, 15], "name": "SIZE"}, 11610 {"bits": [16, 31], "name": "UNUSED"} 11611 ] 11612 }, 11613 "GDS_GWS_RESOURCE": { 11614 "fields": [ 11615 {"bits": [0, 0], "name": "FLAG"}, 11616 {"bits": [1, 12], "name": "COUNTER"}, 11617 {"bits": [13, 13], "name": "TYPE"}, 11618 {"bits": [14, 14], "name": "DED"}, 11619 {"bits": [15, 15], "name": "RELEASE_ALL"}, 11620 {"bits": [16, 27], "name": "HEAD_QUEUE"}, 11621 {"bits": [28, 28], "name": "HEAD_VALID"}, 11622 {"bits": [29, 29], "name": "HEAD_FLAG"}, 11623 {"bits": [30, 30], "name": "HALTED"}, 11624 {"bits": [31, 31], "name": "UNUSED1"} 11625 ] 11626 }, 11627 "GDS_GWS_RESOURCE_CNT": { 11628 "fields": [ 11629 {"bits": [0, 15], "name": "RESOURCE_CNT"}, 11630 {"bits": [16, 31], "name": "UNUSED"} 11631 ] 11632 }, 11633 "GDS_GWS_RESOURCE_CNTL": { 11634 "fields": [ 11635 {"bits": [0, 5], "name": "INDEX"}, 11636 {"bits": [6, 31], "name": "UNUSED"} 11637 ] 11638 }, 11639 "GDS_OA_ADDRESS": { 11640 "fields": [ 11641 {"bits": [0, 15], "name": "DS_ADDRESS"}, 11642 {"bits": [16, 19], "name": "CRAWLER"}, 11643 {"bits": [20, 21], "name": "CRAWLER_TYPE"}, 11644 {"bits": [22, 29], "name": "UNUSED"}, 11645 {"bits": [30, 30], "name": "NO_ALLOC"}, 11646 {"bits": [31, 31], "name": "ENABLE"} 11647 ] 11648 }, 11649 "GDS_OA_CNTL": { 11650 "fields": [ 11651 {"bits": [0, 3], "name": "INDEX"}, 11652 {"bits": [4, 31], "name": "UNUSED"} 11653 ] 11654 }, 11655 "GDS_OA_INCDEC": { 11656 "fields": [ 11657 {"bits": [0, 30], "name": "VALUE"}, 11658 {"bits": [31, 31], "name": "INCDEC"} 11659 ] 11660 }, 11661 "GRBM_GFX_INDEX": { 11662 "fields": [ 11663 {"bits": [0, 7], "name": "INSTANCE_INDEX"}, 11664 {"bits": [8, 15], "name": "SH_INDEX"}, 11665 {"bits": [16, 23], "name": "SE_INDEX"}, 11666 {"bits": [29, 29], "name": "SH_BROADCAST_WRITES"}, 11667 {"bits": [30, 30], "name": "INSTANCE_BROADCAST_WRITES"}, 11668 {"bits": [31, 31], "name": "SE_BROADCAST_WRITES"} 11669 ] 11670 }, 11671 "GRBM_PERFCOUNTER0_SELECT": { 11672 "fields": [ 11673 {"bits": [0, 5], "name": "PERF_SEL"}, 11674 {"bits": [10, 10], "name": "DB_CLEAN_USER_DEFINED_MASK"}, 11675 {"bits": [11, 11], "name": "CB_CLEAN_USER_DEFINED_MASK"}, 11676 {"bits": [12, 12], "name": "VGT_BUSY_USER_DEFINED_MASK"}, 11677 {"bits": [13, 13], "name": "TA_BUSY_USER_DEFINED_MASK"}, 11678 {"bits": [14, 14], "name": "SX_BUSY_USER_DEFINED_MASK"}, 11679 {"bits": [16, 16], "name": "SPI_BUSY_USER_DEFINED_MASK"}, 11680 {"bits": [17, 17], "name": "SC_BUSY_USER_DEFINED_MASK"}, 11681 {"bits": [18, 18], "name": "PA_BUSY_USER_DEFINED_MASK"}, 11682 {"bits": [19, 19], "name": "GRBM_BUSY_USER_DEFINED_MASK"}, 11683 {"bits": [20, 20], "name": "DB_BUSY_USER_DEFINED_MASK"}, 11684 {"bits": [21, 21], "name": "CB_BUSY_USER_DEFINED_MASK"}, 11685 {"bits": [22, 22], "name": "CP_BUSY_USER_DEFINED_MASK"}, 11686 {"bits": [23, 23], "name": "IA_BUSY_USER_DEFINED_MASK"}, 11687 {"bits": [24, 24], "name": "GDS_BUSY_USER_DEFINED_MASK"}, 11688 {"bits": [25, 25], "name": "BCI_BUSY_USER_DEFINED_MASK"}, 11689 {"bits": [26, 26], "name": "RLC_BUSY_USER_DEFINED_MASK"}, 11690 {"bits": [27, 27], "name": "TC_BUSY_USER_DEFINED_MASK"}, 11691 {"bits": [28, 28], "name": "WD_BUSY_USER_DEFINED_MASK"}, 11692 {"bits": [29, 29], "name": "UTCL2_BUSY_USER_DEFINED_MASK"}, 11693 {"bits": [30, 30], "name": "EA_BUSY_USER_DEFINED_MASK"}, 11694 {"bits": [31, 31], "name": "RMI_BUSY_USER_DEFINED_MASK"} 11695 ] 11696 }, 11697 "GRBM_SE0_PERFCOUNTER_SELECT": { 11698 "fields": [ 11699 {"bits": [0, 5], "name": "PERF_SEL"}, 11700 {"bits": [10, 10], "name": "DB_CLEAN_USER_DEFINED_MASK"}, 11701 {"bits": [11, 11], "name": "CB_CLEAN_USER_DEFINED_MASK"}, 11702 {"bits": [12, 12], "name": "TA_BUSY_USER_DEFINED_MASK"}, 11703 {"bits": [13, 13], "name": "SX_BUSY_USER_DEFINED_MASK"}, 11704 {"bits": [15, 15], "name": "SPI_BUSY_USER_DEFINED_MASK"}, 11705 {"bits": [16, 16], "name": "SC_BUSY_USER_DEFINED_MASK"}, 11706 {"bits": [17, 17], "name": "DB_BUSY_USER_DEFINED_MASK"}, 11707 {"bits": [18, 18], "name": "CB_BUSY_USER_DEFINED_MASK"}, 11708 {"bits": [19, 19], "name": "VGT_BUSY_USER_DEFINED_MASK"}, 11709 {"bits": [20, 20], "name": "PA_BUSY_USER_DEFINED_MASK"}, 11710 {"bits": [21, 21], "name": "BCI_BUSY_USER_DEFINED_MASK"}, 11711 {"bits": [22, 22], "name": "RMI_BUSY_USER_DEFINED_MASK"} 11712 ] 11713 }, 11714 "GRBM_STATUS": { 11715 "fields": [ 11716 {"bits": [0, 3], "name": "ME0PIPE0_CMDFIFO_AVAIL"}, 11717 {"bits": [5, 5], "name": "RSMU_RQ_PENDING"}, 11718 {"bits": [7, 7], "name": "ME0PIPE0_CF_RQ_PENDING"}, 11719 {"bits": [8, 8], "name": "ME0PIPE0_PF_RQ_PENDING"}, 11720 {"bits": [9, 9], "name": "GDS_DMA_RQ_PENDING"}, 11721 {"bits": [12, 12], "name": "DB_CLEAN"}, 11722 {"bits": [13, 13], "name": "CB_CLEAN"}, 11723 {"bits": [14, 14], "name": "TA_BUSY"}, 11724 {"bits": [15, 15], "name": "GDS_BUSY"}, 11725 {"bits": [16, 16], "name": "WD_BUSY_NO_DMA"}, 11726 {"bits": [17, 17], "name": "VGT_BUSY"}, 11727 {"bits": [18, 18], "name": "IA_BUSY_NO_DMA"}, 11728 {"bits": [19, 19], "name": "IA_BUSY"}, 11729 {"bits": [20, 20], "name": "SX_BUSY"}, 11730 {"bits": [21, 21], "name": "WD_BUSY"}, 11731 {"bits": [22, 22], "name": "SPI_BUSY"}, 11732 {"bits": [23, 23], "name": "BCI_BUSY"}, 11733 {"bits": [24, 24], "name": "SC_BUSY"}, 11734 {"bits": [25, 25], "name": "PA_BUSY"}, 11735 {"bits": [26, 26], "name": "DB_BUSY"}, 11736 {"bits": [28, 28], "name": "CP_COHERENCY_BUSY"}, 11737 {"bits": [29, 29], "name": "CP_BUSY"}, 11738 {"bits": [30, 30], "name": "CB_BUSY"}, 11739 {"bits": [31, 31], "name": "GUI_ACTIVE"} 11740 ] 11741 }, 11742 "GRBM_STATUS2": { 11743 "fields": [ 11744 {"bits": [0, 3], "name": "ME0PIPE1_CMDFIFO_AVAIL"}, 11745 {"bits": [4, 4], "name": "ME0PIPE1_CF_RQ_PENDING"}, 11746 {"bits": [5, 5], "name": "ME0PIPE1_PF_RQ_PENDING"}, 11747 {"bits": [6, 6], "name": "ME1PIPE0_RQ_PENDING"}, 11748 {"bits": [7, 7], "name": "ME1PIPE1_RQ_PENDING"}, 11749 {"bits": [8, 8], "name": "ME1PIPE2_RQ_PENDING"}, 11750 {"bits": [9, 9], "name": "ME1PIPE3_RQ_PENDING"}, 11751 {"bits": [10, 10], "name": "ME2PIPE0_RQ_PENDING"}, 11752 {"bits": [11, 11], "name": "ME2PIPE1_RQ_PENDING"}, 11753 {"bits": [12, 12], "name": "ME2PIPE2_RQ_PENDING"}, 11754 {"bits": [13, 13], "name": "ME2PIPE3_RQ_PENDING"}, 11755 {"bits": [14, 14], "name": "RLC_RQ_PENDING"}, 11756 {"bits": [15, 15], "name": "UTCL2_BUSY"}, 11757 {"bits": [16, 16], "name": "EA_BUSY"}, 11758 {"bits": [17, 17], "name": "RMI_BUSY"}, 11759 {"bits": [18, 18], "name": "UTCL2_RQ_PENDING"}, 11760 {"bits": [19, 19], "name": "CPF_RQ_PENDING"}, 11761 {"bits": [20, 20], "name": "EA_LINK_BUSY"}, 11762 {"bits": [24, 24], "name": "RLC_BUSY"}, 11763 {"bits": [25, 25], "name": "TC_BUSY"}, 11764 {"bits": [26, 26], "name": "TCC_CC_RESIDENT"}, 11765 {"bits": [28, 28], "name": "CPF_BUSY"}, 11766 {"bits": [29, 29], "name": "CPC_BUSY"}, 11767 {"bits": [30, 30], "name": "CPG_BUSY"}, 11768 {"bits": [31, 31], "name": "CPAXI_BUSY"} 11769 ] 11770 }, 11771 "GRBM_STATUS_SE0": { 11772 "fields": [ 11773 {"bits": [1, 1], "name": "DB_CLEAN"}, 11774 {"bits": [2, 2], "name": "CB_CLEAN"}, 11775 {"bits": [21, 21], "name": "RMI_BUSY"}, 11776 {"bits": [22, 22], "name": "BCI_BUSY"}, 11777 {"bits": [23, 23], "name": "VGT_BUSY"}, 11778 {"bits": [24, 24], "name": "PA_BUSY"}, 11779 {"bits": [25, 25], "name": "TA_BUSY"}, 11780 {"bits": [26, 26], "name": "SX_BUSY"}, 11781 {"bits": [27, 27], "name": "SPI_BUSY"}, 11782 {"bits": [29, 29], "name": "SC_BUSY"}, 11783 {"bits": [30, 30], "name": "DB_BUSY"}, 11784 {"bits": [31, 31], "name": "CB_BUSY"} 11785 ] 11786 }, 11787 "IA_MULTI_VGT_PARAM": { 11788 "fields": [ 11789 {"bits": [0, 15], "name": "PRIMGROUP_SIZE"}, 11790 {"bits": [16, 16], "name": "PARTIAL_VS_WAVE_ON"}, 11791 {"bits": [17, 17], "name": "SWITCH_ON_EOP"}, 11792 {"bits": [18, 18], "name": "PARTIAL_ES_WAVE_ON"}, 11793 {"bits": [19, 19], "name": "SWITCH_ON_EOI"}, 11794 {"bits": [20, 20], "name": "WD_SWITCH_ON_EOP"}, 11795 {"bits": [21, 21], "name": "EN_INST_OPT_BASIC"}, 11796 {"bits": [22, 22], "name": "EN_INST_OPT_ADV"}, 11797 {"bits": [23, 23], "name": "HW_USE_ONLY"} 11798 ] 11799 }, 11800 "IA_PERFCOUNTER0_SELECT": { 11801 "fields": [ 11802 {"bits": [0, 9], "name": "PERF_SEL"}, 11803 {"bits": [10, 19], "name": "PERF_SEL1"}, 11804 {"bits": [20, 23], "name": "CNTR_MODE"}, 11805 {"bits": [24, 27], "name": "PERF_MODE1"}, 11806 {"bits": [28, 31], "name": "PERF_MODE"} 11807 ] 11808 }, 11809 "IA_PERFCOUNTER0_SELECT1": { 11810 "fields": [ 11811 {"bits": [0, 9], "name": "PERF_SEL2"}, 11812 {"bits": [10, 19], "name": "PERF_SEL3"}, 11813 {"bits": [24, 27], "name": "PERF_MODE3"}, 11814 {"bits": [28, 31], "name": "PERF_MODE2"} 11815 ] 11816 }, 11817 "PA_CL_CLIP_CNTL": { 11818 "fields": [ 11819 {"bits": [0, 0], "name": "UCP_ENA_0"}, 11820 {"bits": [1, 1], "name": "UCP_ENA_1"}, 11821 {"bits": [2, 2], "name": "UCP_ENA_2"}, 11822 {"bits": [3, 3], "name": "UCP_ENA_3"}, 11823 {"bits": [4, 4], "name": "UCP_ENA_4"}, 11824 {"bits": [5, 5], "name": "UCP_ENA_5"}, 11825 {"bits": [13, 13], "name": "PS_UCP_Y_SCALE_NEG"}, 11826 {"bits": [14, 15], "name": "PS_UCP_MODE"}, 11827 {"bits": [16, 16], "name": "CLIP_DISABLE"}, 11828 {"bits": [17, 17], "name": "UCP_CULL_ONLY_ENA"}, 11829 {"bits": [18, 18], "name": "BOUNDARY_EDGE_FLAG_ENA"}, 11830 {"bits": [19, 19], "name": "DX_CLIP_SPACE_DEF"}, 11831 {"bits": [20, 20], "name": "DIS_CLIP_ERR_DETECT"}, 11832 {"bits": [21, 21], "name": "VTX_KILL_OR"}, 11833 {"bits": [22, 22], "name": "DX_RASTERIZATION_KILL"}, 11834 {"bits": [24, 24], "name": "DX_LINEAR_ATTR_CLIP_ENA"}, 11835 {"bits": [25, 25], "name": "VTE_VPORT_PROVOKE_DISABLE"}, 11836 {"bits": [26, 26], "name": "ZCLIP_NEAR_DISABLE"}, 11837 {"bits": [27, 27], "name": "ZCLIP_FAR_DISABLE"}, 11838 {"bits": [28, 28], "name": "ZCLIP_PROG_NEAR_ENA"} 11839 ] 11840 }, 11841 "PA_CL_NANINF_CNTL": { 11842 "fields": [ 11843 {"bits": [0, 0], "name": "VTE_XY_INF_DISCARD"}, 11844 {"bits": [1, 1], "name": "VTE_Z_INF_DISCARD"}, 11845 {"bits": [2, 2], "name": "VTE_W_INF_DISCARD"}, 11846 {"bits": [3, 3], "name": "VTE_0XNANINF_IS_0"}, 11847 {"bits": [4, 4], "name": "VTE_XY_NAN_RETAIN"}, 11848 {"bits": [5, 5], "name": "VTE_Z_NAN_RETAIN"}, 11849 {"bits": [6, 6], "name": "VTE_W_NAN_RETAIN"}, 11850 {"bits": [7, 7], "name": "VTE_W_RECIP_NAN_IS_0"}, 11851 {"bits": [8, 8], "name": "VS_XY_NAN_TO_INF"}, 11852 {"bits": [9, 9], "name": "VS_XY_INF_RETAIN"}, 11853 {"bits": [10, 10], "name": "VS_Z_NAN_TO_INF"}, 11854 {"bits": [11, 11], "name": "VS_Z_INF_RETAIN"}, 11855 {"bits": [12, 12], "name": "VS_W_NAN_TO_INF"}, 11856 {"bits": [13, 13], "name": "VS_W_INF_RETAIN"}, 11857 {"bits": [14, 14], "name": "VS_CLIP_DIST_INF_DISCARD"}, 11858 {"bits": [20, 20], "name": "VTE_NO_OUTPUT_NEG_0"} 11859 ] 11860 }, 11861 "PA_CL_NGG_CNTL": { 11862 "fields": [ 11863 {"bits": [0, 0], "name": "VERTEX_REUSE_OFF"}, 11864 {"bits": [1, 1], "name": "INDEX_BUF_EDGE_FLAG_ENA"} 11865 ] 11866 }, 11867 "PA_CL_OBJPRIM_ID_CNTL": { 11868 "fields": [ 11869 {"bits": [0, 0], "name": "OBJ_ID_SEL"}, 11870 {"bits": [1, 1], "name": "ADD_PIPED_PRIM_ID"}, 11871 {"bits": [2, 2], "name": "EN_32BIT_OBJPRIMID"} 11872 ] 11873 }, 11874 "PA_CL_VS_OUT_CNTL": { 11875 "fields": [ 11876 {"bits": [0, 0], "name": "CLIP_DIST_ENA_0"}, 11877 {"bits": [1, 1], "name": "CLIP_DIST_ENA_1"}, 11878 {"bits": [2, 2], "name": "CLIP_DIST_ENA_2"}, 11879 {"bits": [3, 3], "name": "CLIP_DIST_ENA_3"}, 11880 {"bits": [4, 4], "name": "CLIP_DIST_ENA_4"}, 11881 {"bits": [5, 5], "name": "CLIP_DIST_ENA_5"}, 11882 {"bits": [6, 6], "name": "CLIP_DIST_ENA_6"}, 11883 {"bits": [7, 7], "name": "CLIP_DIST_ENA_7"}, 11884 {"bits": [8, 8], "name": "CULL_DIST_ENA_0"}, 11885 {"bits": [9, 9], "name": "CULL_DIST_ENA_1"}, 11886 {"bits": [10, 10], "name": "CULL_DIST_ENA_2"}, 11887 {"bits": [11, 11], "name": "CULL_DIST_ENA_3"}, 11888 {"bits": [12, 12], "name": "CULL_DIST_ENA_4"}, 11889 {"bits": [13, 13], "name": "CULL_DIST_ENA_5"}, 11890 {"bits": [14, 14], "name": "CULL_DIST_ENA_6"}, 11891 {"bits": [15, 15], "name": "CULL_DIST_ENA_7"}, 11892 {"bits": [16, 16], "name": "USE_VTX_POINT_SIZE"}, 11893 {"bits": [17, 17], "name": "USE_VTX_EDGE_FLAG"}, 11894 {"bits": [18, 18], "name": "USE_VTX_RENDER_TARGET_INDX"}, 11895 {"bits": [19, 19], "name": "USE_VTX_VIEWPORT_INDX"}, 11896 {"bits": [20, 20], "name": "USE_VTX_KILL_FLAG"}, 11897 {"bits": [21, 21], "name": "VS_OUT_MISC_VEC_ENA"}, 11898 {"bits": [22, 22], "name": "VS_OUT_CCDIST0_VEC_ENA"}, 11899 {"bits": [23, 23], "name": "VS_OUT_CCDIST1_VEC_ENA"}, 11900 {"bits": [24, 24], "name": "VS_OUT_MISC_SIDE_BUS_ENA"}, 11901 {"bits": [25, 25], "name": "USE_VTX_GS_CUT_FLAG"}, 11902 {"bits": [26, 26], "name": "USE_VTX_LINE_WIDTH"}, 11903 {"bits": [27, 27], "name": "USE_VTX_SHD_OBJPRIM_ID"} 11904 ] 11905 }, 11906 "PA_CL_VTE_CNTL": { 11907 "fields": [ 11908 {"bits": [0, 0], "name": "VPORT_X_SCALE_ENA"}, 11909 {"bits": [1, 1], "name": "VPORT_X_OFFSET_ENA"}, 11910 {"bits": [2, 2], "name": "VPORT_Y_SCALE_ENA"}, 11911 {"bits": [3, 3], "name": "VPORT_Y_OFFSET_ENA"}, 11912 {"bits": [4, 4], "name": "VPORT_Z_SCALE_ENA"}, 11913 {"bits": [5, 5], "name": "VPORT_Z_OFFSET_ENA"}, 11914 {"bits": [8, 8], "name": "VTX_XY_FMT"}, 11915 {"bits": [9, 9], "name": "VTX_Z_FMT"}, 11916 {"bits": [10, 10], "name": "VTX_W0_FMT"}, 11917 {"bits": [11, 11], "name": "PERFCOUNTER_REF"} 11918 ] 11919 }, 11920 "PA_SC_AA_CONFIG": { 11921 "fields": [ 11922 {"bits": [0, 2], "name": "MSAA_NUM_SAMPLES"}, 11923 {"bits": [4, 4], "name": "AA_MASK_CENTROID_DTMN"}, 11924 {"bits": [13, 16], "name": "MAX_SAMPLE_DIST"}, 11925 {"bits": [20, 22], "name": "MSAA_EXPOSED_SAMPLES"}, 11926 {"bits": [24, 25], "name": "DETAIL_TO_EXPOSED_MODE"}, 11927 {"bits": [26, 27], "enum_ref": "CovToShaderSel", "name": "COVERAGE_TO_SHADER_SELECT"} 11928 ] 11929 }, 11930 "PA_SC_AA_MASK_X0Y0_X1Y0": { 11931 "fields": [ 11932 {"bits": [0, 15], "name": "AA_MASK_X0Y0"}, 11933 {"bits": [16, 31], "name": "AA_MASK_X1Y0"} 11934 ] 11935 }, 11936 "PA_SC_AA_MASK_X0Y1_X1Y1": { 11937 "fields": [ 11938 {"bits": [0, 15], "name": "AA_MASK_X0Y1"}, 11939 {"bits": [16, 31], "name": "AA_MASK_X1Y1"} 11940 ] 11941 }, 11942 "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0": { 11943 "fields": [ 11944 {"bits": [0, 3], "name": "S0_X"}, 11945 {"bits": [4, 7], "name": "S0_Y"}, 11946 {"bits": [8, 11], "name": "S1_X"}, 11947 {"bits": [12, 15], "name": "S1_Y"}, 11948 {"bits": [16, 19], "name": "S2_X"}, 11949 {"bits": [20, 23], "name": "S2_Y"}, 11950 {"bits": [24, 27], "name": "S3_X"}, 11951 {"bits": [28, 31], "name": "S3_Y"} 11952 ] 11953 }, 11954 "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1": { 11955 "fields": [ 11956 {"bits": [0, 3], "name": "S4_X"}, 11957 {"bits": [4, 7], "name": "S4_Y"}, 11958 {"bits": [8, 11], "name": "S5_X"}, 11959 {"bits": [12, 15], "name": "S5_Y"}, 11960 {"bits": [16, 19], "name": "S6_X"}, 11961 {"bits": [20, 23], "name": "S6_Y"}, 11962 {"bits": [24, 27], "name": "S7_X"}, 11963 {"bits": [28, 31], "name": "S7_Y"} 11964 ] 11965 }, 11966 "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2": { 11967 "fields": [ 11968 {"bits": [0, 3], "name": "S8_X"}, 11969 {"bits": [4, 7], "name": "S8_Y"}, 11970 {"bits": [8, 11], "name": "S9_X"}, 11971 {"bits": [12, 15], "name": "S9_Y"}, 11972 {"bits": [16, 19], "name": "S10_X"}, 11973 {"bits": [20, 23], "name": "S10_Y"}, 11974 {"bits": [24, 27], "name": "S11_X"}, 11975 {"bits": [28, 31], "name": "S11_Y"} 11976 ] 11977 }, 11978 "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3": { 11979 "fields": [ 11980 {"bits": [0, 3], "name": "S12_X"}, 11981 {"bits": [4, 7], "name": "S12_Y"}, 11982 {"bits": [8, 11], "name": "S13_X"}, 11983 {"bits": [12, 15], "name": "S13_Y"}, 11984 {"bits": [16, 19], "name": "S14_X"}, 11985 {"bits": [20, 23], "name": "S14_Y"}, 11986 {"bits": [24, 27], "name": "S15_X"}, 11987 {"bits": [28, 31], "name": "S15_Y"} 11988 ] 11989 }, 11990 "PA_SC_BINNER_CNTL_0": { 11991 "fields": [ 11992 {"bits": [0, 1], "enum_ref": "BinningMode", "name": "BINNING_MODE"}, 11993 {"bits": [2, 2], "name": "BIN_SIZE_X"}, 11994 {"bits": [3, 3], "name": "BIN_SIZE_Y"}, 11995 {"bits": [4, 6], "enum_ref": "BinSizeExtend", "name": "BIN_SIZE_X_EXTEND"}, 11996 {"bits": [7, 9], "enum_ref": "BinSizeExtend", "name": "BIN_SIZE_Y_EXTEND"}, 11997 {"bits": [10, 12], "name": "CONTEXT_STATES_PER_BIN"}, 11998 {"bits": [13, 17], "name": "PERSISTENT_STATES_PER_BIN"}, 11999 {"bits": [18, 18], "name": "DISABLE_START_OF_PRIM"}, 12000 {"bits": [19, 26], "name": "FPOVS_PER_BATCH"}, 12001 {"bits": [27, 27], "name": "OPTIMAL_BIN_SELECTION"}, 12002 {"bits": [28, 28], "name": "FLUSH_ON_BINNING_TRANSITION"} 12003 ] 12004 }, 12005 "PA_SC_BINNER_CNTL_1": { 12006 "fields": [ 12007 {"bits": [0, 15], "name": "MAX_ALLOC_COUNT"}, 12008 {"bits": [16, 31], "name": "MAX_PRIM_PER_BATCH"} 12009 ] 12010 }, 12011 "PA_SC_CENTROID_PRIORITY_0": { 12012 "fields": [ 12013 {"bits": [0, 3], "name": "DISTANCE_0"}, 12014 {"bits": [4, 7], "name": "DISTANCE_1"}, 12015 {"bits": [8, 11], "name": "DISTANCE_2"}, 12016 {"bits": [12, 15], "name": "DISTANCE_3"}, 12017 {"bits": [16, 19], "name": "DISTANCE_4"}, 12018 {"bits": [20, 23], "name": "DISTANCE_5"}, 12019 {"bits": [24, 27], "name": "DISTANCE_6"}, 12020 {"bits": [28, 31], "name": "DISTANCE_7"} 12021 ] 12022 }, 12023 "PA_SC_CENTROID_PRIORITY_1": { 12024 "fields": [ 12025 {"bits": [0, 3], "name": "DISTANCE_8"}, 12026 {"bits": [4, 7], "name": "DISTANCE_9"}, 12027 {"bits": [8, 11], "name": "DISTANCE_10"}, 12028 {"bits": [12, 15], "name": "DISTANCE_11"}, 12029 {"bits": [16, 19], "name": "DISTANCE_12"}, 12030 {"bits": [20, 23], "name": "DISTANCE_13"}, 12031 {"bits": [24, 27], "name": "DISTANCE_14"}, 12032 {"bits": [28, 31], "name": "DISTANCE_15"} 12033 ] 12034 }, 12035 "PA_SC_CLIPRECT_0_TL": { 12036 "fields": [ 12037 {"bits": [0, 14], "name": "TL_X"}, 12038 {"bits": [16, 30], "name": "TL_Y"} 12039 ] 12040 }, 12041 "PA_SC_CLIPRECT_RULE": { 12042 "fields": [ 12043 {"bits": [0, 15], "enum_ref": "CLIP_RULE", "name": "CLIP_RULE"} 12044 ] 12045 }, 12046 "PA_SC_CONSERVATIVE_RASTERIZATION_CNTL": { 12047 "fields": [ 12048 {"bits": [0, 0], "name": "OVER_RAST_ENABLE"}, 12049 {"bits": [1, 4], "name": "OVER_RAST_SAMPLE_SELECT"}, 12050 {"bits": [5, 5], "name": "UNDER_RAST_ENABLE"}, 12051 {"bits": [6, 9], "name": "UNDER_RAST_SAMPLE_SELECT"}, 12052 {"bits": [10, 10], "name": "PBB_UNCERTAINTY_REGION_ENABLE"}, 12053 {"bits": [11, 11], "name": "ZMM_TRI_EXTENT"}, 12054 {"bits": [12, 12], "name": "ZMM_TRI_OFFSET"}, 12055 {"bits": [13, 13], "name": "OVERRIDE_OVER_RAST_INNER_TO_NORMAL"}, 12056 {"bits": [14, 14], "name": "OVERRIDE_UNDER_RAST_INNER_TO_NORMAL"}, 12057 {"bits": [15, 15], "name": "DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE"}, 12058 {"bits": [16, 17], "enum_ref": "ScUncertaintyRegionMode", "name": "UNCERTAINTY_REGION_MODE"}, 12059 {"bits": [18, 18], "name": "OUTER_UNCERTAINTY_EDGERULE_OVERRIDE"}, 12060 {"bits": [19, 19], "name": "INNER_UNCERTAINTY_EDGERULE_OVERRIDE"}, 12061 {"bits": [20, 20], "name": "NULL_SQUAD_AA_MASK_ENABLE"}, 12062 {"bits": [21, 21], "name": "COVERAGE_AA_MASK_ENABLE"}, 12063 {"bits": [22, 22], "name": "PREZ_AA_MASK_ENABLE"}, 12064 {"bits": [23, 23], "name": "POSTZ_AA_MASK_ENABLE"}, 12065 {"bits": [24, 24], "name": "CENTROID_SAMPLE_OVERRIDE"} 12066 ] 12067 }, 12068 "PA_SC_EDGERULE": { 12069 "fields": [ 12070 {"bits": [0, 3], "name": "ER_TRI"}, 12071 {"bits": [4, 7], "name": "ER_POINT"}, 12072 {"bits": [8, 11], "name": "ER_RECT"}, 12073 {"bits": [12, 17], "name": "ER_LINE_LR"}, 12074 {"bits": [18, 23], "name": "ER_LINE_RL"}, 12075 {"bits": [24, 27], "name": "ER_LINE_TB"}, 12076 {"bits": [28, 31], "name": "ER_LINE_BT"} 12077 ] 12078 }, 12079 "PA_SC_HORIZ_GRID": { 12080 "fields": [ 12081 {"bits": [0, 7], "name": "TOP_QTR"}, 12082 {"bits": [8, 15], "name": "TOP_HALF"}, 12083 {"bits": [16, 23], "name": "BOT_HALF"}, 12084 {"bits": [24, 31], "name": "BOT_QTR"} 12085 ] 12086 }, 12087 "PA_SC_LINE_CNTL": { 12088 "fields": [ 12089 {"bits": [9, 9], "name": "EXPAND_LINE_WIDTH"}, 12090 {"bits": [10, 10], "name": "LAST_PIXEL"}, 12091 {"bits": [11, 11], "name": "PERPENDICULAR_ENDCAP_ENA"}, 12092 {"bits": [12, 12], "name": "DX10_DIAMOND_TEST_ENA"}, 12093 {"bits": [13, 13], "name": "EXTRA_DX_DY_PRECISION"} 12094 ] 12095 }, 12096 "PA_SC_LINE_STIPPLE": { 12097 "fields": [ 12098 {"bits": [0, 15], "name": "LINE_PATTERN"}, 12099 {"bits": [16, 23], "name": "REPEAT_COUNT"}, 12100 {"bits": [28, 28], "name": "PATTERN_BIT_ORDER"}, 12101 {"bits": [29, 30], "name": "AUTO_RESET_CNTL"} 12102 ] 12103 }, 12104 "PA_SC_LINE_STIPPLE_STATE": { 12105 "fields": [ 12106 {"bits": [0, 3], "name": "CURRENT_PTR"}, 12107 {"bits": [8, 15], "name": "CURRENT_COUNT"} 12108 ] 12109 }, 12110 "PA_SC_MODE_CNTL_0": { 12111 "fields": [ 12112 {"bits": [0, 0], "name": "MSAA_ENABLE"}, 12113 {"bits": [1, 1], "name": "VPORT_SCISSOR_ENABLE"}, 12114 {"bits": [2, 2], "name": "LINE_STIPPLE_ENABLE"}, 12115 {"bits": [3, 3], "name": "SEND_UNLIT_STILES_TO_PKR"}, 12116 {"bits": [4, 4], "name": "SCALE_LINE_WIDTH_PAD"}, 12117 {"bits": [5, 5], "name": "ALTERNATE_RBS_PER_TILE"}, 12118 {"bits": [6, 6], "name": "COARSE_TILE_STARTS_ON_EVEN_RB"} 12119 ] 12120 }, 12121 "PA_SC_MODE_CNTL_1": { 12122 "fields": [ 12123 {"bits": [0, 0], "name": "WALK_SIZE"}, 12124 {"bits": [1, 1], "name": "WALK_ALIGNMENT"}, 12125 {"bits": [2, 2], "name": "WALK_ALIGN8_PRIM_FITS_ST"}, 12126 {"bits": [3, 3], "name": "WALK_FENCE_ENABLE"}, 12127 {"bits": [4, 6], "name": "WALK_FENCE_SIZE"}, 12128 {"bits": [7, 7], "name": "SUPERTILE_WALK_ORDER_ENABLE"}, 12129 {"bits": [8, 8], "name": "TILE_WALK_ORDER_ENABLE"}, 12130 {"bits": [9, 9], "name": "TILE_COVER_DISABLE"}, 12131 {"bits": [10, 10], "name": "TILE_COVER_NO_SCISSOR"}, 12132 {"bits": [11, 11], "name": "ZMM_LINE_EXTENT"}, 12133 {"bits": [12, 12], "name": "ZMM_LINE_OFFSET"}, 12134 {"bits": [13, 13], "name": "ZMM_RECT_EXTENT"}, 12135 {"bits": [14, 14], "name": "KILL_PIX_POST_HI_Z"}, 12136 {"bits": [15, 15], "name": "KILL_PIX_POST_DETAIL_MASK"}, 12137 {"bits": [16, 16], "name": "PS_ITER_SAMPLE"}, 12138 {"bits": [17, 17], "name": "MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE"}, 12139 {"bits": [18, 18], "name": "MULTI_GPU_SUPERTILE_ENABLE"}, 12140 {"bits": [19, 19], "name": "GPU_ID_OVERRIDE_ENABLE"}, 12141 {"bits": [20, 23], "name": "GPU_ID_OVERRIDE"}, 12142 {"bits": [24, 24], "name": "MULTI_GPU_PRIM_DISCARD_ENABLE"}, 12143 {"bits": [25, 25], "name": "FORCE_EOV_CNTDWN_ENABLE"}, 12144 {"bits": [26, 26], "name": "FORCE_EOV_REZ_ENABLE"}, 12145 {"bits": [27, 27], "name": "OUT_OF_ORDER_PRIMITIVE_ENABLE"}, 12146 {"bits": [28, 30], "name": "OUT_OF_ORDER_WATER_MARK"} 12147 ] 12148 }, 12149 "PA_SC_NGG_MODE_CNTL": { 12150 "fields": [ 12151 {"bits": [0, 10], "name": "MAX_DEALLOCS_IN_WAVE"} 12152 ] 12153 }, 12154 "PA_SC_P3D_TRAP_SCREEN_H": { 12155 "fields": [ 12156 {"bits": [0, 13], "name": "X_COORD"} 12157 ] 12158 }, 12159 "PA_SC_P3D_TRAP_SCREEN_HV_EN": { 12160 "fields": [ 12161 {"bits": [0, 0], "name": "ENABLE_HV_PRE_SHADER"}, 12162 {"bits": [1, 1], "name": "FORCE_PRE_SHADER_ALL_PIXELS"} 12163 ] 12164 }, 12165 "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE": { 12166 "fields": [ 12167 {"bits": [0, 15], "name": "COUNT"} 12168 ] 12169 }, 12170 "PA_SC_P3D_TRAP_SCREEN_V": { 12171 "fields": [ 12172 {"bits": [0, 13], "name": "Y_COORD"} 12173 ] 12174 }, 12175 "PA_SC_PERFCOUNTER1_SELECT": { 12176 "fields": [ 12177 {"bits": [0, 9], "name": "PERF_SEL"} 12178 ] 12179 }, 12180 "PA_SC_RASTER_CONFIG": { 12181 "fields": [ 12182 {"bits": [0, 1], "enum_ref": "RbMap", "name": "RB_MAP_PKR0"}, 12183 {"bits": [2, 3], "enum_ref": "RbMap", "name": "RB_MAP_PKR1"}, 12184 {"bits": [4, 5], "enum_ref": "RbXsel2", "name": "RB_XSEL2"}, 12185 {"bits": [6, 6], "enum_ref": "RbXsel", "name": "RB_XSEL"}, 12186 {"bits": [7, 7], "enum_ref": "RbYsel", "name": "RB_YSEL"}, 12187 {"bits": [8, 9], "enum_ref": "PkrMap", "name": "PKR_MAP"}, 12188 {"bits": [10, 11], "enum_ref": "PkrXsel", "name": "PKR_XSEL"}, 12189 {"bits": [12, 13], "enum_ref": "PkrYsel", "name": "PKR_YSEL"}, 12190 {"bits": [14, 15], "enum_ref": "PkrXsel2", "name": "PKR_XSEL2"}, 12191 {"bits": [16, 17], "enum_ref": "ScMap", "name": "SC_MAP"}, 12192 {"bits": [18, 19], "enum_ref": "ScXsel", "name": "SC_XSEL"}, 12193 {"bits": [20, 21], "enum_ref": "ScYsel", "name": "SC_YSEL"}, 12194 {"bits": [24, 25], "enum_ref": "SeMap", "name": "SE_MAP"}, 12195 {"bits": [26, 28], "enum_ref": "SeXsel", "name": "SE_XSEL"}, 12196 {"bits": [29, 31], "enum_ref": "SeYsel", "name": "SE_YSEL"} 12197 ] 12198 }, 12199 "PA_SC_RASTER_CONFIG_1": { 12200 "fields": [ 12201 {"bits": [0, 1], "enum_ref": "SePairMap", "name": "SE_PAIR_MAP"}, 12202 {"bits": [2, 4], "enum_ref": "SePairXsel", "name": "SE_PAIR_XSEL"}, 12203 {"bits": [5, 7], "enum_ref": "SePairYsel", "name": "SE_PAIR_YSEL"} 12204 ] 12205 }, 12206 "PA_SC_RIGHT_VERT_GRID": { 12207 "fields": [ 12208 {"bits": [0, 7], "name": "LEFT_QTR"}, 12209 {"bits": [8, 15], "name": "LEFT_HALF"}, 12210 {"bits": [16, 23], "name": "RIGHT_HALF"}, 12211 {"bits": [24, 31], "name": "RIGHT_QTR"} 12212 ] 12213 }, 12214 "PA_SC_SCREEN_EXTENT_CONTROL": { 12215 "fields": [ 12216 {"bits": [0, 1], "name": "SLICE_EVEN_ENABLE"}, 12217 {"bits": [2, 3], "name": "SLICE_ODD_ENABLE"} 12218 ] 12219 }, 12220 "PA_SC_SCREEN_EXTENT_MIN_0": { 12221 "fields": [ 12222 {"bits": [0, 15], "name": "X"}, 12223 {"bits": [16, 31], "name": "Y"} 12224 ] 12225 }, 12226 "PA_SC_SCREEN_SCISSOR_BR": { 12227 "fields": [ 12228 {"bits": [0, 15], "name": "BR_X"}, 12229 {"bits": [16, 31], "name": "BR_Y"} 12230 ] 12231 }, 12232 "PA_SC_SCREEN_SCISSOR_TL": { 12233 "fields": [ 12234 {"bits": [0, 15], "name": "TL_X"}, 12235 {"bits": [16, 31], "name": "TL_Y"} 12236 ] 12237 }, 12238 "PA_SC_SHADER_CONTROL": { 12239 "fields": [ 12240 {"bits": [0, 1], "name": "REALIGN_DQUADS_AFTER_N_WAVES"}, 12241 {"bits": [2, 2], "name": "LOAD_COLLISION_WAVEID"}, 12242 {"bits": [3, 3], "name": "LOAD_INTRAWAVE_COLLISION"} 12243 ] 12244 }, 12245 "PA_SC_TILE_STEERING_OVERRIDE": { 12246 "fields": [ 12247 {"bits": [0, 0], "name": "ENABLE"}, 12248 {"bits": [1, 2], "name": "NUM_SE"}, 12249 {"bits": [5, 6], "name": "NUM_RB_PER_SE"} 12250 ] 12251 }, 12252 "PA_SC_WINDOW_OFFSET": { 12253 "fields": [ 12254 {"bits": [0, 15], "name": "WINDOW_X_OFFSET"}, 12255 {"bits": [16, 31], "name": "WINDOW_Y_OFFSET"} 12256 ] 12257 }, 12258 "PA_SC_WINDOW_SCISSOR_BR": { 12259 "fields": [ 12260 {"bits": [0, 14], "name": "BR_X"}, 12261 {"bits": [16, 30], "name": "BR_Y"} 12262 ] 12263 }, 12264 "PA_SC_WINDOW_SCISSOR_TL": { 12265 "fields": [ 12266 {"bits": [0, 14], "name": "TL_X"}, 12267 {"bits": [16, 30], "name": "TL_Y"}, 12268 {"bits": [31, 31], "name": "WINDOW_OFFSET_DISABLE"} 12269 ] 12270 }, 12271 "PA_STEREO_CNTL": { 12272 "fields": [ 12273 {"bits": [0, 0], "name": "EN_STEREO"}, 12274 {"bits": [1, 4], "name": "STEREO_MODE"}, 12275 {"bits": [5, 7], "name": "RT_SLICE_MODE"}, 12276 {"bits": [8, 9], "name": "RT_SLICE_OFFSET"}, 12277 {"bits": [10, 12], "name": "VP_ID_MODE"}, 12278 {"bits": [13, 16], "name": "VP_ID_OFFSET"} 12279 ] 12280 }, 12281 "PA_SU_HARDWARE_SCREEN_OFFSET": { 12282 "fields": [ 12283 {"bits": [0, 8], "name": "HW_SCREEN_OFFSET_X"}, 12284 {"bits": [16, 24], "name": "HW_SCREEN_OFFSET_Y"} 12285 ] 12286 }, 12287 "PA_SU_LINE_CNTL": { 12288 "fields": [ 12289 {"bits": [0, 15], "name": "WIDTH"} 12290 ] 12291 }, 12292 "PA_SU_LINE_STIPPLE_CNTL": { 12293 "fields": [ 12294 {"bits": [0, 1], "name": "LINE_STIPPLE_RESET"}, 12295 {"bits": [2, 2], "name": "EXPAND_FULL_LENGTH"}, 12296 {"bits": [3, 3], "name": "FRACTIONAL_ACCUM"}, 12297 {"bits": [4, 4], "name": "DIAMOND_ADJUST"} 12298 ] 12299 }, 12300 "PA_SU_LINE_STIPPLE_VALUE": { 12301 "fields": [ 12302 {"bits": [0, 23], "name": "LINE_STIPPLE_VALUE"} 12303 ] 12304 }, 12305 "PA_SU_OVER_RASTERIZATION_CNTL": { 12306 "fields": [ 12307 {"bits": [0, 0], "name": "DISCARD_0_AREA_TRIANGLES"}, 12308 {"bits": [1, 1], "name": "DISCARD_0_AREA_LINES"}, 12309 {"bits": [2, 2], "name": "DISCARD_0_AREA_POINTS"}, 12310 {"bits": [3, 3], "name": "DISCARD_0_AREA_RECTANGLES"}, 12311 {"bits": [4, 4], "name": "USE_PROVOKING_ZW"} 12312 ] 12313 }, 12314 "PA_SU_PERFCOUNTER0_HI": { 12315 "fields": [ 12316 {"bits": [0, 15], "name": "PERFCOUNTER_HI"} 12317 ] 12318 }, 12319 "PA_SU_PERFCOUNTER2_SELECT": { 12320 "fields": [ 12321 {"bits": [0, 9], "name": "PERF_SEL"}, 12322 {"bits": [20, 23], "name": "CNTR_MODE"}, 12323 {"bits": [28, 31], "name": "PERF_MODE"} 12324 ] 12325 }, 12326 "PA_SU_POINT_MINMAX": { 12327 "fields": [ 12328 {"bits": [0, 15], "name": "MIN_SIZE"}, 12329 {"bits": [16, 31], "name": "MAX_SIZE"} 12330 ] 12331 }, 12332 "PA_SU_POINT_SIZE": { 12333 "fields": [ 12334 {"bits": [0, 15], "name": "HEIGHT"}, 12335 {"bits": [16, 31], "name": "WIDTH"} 12336 ] 12337 }, 12338 "PA_SU_POLY_OFFSET_DB_FMT_CNTL": { 12339 "fields": [ 12340 {"bits": [0, 7], "name": "POLY_OFFSET_NEG_NUM_DB_BITS"}, 12341 {"bits": [8, 8], "name": "POLY_OFFSET_DB_IS_FLOAT_FMT"} 12342 ] 12343 }, 12344 "PA_SU_PRIM_FILTER_CNTL": { 12345 "fields": [ 12346 {"bits": [0, 0], "name": "TRIANGLE_FILTER_DISABLE"}, 12347 {"bits": [1, 1], "name": "LINE_FILTER_DISABLE"}, 12348 {"bits": [2, 2], "name": "POINT_FILTER_DISABLE"}, 12349 {"bits": [3, 3], "name": "RECTANGLE_FILTER_DISABLE"}, 12350 {"bits": [4, 4], "name": "TRIANGLE_EXPAND_ENA"}, 12351 {"bits": [5, 5], "name": "LINE_EXPAND_ENA"}, 12352 {"bits": [6, 6], "name": "POINT_EXPAND_ENA"}, 12353 {"bits": [7, 7], "name": "RECTANGLE_EXPAND_ENA"}, 12354 {"bits": [8, 15], "name": "PRIM_EXPAND_CONSTANT"}, 12355 {"bits": [30, 30], "name": "XMAX_RIGHT_EXCLUSION"}, 12356 {"bits": [31, 31], "name": "YMAX_BOTTOM_EXCLUSION"} 12357 ] 12358 }, 12359 "PA_SU_SC_MODE_CNTL": { 12360 "fields": [ 12361 {"bits": [0, 0], "name": "CULL_FRONT"}, 12362 {"bits": [1, 1], "name": "CULL_BACK"}, 12363 {"bits": [2, 2], "name": "FACE"}, 12364 {"bits": [3, 4], "enum_ref": "PA_SU_SC_MODE_CNTL__POLY_MODE", "name": "POLY_MODE"}, 12365 {"bits": [5, 7], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE_FRONT_PTYPE"}, 12366 {"bits": [8, 10], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE_BACK_PTYPE"}, 12367 {"bits": [11, 11], "name": "POLY_OFFSET_FRONT_ENABLE"}, 12368 {"bits": [12, 12], "name": "POLY_OFFSET_BACK_ENABLE"}, 12369 {"bits": [13, 13], "name": "POLY_OFFSET_PARA_ENABLE"}, 12370 {"bits": [16, 16], "name": "VTX_WINDOW_OFFSET_ENABLE"}, 12371 {"bits": [19, 19], "name": "PROVOKING_VTX_LAST"}, 12372 {"bits": [20, 20], "name": "PERSP_CORR_DIS"}, 12373 {"bits": [21, 21], "name": "MULTI_PRIM_IB_ENA"}, 12374 {"bits": [22, 22], "name": "RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF"}, 12375 {"bits": [23, 23], "name": "NEW_QUAD_DECOMPOSITION"} 12376 ] 12377 }, 12378 "PA_SU_SMALL_PRIM_FILTER_CNTL": { 12379 "fields": [ 12380 {"bits": [0, 0], "name": "SMALL_PRIM_FILTER_ENABLE"}, 12381 {"bits": [1, 1], "name": "TRIANGLE_FILTER_DISABLE"}, 12382 {"bits": [2, 2], "name": "LINE_FILTER_DISABLE"}, 12383 {"bits": [3, 3], "name": "POINT_FILTER_DISABLE"}, 12384 {"bits": [4, 4], "name": "RECTANGLE_FILTER_DISABLE"}, 12385 {"bits": [6, 6], "name": "SC_1XMSAA_COMPATIBLE_DISABLE"} 12386 ] 12387 }, 12388 "PA_SU_VTX_CNTL": { 12389 "fields": [ 12390 {"bits": [0, 0], "name": "PIX_CENTER"}, 12391 {"bits": [1, 2], "enum_ref": "PA_SU_VTX_CNTL__ROUND_MODE", "name": "ROUND_MODE"}, 12392 {"bits": [3, 5], "enum_ref": "QUANT_MODE", "name": "QUANT_MODE"} 12393 ] 12394 }, 12395 "RLC_GPM_PERF_COUNT_0": { 12396 "fields": [ 12397 {"bits": [0, 3], "name": "FEATURE_SEL"}, 12398 {"bits": [4, 7], "name": "SE_INDEX"}, 12399 {"bits": [8, 11], "name": "SH_INDEX"}, 12400 {"bits": [12, 15], "name": "CU_INDEX"}, 12401 {"bits": [16, 17], "name": "EVENT_SEL"}, 12402 {"bits": [18, 19], "name": "UNUSED"}, 12403 {"bits": [20, 20], "name": "ENABLE"}, 12404 {"bits": [21, 31], "name": "RESERVED"} 12405 ] 12406 }, 12407 "RLC_GPU_IOV_PERF_CNT_CNTL": { 12408 "fields": [ 12409 {"bits": [0, 0], "name": "ENABLE"}, 12410 {"bits": [1, 1], "name": "MODE_SELECT"}, 12411 {"bits": [2, 2], "name": "RESET"}, 12412 {"bits": [3, 31], "name": "RESERVED"} 12413 ] 12414 }, 12415 "RLC_GPU_IOV_PERF_CNT_WR_ADDR": { 12416 "fields": [ 12417 {"bits": [0, 3], "name": "VFID"}, 12418 {"bits": [4, 5], "name": "CNT_ID"}, 12419 {"bits": [6, 31], "name": "RESERVED"} 12420 ] 12421 }, 12422 "RLC_PERFCOUNTER0_SELECT": { 12423 "fields": [ 12424 {"bits": [0, 7], "name": "PERFCOUNTER_SELECT"} 12425 ] 12426 }, 12427 "RLC_PERFMON_CLK_CNTL_UCODE": { 12428 "fields": [ 12429 {"bits": [0, 0], "name": "PERFMON_CLOCK_STATE"} 12430 ] 12431 }, 12432 "RLC_PERFMON_CNTL": { 12433 "fields": [ 12434 {"bits": [0, 2], "enum_ref": "CP_PERFMON_STATE", "name": "PERFMON_STATE"}, 12435 {"bits": [10, 10], "name": "PERFMON_SAMPLE_ENABLE"} 12436 ] 12437 }, 12438 "RLC_SPM_CPG_PERFMON_SAMPLE_DELAY": { 12439 "fields": [ 12440 {"bits": [0, 7], "name": "PERFMON_SAMPLE_DELAY"}, 12441 {"bits": [8, 31], "name": "RESERVED"} 12442 ] 12443 }, 12444 "RLC_SPM_PERFMON_CNTL": { 12445 "fields": [ 12446 {"bits": [0, 11], "name": "RESERVED1"}, 12447 {"bits": [12, 13], "name": "PERFMON_RING_MODE"}, 12448 {"bits": [14, 15], "name": "RESERVED"}, 12449 {"bits": [16, 31], "name": "PERFMON_SAMPLE_INTERVAL"} 12450 ] 12451 }, 12452 "RLC_SPM_PERFMON_RING_BASE_HI": { 12453 "fields": [ 12454 {"bits": [0, 15], "name": "RING_BASE_HI"}, 12455 {"bits": [16, 31], "name": "RESERVED"} 12456 ] 12457 }, 12458 "RLC_SPM_PERFMON_SAMPLE_DELAY_MAX": { 12459 "fields": [ 12460 {"bits": [0, 7], "name": "PERFMON_MAX_SAMPLE_DELAY"}, 12461 {"bits": [8, 31], "name": "RESERVED"} 12462 ] 12463 }, 12464 "RLC_SPM_PERFMON_SEGMENT_SIZE": { 12465 "fields": [ 12466 {"bits": [0, 7], "name": "PERFMON_SEGMENT_SIZE"}, 12467 {"bits": [8, 10], "name": "RESERVED1"}, 12468 {"bits": [11, 15], "name": "GLOBAL_NUM_LINE"}, 12469 {"bits": [16, 20], "name": "SE0_NUM_LINE"}, 12470 {"bits": [21, 25], "name": "SE1_NUM_LINE"}, 12471 {"bits": [26, 30], "name": "SE2_NUM_LINE"}, 12472 {"bits": [31, 31], "name": "RESERVED"} 12473 ] 12474 }, 12475 "RMI_PERF_COUNTER_CNTL": { 12476 "fields": [ 12477 {"bits": [0, 1], "name": "TRANS_BASED_PERF_EN_SEL"}, 12478 {"bits": [2, 3], "name": "EVENT_BASED_PERF_EN_SEL"}, 12479 {"bits": [4, 5], "name": "TC_PERF_EN_SEL"}, 12480 {"bits": [6, 7], "name": "PERF_EVENT_WINDOW_MASK0"}, 12481 {"bits": [8, 9], "name": "PERF_EVENT_WINDOW_MASK1"}, 12482 {"bits": [10, 13], "name": "PERF_COUNTER_CID"}, 12483 {"bits": [14, 18], "name": "PERF_COUNTER_VMID"}, 12484 {"bits": [19, 24], "name": "PERF_COUNTER_BURST_LENGTH_THRESHOLD"}, 12485 {"bits": [25, 25], "name": "PERF_SOFT_RESET"}, 12486 {"bits": [26, 26], "name": "PERF_CNTR_SPM_SEL"} 12487 ] 12488 }, 12489 "SCRATCH_UMSK": { 12490 "fields": [ 12491 {"bits": [0, 7], "name": "OBSOLETE_UMSK"}, 12492 {"bits": [16, 17], "name": "OBSOLETE_SWAP"} 12493 ] 12494 }, 12495 "SPI_BARYC_CNTL": { 12496 "fields": [ 12497 {"bits": [0, 0], "name": "PERSP_CENTER_CNTL"}, 12498 {"bits": [4, 4], "name": "PERSP_CENTROID_CNTL"}, 12499 {"bits": [8, 8], "name": "LINEAR_CENTER_CNTL"}, 12500 {"bits": [12, 12], "name": "LINEAR_CENTROID_CNTL"}, 12501 {"bits": [16, 17], "name": "POS_FLOAT_LOCATION"}, 12502 {"bits": [20, 20], "name": "POS_FLOAT_ULC"}, 12503 {"bits": [24, 24], "name": "FRONT_FACE_ALL_BITS"} 12504 ] 12505 }, 12506 "SPI_CONFIG_CNTL": { 12507 "fields": [ 12508 {"bits": [0, 20], "name": "GPR_WRITE_PRIORITY"}, 12509 {"bits": [21, 23], "name": "EXP_PRIORITY_ORDER"}, 12510 {"bits": [24, 24], "name": "ENABLE_SQG_TOP_EVENTS"}, 12511 {"bits": [25, 25], "name": "ENABLE_SQG_BOP_EVENTS"}, 12512 {"bits": [26, 26], "name": "RSRC_MGMT_RESET"}, 12513 {"bits": [27, 27], "name": "TTRACE_STALL_ALL"}, 12514 {"bits": [28, 28], "name": "ALLOC_ARB_LRU_ENA"}, 12515 {"bits": [29, 29], "name": "EXP_ARB_LRU_ENA"}, 12516 {"bits": [30, 31], "name": "PS_PKR_PRIORITY_CNTL"} 12517 ] 12518 }, 12519 "SPI_CONFIG_CNTL_1": { 12520 "fields": [ 12521 {"bits": [0, 3], "name": "VTX_DONE_DELAY"}, 12522 {"bits": [4, 4], "name": "INTERP_ONE_PRIM_PER_ROW"}, 12523 {"bits": [5, 5], "name": "BATON_RESET_DISABLE"}, 12524 {"bits": [6, 6], "name": "PC_LIMIT_ENABLE"}, 12525 {"bits": [7, 7], "name": "PC_LIMIT_STRICT"}, 12526 {"bits": [8, 8], "name": "CRC_SIMD_ID_WADDR_DISABLE"}, 12527 {"bits": [9, 9], "name": "LBPW_CU_CHK_MODE"}, 12528 {"bits": [10, 13], "name": "LBPW_CU_CHK_CNT"}, 12529 {"bits": [14, 14], "name": "CSC_PWR_SAVE_DISABLE"}, 12530 {"bits": [15, 15], "name": "CSG_PWR_SAVE_DISABLE"}, 12531 {"bits": [16, 31], "name": "PC_LIMIT_SIZE"} 12532 ] 12533 }, 12534 "SPI_CONFIG_CNTL_2": { 12535 "fields": [ 12536 {"bits": [0, 3], "name": "CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD"}, 12537 {"bits": [4, 7], "name": "CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD"} 12538 ] 12539 }, 12540 "SPI_INTERP_CONTROL_0": { 12541 "fields": [ 12542 {"bits": [0, 0], "name": "FLAT_SHADE_ENA"}, 12543 {"bits": [1, 1], "name": "PNT_SPRITE_ENA"}, 12544 {"bits": [2, 4], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_X"}, 12545 {"bits": [5, 7], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Y"}, 12546 {"bits": [8, 10], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Z"}, 12547 {"bits": [11, 13], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_W"}, 12548 {"bits": [14, 14], "name": "PNT_SPRITE_TOP_1"} 12549 ] 12550 }, 12551 "SPI_PERFCOUNTER4_SELECT": { 12552 "fields": [ 12553 {"bits": [0, 7], "name": "PERF_SEL"} 12554 ] 12555 }, 12556 "SPI_PERFCOUNTER_BINS": { 12557 "fields": [ 12558 {"bits": [0, 3], "name": "BIN0_MIN"}, 12559 {"bits": [4, 7], "name": "BIN0_MAX"}, 12560 {"bits": [8, 11], "name": "BIN1_MIN"}, 12561 {"bits": [12, 15], "name": "BIN1_MAX"}, 12562 {"bits": [16, 19], "name": "BIN2_MIN"}, 12563 {"bits": [20, 23], "name": "BIN2_MAX"}, 12564 {"bits": [24, 27], "name": "BIN3_MIN"}, 12565 {"bits": [28, 31], "name": "BIN3_MAX"} 12566 ] 12567 }, 12568 "SPI_PS_INPUT_CNTL_0": { 12569 "fields": [ 12570 {"bits": [0, 5], "name": "OFFSET"}, 12571 {"bits": [8, 9], "name": "DEFAULT_VAL"}, 12572 {"bits": [10, 10], "name": "FLAT_SHADE"}, 12573 {"bits": [13, 16], "name": "CYL_WRAP"}, 12574 {"bits": [17, 17], "name": "PT_SPRITE_TEX"}, 12575 {"bits": [18, 18], "name": "DUP"}, 12576 {"bits": [19, 19], "name": "FP16_INTERP_MODE"}, 12577 {"bits": [20, 20], "name": "USE_DEFAULT_ATTR1"}, 12578 {"bits": [21, 22], "name": "DEFAULT_VAL_ATTR1"}, 12579 {"bits": [23, 23], "name": "PT_SPRITE_TEX_ATTR1"}, 12580 {"bits": [24, 24], "name": "ATTR0_VALID"}, 12581 {"bits": [25, 25], "name": "ATTR1_VALID"} 12582 ] 12583 }, 12584 "SPI_PS_INPUT_CNTL_20": { 12585 "fields": [ 12586 {"bits": [0, 5], "name": "OFFSET"}, 12587 {"bits": [8, 9], "name": "DEFAULT_VAL"}, 12588 {"bits": [10, 10], "name": "FLAT_SHADE"}, 12589 {"bits": [18, 18], "name": "DUP"}, 12590 {"bits": [19, 19], "name": "FP16_INTERP_MODE"}, 12591 {"bits": [20, 20], "name": "USE_DEFAULT_ATTR1"}, 12592 {"bits": [21, 22], "name": "DEFAULT_VAL_ATTR1"}, 12593 {"bits": [24, 24], "name": "ATTR0_VALID"}, 12594 {"bits": [25, 25], "name": "ATTR1_VALID"} 12595 ] 12596 }, 12597 "SPI_PS_INPUT_ENA": { 12598 "fields": [ 12599 {"bits": [0, 0], "name": "PERSP_SAMPLE_ENA"}, 12600 {"bits": [1, 1], "name": "PERSP_CENTER_ENA"}, 12601 {"bits": [2, 2], "name": "PERSP_CENTROID_ENA"}, 12602 {"bits": [3, 3], "name": "PERSP_PULL_MODEL_ENA"}, 12603 {"bits": [4, 4], "name": "LINEAR_SAMPLE_ENA"}, 12604 {"bits": [5, 5], "name": "LINEAR_CENTER_ENA"}, 12605 {"bits": [6, 6], "name": "LINEAR_CENTROID_ENA"}, 12606 {"bits": [7, 7], "name": "LINE_STIPPLE_TEX_ENA"}, 12607 {"bits": [8, 8], "name": "POS_X_FLOAT_ENA"}, 12608 {"bits": [9, 9], "name": "POS_Y_FLOAT_ENA"}, 12609 {"bits": [10, 10], "name": "POS_Z_FLOAT_ENA"}, 12610 {"bits": [11, 11], "name": "POS_W_FLOAT_ENA"}, 12611 {"bits": [12, 12], "name": "FRONT_FACE_ENA"}, 12612 {"bits": [13, 13], "name": "ANCILLARY_ENA"}, 12613 {"bits": [14, 14], "name": "SAMPLE_COVERAGE_ENA"}, 12614 {"bits": [15, 15], "name": "POS_FIXED_PT_ENA"} 12615 ] 12616 }, 12617 "SPI_PS_IN_CONTROL": { 12618 "fields": [ 12619 {"bits": [0, 5], "name": "NUM_INTERP"}, 12620 {"bits": [6, 6], "name": "PARAM_GEN"}, 12621 {"bits": [7, 7], "name": "OFFCHIP_PARAM_EN"}, 12622 {"bits": [8, 8], "name": "LATE_PC_DEALLOC"}, 12623 {"bits": [14, 14], "name": "BC_OPTIMIZE_DISABLE"} 12624 ] 12625 }, 12626 "SPI_SHADER_COL_FORMAT": { 12627 "fields": [ 12628 {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL0_EXPORT_FORMAT"}, 12629 {"bits": [4, 7], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL1_EXPORT_FORMAT"}, 12630 {"bits": [8, 11], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL2_EXPORT_FORMAT"}, 12631 {"bits": [12, 15], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL3_EXPORT_FORMAT"}, 12632 {"bits": [16, 19], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL4_EXPORT_FORMAT"}, 12633 {"bits": [20, 23], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL5_EXPORT_FORMAT"}, 12634 {"bits": [24, 27], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL6_EXPORT_FORMAT"}, 12635 {"bits": [28, 31], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL7_EXPORT_FORMAT"} 12636 ] 12637 }, 12638 "SPI_SHADER_LATE_ALLOC_VS": { 12639 "fields": [ 12640 {"bits": [0, 5], "name": "LIMIT"} 12641 ] 12642 }, 12643 "SPI_SHADER_PGM_HI_PS": { 12644 "fields": [ 12645 {"bits": [0, 7], "name": "MEM_BASE"} 12646 ] 12647 }, 12648 "SPI_SHADER_PGM_RSRC1_GS": { 12649 "fields": [ 12650 {"bits": [0, 5], "name": "VGPRS"}, 12651 {"bits": [6, 9], "name": "SGPRS"}, 12652 {"bits": [10, 11], "name": "PRIORITY"}, 12653 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, 12654 {"bits": [20, 20], "name": "PRIV"}, 12655 {"bits": [21, 21], "name": "DX10_CLAMP"}, 12656 {"bits": [22, 22], "name": "DEBUG_MODE"}, 12657 {"bits": [23, 23], "name": "IEEE_MODE"}, 12658 {"bits": [24, 24], "name": "CU_GROUP_ENABLE"}, 12659 {"bits": [28, 28], "name": "CDBG_USER"}, 12660 {"bits": [29, 30], "name": "GS_VGPR_COMP_CNT"}, 12661 {"bits": [31, 31], "name": "FP16_OVFL"} 12662 ] 12663 }, 12664 "SPI_SHADER_PGM_RSRC1_HS": { 12665 "fields": [ 12666 {"bits": [0, 5], "name": "VGPRS"}, 12667 {"bits": [6, 9], "name": "SGPRS"}, 12668 {"bits": [10, 11], "name": "PRIORITY"}, 12669 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, 12670 {"bits": [20, 20], "name": "PRIV"}, 12671 {"bits": [21, 21], "name": "DX10_CLAMP"}, 12672 {"bits": [22, 22], "name": "DEBUG_MODE"}, 12673 {"bits": [23, 23], "name": "IEEE_MODE"}, 12674 {"bits": [27, 27], "name": "CDBG_USER"}, 12675 {"bits": [28, 29], "name": "LS_VGPR_COMP_CNT"}, 12676 {"bits": [30, 30], "name": "FP16_OVFL"} 12677 ] 12678 }, 12679 "SPI_SHADER_PGM_RSRC1_PS": { 12680 "fields": [ 12681 {"bits": [0, 5], "name": "VGPRS"}, 12682 {"bits": [6, 9], "name": "SGPRS"}, 12683 {"bits": [10, 11], "name": "PRIORITY"}, 12684 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, 12685 {"bits": [20, 20], "name": "PRIV"}, 12686 {"bits": [21, 21], "name": "DX10_CLAMP"}, 12687 {"bits": [22, 22], "name": "DEBUG_MODE"}, 12688 {"bits": [23, 23], "name": "IEEE_MODE"}, 12689 {"bits": [24, 24], "name": "CU_GROUP_DISABLE"}, 12690 {"bits": [28, 28], "name": "CDBG_USER"}, 12691 {"bits": [29, 29], "name": "FP16_OVFL"} 12692 ] 12693 }, 12694 "SPI_SHADER_PGM_RSRC1_VS": { 12695 "fields": [ 12696 {"bits": [0, 5], "name": "VGPRS"}, 12697 {"bits": [6, 9], "name": "SGPRS"}, 12698 {"bits": [10, 11], "name": "PRIORITY"}, 12699 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, 12700 {"bits": [20, 20], "name": "PRIV"}, 12701 {"bits": [21, 21], "name": "DX10_CLAMP"}, 12702 {"bits": [22, 22], "name": "DEBUG_MODE"}, 12703 {"bits": [23, 23], "name": "IEEE_MODE"}, 12704 {"bits": [24, 25], "name": "VGPR_COMP_CNT"}, 12705 {"bits": [26, 26], "name": "CU_GROUP_ENABLE"}, 12706 {"bits": [30, 30], "name": "CDBG_USER"}, 12707 {"bits": [31, 31], "name": "FP16_OVFL"} 12708 ] 12709 }, 12710 "SPI_SHADER_PGM_RSRC2_GS": { 12711 "fields": [ 12712 {"bits": [0, 0], "name": "SCRATCH_EN"}, 12713 {"bits": [1, 5], "name": "USER_SGPR"}, 12714 {"bits": [6, 6], "name": "TRAP_PRESENT"}, 12715 {"bits": [7, 15], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, 12716 {"bits": [16, 17], "name": "ES_VGPR_COMP_CNT"}, 12717 {"bits": [18, 18], "name": "OC_LDS_EN"}, 12718 {"bits": [19, 26], "name": "LDS_SIZE"}, 12719 {"bits": [27, 27], "name": "SKIP_USGPR0"}, 12720 {"bits": [28, 28], "name": "USER_SGPR_MSB"} 12721 ] 12722 }, 12723 "SPI_SHADER_PGM_RSRC2_GS_VS": { 12724 "fields": [ 12725 {"bits": [0, 0], "name": "SCRATCH_EN"}, 12726 {"bits": [1, 5], "name": "USER_SGPR"}, 12727 {"bits": [6, 6], "name": "TRAP_PRESENT"}, 12728 {"bits": [7, 15], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, 12729 {"bits": [16, 17], "name": "VGPR_COMP_CNT"}, 12730 {"bits": [18, 18], "name": "OC_LDS_EN"}, 12731 {"bits": [19, 26], "name": "LDS_SIZE"}, 12732 {"bits": [27, 27], "name": "SKIP_USGPR0"}, 12733 {"bits": [28, 28], "name": "USER_SGPR_MSB"} 12734 ] 12735 }, 12736 "SPI_SHADER_PGM_RSRC2_HS": { 12737 "fields": [ 12738 {"bits": [0, 0], "name": "SCRATCH_EN"}, 12739 {"bits": [1, 5], "name": "USER_SGPR"}, 12740 {"bits": [6, 6], "name": "TRAP_PRESENT"}, 12741 {"bits": [7, 15], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, 12742 {"bits": [16, 24], "name": "LDS_SIZE"}, 12743 {"bits": [27, 27], "name": "SKIP_USGPR0"}, 12744 {"bits": [28, 28], "name": "USER_SGPR_MSB"} 12745 ] 12746 }, 12747 "SPI_SHADER_PGM_RSRC2_PS": { 12748 "fields": [ 12749 {"bits": [0, 0], "name": "SCRATCH_EN"}, 12750 {"bits": [1, 5], "name": "USER_SGPR"}, 12751 {"bits": [6, 6], "name": "TRAP_PRESENT"}, 12752 {"bits": [7, 7], "name": "WAVE_CNT_EN"}, 12753 {"bits": [8, 15], "name": "EXTRA_LDS_SIZE"}, 12754 {"bits": [16, 24], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, 12755 {"bits": [25, 25], "name": "LOAD_COLLISION_WAVEID"}, 12756 {"bits": [26, 26], "name": "LOAD_INTRAWAVE_COLLISION"}, 12757 {"bits": [27, 27], "name": "SKIP_USGPR0"}, 12758 {"bits": [28, 28], "name": "USER_SGPR_MSB"} 12759 ] 12760 }, 12761 "SPI_SHADER_PGM_RSRC2_VS": { 12762 "fields": [ 12763 {"bits": [0, 0], "name": "SCRATCH_EN"}, 12764 {"bits": [1, 5], "name": "USER_SGPR"}, 12765 {"bits": [6, 6], "name": "TRAP_PRESENT"}, 12766 {"bits": [7, 7], "name": "OC_LDS_EN"}, 12767 {"bits": [8, 8], "name": "SO_BASE0_EN"}, 12768 {"bits": [9, 9], "name": "SO_BASE1_EN"}, 12769 {"bits": [10, 10], "name": "SO_BASE2_EN"}, 12770 {"bits": [11, 11], "name": "SO_BASE3_EN"}, 12771 {"bits": [12, 12], "name": "SO_EN"}, 12772 {"bits": [13, 21], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, 12773 {"bits": [22, 22], "name": "PC_BASE_EN"}, 12774 {"bits": [24, 24], "name": "DISPATCH_DRAW_EN"}, 12775 {"bits": [27, 27], "name": "SKIP_USGPR0"}, 12776 {"bits": [28, 28], "name": "USER_SGPR_MSB"} 12777 ] 12778 }, 12779 "SPI_SHADER_PGM_RSRC3_HS": { 12780 "fields": [ 12781 {"bits": [0, 5], "name": "WAVE_LIMIT"}, 12782 {"bits": [6, 9], "name": "LOCK_LOW_THRESHOLD"}, 12783 {"bits": [10, 13], "name": "SIMD_DISABLE"}, 12784 {"bits": [16, 31], "name": "CU_EN"} 12785 ] 12786 }, 12787 "SPI_SHADER_PGM_RSRC3_PS": { 12788 "fields": [ 12789 {"bits": [0, 15], "name": "CU_EN"}, 12790 {"bits": [16, 21], "name": "WAVE_LIMIT"}, 12791 {"bits": [22, 25], "name": "LOCK_LOW_THRESHOLD"}, 12792 {"bits": [26, 29], "name": "SIMD_DISABLE"} 12793 ] 12794 }, 12795 "SPI_SHADER_PGM_RSRC4_GS": { 12796 "fields": [ 12797 {"bits": [0, 6], "name": "GROUP_FIFO_DEPTH"}, 12798 {"bits": [7, 13], "name": "SPI_SHADER_LATE_ALLOC_GS"} 12799 ] 12800 }, 12801 "SPI_SHADER_PGM_RSRC4_HS": { 12802 "fields": [ 12803 {"bits": [0, 6], "name": "GROUP_FIFO_DEPTH"} 12804 ] 12805 }, 12806 "SPI_SHADER_POS_FORMAT": { 12807 "fields": [ 12808 {"bits": [0, 3], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS0_EXPORT_FORMAT"}, 12809 {"bits": [4, 7], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS1_EXPORT_FORMAT"}, 12810 {"bits": [8, 11], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS2_EXPORT_FORMAT"}, 12811 {"bits": [12, 15], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS3_EXPORT_FORMAT"} 12812 ] 12813 }, 12814 "SPI_SHADER_Z_FORMAT": { 12815 "fields": [ 12816 {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "Z_EXPORT_FORMAT"} 12817 ] 12818 }, 12819 "SPI_VS_OUT_CONFIG": { 12820 "fields": [ 12821 {"bits": [1, 5], "name": "VS_EXPORT_COUNT"}, 12822 {"bits": [6, 6], "name": "VS_HALF_PACK"} 12823 ] 12824 }, 12825 "SPI_WAVE_LIMIT_CNTL": { 12826 "fields": [ 12827 {"bits": [0, 1], "name": "PS_WAVE_GRAN"}, 12828 {"bits": [2, 3], "name": "VS_WAVE_GRAN"}, 12829 {"bits": [4, 5], "name": "GS_WAVE_GRAN"}, 12830 {"bits": [6, 7], "name": "HS_WAVE_GRAN"} 12831 ] 12832 }, 12833 "SQC_CACHES": { 12834 "fields": [ 12835 {"bits": [0, 0], "name": "TARGET_INST"}, 12836 {"bits": [1, 1], "name": "TARGET_DATA"}, 12837 {"bits": [2, 2], "name": "INVALIDATE"}, 12838 {"bits": [3, 3], "name": "WRITEBACK"}, 12839 {"bits": [4, 4], "name": "VOL"}, 12840 {"bits": [16, 16], "name": "COMPLETE"} 12841 ] 12842 }, 12843 "SQC_WRITEBACK": { 12844 "fields": [ 12845 {"bits": [0, 0], "name": "DWB"}, 12846 {"bits": [1, 1], "name": "DIRTY"} 12847 ] 12848 }, 12849 "SQ_BUF_RSRC_WORD1": { 12850 "fields": [ 12851 {"bits": [0, 15], "name": "BASE_ADDRESS_HI"}, 12852 {"bits": [16, 29], "name": "STRIDE"}, 12853 {"bits": [30, 30], "name": "CACHE_SWIZZLE"}, 12854 {"bits": [31, 31], "name": "SWIZZLE_ENABLE"} 12855 ] 12856 }, 12857 "SQ_BUF_RSRC_WORD3": { 12858 "fields": [ 12859 {"bits": [0, 2], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_X"}, 12860 {"bits": [3, 5], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Y"}, 12861 {"bits": [6, 8], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Z"}, 12862 {"bits": [9, 11], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_W"}, 12863 {"bits": [12, 14], "enum_ref": "BUF_NUM_FORMAT", "name": "NUM_FORMAT"}, 12864 {"bits": [15, 18], "enum_ref": "BUF_DATA_FORMAT", "name": "DATA_FORMAT"}, 12865 {"bits": [19, 19], "name": "USER_VM_ENABLE"}, 12866 {"bits": [20, 20], "name": "USER_VM_MODE"}, 12867 {"bits": [21, 22], "name": "INDEX_STRIDE"}, 12868 {"bits": [23, 23], "name": "ADD_TID_ENABLE"}, 12869 {"bits": [27, 27], "name": "NV"}, 12870 {"bits": [30, 31], "enum_ref": "SQ_RSRC_BUF_TYPE", "name": "TYPE"} 12871 ] 12872 }, 12873 "SQ_IMG_RSRC_WORD1": { 12874 "fields": [ 12875 {"bits": [0, 7], "name": "BASE_ADDRESS_HI"}, 12876 {"bits": [8, 19], "name": "MIN_LOD"}, 12877 {"bits": [20, 25], "enum_ref": "IMG_DATA_FORMAT", "name": "DATA_FORMAT"}, 12878 {"bits": [20, 25], "enum_ref": "IMG_DATA_FORMAT_STENCIL", "name": "DATA_FORMAT_STENCIL"}, 12879 {"bits": [26, 29], "enum_ref": "IMG_NUM_FORMAT", "name": "NUM_FORMAT"}, 12880 {"bits": [26, 29], "enum_ref": "IMG_NUM_FORMAT_FMASK", "name": "NUM_FORMAT_FMASK"}, 12881 {"bits": [30, 30], "name": "NV"}, 12882 {"bits": [31, 31], "name": "META_DIRECT"} 12883 ] 12884 }, 12885 "SQ_IMG_RSRC_WORD2": { 12886 "fields": [ 12887 {"bits": [0, 13], "name": "WIDTH"}, 12888 {"bits": [14, 27], "name": "HEIGHT"}, 12889 {"bits": [28, 30], "name": "PERF_MOD"} 12890 ] 12891 }, 12892 "SQ_IMG_RSRC_WORD3": { 12893 "fields": [ 12894 {"bits": [0, 2], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_X"}, 12895 {"bits": [3, 5], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Y"}, 12896 {"bits": [6, 8], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Z"}, 12897 {"bits": [9, 11], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_W"}, 12898 {"bits": [12, 15], "name": "BASE_LEVEL"}, 12899 {"bits": [16, 19], "name": "LAST_LEVEL"}, 12900 {"bits": [20, 24], "name": "SW_MODE"}, 12901 {"bits": [28, 31], "enum_ref": "SQ_RSRC_IMG_TYPE", "name": "TYPE"} 12902 ] 12903 }, 12904 "SQ_IMG_RSRC_WORD4": { 12905 "fields": [ 12906 {"bits": [0, 12], "name": "DEPTH"}, 12907 {"bits": [13, 28], "name": "PITCH"}, 12908 {"bits": [29, 31], "enum_ref": "SQ_IMG_RSRC_WORD4__BC_SWIZZLE", "name": "BC_SWIZZLE"} 12909 ] 12910 }, 12911 "SQ_IMG_RSRC_WORD5": { 12912 "fields": [ 12913 {"bits": [0, 12], "name": "BASE_ARRAY"}, 12914 {"bits": [13, 16], "name": "ARRAY_PITCH"}, 12915 {"bits": [17, 24], "name": "META_DATA_ADDRESS"}, 12916 {"bits": [25, 25], "name": "META_LINEAR"}, 12917 {"bits": [26, 26], "name": "META_PIPE_ALIGNED"}, 12918 {"bits": [27, 27], "name": "META_RB_ALIGNED"}, 12919 {"bits": [28, 31], "name": "MAX_MIP"} 12920 ] 12921 }, 12922 "SQ_IMG_RSRC_WORD6": { 12923 "fields": [ 12924 {"bits": [0, 11], "name": "MIN_LOD_WARN"}, 12925 {"bits": [12, 19], "name": "COUNTER_BANK_ID"}, 12926 {"bits": [20, 20], "name": "LOD_HDW_CNT_EN"}, 12927 {"bits": [21, 21], "name": "COMPRESSION_EN"}, 12928 {"bits": [22, 22], "name": "ALPHA_IS_ON_MSB"}, 12929 {"bits": [23, 23], "name": "COLOR_TRANSFORM"}, 12930 {"bits": [24, 27], "name": "LOST_ALPHA_BITS"}, 12931 {"bits": [28, 31], "name": "LOST_COLOR_BITS"} 12932 ] 12933 }, 12934 "SQ_IMG_SAMP_WORD0": { 12935 "fields": [ 12936 {"bits": [0, 2], "enum_ref": "SQ_TEX_CLAMP", "name": "CLAMP_X"}, 12937 {"bits": [3, 5], "enum_ref": "SQ_TEX_CLAMP", "name": "CLAMP_Y"}, 12938 {"bits": [6, 8], "enum_ref": "SQ_TEX_CLAMP", "name": "CLAMP_Z"}, 12939 {"bits": [9, 11], "name": "MAX_ANISO_RATIO"}, 12940 {"bits": [12, 14], "enum_ref": "SQ_TEX_DEPTH_COMPARE", "name": "DEPTH_COMPARE_FUNC"}, 12941 {"bits": [15, 15], "name": "FORCE_UNNORMALIZED"}, 12942 {"bits": [16, 18], "name": "ANISO_THRESHOLD"}, 12943 {"bits": [19, 19], "name": "MC_COORD_TRUNC"}, 12944 {"bits": [20, 20], "name": "FORCE_DEGAMMA"}, 12945 {"bits": [21, 26], "name": "ANISO_BIAS"}, 12946 {"bits": [27, 27], "name": "TRUNC_COORD"}, 12947 {"bits": [28, 28], "name": "DISABLE_CUBE_WRAP"}, 12948 {"bits": [29, 30], "enum_ref": "SQ_IMG_FILTER_TYPE", "name": "FILTER_MODE"}, 12949 {"bits": [31, 31], "name": "COMPAT_MODE"} 12950 ] 12951 }, 12952 "SQ_IMG_SAMP_WORD1": { 12953 "fields": [ 12954 {"bits": [0, 11], "name": "MIN_LOD"}, 12955 {"bits": [12, 23], "name": "MAX_LOD"}, 12956 {"bits": [24, 27], "name": "PERF_MIP"}, 12957 {"bits": [28, 31], "name": "PERF_Z"} 12958 ] 12959 }, 12960 "SQ_IMG_SAMP_WORD2": { 12961 "fields": [ 12962 {"bits": [0, 13], "name": "LOD_BIAS"}, 12963 {"bits": [14, 19], "name": "LOD_BIAS_SEC"}, 12964 {"bits": [20, 21], "enum_ref": "SQ_TEX_XY_FILTER", "name": "XY_MAG_FILTER"}, 12965 {"bits": [22, 23], "enum_ref": "SQ_TEX_XY_FILTER", "name": "XY_MIN_FILTER"}, 12966 {"bits": [24, 25], "enum_ref": "SQ_TEX_Z_FILTER", "name": "Z_FILTER"}, 12967 {"bits": [26, 27], "enum_ref": "SQ_TEX_MIP_FILTER", "name": "MIP_FILTER"}, 12968 {"bits": [28, 28], "name": "MIP_POINT_PRECLAMP"}, 12969 {"bits": [29, 29], "name": "BLEND_ZERO_PRT"}, 12970 {"bits": [30, 30], "name": "FILTER_PREC_FIX"}, 12971 {"bits": [31, 31], "name": "ANISO_OVERRIDE"} 12972 ] 12973 }, 12974 "SQ_IMG_SAMP_WORD3": { 12975 "fields": [ 12976 {"bits": [0, 11], "name": "BORDER_COLOR_PTR"}, 12977 {"bits": [12, 12], "name": "SKIP_DEGAMMA"}, 12978 {"bits": [30, 31], "enum_ref": "SQ_TEX_BORDER_COLOR", "name": "BORDER_COLOR_TYPE"} 12979 ] 12980 }, 12981 "SQ_PERFCOUNTER0_SELECT": { 12982 "fields": [ 12983 {"bits": [0, 8], "name": "PERF_SEL"}, 12984 {"bits": [12, 15], "name": "SQC_BANK_MASK"}, 12985 {"bits": [16, 19], "name": "SQC_CLIENT_MASK"}, 12986 {"bits": [20, 23], "name": "SPM_MODE"}, 12987 {"bits": [24, 27], "name": "SIMD_MASK"}, 12988 {"bits": [28, 31], "name": "PERF_MODE"} 12989 ] 12990 }, 12991 "SQ_PERFCOUNTER_CTRL": { 12992 "fields": [ 12993 {"bits": [0, 0], "name": "PS_EN"}, 12994 {"bits": [1, 1], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"}, 12995 {"bits": [2, 2], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"}, 12996 {"bits": [3, 3], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"}, 12997 {"bits": [4, 4], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"}, 12998 {"bits": [5, 5], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"}, 12999 {"bits": [6, 6], "name": "CS_EN"}, 13000 {"bits": [8, 12], "name": "CNTR_RATE"}, 13001 {"bits": [13, 13], "name": "DISABLE_FLUSH"} 13002 ] 13003 }, 13004 "SQ_PERFCOUNTER_CTRL2": { 13005 "fields": [ 13006 {"bits": [0, 0], "name": "FORCE_EN"} 13007 ] 13008 }, 13009 "SQ_THREAD_TRACE_BASE2": { 13010 "fields": [ 13011 {"bits": [0, 3], "name": "ADDR_HI"} 13012 ] 13013 }, 13014 "SQ_THREAD_TRACE_CTRL": { 13015 "fields": [ 13016 {"bits": [31, 31], "name": "RESET_BUFFER"} 13017 ] 13018 }, 13019 "SQ_THREAD_TRACE_HIWATER": { 13020 "fields": [ 13021 {"bits": [0, 2], "name": "HIWATER"} 13022 ] 13023 }, 13024 "SQ_THREAD_TRACE_MASK": { 13025 "fields": [ 13026 {"bits": [0, 4], "name": "CU_SEL"}, 13027 {"bits": [5, 5], "name": "SH_SEL"}, 13028 {"bits": [7, 7], "name": "REG_STALL_EN"}, 13029 {"bits": [8, 11], "name": "SIMD_EN"}, 13030 {"bits": [12, 13], "name": "VM_ID_MASK"}, 13031 {"bits": [14, 14], "name": "SPI_STALL_EN"}, 13032 {"bits": [15, 15], "name": "SQ_STALL_EN"} 13033 ] 13034 }, 13035 "SQ_THREAD_TRACE_MODE": { 13036 "fields": [ 13037 {"bits": [0, 2], "name": "MASK_PS"}, 13038 {"bits": [3, 5], "name": "MASK_VS"}, 13039 {"bits": [6, 8], "name": "MASK_GS"}, 13040 {"bits": [9, 11], "name": "MASK_ES"}, 13041 {"bits": [12, 14], "name": "MASK_HS"}, 13042 {"bits": [15, 17], "name": "MASK_LS"}, 13043 {"bits": [18, 20], "name": "MASK_CS"}, 13044 {"bits": [21, 22], "name": "MODE"}, 13045 {"bits": [23, 24], "name": "CAPTURE_MODE"}, 13046 {"bits": [25, 25], "name": "AUTOFLUSH_EN"}, 13047 {"bits": [26, 26], "name": "TC_PERF_EN"}, 13048 {"bits": [27, 28], "name": "ISSUE_MASK"}, 13049 {"bits": [29, 29], "name": "TEST_MODE"}, 13050 {"bits": [30, 30], "name": "INTERRUPT_EN"}, 13051 {"bits": [31, 31], "name": "WRAP"} 13052 ] 13053 }, 13054 "SQ_THREAD_TRACE_PERF_MASK": { 13055 "fields": [ 13056 {"bits": [0, 15], "name": "SH0_MASK"}, 13057 {"bits": [16, 31], "name": "SH1_MASK"} 13058 ] 13059 }, 13060 "SQ_THREAD_TRACE_SIZE": { 13061 "fields": [ 13062 {"bits": [0, 21], "name": "SIZE"} 13063 ] 13064 }, 13065 "SQ_THREAD_TRACE_STATUS": { 13066 "fields": [ 13067 {"bits": [0, 9], "name": "FINISH_PENDING"}, 13068 {"bits": [16, 25], "name": "FINISH_DONE"}, 13069 {"bits": [28, 28], "name": "UTC_ERROR"}, 13070 {"bits": [29, 29], "name": "NEW_BUF"}, 13071 {"bits": [30, 30], "name": "BUSY"}, 13072 {"bits": [31, 31], "name": "FULL"} 13073 ] 13074 }, 13075 "SQ_THREAD_TRACE_TOKEN_MASK": { 13076 "fields": [ 13077 {"bits": [0, 15], "name": "TOKEN_MASK"}, 13078 {"bits": [16, 23], "name": "REG_MASK"}, 13079 {"bits": [24, 24], "name": "REG_DROP_ON_STALL"} 13080 ] 13081 }, 13082 "SQ_THREAD_TRACE_WPTR": { 13083 "fields": [ 13084 {"bits": [0, 29], "name": "WPTR"}, 13085 {"bits": [30, 31], "name": "READ_OFFSET"} 13086 ] 13087 }, 13088 "SQ_WAVE_GPR_ALLOC": { 13089 "fields": [ 13090 {"bits": [0, 5], "name": "VGPR_BASE"}, 13091 {"bits": [8, 13], "name": "VGPR_SIZE"}, 13092 {"bits": [16, 21], "name": "SGPR_BASE"}, 13093 {"bits": [24, 27], "name": "SGPR_SIZE"} 13094 ] 13095 }, 13096 "SQ_WAVE_HW_ID": { 13097 "fields": [ 13098 {"bits": [0, 3], "name": "WAVE_ID"}, 13099 {"bits": [4, 5], "name": "SIMD_ID"}, 13100 {"bits": [6, 7], "name": "PIPE_ID"}, 13101 {"bits": [8, 11], "name": "CU_ID"}, 13102 {"bits": [12, 12], "name": "SH_ID"}, 13103 {"bits": [13, 14], "name": "SE_ID"}, 13104 {"bits": [16, 19], "name": "TG_ID"}, 13105 {"bits": [20, 23], "name": "VM_ID"}, 13106 {"bits": [24, 26], "name": "QUEUE_ID"}, 13107 {"bits": [27, 29], "name": "STATE_ID"}, 13108 {"bits": [30, 31], "name": "ME_ID"} 13109 ] 13110 }, 13111 "SQ_WAVE_IB_DBG0": { 13112 "fields": [ 13113 {"bits": [0, 2], "name": "IBUF_ST"}, 13114 {"bits": [3, 3], "name": "PC_INVALID"}, 13115 {"bits": [4, 4], "name": "NEED_NEXT_DW"}, 13116 {"bits": [5, 7], "name": "NO_PREFETCH_CNT"}, 13117 {"bits": [8, 9], "name": "IBUF_RPTR"}, 13118 {"bits": [10, 11], "name": "IBUF_WPTR"}, 13119 {"bits": [16, 19], "name": "INST_STR_ST"}, 13120 {"bits": [24, 25], "name": "ECC_ST"}, 13121 {"bits": [26, 26], "name": "IS_HYB"}, 13122 {"bits": [27, 28], "name": "HYB_CNT"}, 13123 {"bits": [29, 29], "name": "KILL"}, 13124 {"bits": [30, 30], "name": "NEED_KILL_IFETCH"}, 13125 {"bits": [31, 31], "name": "NO_PREFETCH_CNT_HI"} 13126 ] 13127 }, 13128 "SQ_WAVE_IB_DBG1": { 13129 "fields": [ 13130 {"bits": [0, 0], "name": "IXNACK"}, 13131 {"bits": [1, 1], "name": "XNACK"}, 13132 {"bits": [2, 2], "name": "TA_NEED_RESET"}, 13133 {"bits": [4, 8], "name": "XCNT"}, 13134 {"bits": [11, 15], "name": "QCNT"}, 13135 {"bits": [18, 22], "name": "RCNT"}, 13136 {"bits": [25, 31], "name": "MISC_CNT"} 13137 ] 13138 }, 13139 "SQ_WAVE_IB_STS": { 13140 "fields": [ 13141 {"bits": [0, 3], "name": "VM_CNT"}, 13142 {"bits": [4, 6], "name": "EXP_CNT"}, 13143 {"bits": [8, 11], "name": "LGKM_CNT"}, 13144 {"bits": [12, 14], "name": "VALU_CNT"}, 13145 {"bits": [15, 15], "name": "FIRST_REPLAY"}, 13146 {"bits": [16, 20], "name": "RCNT"}, 13147 {"bits": [22, 23], "name": "VM_CNT_HI"} 13148 ] 13149 }, 13150 "SQ_WAVE_LDS_ALLOC": { 13151 "fields": [ 13152 {"bits": [0, 7], "name": "LDS_BASE"}, 13153 {"bits": [12, 20], "name": "LDS_SIZE"} 13154 ] 13155 }, 13156 "SQ_WAVE_MODE": { 13157 "fields": [ 13158 {"bits": [0, 3], "name": "FP_ROUND"}, 13159 {"bits": [4, 7], "name": "FP_DENORM"}, 13160 {"bits": [8, 8], "name": "DX10_CLAMP"}, 13161 {"bits": [9, 9], "name": "IEEE"}, 13162 {"bits": [10, 10], "name": "LOD_CLAMPED"}, 13163 {"bits": [11, 11], "name": "DEBUG_EN"}, 13164 {"bits": [12, 20], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, 13165 {"bits": [23, 23], "name": "FP16_OVFL"}, 13166 {"bits": [24, 24], "name": "POPS_PACKER0"}, 13167 {"bits": [25, 25], "name": "POPS_PACKER1"}, 13168 {"bits": [26, 26], "name": "DISABLE_PERF"}, 13169 {"bits": [27, 27], "name": "GPR_IDX_EN"}, 13170 {"bits": [28, 28], "name": "VSKIP"}, 13171 {"bits": [29, 31], "name": "CSP"} 13172 ] 13173 }, 13174 "SQ_WAVE_PC_HI": { 13175 "fields": [ 13176 {"bits": [0, 15], "name": "PC_HI"} 13177 ] 13178 }, 13179 "SQ_WAVE_STATUS": { 13180 "fields": [ 13181 {"bits": [0, 0], "name": "SCC"}, 13182 {"bits": [1, 2], "name": "SPI_PRIO"}, 13183 {"bits": [3, 4], "name": "USER_PRIO"}, 13184 {"bits": [5, 5], "name": "PRIV"}, 13185 {"bits": [6, 6], "name": "TRAP_EN"}, 13186 {"bits": [7, 7], "name": "TTRACE_EN"}, 13187 {"bits": [8, 8], "name": "EXPORT_RDY"}, 13188 {"bits": [9, 9], "name": "EXECZ"}, 13189 {"bits": [10, 10], "name": "VCCZ"}, 13190 {"bits": [11, 11], "name": "IN_TG"}, 13191 {"bits": [12, 12], "name": "IN_BARRIER"}, 13192 {"bits": [13, 13], "name": "HALT"}, 13193 {"bits": [14, 14], "name": "TRAP"}, 13194 {"bits": [15, 15], "name": "TTRACE_CU_EN"}, 13195 {"bits": [16, 16], "name": "VALID"}, 13196 {"bits": [17, 17], "name": "ECC_ERR"}, 13197 {"bits": [18, 18], "name": "SKIP_EXPORT"}, 13198 {"bits": [19, 19], "name": "PERF_EN"}, 13199 {"bits": [20, 20], "name": "COND_DBG_USER"}, 13200 {"bits": [21, 21], "name": "COND_DBG_SYS"}, 13201 {"bits": [22, 22], "name": "ALLOW_REPLAY"}, 13202 {"bits": [23, 23], "name": "FATAL_HALT"}, 13203 {"bits": [27, 27], "name": "MUST_EXPORT"} 13204 ] 13205 }, 13206 "SQ_WAVE_TRAPSTS": { 13207 "fields": [ 13208 {"bits": [0, 8], "enum_ref": "EXCP_EN", "name": "EXCP"}, 13209 {"bits": [10, 10], "name": "SAVECTX"}, 13210 {"bits": [11, 11], "name": "ILLEGAL_INST"}, 13211 {"bits": [12, 14], "name": "EXCP_HI"}, 13212 {"bits": [16, 21], "name": "EXCP_CYCLE"}, 13213 {"bits": [28, 28], "name": "XNACK_ERROR"}, 13214 {"bits": [29, 31], "name": "DP_RATE"} 13215 ] 13216 }, 13217 "SX_BLEND_OPT_CONTROL": { 13218 "fields": [ 13219 {"bits": [0, 0], "name": "MRT0_COLOR_OPT_DISABLE"}, 13220 {"bits": [1, 1], "name": "MRT0_ALPHA_OPT_DISABLE"}, 13221 {"bits": [4, 4], "name": "MRT1_COLOR_OPT_DISABLE"}, 13222 {"bits": [5, 5], "name": "MRT1_ALPHA_OPT_DISABLE"}, 13223 {"bits": [8, 8], "name": "MRT2_COLOR_OPT_DISABLE"}, 13224 {"bits": [9, 9], "name": "MRT2_ALPHA_OPT_DISABLE"}, 13225 {"bits": [12, 12], "name": "MRT3_COLOR_OPT_DISABLE"}, 13226 {"bits": [13, 13], "name": "MRT3_ALPHA_OPT_DISABLE"}, 13227 {"bits": [16, 16], "name": "MRT4_COLOR_OPT_DISABLE"}, 13228 {"bits": [17, 17], "name": "MRT4_ALPHA_OPT_DISABLE"}, 13229 {"bits": [20, 20], "name": "MRT5_COLOR_OPT_DISABLE"}, 13230 {"bits": [21, 21], "name": "MRT5_ALPHA_OPT_DISABLE"}, 13231 {"bits": [24, 24], "name": "MRT6_COLOR_OPT_DISABLE"}, 13232 {"bits": [25, 25], "name": "MRT6_ALPHA_OPT_DISABLE"}, 13233 {"bits": [28, 28], "name": "MRT7_COLOR_OPT_DISABLE"}, 13234 {"bits": [29, 29], "name": "MRT7_ALPHA_OPT_DISABLE"}, 13235 {"bits": [31, 31], "name": "PIXEN_ZERO_OPT_DISABLE"} 13236 ] 13237 }, 13238 "SX_BLEND_OPT_EPSILON": { 13239 "fields": [ 13240 {"bits": [0, 3], "enum_ref": "SX_BLEND_OPT_EPSILON__MRT0_EPSILON", "name": "MRT0_EPSILON"}, 13241 {"bits": [4, 7], "name": "MRT1_EPSILON"}, 13242 {"bits": [8, 11], "name": "MRT2_EPSILON"}, 13243 {"bits": [12, 15], "name": "MRT3_EPSILON"}, 13244 {"bits": [16, 19], "name": "MRT4_EPSILON"}, 13245 {"bits": [20, 23], "name": "MRT5_EPSILON"}, 13246 {"bits": [24, 27], "name": "MRT6_EPSILON"}, 13247 {"bits": [28, 31], "name": "MRT7_EPSILON"} 13248 ] 13249 }, 13250 "SX_MRT0_BLEND_OPT": { 13251 "fields": [ 13252 {"bits": [0, 2], "enum_ref": "SX_BLEND_OPT", "name": "COLOR_SRC_OPT"}, 13253 {"bits": [4, 6], "enum_ref": "SX_BLEND_OPT", "name": "COLOR_DST_OPT"}, 13254 {"bits": [8, 10], "enum_ref": "SX_OPT_COMB_FCN", "name": "COLOR_COMB_FCN"}, 13255 {"bits": [16, 18], "enum_ref": "SX_BLEND_OPT", "name": "ALPHA_SRC_OPT"}, 13256 {"bits": [20, 22], "enum_ref": "SX_BLEND_OPT", "name": "ALPHA_DST_OPT"}, 13257 {"bits": [24, 26], "enum_ref": "SX_OPT_COMB_FCN", "name": "ALPHA_COMB_FCN"} 13258 ] 13259 }, 13260 "SX_PS_DOWNCONVERT": { 13261 "fields": [ 13262 {"bits": [0, 3], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT0"}, 13263 {"bits": [4, 7], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT1"}, 13264 {"bits": [8, 11], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT2"}, 13265 {"bits": [12, 15], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT3"}, 13266 {"bits": [16, 19], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT4"}, 13267 {"bits": [20, 23], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT5"}, 13268 {"bits": [24, 27], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT6"}, 13269 {"bits": [28, 31], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT7"} 13270 ] 13271 }, 13272 "TA_BC_BASE_ADDR_HI": { 13273 "fields": [ 13274 {"bits": [0, 7], "name": "ADDRESS"} 13275 ] 13276 }, 13277 "TA_PERFCOUNTER0_SELECT": { 13278 "fields": [ 13279 {"bits": [0, 7], "name": "PERF_SEL"}, 13280 {"bits": [10, 17], "name": "PERF_SEL1"}, 13281 {"bits": [20, 23], "name": "CNTR_MODE"}, 13282 {"bits": [24, 27], "name": "PERF_MODE1"}, 13283 {"bits": [28, 31], "name": "PERF_MODE"} 13284 ] 13285 }, 13286 "TA_PERFCOUNTER0_SELECT1": { 13287 "fields": [ 13288 {"bits": [0, 7], "name": "PERF_SEL2"}, 13289 {"bits": [10, 17], "name": "PERF_SEL3"}, 13290 {"bits": [24, 27], "name": "PERF_MODE3"}, 13291 {"bits": [28, 31], "name": "PERF_MODE2"} 13292 ] 13293 }, 13294 "TA_PERFCOUNTER1_SELECT": { 13295 "fields": [ 13296 {"bits": [0, 7], "name": "PERF_SEL"}, 13297 {"bits": [20, 23], "name": "CNTR_MODE"}, 13298 {"bits": [28, 31], "name": "PERF_MODE"} 13299 ] 13300 }, 13301 "TCC_PERFCOUNTER0_SELECT1": { 13302 "fields": [ 13303 {"bits": [0, 9], "name": "PERF_SEL2"}, 13304 {"bits": [10, 19], "name": "PERF_SEL3"}, 13305 {"bits": [24, 27], "name": "PERF_MODE2"}, 13306 {"bits": [28, 31], "name": "PERF_MODE3"} 13307 ] 13308 }, 13309 "VGT_DMA_BASE_HI": { 13310 "fields": [ 13311 {"bits": [0, 15], "name": "BASE_ADDR"} 13312 ] 13313 }, 13314 "VGT_DMA_INDEX_TYPE": { 13315 "fields": [ 13316 {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"}, 13317 {"bits": [2, 3], "enum_ref": "VGT_DMA_SWAP_MODE", "name": "SWAP_MODE"}, 13318 {"bits": [4, 5], "enum_ref": "VGT_DMA_BUF_TYPE", "name": "BUF_TYPE"}, 13319 {"bits": [6, 6], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"}, 13320 {"bits": [8, 8], "name": "PRIMGEN_EN"}, 13321 {"bits": [9, 9], "name": "NOT_EOP"}, 13322 {"bits": [10, 10], "name": "REQ_PATH"} 13323 ] 13324 }, 13325 "VGT_DRAW_INITIATOR": { 13326 "fields": [ 13327 {"bits": [0, 1], "enum_ref": "VGT_DI_SOURCE_SELECT", "name": "SOURCE_SELECT"}, 13328 {"bits": [2, 3], "enum_ref": "VGT_DI_MAJOR_MODE_SELECT", "name": "MAJOR_MODE"}, 13329 {"bits": [4, 4], "name": "SPRITE_EN_R6XX"}, 13330 {"bits": [5, 5], "name": "NOT_EOP"}, 13331 {"bits": [6, 6], "name": "USE_OPAQUE"}, 13332 {"bits": [7, 7], "name": "UNROLLED_INST"}, 13333 {"bits": [8, 8], "name": "GRBM_SKEW_NO_DEC"}, 13334 {"bits": [29, 31], "name": "REG_RT_INDEX"} 13335 ] 13336 }, 13337 "VGT_DRAW_PAYLOAD_CNTL": { 13338 "fields": [ 13339 {"bits": [0, 0], "name": "OBJPRIM_ID_EN"}, 13340 {"bits": [1, 1], "name": "EN_REG_RT_INDEX"}, 13341 {"bits": [2, 2], "name": "EN_PIPELINE_PRIMID"}, 13342 {"bits": [3, 3], "name": "OBJECT_ID_INST_EN"} 13343 ] 13344 }, 13345 "VGT_ESGS_RING_ITEMSIZE": { 13346 "fields": [ 13347 {"bits": [0, 14], "name": "ITEMSIZE"} 13348 ] 13349 }, 13350 "VGT_ES_PER_GS": { 13351 "fields": [ 13352 {"bits": [0, 10], "name": "ES_PER_GS"} 13353 ] 13354 }, 13355 "VGT_EVENT_ADDRESS_REG": { 13356 "fields": [ 13357 {"bits": [0, 27], "name": "ADDRESS_LOW"} 13358 ] 13359 }, 13360 "VGT_EVENT_INITIATOR": { 13361 "fields": [ 13362 {"bits": [0, 5], "enum_ref": "VGT_EVENT_TYPE", "name": "EVENT_TYPE"}, 13363 {"bits": [10, 26], "name": "ADDRESS_HI"}, 13364 {"bits": [27, 27], "name": "EXTENDED_EVENT"} 13365 ] 13366 }, 13367 "VGT_GROUP_DECR": { 13368 "fields": [ 13369 {"bits": [0, 3], "name": "DECR"} 13370 ] 13371 }, 13372 "VGT_GROUP_FIRST_DECR": { 13373 "fields": [ 13374 {"bits": [0, 3], "name": "FIRST_DECR"} 13375 ] 13376 }, 13377 "VGT_GROUP_PRIM_TYPE": { 13378 "fields": [ 13379 {"bits": [0, 4], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"}, 13380 {"bits": [14, 14], "name": "RETAIN_ORDER"}, 13381 {"bits": [15, 15], "name": "RETAIN_QUADS"}, 13382 {"bits": [16, 18], "name": "PRIM_ORDER"} 13383 ] 13384 }, 13385 "VGT_GROUP_VECT_0_CNTL": { 13386 "fields": [ 13387 {"bits": [0, 0], "name": "COMP_X_EN"}, 13388 {"bits": [1, 1], "name": "COMP_Y_EN"}, 13389 {"bits": [2, 2], "name": "COMP_Z_EN"}, 13390 {"bits": [3, 3], "name": "COMP_W_EN"}, 13391 {"bits": [8, 15], "name": "STRIDE"}, 13392 {"bits": [16, 23], "name": "SHIFT"} 13393 ] 13394 }, 13395 "VGT_GROUP_VECT_0_FMT_CNTL": { 13396 "fields": [ 13397 {"bits": [0, 3], "name": "X_CONV"}, 13398 {"bits": [4, 7], "name": "X_OFFSET"}, 13399 {"bits": [8, 11], "name": "Y_CONV"}, 13400 {"bits": [12, 15], "name": "Y_OFFSET"}, 13401 {"bits": [16, 19], "name": "Z_CONV"}, 13402 {"bits": [20, 23], "name": "Z_OFFSET"}, 13403 {"bits": [24, 27], "name": "W_CONV"}, 13404 {"bits": [28, 31], "name": "W_OFFSET"} 13405 ] 13406 }, 13407 "VGT_GSVS_RING_OFFSET_1": { 13408 "fields": [ 13409 {"bits": [0, 14], "name": "OFFSET"} 13410 ] 13411 }, 13412 "VGT_GS_INSTANCE_CNT": { 13413 "fields": [ 13414 {"bits": [0, 0], "name": "ENABLE"}, 13415 {"bits": [2, 8], "name": "CNT"} 13416 ] 13417 }, 13418 "VGT_GS_MAX_PRIMS_PER_SUBGROUP": { 13419 "fields": [ 13420 {"bits": [0, 15], "name": "MAX_PRIMS_PER_SUBGROUP"} 13421 ] 13422 }, 13423 "VGT_GS_MAX_VERT_OUT": { 13424 "fields": [ 13425 {"bits": [0, 10], "name": "MAX_VERT_OUT"} 13426 ] 13427 }, 13428 "VGT_GS_MODE": { 13429 "fields": [ 13430 {"bits": [0, 2], "enum_ref": "VGT_GS_MODE_TYPE", "name": "MODE"}, 13431 {"bits": [3, 3], "name": "RESERVED_0"}, 13432 {"bits": [4, 5], "enum_ref": "VGT_GS_CUT_MODE", "name": "CUT_MODE"}, 13433 {"bits": [6, 10], "name": "RESERVED_1"}, 13434 {"bits": [11, 11], "name": "GS_C_PACK_EN"}, 13435 {"bits": [12, 12], "name": "RESERVED_2"}, 13436 {"bits": [13, 13], "name": "ES_PASSTHRU"}, 13437 {"bits": [14, 14], "name": "RESERVED_3"}, 13438 {"bits": [15, 15], "name": "RESERVED_4"}, 13439 {"bits": [16, 16], "name": "RESERVED_5"}, 13440 {"bits": [17, 17], "name": "PARTIAL_THD_AT_EOI"}, 13441 {"bits": [18, 18], "name": "SUPPRESS_CUTS"}, 13442 {"bits": [19, 19], "name": "ES_WRITE_OPTIMIZE"}, 13443 {"bits": [20, 20], "name": "GS_WRITE_OPTIMIZE"}, 13444 {"bits": [21, 22], "name": "ONCHIP"} 13445 ] 13446 }, 13447 "VGT_GS_ONCHIP_CNTL": { 13448 "fields": [ 13449 {"bits": [0, 10], "name": "ES_VERTS_PER_SUBGRP"}, 13450 {"bits": [11, 21], "name": "GS_PRIMS_PER_SUBGRP"}, 13451 {"bits": [22, 31], "name": "GS_INST_PRIMS_IN_SUBGRP"} 13452 ] 13453 }, 13454 "VGT_GS_OUT_PRIM_TYPE": { 13455 "fields": [ 13456 {"bits": [0, 5], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE"}, 13457 {"bits": [8, 13], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_1"}, 13458 {"bits": [16, 21], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_2"}, 13459 {"bits": [22, 27], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_3"}, 13460 {"bits": [31, 31], "name": "UNIQUE_TYPE_PER_STREAM"} 13461 ] 13462 }, 13463 "VGT_GS_PER_ES": { 13464 "fields": [ 13465 {"bits": [0, 10], "name": "GS_PER_ES"} 13466 ] 13467 }, 13468 "VGT_GS_PER_VS": { 13469 "fields": [ 13470 {"bits": [0, 3], "name": "GS_PER_VS"} 13471 ] 13472 }, 13473 "VGT_HOS_CNTL": { 13474 "fields": [ 13475 {"bits": [0, 1], "name": "TESS_MODE"} 13476 ] 13477 }, 13478 "VGT_HOS_REUSE_DEPTH": { 13479 "fields": [ 13480 {"bits": [0, 7], "name": "REUSE_DEPTH"} 13481 ] 13482 }, 13483 "VGT_HS_OFFCHIP_PARAM": { 13484 "fields": [ 13485 {"bits": [0, 8], "name": "OFFCHIP_BUFFERING"}, 13486 {"bits": [9, 10], "enum_ref": "VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY", "name": "OFFCHIP_GRANULARITY"} 13487 ] 13488 }, 13489 "VGT_INDEX_TYPE": { 13490 "fields": [ 13491 {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"}, 13492 {"bits": [8, 8], "name": "PRIMGEN_EN"} 13493 ] 13494 }, 13495 "VGT_LS_HS_CONFIG": { 13496 "fields": [ 13497 {"bits": [0, 7], "name": "NUM_PATCHES"}, 13498 {"bits": [8, 13], "name": "HS_NUM_INPUT_CP"}, 13499 {"bits": [14, 19], "name": "HS_NUM_OUTPUT_CP"} 13500 ] 13501 }, 13502 "VGT_MULTI_PRIM_IB_RESET_EN": { 13503 "fields": [ 13504 {"bits": [0, 0], "name": "RESET_EN"}, 13505 {"bits": [1, 1], "name": "MATCH_ALL_BITS"} 13506 ] 13507 }, 13508 "VGT_OUTPUT_PATH_CNTL": { 13509 "fields": [ 13510 {"bits": [0, 2], "name": "PATH_SELECT"} 13511 ] 13512 }, 13513 "VGT_OUT_DEALLOC_CNTL": { 13514 "fields": [ 13515 {"bits": [0, 6], "name": "DEALLOC_DIST"} 13516 ] 13517 }, 13518 "VGT_PERFCOUNTER_SEID_MASK": { 13519 "fields": [ 13520 {"bits": [0, 7], "name": "PERF_SEID_IGNORE_MASK"} 13521 ] 13522 }, 13523 "VGT_PRIMITIVEID_EN": { 13524 "fields": [ 13525 {"bits": [0, 0], "name": "PRIMITIVEID_EN"}, 13526 {"bits": [1, 1], "name": "DISABLE_RESET_ON_EOI"}, 13527 {"bits": [2, 2], "name": "NGG_DISABLE_PROVOK_REUSE"} 13528 ] 13529 }, 13530 "VGT_PRIMITIVE_TYPE": { 13531 "fields": [ 13532 {"bits": [0, 5], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"} 13533 ] 13534 }, 13535 "VGT_REUSE_OFF": { 13536 "fields": [ 13537 {"bits": [0, 0], "name": "REUSE_OFF"} 13538 ] 13539 }, 13540 "VGT_SHADER_STAGES_EN": { 13541 "fields": [ 13542 {"bits": [0, 1], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"}, 13543 {"bits": [2, 2], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"}, 13544 {"bits": [3, 4], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"}, 13545 {"bits": [5, 5], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"}, 13546 {"bits": [6, 7], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"}, 13547 {"bits": [9, 9], "name": "DISPATCH_DRAW_EN"}, 13548 {"bits": [10, 10], "name": "DIS_DEALLOC_ACCUM_0"}, 13549 {"bits": [11, 11], "name": "DIS_DEALLOC_ACCUM_1"}, 13550 {"bits": [12, 12], "name": "VS_WAVE_ID_EN"}, 13551 {"bits": [13, 13], "name": "PRIMGEN_EN"}, 13552 {"bits": [14, 14], "name": "ORDERED_ID_MODE"}, 13553 {"bits": [15, 18], "name": "MAX_PRIMGRP_IN_WAVE"}, 13554 {"bits": [19, 20], "name": "GS_FAST_LAUNCH"} 13555 ] 13556 }, 13557 "VGT_STRMOUT_BUFFER_CONFIG": { 13558 "fields": [ 13559 {"bits": [0, 3], "name": "STREAM_0_BUFFER_EN"}, 13560 {"bits": [4, 7], "name": "STREAM_1_BUFFER_EN"}, 13561 {"bits": [8, 11], "name": "STREAM_2_BUFFER_EN"}, 13562 {"bits": [12, 15], "name": "STREAM_3_BUFFER_EN"} 13563 ] 13564 }, 13565 "VGT_STRMOUT_CONFIG": { 13566 "fields": [ 13567 {"bits": [0, 0], "name": "STREAMOUT_0_EN"}, 13568 {"bits": [1, 1], "name": "STREAMOUT_1_EN"}, 13569 {"bits": [2, 2], "name": "STREAMOUT_2_EN"}, 13570 {"bits": [3, 3], "name": "STREAMOUT_3_EN"}, 13571 {"bits": [4, 6], "name": "RAST_STREAM"}, 13572 {"bits": [7, 7], "name": "EN_PRIMS_NEEDED_CNT"}, 13573 {"bits": [8, 11], "name": "RAST_STREAM_MASK"}, 13574 {"bits": [31, 31], "name": "USE_RAST_STREAM_MASK"} 13575 ] 13576 }, 13577 "VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE": { 13578 "fields": [ 13579 {"bits": [0, 8], "name": "VERTEX_STRIDE"} 13580 ] 13581 }, 13582 "VGT_STRMOUT_VTX_STRIDE_0": { 13583 "fields": [ 13584 {"bits": [0, 9], "name": "STRIDE"} 13585 ] 13586 }, 13587 "VGT_TESS_DISTRIBUTION": { 13588 "fields": [ 13589 {"bits": [0, 7], "name": "ACCUM_ISOLINE"}, 13590 {"bits": [8, 15], "name": "ACCUM_TRI"}, 13591 {"bits": [16, 23], "name": "ACCUM_QUAD"}, 13592 {"bits": [24, 28], "name": "DONUT_SPLIT"}, 13593 {"bits": [29, 31], "name": "TRAP_SPLIT"} 13594 ] 13595 }, 13596 "VGT_TF_PARAM": { 13597 "fields": [ 13598 {"bits": [0, 1], "enum_ref": "VGT_TESS_TYPE", "name": "TYPE"}, 13599 {"bits": [2, 4], "enum_ref": "VGT_TESS_PARTITION", "name": "PARTITIONING"}, 13600 {"bits": [5, 7], "enum_ref": "VGT_TESS_TOPOLOGY", "name": "TOPOLOGY"}, 13601 {"bits": [8, 8], "name": "RESERVED_REDUC_AXIS"}, 13602 {"bits": [9, 9], "name": "DEPRECATED"}, 13603 {"bits": [14, 14], "name": "DISABLE_DONUTS"}, 13604 {"bits": [15, 15], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"}, 13605 {"bits": [17, 18], "enum_ref": "VGT_DIST_MODE", "name": "DISTRIBUTION_MODE"} 13606 ] 13607 }, 13608 "VGT_TF_RING_SIZE": { 13609 "fields": [ 13610 {"bits": [0, 15], "name": "SIZE"} 13611 ] 13612 }, 13613 "VGT_VERTEX_REUSE_BLOCK_CNTL": { 13614 "fields": [ 13615 {"bits": [0, 7], "name": "VTX_REUSE_DEPTH"} 13616 ] 13617 }, 13618 "VGT_VTX_CNT_EN": { 13619 "fields": [ 13620 {"bits": [0, 0], "name": "VTX_CNT_EN"} 13621 ] 13622 }, 13623 "WD_PERFCOUNTER0_SELECT": { 13624 "fields": [ 13625 {"bits": [0, 7], "name": "PERF_SEL"}, 13626 {"bits": [28, 31], "name": "PERF_MODE"} 13627 ] 13628 } 13629 } 13630} 13631