1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * SPDX-License-Identifier: MIT
9 */
10 #ifndef RADV_ACO_SHADER_INFO_H
11 #define RADV_ACO_SHADER_INFO_H
12
13 /* this will convert from radv shader info to the ACO one. */
14
15 #include "ac_hw_stage.h"
16 #include "aco_shader_info.h"
17
18 #define ASSIGN_FIELD(x) aco_info->x = radv->x
19 #define ASSIGN_FIELD_CP(x) memcpy(&aco_info->x, &radv->x, sizeof(radv->x))
20
21 static inline void radv_aco_convert_ps_epilog_key(struct aco_ps_epilog_info *aco_info,
22 const struct radv_ps_epilog_key *radv,
23 const struct radv_shader_args *radv_args);
24
25 static inline void
radv_aco_convert_shader_info(struct aco_shader_info * aco_info,const struct radv_shader_info * radv,const struct radv_shader_args * radv_args,const struct radv_device_cache_key * radv_key,const enum amd_gfx_level gfx_level)26 radv_aco_convert_shader_info(struct aco_shader_info *aco_info, const struct radv_shader_info *radv,
27 const struct radv_shader_args *radv_args, const struct radv_device_cache_key *radv_key,
28 const enum amd_gfx_level gfx_level)
29 {
30 ASSIGN_FIELD(wave_size);
31 ASSIGN_FIELD(workgroup_size);
32 ASSIGN_FIELD(ps.has_epilog);
33 ASSIGN_FIELD(merged_shader_compiled_separately);
34 ASSIGN_FIELD(vs.tcs_in_out_eq);
35 ASSIGN_FIELD(vs.has_prolog);
36 ASSIGN_FIELD(tcs.num_lds_blocks);
37 ASSIGN_FIELD(ps.num_inputs);
38 ASSIGN_FIELD(cs.uses_full_subgroups);
39 aco_info->vs.any_tcs_inputs_via_lds = radv->vs.tcs_inputs_via_lds != 0;
40 aco_info->ps.spi_ps_input_ena = radv->ps.spi_ps_input_ena;
41 aco_info->ps.spi_ps_input_addr = radv->ps.spi_ps_input_addr;
42 aco_info->ps.has_prolog = false;
43 aco_info->gfx9_gs_ring_lds_size = radv->gs_ring_info.lds_size;
44 aco_info->image_2d_view_of_3d = radv_key->image_2d_view_of_3d;
45 aco_info->epilog_pc = radv_args->epilog_pc;
46 aco_info->hw_stage = radv_select_hw_stage(radv, gfx_level);
47 aco_info->tcs.tcs_offchip_layout = radv_args->tcs_offchip_layout;
48 aco_info->next_stage_pc = radv_args->next_stage_pc;
49 aco_info->schedule_ngg_pos_exports = gfx_level < GFX11 && radv->has_ngg_culling && radv->has_ngg_early_prim_export;
50 }
51
52 static inline void
radv_aco_convert_vs_prolog_key(struct aco_vs_prolog_info * aco_info,const struct radv_vs_prolog_key * radv,const struct radv_shader_args * radv_args)53 radv_aco_convert_vs_prolog_key(struct aco_vs_prolog_info *aco_info, const struct radv_vs_prolog_key *radv,
54 const struct radv_shader_args *radv_args)
55 {
56 ASSIGN_FIELD(instance_rate_inputs);
57 ASSIGN_FIELD(nontrivial_divisors);
58 ASSIGN_FIELD(zero_divisors);
59 ASSIGN_FIELD(post_shuffle);
60 ASSIGN_FIELD(alpha_adjust_lo);
61 ASSIGN_FIELD(alpha_adjust_hi);
62 ASSIGN_FIELD_CP(formats);
63 ASSIGN_FIELD(num_attributes);
64 ASSIGN_FIELD(misaligned_mask);
65 ASSIGN_FIELD(unaligned_mask);
66 ASSIGN_FIELD(is_ngg);
67 ASSIGN_FIELD(next_stage);
68
69 aco_info->inputs = radv_args->prolog_inputs;
70 }
71
72 static inline void
radv_aco_convert_ps_epilog_key(struct aco_ps_epilog_info * aco_info,const struct radv_ps_epilog_key * radv,const struct radv_shader_args * radv_args)73 radv_aco_convert_ps_epilog_key(struct aco_ps_epilog_info *aco_info, const struct radv_ps_epilog_key *radv,
74 const struct radv_shader_args *radv_args)
75 {
76 ASSIGN_FIELD(spi_shader_col_format);
77 ASSIGN_FIELD(color_is_int8);
78 ASSIGN_FIELD(color_is_int10);
79 ASSIGN_FIELD(mrt0_is_dual_src);
80 ASSIGN_FIELD(alpha_to_coverage_via_mrtz);
81 ASSIGN_FIELD(alpha_to_one);
82
83 memcpy(aco_info->colors, radv_args->colors, sizeof(aco_info->colors));
84 memcpy(aco_info->color_map, radv->color_map, sizeof(aco_info->color_map));
85 aco_info->depth = radv_args->depth;
86 aco_info->stencil = radv_args->stencil;
87 aco_info->samplemask = radv_args->sample_mask;
88
89 aco_info->alpha_func = COMPARE_FUNC_ALWAYS;
90 }
91
92 static inline void
radv_aco_convert_opts(struct aco_compiler_options * aco_info,const struct radv_nir_compiler_options * radv,const struct radv_shader_args * radv_args,const struct radv_shader_stage_key * stage_key)93 radv_aco_convert_opts(struct aco_compiler_options *aco_info, const struct radv_nir_compiler_options *radv,
94 const struct radv_shader_args *radv_args, const struct radv_shader_stage_key *stage_key)
95 {
96 ASSIGN_FIELD(dump_ir);
97 ASSIGN_FIELD(dump_preoptir);
98 ASSIGN_FIELD(record_asm);
99 ASSIGN_FIELD(record_ir);
100 ASSIGN_FIELD(record_stats);
101 ASSIGN_FIELD(enable_mrt_output_nan_fixup);
102 ASSIGN_FIELD(wgp_mode);
103 ASSIGN_FIELD(debug.func);
104 ASSIGN_FIELD(debug.private_data);
105 ASSIGN_FIELD(debug.private_data);
106 aco_info->is_opengl = false;
107 aco_info->load_grid_size_from_user_sgpr = radv_args->load_grid_size_from_user_sgpr;
108 aco_info->optimisations_disabled = stage_key->optimisations_disabled;
109 aco_info->gfx_level = radv->info->gfx_level;
110 aco_info->family = radv->info->family;
111 aco_info->address32_hi = radv->info->address32_hi;
112 aco_info->has_ls_vgpr_init_bug = radv->info->has_ls_vgpr_init_bug;
113 }
114 #undef ASSIGN_VS_STATE_FIELD
115 #undef ASSIGN_VS_STATE_FIELD_CP
116 #undef ASSIGN_FIELD
117 #undef ASSIGN_FIELD_CP
118
119 #endif /* RADV_ACO_SHADER_INFO_H */
120