• Home
  • Line#
  • Scopes#
  • Navigate#
  • Raw
  • Download
1 /*
2  * Copyright © 2024 Valve Corporation
3  *
4  * SPDX-License-Identifier: MIT
5  */
6 
7 #ifndef RADV_DGC_H
8 #define RADV_DGC_H
9 
10 #include "compiler/shader_enums.h"
11 
12 #include "radv_constants.h"
13 
14 #include "vk_device_generated_commands.h"
15 
16 struct radv_cmd_buffer;
17 struct radv_device;
18 enum radv_queue_family;
19 
20 struct radv_indirect_command_layout {
21    struct vk_indirect_command_layout vk;
22 
23    uint64_t push_constant_mask;
24    uint32_t push_constant_offsets[MAX_PUSH_CONSTANTS_SIZE / 4];
25    uint64_t sequence_index_mask;
26 
27    VkPipelineLayout pipeline_layout;
28    VkPipeline pipeline;
29 };
30 
31 VK_DEFINE_NONDISP_HANDLE_CASTS(radv_indirect_command_layout, vk.base, VkIndirectCommandsLayoutEXT,
32                                VK_OBJECT_TYPE_INDIRECT_COMMANDS_LAYOUT_EXT)
33 
34 struct radv_indirect_execution_set {
35    struct vk_object_base base;
36 
37    struct radeon_winsys_bo *bo;
38    uint64_t va;
39    uint8_t *mapped_ptr;
40 
41    uint32_t stride;
42 
43    uint32_t compute_scratch_size_per_wave;
44    uint32_t compute_scratch_waves;
45 };
46 
47 VK_DEFINE_NONDISP_HANDLE_CASTS(radv_indirect_execution_set, base, VkIndirectExecutionSetEXT,
48                                VK_OBJECT_TYPE_INDIRECT_EXECUTION_SET_EXT);
49 
50 uint32_t radv_dgc_get_buffer_alignment(const struct radv_device *device);
51 
52 uint32_t radv_get_indirect_main_cmdbuf_offset(const VkGeneratedCommandsInfoEXT *pGeneratedCommandsInfo);
53 uint32_t radv_get_indirect_ace_cmdbuf_offset(const VkGeneratedCommandsInfoEXT *pGeneratedCommandsInfo);
54 
55 uint32_t radv_get_indirect_main_cmdbuf_size(const VkGeneratedCommandsInfoEXT *pGeneratedCommandsInfo);
56 uint32_t radv_get_indirect_ace_cmdbuf_size(const VkGeneratedCommandsInfoEXT *pGeneratedCommandsInfo);
57 
58 uint32_t radv_get_indirect_main_trailer_offset(const VkGeneratedCommandsInfoEXT *pGeneratedCommandsInfo);
59 uint32_t radv_get_indirect_ace_trailer_offset(const VkGeneratedCommandsInfoEXT *pGeneratedCommandsInfo);
60 
61 void radv_prepare_dgc(struct radv_cmd_buffer *cmd_buffer, const VkGeneratedCommandsInfoEXT *pGeneratedCommandsInfo,
62                       struct radv_cmd_buffer *state_cmd_buffer, bool cond_render_enabled);
63 
64 bool radv_use_dgc_predication(struct radv_cmd_buffer *cmd_buffer,
65                               const VkGeneratedCommandsInfoEXT *pGeneratedCommandsInfo);
66 
67 struct radv_shader *radv_dgc_get_shader(const VkGeneratedCommandsPipelineInfoEXT *pipeline_info,
68                                         const VkGeneratedCommandsShaderInfoEXT *eso_info, gl_shader_stage stage);
69 
70 #endif /* RADV_DGC_H */
71