1 /**************************************************************************
2 *
3 * Copyright 2017 Advanced Micro Devices, Inc.
4 * Copyright 2023 Red Hat Inc.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 **************************************************************************/
28 #include "radv_buffer.h"
29 #include "radv_cs.h"
30 #include "radv_debug.h"
31 #include "radv_device_memory.h"
32 #include "radv_entrypoints.h"
33 #include "radv_image_view.h"
34 #include "radv_physical_device.h"
35 #include "radv_query.h"
36 #include "radv_video.h"
37
38 #include "ac_vcn_enc.h"
39
40 #define RENCODE_V4_FW_INTERFACE_MAJOR_VERSION 1
41 #define RENCODE_V4_FW_INTERFACE_MINOR_VERSION 7
42
43 #define RENCODE_V4_IB_PARAM_ENCODE_STATISTICS 0x0000001a
44
45 #define RENCODE_V3_FW_INTERFACE_MAJOR_VERSION 1
46 #define RENCODE_V3_FW_INTERFACE_MINOR_VERSION 27
47
48 #define RENCODE_V2_IB_PARAM_SESSION_INFO 0x00000001
49 #define RENCODE_V2_IB_PARAM_TASK_INFO 0x00000002
50 #define RENCODE_V2_IB_PARAM_SESSION_INIT 0x00000003
51 #define RENCODE_V2_IB_PARAM_LAYER_CONTROL 0x00000004
52 #define RENCODE_V2_IB_PARAM_LAYER_SELECT 0x00000005
53 #define RENCODE_V2_IB_PARAM_RATE_CONTROL_SESSION_INIT 0x00000006
54 #define RENCODE_V2_IB_PARAM_RATE_CONTROL_LAYER_INIT 0x00000007
55 #define RENCODE_V2_IB_PARAM_RATE_CONTROL_PER_PICTURE 0x00000008
56 #define RENCODE_V2_IB_PARAM_QUALITY_PARAMS 0x00000009
57 #define RENCODE_V2_IB_PARAM_DIRECT_OUTPUT_NALU 0x0000000a
58 #define RENCODE_V2_IB_PARAM_SLICE_HEADER 0x0000000b
59 #define RENCODE_V2_IB_PARAM_INPUT_FORMAT 0x0000000c
60 #define RENCODE_V2_IB_PARAM_OUTPUT_FORMAT 0x0000000d
61 #define RENCODE_V2_IB_PARAM_ENCODE_PARAMS 0x0000000f
62 #define RENCODE_V2_IB_PARAM_INTRA_REFRESH 0x00000010
63 #define RENCODE_V2_IB_PARAM_ENCODE_CONTEXT_BUFFER 0x00000011
64 #define RENCODE_V2_IB_PARAM_VIDEO_BITSTREAM_BUFFER 0x00000012
65 #define RENCODE_V2_IB_PARAM_FEEDBACK_BUFFER 0x00000015
66 #define RENCODE_V2_IB_PARAM_ENCODE_STATISTICS 0x00000019
67 #define RENCODE_V2_IB_PARAM_RATE_CONTROL_PER_PIC_EX 0x0000001d
68
69 #define RENCODE_V2_HEVC_IB_PARAM_SLICE_CONTROL 0x00100001
70 #define RENCODE_V2_HEVC_IB_PARAM_SPEC_MISC 0x00100002
71 #define RENCODE_V2_HEVC_IB_PARAM_LOOP_FILTER 0x00100003
72
73 #define RENCODE_V2_H264_IB_PARAM_SLICE_CONTROL 0x00200001
74 #define RENCODE_V2_H264_IB_PARAM_SPEC_MISC 0x00200002
75 #define RENCODE_V2_H264_IB_PARAM_ENCODE_PARAMS 0x00200003
76 #define RENCODE_V2_H264_IB_PARAM_DEBLOCKING_FILTER 0x00200004
77
78 #define RENCODE_V2_FW_INTERFACE_MAJOR_VERSION 1
79 #define RENCODE_V2_FW_INTERFACE_MINOR_VERSION 18
80
81 #define RENCODE_IB_PARAM_SESSION_INFO 0x00000001
82 #define RENCODE_IB_PARAM_TASK_INFO 0x00000002
83 #define RENCODE_IB_PARAM_SESSION_INIT 0x00000003
84 #define RENCODE_IB_PARAM_LAYER_CONTROL 0x00000004
85 #define RENCODE_IB_PARAM_LAYER_SELECT 0x00000005
86 #define RENCODE_IB_PARAM_RATE_CONTROL_SESSION_INIT 0x00000006
87 #define RENCODE_IB_PARAM_RATE_CONTROL_LAYER_INIT 0x00000007
88 #define RENCODE_IB_PARAM_RATE_CONTROL_PER_PICTURE 0x00000008
89 #define RENCODE_IB_PARAM_QUALITY_PARAMS 0x00000009
90 #define RENCODE_IB_PARAM_SLICE_HEADER 0x0000000a
91 #define RENCODE_IB_PARAM_ENCODE_PARAMS 0x0000000b
92 #define RENCODE_IB_PARAM_INTRA_REFRESH 0x0000000c
93 #define RENCODE_IB_PARAM_ENCODE_CONTEXT_BUFFER 0x0000000d
94 #define RENCODE_IB_PARAM_VIDEO_BITSTREAM_BUFFER 0x0000000e
95 #define RENCODE_IB_PARAM_FEEDBACK_BUFFER 0x00000010
96 #define RENCODE_IB_PARAM_RATE_CONTROL_PER_PIC_EX 0x0000001d
97 #define RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU 0x00000020
98 #define RENCODE_IB_PARAM_ENCODE_STATISTICS 0x00000024
99
100 #define RENCODE_HEVC_IB_PARAM_SLICE_CONTROL 0x00100001
101 #define RENCODE_HEVC_IB_PARAM_SPEC_MISC 0x00100002
102 #define RENCODE_HEVC_IB_PARAM_DEBLOCKING_FILTER 0x00100003
103
104 #define RENCODE_H264_IB_PARAM_SLICE_CONTROL 0x00200001
105 #define RENCODE_H264_IB_PARAM_SPEC_MISC 0x00200002
106 #define RENCODE_H264_IB_PARAM_ENCODE_PARAMS 0x00200003
107 #define RENCODE_H264_IB_PARAM_DEBLOCKING_FILTER 0x00200004
108
109 #define RENCODE_FW_INTERFACE_MAJOR_VERSION 1
110 #define RENCODE_FW_INTERFACE_MINOR_VERSION 15
111
112 void
radv_probe_video_encode(struct radv_physical_device * pdev)113 radv_probe_video_encode(struct radv_physical_device *pdev)
114 {
115 pdev->video_encode_enabled = false;
116
117 /* TODO: Add VCN 5.0+. */
118 if (pdev->info.vcn_ip_version >= VCN_5_0_0)
119 return;
120
121 if (pdev->info.vcn_ip_version >= VCN_4_0_0) {
122 if (pdev->info.vcn_enc_major_version != RENCODE_V4_FW_INTERFACE_MAJOR_VERSION)
123 return;
124 if (pdev->info.vcn_enc_minor_version < RENCODE_V4_FW_INTERFACE_MINOR_VERSION)
125 return;
126
127 /* VCN 4 FW 1.22 has all the necessary pieces to pass CTS */
128 if (pdev->info.vcn_enc_minor_version >= 22) {
129 pdev->video_encode_enabled = true;
130 return;
131 }
132 } else if (pdev->info.vcn_ip_version >= VCN_3_0_0) {
133 if (pdev->info.vcn_enc_major_version != RENCODE_V3_FW_INTERFACE_MAJOR_VERSION)
134 return;
135 if (pdev->info.vcn_enc_minor_version < RENCODE_V3_FW_INTERFACE_MINOR_VERSION)
136 return;
137
138 /* VCN 3 FW 1.33 has all the necessary pieces to pass CTS */
139 if (pdev->info.vcn_enc_minor_version >= 33) {
140 pdev->video_encode_enabled = true;
141 return;
142 }
143 } else if (pdev->info.vcn_ip_version >= VCN_2_0_0) {
144 if (pdev->info.vcn_enc_major_version != RENCODE_V2_FW_INTERFACE_MAJOR_VERSION)
145 return;
146 if (pdev->info.vcn_enc_minor_version < RENCODE_V2_FW_INTERFACE_MINOR_VERSION)
147 return;
148
149 /* VCN 2 FW 1.24 has all the necessary pieces to pass CTS */
150 if (pdev->info.vcn_enc_minor_version >= 24) {
151 pdev->video_encode_enabled = true;
152 return;
153 }
154 } else {
155 if (pdev->info.vcn_enc_major_version != RENCODE_FW_INTERFACE_MAJOR_VERSION)
156 return;
157 if (pdev->info.vcn_enc_minor_version < RENCODE_FW_INTERFACE_MINOR_VERSION)
158 return;
159 }
160
161 struct radv_instance *instance = radv_physical_device_instance(pdev);
162 pdev->video_encode_enabled = !!(instance->perftest_flags & RADV_PERFTEST_VIDEO_ENCODE);
163 }
164
165 void
radv_init_physical_device_encoder(struct radv_physical_device * pdev)166 radv_init_physical_device_encoder(struct radv_physical_device *pdev)
167 {
168 if (pdev->info.vcn_ip_version >= VCN_4_0_0) {
169 pdev->enc_hw_ver = RADV_VIDEO_ENC_HW_4;
170 pdev->encoder_interface_version = ((RENCODE_V4_FW_INTERFACE_MAJOR_VERSION << RENCODE_IF_MAJOR_VERSION_SHIFT) |
171 (RENCODE_V4_FW_INTERFACE_MINOR_VERSION << RENCODE_IF_MINOR_VERSION_SHIFT));
172 } else if (pdev->info.vcn_ip_version >= VCN_3_0_0) {
173 pdev->enc_hw_ver = RADV_VIDEO_ENC_HW_3;
174 pdev->encoder_interface_version = ((RENCODE_V3_FW_INTERFACE_MAJOR_VERSION << RENCODE_IF_MAJOR_VERSION_SHIFT) |
175 (RENCODE_V3_FW_INTERFACE_MINOR_VERSION << RENCODE_IF_MINOR_VERSION_SHIFT));
176 } else if (pdev->info.vcn_ip_version >= VCN_2_0_0) {
177 pdev->enc_hw_ver = RADV_VIDEO_ENC_HW_2;
178 pdev->encoder_interface_version = ((RENCODE_V2_FW_INTERFACE_MAJOR_VERSION << RENCODE_IF_MAJOR_VERSION_SHIFT) |
179 (RENCODE_V2_FW_INTERFACE_MINOR_VERSION << RENCODE_IF_MINOR_VERSION_SHIFT));
180 } else {
181 pdev->enc_hw_ver = RADV_VIDEO_ENC_HW_1_2;
182 pdev->encoder_interface_version = ((RENCODE_FW_INTERFACE_MAJOR_VERSION << RENCODE_IF_MAJOR_VERSION_SHIFT) |
183 (RENCODE_FW_INTERFACE_MINOR_VERSION << RENCODE_IF_MINOR_VERSION_SHIFT));
184 }
185
186 if (pdev->info.vcn_ip_version >= VCN_2_0_0) {
187 pdev->vcn_enc_cmds.session_info = RENCODE_V2_IB_PARAM_SESSION_INFO;
188 pdev->vcn_enc_cmds.task_info = RENCODE_V2_IB_PARAM_TASK_INFO;
189 pdev->vcn_enc_cmds.session_init = RENCODE_V2_IB_PARAM_SESSION_INIT;
190 pdev->vcn_enc_cmds.layer_control = RENCODE_V2_IB_PARAM_LAYER_CONTROL;
191 pdev->vcn_enc_cmds.layer_select = RENCODE_V2_IB_PARAM_LAYER_SELECT;
192 pdev->vcn_enc_cmds.rc_session_init = RENCODE_V2_IB_PARAM_RATE_CONTROL_SESSION_INIT;
193 pdev->vcn_enc_cmds.rc_layer_init = RENCODE_V2_IB_PARAM_RATE_CONTROL_LAYER_INIT;
194 pdev->vcn_enc_cmds.rc_per_pic = RENCODE_V2_IB_PARAM_RATE_CONTROL_PER_PIC_EX;
195 pdev->vcn_enc_cmds.quality_params = RENCODE_V2_IB_PARAM_QUALITY_PARAMS;
196 pdev->vcn_enc_cmds.nalu = RENCODE_V2_IB_PARAM_DIRECT_OUTPUT_NALU;
197 pdev->vcn_enc_cmds.slice_header = RENCODE_V2_IB_PARAM_SLICE_HEADER;
198 pdev->vcn_enc_cmds.input_format = RENCODE_V2_IB_PARAM_INPUT_FORMAT;
199 pdev->vcn_enc_cmds.output_format = RENCODE_V2_IB_PARAM_OUTPUT_FORMAT;
200 pdev->vcn_enc_cmds.enc_params = RENCODE_V2_IB_PARAM_ENCODE_PARAMS;
201 pdev->vcn_enc_cmds.intra_refresh = RENCODE_V2_IB_PARAM_INTRA_REFRESH;
202 pdev->vcn_enc_cmds.ctx = RENCODE_V2_IB_PARAM_ENCODE_CONTEXT_BUFFER;
203 pdev->vcn_enc_cmds.bitstream = RENCODE_V2_IB_PARAM_VIDEO_BITSTREAM_BUFFER;
204 pdev->vcn_enc_cmds.feedback = RENCODE_V2_IB_PARAM_FEEDBACK_BUFFER;
205 pdev->vcn_enc_cmds.slice_control_hevc = RENCODE_V2_HEVC_IB_PARAM_SLICE_CONTROL;
206 pdev->vcn_enc_cmds.spec_misc_hevc = RENCODE_V2_HEVC_IB_PARAM_SPEC_MISC;
207 pdev->vcn_enc_cmds.deblocking_filter_hevc = RENCODE_V2_HEVC_IB_PARAM_LOOP_FILTER;
208 pdev->vcn_enc_cmds.slice_control_h264 = RENCODE_V2_H264_IB_PARAM_SLICE_CONTROL;
209 pdev->vcn_enc_cmds.spec_misc_h264 = RENCODE_V2_H264_IB_PARAM_SPEC_MISC;
210 pdev->vcn_enc_cmds.enc_params_h264 = RENCODE_V2_H264_IB_PARAM_ENCODE_PARAMS;
211 pdev->vcn_enc_cmds.deblocking_filter_h264 = RENCODE_V2_H264_IB_PARAM_DEBLOCKING_FILTER;
212 if (pdev->enc_hw_ver == RADV_VIDEO_ENC_HW_4) {
213 pdev->vcn_enc_cmds.enc_statistics = RENCODE_V4_IB_PARAM_ENCODE_STATISTICS;
214 } else
215 pdev->vcn_enc_cmds.enc_statistics = RENCODE_V2_IB_PARAM_ENCODE_STATISTICS;
216 } else {
217 pdev->vcn_enc_cmds.session_info = RENCODE_IB_PARAM_SESSION_INFO;
218 pdev->vcn_enc_cmds.task_info = RENCODE_IB_PARAM_TASK_INFO;
219 pdev->vcn_enc_cmds.session_init = RENCODE_IB_PARAM_SESSION_INIT;
220 pdev->vcn_enc_cmds.layer_control = RENCODE_IB_PARAM_LAYER_CONTROL;
221 pdev->vcn_enc_cmds.layer_select = RENCODE_IB_PARAM_LAYER_SELECT;
222 pdev->vcn_enc_cmds.rc_session_init = RENCODE_IB_PARAM_RATE_CONTROL_SESSION_INIT;
223 pdev->vcn_enc_cmds.rc_layer_init = RENCODE_IB_PARAM_RATE_CONTROL_LAYER_INIT;
224 pdev->vcn_enc_cmds.rc_per_pic = RENCODE_IB_PARAM_RATE_CONTROL_PER_PIC_EX;
225 pdev->vcn_enc_cmds.quality_params = RENCODE_IB_PARAM_QUALITY_PARAMS;
226 pdev->vcn_enc_cmds.nalu = RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU;
227 pdev->vcn_enc_cmds.slice_header = RENCODE_IB_PARAM_SLICE_HEADER;
228 pdev->vcn_enc_cmds.enc_params = RENCODE_IB_PARAM_ENCODE_PARAMS;
229 pdev->vcn_enc_cmds.intra_refresh = RENCODE_IB_PARAM_INTRA_REFRESH;
230 pdev->vcn_enc_cmds.ctx = RENCODE_IB_PARAM_ENCODE_CONTEXT_BUFFER;
231 pdev->vcn_enc_cmds.bitstream = RENCODE_IB_PARAM_VIDEO_BITSTREAM_BUFFER;
232 pdev->vcn_enc_cmds.feedback = RENCODE_IB_PARAM_FEEDBACK_BUFFER;
233 pdev->vcn_enc_cmds.slice_control_hevc = RENCODE_HEVC_IB_PARAM_SLICE_CONTROL;
234 pdev->vcn_enc_cmds.spec_misc_hevc = RENCODE_HEVC_IB_PARAM_SPEC_MISC;
235 pdev->vcn_enc_cmds.deblocking_filter_hevc = RENCODE_HEVC_IB_PARAM_DEBLOCKING_FILTER;
236 pdev->vcn_enc_cmds.slice_control_h264 = RENCODE_H264_IB_PARAM_SLICE_CONTROL;
237 pdev->vcn_enc_cmds.spec_misc_h264 = RENCODE_H264_IB_PARAM_SPEC_MISC;
238 pdev->vcn_enc_cmds.enc_params_h264 = RENCODE_H264_IB_PARAM_ENCODE_PARAMS;
239 pdev->vcn_enc_cmds.deblocking_filter_h264 = RENCODE_H264_IB_PARAM_DEBLOCKING_FILTER;
240 pdev->vcn_enc_cmds.enc_statistics = RENCODE_IB_PARAM_ENCODE_STATISTICS;
241 }
242 }
243
244 /* to process invalid frame rate */
245 static void
radv_vcn_enc_invalid_frame_rate(uint32_t * den,uint32_t * num)246 radv_vcn_enc_invalid_frame_rate(uint32_t *den, uint32_t *num)
247 {
248 if (*den == 0 || *num == 0) {
249 *den = 1;
250 *num = 30;
251 }
252 }
253
254 static uint32_t
radv_vcn_per_frame_integer(uint32_t bitrate,uint32_t den,uint32_t num)255 radv_vcn_per_frame_integer(uint32_t bitrate, uint32_t den, uint32_t num)
256 {
257 uint64_t rate_den = (uint64_t)bitrate * (uint64_t)den;
258
259 return (uint32_t)(rate_den / num);
260 }
261
262 static uint32_t
radv_vcn_per_frame_frac(uint32_t bitrate,uint32_t den,uint32_t num)263 radv_vcn_per_frame_frac(uint32_t bitrate, uint32_t den, uint32_t num)
264 {
265 uint64_t rate_den = (uint64_t)bitrate * (uint64_t)den;
266 uint64_t remainder = rate_den % num;
267
268 return (uint32_t)((remainder << 32) / num);
269 }
270
271 static void
radv_enc_set_emulation_prevention(struct radv_cmd_buffer * cmd_buffer,bool set)272 radv_enc_set_emulation_prevention(struct radv_cmd_buffer *cmd_buffer, bool set)
273 {
274 struct radv_enc_state *enc = &cmd_buffer->video.enc;
275 if (set != enc->emulation_prevention) {
276 enc->emulation_prevention = set;
277 enc->num_zeros = 0;
278 }
279 }
280
281 static uint32_t
radv_enc_value_bits(uint32_t value)282 radv_enc_value_bits(uint32_t value)
283 {
284 uint32_t i = 1;
285
286 while (value > 1) {
287 i++;
288 value >>= 1;
289 }
290
291 return i;
292 }
293
294 static const unsigned index_to_shifts[4] = {24, 16, 8, 0};
295
296 static void
radv_enc_output_one_byte(struct radv_cmd_buffer * cmd_buffer,unsigned char byte)297 radv_enc_output_one_byte(struct radv_cmd_buffer *cmd_buffer, unsigned char byte)
298 {
299 struct radeon_cmdbuf *cs = cmd_buffer->cs;
300 struct radv_enc_state *enc = &cmd_buffer->video.enc;
301 if (enc->byte_index == 0)
302 cs->buf[cs->cdw] = 0;
303 cs->buf[cs->cdw] |= ((unsigned int)(byte) << index_to_shifts[enc->byte_index]);
304 enc->byte_index++;
305
306 if (enc->byte_index >= 4) {
307 enc->byte_index = 0;
308 cs->cdw++;
309 }
310 }
311
312 static void
radv_enc_emulation_prevention(struct radv_cmd_buffer * cmd_buffer,unsigned char byte)313 radv_enc_emulation_prevention(struct radv_cmd_buffer *cmd_buffer, unsigned char byte)
314 {
315 struct radv_enc_state *enc = &cmd_buffer->video.enc;
316 if (enc->emulation_prevention) {
317 if ((enc->num_zeros >= 2) && ((byte == 0x00) || (byte == 0x01) || (byte == 0x02) || (byte == 0x03))) {
318 radv_enc_output_one_byte(cmd_buffer, 0x03);
319 enc->bits_output += 8;
320 enc->num_zeros = 0;
321 }
322 enc->num_zeros = (byte == 0 ? (enc->num_zeros + 1) : 0);
323 }
324 }
325
326 static void
radv_enc_code_fixed_bits(struct radv_cmd_buffer * cmd_buffer,unsigned int value,unsigned int num_bits)327 radv_enc_code_fixed_bits(struct radv_cmd_buffer *cmd_buffer, unsigned int value, unsigned int num_bits)
328 {
329 struct radv_enc_state *enc = &cmd_buffer->video.enc;
330 unsigned int bits_to_pack = 0;
331 enc->bits_size += num_bits;
332
333 while (num_bits > 0) {
334 unsigned int value_to_pack = value & (0xffffffff >> (32 - num_bits));
335 bits_to_pack = num_bits > (32 - enc->bits_in_shifter) ? (32 - enc->bits_in_shifter) : num_bits;
336
337 if (bits_to_pack < num_bits)
338 value_to_pack = value_to_pack >> (num_bits - bits_to_pack);
339
340 enc->shifter |= value_to_pack << (32 - enc->bits_in_shifter - bits_to_pack);
341 num_bits -= bits_to_pack;
342 enc->bits_in_shifter += bits_to_pack;
343
344 while (enc->bits_in_shifter >= 8) {
345 unsigned char output_byte = (unsigned char)(enc->shifter >> 24);
346 enc->shifter <<= 8;
347 radv_enc_emulation_prevention(cmd_buffer, output_byte);
348 radv_enc_output_one_byte(cmd_buffer, output_byte);
349 enc->bits_in_shifter -= 8;
350 enc->bits_output += 8;
351 }
352 }
353 }
354
355 static void
radv_enc_reset(struct radv_cmd_buffer * cmd_buffer)356 radv_enc_reset(struct radv_cmd_buffer *cmd_buffer)
357 {
358 struct radv_enc_state *enc = &cmd_buffer->video.enc;
359 enc->emulation_prevention = false;
360 enc->shifter = 0;
361 enc->bits_in_shifter = 0;
362 enc->bits_output = 0;
363 enc->num_zeros = 0;
364 enc->byte_index = 0;
365 enc->bits_size = 0;
366 }
367
368 static void
radv_enc_byte_align(struct radv_cmd_buffer * cmd_buffer)369 radv_enc_byte_align(struct radv_cmd_buffer *cmd_buffer)
370 {
371 struct radv_enc_state *enc = &cmd_buffer->video.enc;
372 unsigned int num_padding_zeros = (32 - enc->bits_in_shifter) % 8;
373
374 if (num_padding_zeros > 0)
375 radv_enc_code_fixed_bits(cmd_buffer, 0, num_padding_zeros);
376 }
377
378 static void
radv_enc_flush_headers(struct radv_cmd_buffer * cmd_buffer)379 radv_enc_flush_headers(struct radv_cmd_buffer *cmd_buffer)
380 {
381 struct radv_enc_state *enc = &cmd_buffer->video.enc;
382 struct radeon_cmdbuf *cs = cmd_buffer->cs;
383 if (enc->bits_in_shifter != 0) {
384 unsigned char output_byte = (unsigned char)(enc->shifter >> 24);
385 radv_enc_emulation_prevention(cmd_buffer, output_byte);
386 radv_enc_output_one_byte(cmd_buffer, output_byte);
387 enc->bits_output += enc->bits_in_shifter;
388 enc->shifter = 0;
389 enc->bits_in_shifter = 0;
390 enc->num_zeros = 0;
391 }
392
393 if (enc->byte_index > 0) {
394 cs->cdw++;
395 enc->byte_index = 0;
396 }
397 }
398
399 static void
radv_enc_code_ue(struct radv_cmd_buffer * cmd_buffer,unsigned int value)400 radv_enc_code_ue(struct radv_cmd_buffer *cmd_buffer, unsigned int value)
401 {
402 unsigned int x = 0;
403 unsigned int ue_code = value + 1;
404 value += 1;
405
406 while (value) {
407 value = (value >> 1);
408 x += 1;
409 }
410 if (x > 1)
411 radv_enc_code_fixed_bits(cmd_buffer, 0, x - 1);
412 radv_enc_code_fixed_bits(cmd_buffer, ue_code, x);
413 }
414
415 static void
radv_enc_code_se(struct radv_cmd_buffer * cmd_buffer,int value)416 radv_enc_code_se(struct radv_cmd_buffer *cmd_buffer, int value)
417 {
418 unsigned int v = 0;
419
420 if (value != 0)
421 v = (value < 0 ? ((unsigned int)(0 - value) << 1) : (((unsigned int)(value) << 1) - 1));
422
423 radv_enc_code_ue(cmd_buffer, v);
424 }
425
426 #define ENC_BEGIN \
427 { \
428 uint32_t begin = cs->cdw++;
429
430 #define ENC_END \
431 radeon_emit_direct(cs, begin, (cs->cdw - begin) * 4); \
432 cmd_buffer->video.enc.total_task_size += cs->buf[begin]; \
433 }
434
435 static void
radv_enc_session_info(struct radv_cmd_buffer * cmd_buffer)436 radv_enc_session_info(struct radv_cmd_buffer *cmd_buffer)
437 {
438 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
439 const struct radv_physical_device *pdev = radv_device_physical(device);
440 struct radeon_cmdbuf *cs = cmd_buffer->cs;
441 ENC_BEGIN;
442 radeon_emit(cs, pdev->vcn_enc_cmds.session_info);
443 radeon_emit(cs, pdev->encoder_interface_version);
444
445 radv_cs_add_buffer(device->ws, cs, cmd_buffer->video.vid->sessionctx.mem->bo);
446 uint64_t va = radv_buffer_get_va(cmd_buffer->video.vid->sessionctx.mem->bo);
447 va += cmd_buffer->video.vid->sessionctx.offset;
448 radeon_emit(cs, va >> 32);
449 radeon_emit(cs, va & 0xffffffff);
450 radeon_emit(cs, RENCODE_ENGINE_TYPE_ENCODE);
451 ENC_END;
452 }
453
454 static void
radv_enc_task_info(struct radv_cmd_buffer * cmd_buffer,bool feedback)455 radv_enc_task_info(struct radv_cmd_buffer *cmd_buffer, bool feedback)
456 {
457 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
458 const struct radv_physical_device *pdev = radv_device_physical(device);
459 struct radeon_cmdbuf *cs = cmd_buffer->cs;
460 struct radv_enc_state *enc = &cmd_buffer->video.enc;
461
462 enc->task_id++;
463 ENC_BEGIN;
464 radeon_emit(cs, pdev->vcn_enc_cmds.task_info);
465 enc->task_size_offset = cs->cdw++;
466 radeon_emit(cs, enc->task_id);
467 radeon_emit(cs, feedback ? 1 : 0);
468 ENC_END;
469 }
470
471 static void
radv_enc_session_init(struct radv_cmd_buffer * cmd_buffer,const struct VkVideoEncodeInfoKHR * enc_info)472 radv_enc_session_init(struct radv_cmd_buffer *cmd_buffer, const struct VkVideoEncodeInfoKHR *enc_info)
473 {
474 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
475 const struct radv_physical_device *pdev = radv_device_physical(device);
476 struct radv_video_session *vid = cmd_buffer->video.vid;
477 struct radeon_cmdbuf *cs = cmd_buffer->cs;
478 unsigned alignment_w = 16;
479 unsigned alignment_h = 16;
480 if (vid->vk.op == VK_VIDEO_CODEC_OPERATION_ENCODE_H265_BIT_KHR) {
481 alignment_w = 64;
482 }
483
484 uint32_t w = enc_info->srcPictureResource.codedExtent.width;
485 uint32_t h = enc_info->srcPictureResource.codedExtent.height;
486 uint32_t aligned_picture_width = align(w, alignment_w);
487 uint32_t aligned_picture_height = align(h, alignment_h);
488 uint32_t padding_width = aligned_picture_width - w;
489 uint32_t padding_height = aligned_picture_height - h;
490
491 ENC_BEGIN;
492 radeon_emit(cs, pdev->vcn_enc_cmds.session_init);
493 radeon_emit(cs, vid->enc_session.encode_standard);
494 radeon_emit(cs, aligned_picture_width);
495 radeon_emit(cs, aligned_picture_height);
496 radeon_emit(cs, padding_width);
497 radeon_emit(cs, padding_height);
498 radeon_emit(cs, vid->enc_session.pre_encode_mode);
499 radeon_emit(cs, vid->enc_session.pre_encode_chroma_enabled);
500 if (pdev->enc_hw_ver >= RADV_VIDEO_ENC_HW_3) {
501 radeon_emit(cs, 0); // slice output enabled.
502 }
503 radeon_emit(cs, vid->enc_session.display_remote);
504 if (pdev->enc_hw_ver >= RADV_VIDEO_ENC_HW_4) {
505 radeon_emit(cs, 0);
506 }
507 ENC_END;
508 }
509
510 static void
radv_enc_layer_control(struct radv_cmd_buffer * cmd_buffer,const rvcn_enc_layer_control_t * rc_layer_control)511 radv_enc_layer_control(struct radv_cmd_buffer *cmd_buffer, const rvcn_enc_layer_control_t *rc_layer_control)
512 {
513 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
514 const struct radv_physical_device *pdev = radv_device_physical(device);
515 struct radeon_cmdbuf *cs = cmd_buffer->cs;
516 ENC_BEGIN;
517 radeon_emit(cs, pdev->vcn_enc_cmds.layer_control);
518 radeon_emit(cs, rc_layer_control->max_num_temporal_layers); // max num temporal layesr
519 radeon_emit(cs, rc_layer_control->num_temporal_layers); // num temporal layers
520 ENC_END;
521 }
522
523 static void
radv_enc_layer_select(struct radv_cmd_buffer * cmd_buffer,int tl_idx)524 radv_enc_layer_select(struct radv_cmd_buffer *cmd_buffer, int tl_idx)
525 {
526 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
527 const struct radv_physical_device *pdev = radv_device_physical(device);
528 struct radeon_cmdbuf *cs = cmd_buffer->cs;
529 ENC_BEGIN;
530 radeon_emit(cs, pdev->vcn_enc_cmds.layer_select);
531 radeon_emit(cs, tl_idx); // temporal layer index
532 ENC_END;
533 }
534
535 static void
radv_enc_slice_control(struct radv_cmd_buffer * cmd_buffer,const struct VkVideoEncodeInfoKHR * enc_info)536 radv_enc_slice_control(struct radv_cmd_buffer *cmd_buffer, const struct VkVideoEncodeInfoKHR *enc_info)
537 {
538 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
539 const struct radv_physical_device *pdev = radv_device_physical(device);
540 struct radeon_cmdbuf *cs = cmd_buffer->cs;
541
542 uint32_t num_mbs_in_slice;
543 uint32_t width_in_mbs = DIV_ROUND_UP(enc_info->srcPictureResource.codedExtent.width, 16);
544 uint32_t height_in_mbs = DIV_ROUND_UP(enc_info->srcPictureResource.codedExtent.height, 16);
545 num_mbs_in_slice = width_in_mbs * height_in_mbs;
546 ENC_BEGIN;
547 radeon_emit(cs, pdev->vcn_enc_cmds.slice_control_h264);
548 radeon_emit(cs, RENCODE_H264_SLICE_CONTROL_MODE_FIXED_MBS); // slice control mode
549 radeon_emit(cs, num_mbs_in_slice); // num mbs per slice
550 ENC_END;
551 }
552
553 static void
radv_enc_spec_misc_h264(struct radv_cmd_buffer * cmd_buffer,const struct VkVideoEncodeInfoKHR * enc_info)554 radv_enc_spec_misc_h264(struct radv_cmd_buffer *cmd_buffer, const struct VkVideoEncodeInfoKHR *enc_info)
555 {
556 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
557 const struct radv_physical_device *pdev = radv_device_physical(device);
558 struct radeon_cmdbuf *cs = cmd_buffer->cs;
559 const struct VkVideoEncodeH264PictureInfoKHR *h264_picture_info =
560 vk_find_struct_const(enc_info->pNext, VIDEO_ENCODE_H264_PICTURE_INFO_KHR);
561 const StdVideoEncodeH264PictureInfo *pic = h264_picture_info->pStdPictureInfo;
562 const StdVideoH264SequenceParameterSet *sps =
563 vk_video_find_h264_enc_std_sps(&cmd_buffer->video.params->vk, pic->seq_parameter_set_id);
564 const StdVideoH264PictureParameterSet *pps =
565 vk_video_find_h264_enc_std_pps(&cmd_buffer->video.params->vk, pic->pic_parameter_set_id);
566 ENC_BEGIN;
567 radeon_emit(cs, pdev->vcn_enc_cmds.spec_misc_h264);
568 radeon_emit(cs, pps->flags.constrained_intra_pred_flag); // constrained_intra_pred_flag
569 radeon_emit(cs, pps->flags.entropy_coding_mode_flag); // cabac enable
570 radeon_emit(cs, 0); // cabac init idc
571 radeon_emit(cs, 1); // half pel enabled
572 radeon_emit(cs, 1); // quarter pel enabled
573 radeon_emit(cs, cmd_buffer->video.vid->vk.h264.profile_idc); // profile_idc
574 radeon_emit(cs, vk_video_get_h264_level(sps->level_idc));
575
576 if (pdev->enc_hw_ver >= RADV_VIDEO_ENC_HW_3) {
577 radeon_emit(cs, 0); // v3 b_picture_enabled
578 radeon_emit(cs, pps->weighted_bipred_idc); // v3 weighted bipred idc
579 }
580
581 ENC_END;
582 }
583
584 static void
radv_enc_spec_misc_hevc(struct radv_cmd_buffer * cmd_buffer,const struct VkVideoEncodeInfoKHR * enc_info)585 radv_enc_spec_misc_hevc(struct radv_cmd_buffer *cmd_buffer, const struct VkVideoEncodeInfoKHR *enc_info)
586 {
587 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
588 const struct radv_physical_device *pdev = radv_device_physical(device);
589 struct radeon_cmdbuf *cs = cmd_buffer->cs;
590 const struct VkVideoEncodeH265PictureInfoKHR *h265_picture_info =
591 vk_find_struct_const(enc_info->pNext, VIDEO_ENCODE_H265_PICTURE_INFO_KHR);
592 const StdVideoEncodeH265PictureInfo *pic = h265_picture_info->pStdPictureInfo;
593 const VkVideoEncodeH265NaluSliceSegmentInfoKHR *h265_slice = &h265_picture_info->pNaluSliceSegmentEntries[0];
594 const StdVideoEncodeH265SliceSegmentHeader *slice = h265_slice->pStdSliceSegmentHeader;
595 const StdVideoH265SequenceParameterSet *sps =
596 vk_video_find_h265_enc_std_sps(&cmd_buffer->video.params->vk, pic->pps_seq_parameter_set_id);
597 const StdVideoH265PictureParameterSet *pps =
598 vk_video_find_h265_enc_std_pps(&cmd_buffer->video.params->vk, pic->pps_pic_parameter_set_id);
599 ENC_BEGIN;
600 radeon_emit(cs, pdev->vcn_enc_cmds.spec_misc_hevc);
601 radeon_emit(cs, sps->log2_min_luma_coding_block_size_minus3);
602 radeon_emit(cs, !sps->flags.amp_enabled_flag);
603 radeon_emit(cs, sps->flags.strong_intra_smoothing_enabled_flag);
604 radeon_emit(cs, pps->flags.constrained_intra_pred_flag);
605 radeon_emit(cs, slice->flags.cabac_init_flag);
606 radeon_emit(cs, 1); // enc->enc_pic.hevc_spec_misc.half_pel_enabled
607 radeon_emit(cs, 1); // enc->enc_pic.hevc_spec_misc.quarter_pel_enabled
608 if (pdev->enc_hw_ver >= RADV_VIDEO_ENC_HW_3) {
609 radeon_emit(cs, !pps->flags.transform_skip_enabled_flag);
610 radeon_emit(cs, pps->flags.cu_qp_delta_enabled_flag);
611 }
612 ENC_END;
613 }
614
615 static void
radv_enc_slice_control_hevc(struct radv_cmd_buffer * cmd_buffer,const struct VkVideoEncodeInfoKHR * enc_info)616 radv_enc_slice_control_hevc(struct radv_cmd_buffer *cmd_buffer, const struct VkVideoEncodeInfoKHR *enc_info)
617 {
618 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
619 const struct radv_physical_device *pdev = radv_device_physical(device);
620 struct radeon_cmdbuf *cs = cmd_buffer->cs;
621
622 uint32_t width_in_ctb, height_in_ctb, num_ctbs_in_slice;
623
624 width_in_ctb = DIV_ROUND_UP(enc_info->srcPictureResource.codedExtent.width, 64);
625 height_in_ctb = DIV_ROUND_UP(enc_info->srcPictureResource.codedExtent.height, 64);
626 num_ctbs_in_slice = width_in_ctb * height_in_ctb;
627 ENC_BEGIN;
628 radeon_emit(cs, pdev->vcn_enc_cmds.slice_control_hevc);
629 radeon_emit(cs, RENCODE_HEVC_SLICE_CONTROL_MODE_FIXED_CTBS);
630 radeon_emit(cs, num_ctbs_in_slice); // num_ctbs_in_slice
631 radeon_emit(cs, num_ctbs_in_slice); // num_ctbs_in_slice_segment
632 ENC_END;
633 }
634
635 static void
radv_enc_rc_session_init(struct radv_cmd_buffer * cmd_buffer)636 radv_enc_rc_session_init(struct radv_cmd_buffer *cmd_buffer)
637 {
638 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
639 const struct radv_physical_device *pdev = radv_device_physical(device);
640 struct radeon_cmdbuf *cs = cmd_buffer->cs;
641 struct radv_video_session *vid = cmd_buffer->video.vid;
642 ENC_BEGIN;
643 radeon_emit(cs, pdev->vcn_enc_cmds.rc_session_init);
644 radeon_emit(cs, vid->enc_rate_control_method); // rate_control_method);
645 radeon_emit(cs, vid->enc_vbv_buffer_level); // vbv_buffer_level);
646 ENC_END;
647 }
648
649 static void
radv_enc_rc_layer_init(struct radv_cmd_buffer * cmd_buffer,rvcn_enc_rate_ctl_layer_init_t * layer_init)650 radv_enc_rc_layer_init(struct radv_cmd_buffer *cmd_buffer, rvcn_enc_rate_ctl_layer_init_t *layer_init)
651 {
652 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
653 const struct radv_physical_device *pdev = radv_device_physical(device);
654 struct radeon_cmdbuf *cs = cmd_buffer->cs;
655 ENC_BEGIN;
656 radeon_emit(cs, pdev->vcn_enc_cmds.rc_layer_init);
657 radeon_emit(cs, layer_init->target_bit_rate); // target bit rate
658 radeon_emit(cs, layer_init->peak_bit_rate); // peak bit rate
659 radeon_emit(cs, layer_init->frame_rate_num); // frame rate num
660 radeon_emit(cs, layer_init->frame_rate_den); // frame rate dem
661 radeon_emit(cs, layer_init->vbv_buffer_size); // vbv buffer size
662 radeon_emit(cs, layer_init->avg_target_bits_per_picture); // avg target bits per picture
663 radeon_emit(cs, layer_init->peak_bits_per_picture_integer); // peak bit per picture int
664 radeon_emit(cs, layer_init->peak_bits_per_picture_fractional); // peak bit per picture fract
665 ENC_END;
666 }
667
668 static void
radv_enc_deblocking_filter_h264(struct radv_cmd_buffer * cmd_buffer,const VkVideoEncodeInfoKHR * enc_info)669 radv_enc_deblocking_filter_h264(struct radv_cmd_buffer *cmd_buffer, const VkVideoEncodeInfoKHR *enc_info)
670 {
671 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
672 const struct radv_physical_device *pdev = radv_device_physical(device);
673 struct radeon_cmdbuf *cs = cmd_buffer->cs;
674 const struct VkVideoEncodeH264PictureInfoKHR *h264_picture_info =
675 vk_find_struct_const(enc_info->pNext, VIDEO_ENCODE_H264_PICTURE_INFO_KHR);
676 const VkVideoEncodeH264NaluSliceInfoKHR *h264_slice = &h264_picture_info->pNaluSliceEntries[0];
677 const StdVideoEncodeH264SliceHeader *slice = h264_slice->pStdSliceHeader;
678 ENC_BEGIN;
679 radeon_emit(cs, pdev->vcn_enc_cmds.deblocking_filter_h264);
680 radeon_emit(cs, slice->disable_deblocking_filter_idc);
681 radeon_emit(cs, slice->slice_alpha_c0_offset_div2);
682 radeon_emit(cs, slice->slice_beta_offset_div2);
683 radeon_emit(cs, 0); // cb qp offset
684 radeon_emit(cs, 0); // cr qp offset
685 ENC_END;
686 }
687
688 static void
radv_enc_deblocking_filter_hevc(struct radv_cmd_buffer * cmd_buffer,const VkVideoEncodeInfoKHR * enc_info)689 radv_enc_deblocking_filter_hevc(struct radv_cmd_buffer *cmd_buffer, const VkVideoEncodeInfoKHR *enc_info)
690 {
691 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
692 const struct radv_physical_device *pdev = radv_device_physical(device);
693 struct radeon_cmdbuf *cs = cmd_buffer->cs;
694 const struct VkVideoEncodeH265PictureInfoKHR *h265_picture_info =
695 vk_find_struct_const(enc_info->pNext, VIDEO_ENCODE_H265_PICTURE_INFO_KHR);
696 const StdVideoEncodeH265PictureInfo *pic = h265_picture_info->pStdPictureInfo;
697 const VkVideoEncodeH265NaluSliceSegmentInfoKHR *h265_slice = &h265_picture_info->pNaluSliceSegmentEntries[0];
698 const StdVideoEncodeH265SliceSegmentHeader *slice = h265_slice->pStdSliceSegmentHeader;
699 const StdVideoH265SequenceParameterSet *sps =
700 vk_video_find_h265_enc_std_sps(&cmd_buffer->video.params->vk, pic->pps_seq_parameter_set_id);
701
702 ENC_BEGIN;
703 radeon_emit(cs, pdev->vcn_enc_cmds.deblocking_filter_hevc);
704 radeon_emit(cs, slice->flags.slice_loop_filter_across_slices_enabled_flag);
705 radeon_emit(cs, slice->flags.slice_deblocking_filter_disabled_flag);
706 radeon_emit(cs, slice->slice_beta_offset_div2);
707 radeon_emit(cs, slice->slice_tc_offset_div2);
708 radeon_emit(cs, slice->slice_cb_qp_offset);
709 radeon_emit(cs, slice->slice_cr_qp_offset);
710 if (pdev->enc_hw_ver >= RADV_VIDEO_ENC_HW_2)
711 radeon_emit(cs, !sps->flags.sample_adaptive_offset_enabled_flag);
712 ENC_END;
713 }
714
715 static void
radv_enc_quality_params(struct radv_cmd_buffer * cmd_buffer)716 radv_enc_quality_params(struct radv_cmd_buffer *cmd_buffer)
717 {
718 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
719 const struct radv_physical_device *pdev = radv_device_physical(device);
720 struct radeon_cmdbuf *cs = cmd_buffer->cs;
721 ENC_BEGIN;
722 radeon_emit(cs, pdev->vcn_enc_cmds.quality_params);
723 radeon_emit(cs, 0);
724 radeon_emit(cs, 0);
725 radeon_emit(cs, 0);
726 radeon_emit(cs, 0);
727 if (pdev->enc_hw_ver >= RADV_VIDEO_ENC_HW_2)
728 radeon_emit(cs, 0);
729 ENC_END;
730 }
731
732 static void
radv_enc_slice_header(struct radv_cmd_buffer * cmd_buffer,const VkVideoEncodeInfoKHR * enc_info)733 radv_enc_slice_header(struct radv_cmd_buffer *cmd_buffer, const VkVideoEncodeInfoKHR *enc_info)
734 {
735 struct radv_enc_state *enc = &cmd_buffer->video.enc;
736 uint32_t instruction[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
737 uint32_t num_bits[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
738 const struct VkVideoEncodeH264PictureInfoKHR *h264_picture_info =
739 vk_find_struct_const(enc_info->pNext, VIDEO_ENCODE_H264_PICTURE_INFO_KHR);
740 int slice_count = h264_picture_info->naluSliceEntryCount;
741 const StdVideoEncodeH264PictureInfo *pic = h264_picture_info->pStdPictureInfo;
742 const StdVideoH264SequenceParameterSet *sps =
743 vk_video_find_h264_enc_std_sps(&cmd_buffer->video.params->vk, pic->seq_parameter_set_id);
744 const StdVideoH264PictureParameterSet *pps =
745 vk_video_find_h264_enc_std_pps(&cmd_buffer->video.params->vk, pic->pic_parameter_set_id);
746 const VkVideoEncodeH264NaluSliceInfoKHR *slice_info = &h264_picture_info->pNaluSliceEntries[0];
747
748 unsigned int inst_index = 0;
749 unsigned int cdw_start = 0;
750 unsigned int cdw_filled = 0;
751 unsigned int bits_copied = 0;
752
753 assert(slice_count <= 1);
754
755 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
756 const struct radv_physical_device *pdev = radv_device_physical(device);
757 struct radeon_cmdbuf *cs = cmd_buffer->cs;
758 ENC_BEGIN;
759 radeon_emit(cs, pdev->vcn_enc_cmds.slice_header);
760 radv_enc_reset(cmd_buffer);
761 radv_enc_set_emulation_prevention(cmd_buffer, false);
762
763 cdw_start = cs->cdw;
764
765 if (pic->flags.IdrPicFlag)
766 radv_enc_code_fixed_bits(cmd_buffer, 0x65, 8);
767 else if (!pic->flags.is_reference)
768 radv_enc_code_fixed_bits(cmd_buffer, 0x01, 8);
769 else
770 radv_enc_code_fixed_bits(cmd_buffer, 0x41, 8);
771
772 radv_enc_flush_headers(cmd_buffer);
773 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
774 num_bits[inst_index] = enc->bits_output - bits_copied;
775 bits_copied = enc->bits_output;
776 inst_index++;
777
778 instruction[inst_index] = RENCODE_H264_HEADER_INSTRUCTION_FIRST_MB;
779 inst_index++;
780
781 switch (pic->primary_pic_type) {
782 case STD_VIDEO_H264_PICTURE_TYPE_I:
783 case STD_VIDEO_H264_PICTURE_TYPE_IDR:
784 default:
785 radv_enc_code_ue(cmd_buffer, 7);
786 break;
787 case STD_VIDEO_H264_PICTURE_TYPE_P:
788 radv_enc_code_ue(cmd_buffer, 5);
789 break;
790 case STD_VIDEO_H264_PICTURE_TYPE_B:
791 radv_enc_code_ue(cmd_buffer, 6);
792 break;
793 }
794 radv_enc_code_ue(cmd_buffer, 0x0);
795
796 unsigned int max_frame_num_bits = sps->log2_max_frame_num_minus4 + 4;
797 radv_enc_code_fixed_bits(cmd_buffer, pic->frame_num % (1 << max_frame_num_bits), max_frame_num_bits);
798 #if 0
799 if (enc->enc_pic.h264_enc_params.input_picture_structure !=
800 RENCODE_H264_PICTURE_STRUCTURE_FRAME) {
801 radv_enc_code_fixed_bits(cmd_buffer, 0x1, 1);
802 radv_enc_code_fixed_bits(cmd_buffer,
803 enc->enc_pic.h264_enc_params.input_picture_structure ==
804 RENCODE_H264_PICTURE_STRUCTURE_BOTTOM_FIELD
805 ? 1
806 : 0,
807 1);
808 }
809 #endif
810
811 if (pic->flags.IdrPicFlag)
812 radv_enc_code_ue(cmd_buffer, pic->idr_pic_id);
813
814 if (sps->pic_order_cnt_type == STD_VIDEO_H264_POC_TYPE_0) {
815 unsigned int max_poc_bits = sps->log2_max_pic_order_cnt_lsb_minus4 + 4;
816 radv_enc_code_fixed_bits(cmd_buffer, pic->PicOrderCnt % (1 << max_poc_bits), max_poc_bits);
817 }
818
819 if (pps->flags.redundant_pic_cnt_present_flag)
820 radv_enc_code_ue(cmd_buffer, 0);
821
822 if (pic->primary_pic_type == STD_VIDEO_H264_PICTURE_TYPE_B) {
823 radv_enc_code_fixed_bits(cmd_buffer, slice_info->pStdSliceHeader->flags.direct_spatial_mv_pred_flag, 1);
824 }
825 const StdVideoEncodeH264ReferenceListsInfo *ref_lists = pic->pRefLists;
826 /* ref_pic_list_modification() */
827 if (pic->primary_pic_type != STD_VIDEO_H264_PICTURE_TYPE_IDR &&
828 pic->primary_pic_type != STD_VIDEO_H264_PICTURE_TYPE_I) {
829
830 /* num ref idx active override flag */
831 radv_enc_code_fixed_bits(cmd_buffer, slice_info->pStdSliceHeader->flags.num_ref_idx_active_override_flag, 1);
832 if (slice_info->pStdSliceHeader->flags.num_ref_idx_active_override_flag) {
833 radv_enc_code_ue(cmd_buffer, ref_lists->num_ref_idx_l0_active_minus1);
834 if (pic->primary_pic_type == STD_VIDEO_H264_PICTURE_TYPE_B)
835 radv_enc_code_ue(cmd_buffer, ref_lists->num_ref_idx_l1_active_minus1);
836 }
837
838 radv_enc_code_fixed_bits(cmd_buffer, ref_lists->flags.ref_pic_list_modification_flag_l0, 1);
839 if (ref_lists->flags.ref_pic_list_modification_flag_l0) {
840 for (unsigned op = 0; op < ref_lists->refList0ModOpCount; op++) {
841 const StdVideoEncodeH264RefListModEntry *entry = &ref_lists->pRefList0ModOperations[op];
842
843 radv_enc_code_ue(cmd_buffer, entry->modification_of_pic_nums_idc);
844 if (entry->modification_of_pic_nums_idc ==
845 STD_VIDEO_H264_MODIFICATION_OF_PIC_NUMS_IDC_SHORT_TERM_SUBTRACT ||
846 entry->modification_of_pic_nums_idc == STD_VIDEO_H264_MODIFICATION_OF_PIC_NUMS_IDC_SHORT_TERM_ADD)
847 radv_enc_code_ue(cmd_buffer, entry->abs_diff_pic_num_minus1);
848 else if (entry->modification_of_pic_nums_idc == STD_VIDEO_H264_MODIFICATION_OF_PIC_NUMS_IDC_LONG_TERM)
849 radv_enc_code_ue(cmd_buffer, entry->long_term_pic_num);
850 }
851 }
852
853 if (pic->primary_pic_type == STD_VIDEO_H264_PICTURE_TYPE_B) {
854 radv_enc_code_fixed_bits(cmd_buffer, ref_lists->flags.ref_pic_list_modification_flag_l1, 1);
855 if (ref_lists->flags.ref_pic_list_modification_flag_l1) {
856 for (unsigned op = 0; op < ref_lists->refList1ModOpCount; op++) {
857 const StdVideoEncodeH264RefListModEntry *entry = &ref_lists->pRefList1ModOperations[op];
858
859 radv_enc_code_ue(cmd_buffer, entry->modification_of_pic_nums_idc);
860 if (entry->modification_of_pic_nums_idc ==
861 STD_VIDEO_H264_MODIFICATION_OF_PIC_NUMS_IDC_SHORT_TERM_SUBTRACT ||
862 entry->modification_of_pic_nums_idc == STD_VIDEO_H264_MODIFICATION_OF_PIC_NUMS_IDC_SHORT_TERM_ADD)
863 radv_enc_code_ue(cmd_buffer, entry->abs_diff_pic_num_minus1);
864 else if (entry->modification_of_pic_nums_idc == STD_VIDEO_H264_MODIFICATION_OF_PIC_NUMS_IDC_LONG_TERM)
865 radv_enc_code_ue(cmd_buffer, entry->long_term_pic_num);
866 }
867 }
868 }
869 }
870
871 if (pic->flags.IdrPicFlag) {
872 radv_enc_code_fixed_bits(cmd_buffer, 0x0, 1);
873 radv_enc_code_fixed_bits(cmd_buffer, pic->flags.long_term_reference_flag, 1); /* long_term_reference_flag */
874 } else if (pic->flags.is_reference) {
875 radv_enc_code_fixed_bits(cmd_buffer, ref_lists->refPicMarkingOpCount > 0 ? 1 : 0, 1);
876 for (unsigned op = 0; op < ref_lists->refPicMarkingOpCount; op++) {
877 const StdVideoEncodeH264RefPicMarkingEntry *entry = &ref_lists->pRefPicMarkingOperations[op];
878 radv_enc_code_ue(cmd_buffer, entry->memory_management_control_operation);
879 if (entry->memory_management_control_operation == STD_VIDEO_H264_MEM_MGMT_CONTROL_OP_UNMARK_SHORT_TERM ||
880 entry->memory_management_control_operation == STD_VIDEO_H264_MEM_MGMT_CONTROL_OP_MARK_LONG_TERM)
881 radv_enc_code_ue(cmd_buffer, entry->difference_of_pic_nums_minus1);
882 if (entry->memory_management_control_operation == STD_VIDEO_H264_MEM_MGMT_CONTROL_OP_UNMARK_LONG_TERM)
883 radv_enc_code_ue(cmd_buffer, entry->long_term_pic_num);
884 if (entry->memory_management_control_operation == STD_VIDEO_H264_MEM_MGMT_CONTROL_OP_MARK_LONG_TERM ||
885 entry->memory_management_control_operation == STD_VIDEO_H264_MEM_MGMT_CONTROL_OP_MARK_CURRENT_AS_LONG_TERM)
886 radv_enc_code_ue(cmd_buffer, entry->long_term_frame_idx);
887 if (entry->memory_management_control_operation == STD_VIDEO_H264_MEM_MGMT_CONTROL_OP_SET_MAX_LONG_TERM_INDEX)
888 radv_enc_code_ue(cmd_buffer, entry->max_long_term_frame_idx_plus1);
889 if (entry->memory_management_control_operation == STD_VIDEO_H264_MEM_MGMT_CONTROL_OP_END)
890 break;
891 }
892 }
893
894 if (pic->primary_pic_type != STD_VIDEO_H264_PICTURE_TYPE_IDR &&
895 pic->primary_pic_type != STD_VIDEO_H264_PICTURE_TYPE_I && pps->flags.entropy_coding_mode_flag)
896 radv_enc_code_ue(cmd_buffer, slice_info->pStdSliceHeader->cabac_init_idc);
897
898 radv_enc_flush_headers(cmd_buffer);
899 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
900 num_bits[inst_index] = enc->bits_output - bits_copied;
901 bits_copied = enc->bits_output;
902 inst_index++;
903
904 instruction[inst_index] = RENCODE_H264_HEADER_INSTRUCTION_SLICE_QP_DELTA;
905 inst_index++;
906
907 if (pps->flags.deblocking_filter_control_present_flag) {
908 radv_enc_code_ue(cmd_buffer, slice_info->pStdSliceHeader->disable_deblocking_filter_idc);
909 if (!slice_info->pStdSliceHeader->disable_deblocking_filter_idc) {
910 radv_enc_code_se(cmd_buffer, slice_info->pStdSliceHeader->slice_alpha_c0_offset_div2);
911 radv_enc_code_se(cmd_buffer, slice_info->pStdSliceHeader->slice_beta_offset_div2);
912 }
913 }
914
915 radv_enc_flush_headers(cmd_buffer);
916 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
917 num_bits[inst_index] = enc->bits_output - bits_copied;
918 bits_copied = enc->bits_output;
919 inst_index++;
920
921 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_END;
922
923 cdw_filled = cs->cdw - cdw_start;
924 for (int i = 0; i < RENCODE_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS - cdw_filled; i++)
925 radeon_emit(cs, 0x00000000);
926 for (int j = 0; j < RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS; j++) {
927 radeon_emit(cs, instruction[j]);
928 radeon_emit(cs, num_bits[j]);
929 }
930 ENC_END;
931 }
932
933 static void
radv_enc_slice_header_hevc(struct radv_cmd_buffer * cmd_buffer,const VkVideoEncodeInfoKHR * enc_info)934 radv_enc_slice_header_hevc(struct radv_cmd_buffer *cmd_buffer, const VkVideoEncodeInfoKHR *enc_info)
935 {
936 struct radv_enc_state *enc = &cmd_buffer->video.enc;
937 uint32_t instruction[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
938 uint32_t num_bits[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
939 const struct VkVideoEncodeH265PictureInfoKHR *h265_picture_info =
940 vk_find_struct_const(enc_info->pNext, VIDEO_ENCODE_H265_PICTURE_INFO_KHR);
941 const StdVideoEncodeH265PictureInfo *pic = h265_picture_info->pStdPictureInfo;
942 const VkVideoEncodeH265NaluSliceSegmentInfoKHR *h265_slice = &h265_picture_info->pNaluSliceSegmentEntries[0];
943 const StdVideoEncodeH265SliceSegmentHeader *slice = h265_slice->pStdSliceSegmentHeader;
944 const StdVideoH265SequenceParameterSet *sps =
945 vk_video_find_h265_enc_std_sps(&cmd_buffer->video.params->vk, pic->pps_seq_parameter_set_id);
946 const StdVideoH265PictureParameterSet *pps =
947 vk_video_find_h265_enc_std_pps(&cmd_buffer->video.params->vk, pic->pps_pic_parameter_set_id);
948 unsigned int inst_index = 0;
949 unsigned int cdw_start = 0;
950 unsigned int cdw_filled = 0;
951 unsigned int bits_copied = 0;
952 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
953 const struct radv_physical_device *pdev = radv_device_physical(device);
954 struct radeon_cmdbuf *cs = cmd_buffer->cs;
955 unsigned nal_unit_type = vk_video_get_h265_nal_unit(pic);
956
957 ENC_BEGIN;
958 radeon_emit(cs, pdev->vcn_enc_cmds.slice_header);
959 radv_enc_reset(cmd_buffer);
960 radv_enc_set_emulation_prevention(cmd_buffer, false);
961
962 cdw_start = cs->cdw;
963 radv_enc_code_fixed_bits(cmd_buffer, 0x0, 1);
964 radv_enc_code_fixed_bits(cmd_buffer, nal_unit_type, 6);
965 radv_enc_code_fixed_bits(cmd_buffer, 0x0, 6);
966 radv_enc_code_fixed_bits(cmd_buffer, pic->TemporalId + 1, 3);
967
968 radv_enc_flush_headers(cmd_buffer);
969 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
970 num_bits[inst_index] = enc->bits_output - bits_copied;
971 bits_copied = enc->bits_output;
972 inst_index++;
973
974 instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_FIRST_SLICE;
975 inst_index++;
976
977 if ((nal_unit_type >= 16) && (nal_unit_type <= 23))
978 radv_enc_code_fixed_bits(cmd_buffer, 0x0, 1);
979
980 radv_enc_code_ue(cmd_buffer, pic->pps_pic_parameter_set_id);
981
982 radv_enc_flush_headers(cmd_buffer);
983 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
984 num_bits[inst_index] = enc->bits_output - bits_copied;
985 bits_copied = enc->bits_output;
986 inst_index++;
987
988 instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_SLICE_SEGMENT;
989 inst_index++;
990
991 instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_DEPENDENT_SLICE_END;
992 inst_index++;
993
994 /* slice_type */
995 switch (pic->pic_type) {
996 case STD_VIDEO_H265_PICTURE_TYPE_I:
997 case STD_VIDEO_H265_PICTURE_TYPE_IDR:
998 radv_enc_code_ue(cmd_buffer, 0x2);
999 break;
1000 case STD_VIDEO_H265_PICTURE_TYPE_P:
1001 radv_enc_code_ue(cmd_buffer, 0x1);
1002 break;
1003 case STD_VIDEO_H265_PICTURE_TYPE_B:
1004 radv_enc_code_ue(cmd_buffer, 0x0);
1005 break;
1006 default:
1007 radv_enc_code_ue(cmd_buffer, 0x1);
1008 }
1009
1010 if ((nal_unit_type != 19) && nal_unit_type != 20) {
1011 /* slice_pic_order_cnt_lsb */
1012 unsigned int max_poc_bits = sps->log2_max_pic_order_cnt_lsb_minus4 + 4;
1013 radv_enc_code_fixed_bits(cmd_buffer, pic->PicOrderCntVal % (1 << max_poc_bits), max_poc_bits);
1014 radv_enc_code_fixed_bits(cmd_buffer, pic->flags.short_term_ref_pic_set_sps_flag, 0x1);
1015 if (!pic->flags.short_term_ref_pic_set_sps_flag) {
1016 int st_rps_idx = sps->num_short_term_ref_pic_sets;
1017 const StdVideoH265ShortTermRefPicSet *rps = &pic->pShortTermRefPicSet[st_rps_idx];
1018
1019 if (st_rps_idx != 0)
1020 radv_enc_code_fixed_bits(cmd_buffer, rps->flags.inter_ref_pic_set_prediction_flag, 0x1);
1021
1022 if (rps->flags.inter_ref_pic_set_prediction_flag) {
1023 int ref_rps_idx = st_rps_idx - (rps->delta_idx_minus1 + 1);
1024 if (st_rps_idx == sps->num_short_term_ref_pic_sets)
1025 radv_enc_code_ue(cmd_buffer, rps->delta_idx_minus1);
1026 radv_enc_code_fixed_bits(cmd_buffer, rps->flags.delta_rps_sign, 0x1);
1027 radv_enc_code_ue(cmd_buffer, rps->abs_delta_rps_minus1);
1028
1029 const StdVideoH265ShortTermRefPicSet *rps_ref = &sps->pShortTermRefPicSet[ref_rps_idx];
1030 int num_delta_pocs = rps_ref->num_negative_pics + rps_ref->num_positive_pics;
1031 for (int j = 0; j < num_delta_pocs; j++) {
1032 radv_enc_code_fixed_bits(cmd_buffer, !!(rps->used_by_curr_pic_flag & (1 << j)), 0x1);
1033 if (!(rps->used_by_curr_pic_flag & (1 << j))) {
1034 radv_enc_code_fixed_bits(cmd_buffer, !!(rps->use_delta_flag & (1 << j)), 0x1);
1035 }
1036 }
1037 } else {
1038 radv_enc_code_ue(cmd_buffer, rps->num_negative_pics);
1039 radv_enc_code_ue(cmd_buffer, rps->num_positive_pics);
1040
1041 for (int i = 0; i < rps->num_negative_pics; i++) {
1042 radv_enc_code_ue(cmd_buffer, rps->delta_poc_s0_minus1[i]);
1043 radv_enc_code_fixed_bits(cmd_buffer, !!(rps->used_by_curr_pic_s0_flag & (1 << i)), 0x1);
1044 }
1045 for (int i = 0; i < rps->num_positive_pics; i++) {
1046 radv_enc_code_ue(cmd_buffer, rps->delta_poc_s1_minus1[i]);
1047 radv_enc_code_fixed_bits(cmd_buffer, !!(rps->used_by_curr_pic_s1_flag & (1 << i)), 0x1);
1048 }
1049 }
1050 } else if (sps->num_short_term_ref_pic_sets > 1)
1051 radv_enc_code_ue(cmd_buffer, pic->short_term_ref_pic_set_idx);
1052
1053 if (sps->flags.sps_temporal_mvp_enabled_flag)
1054 radv_enc_code_fixed_bits(cmd_buffer, pic->flags.slice_temporal_mvp_enabled_flag, 1);
1055 }
1056
1057 if (sps->flags.sample_adaptive_offset_enabled_flag) {
1058 radv_enc_flush_headers(cmd_buffer);
1059 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
1060 num_bits[inst_index] = enc->bits_output - bits_copied;
1061 bits_copied = enc->bits_output;
1062 inst_index++;
1063
1064 instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_SAO_ENABLE;
1065 inst_index++;
1066 }
1067
1068 if ((pic->pic_type == STD_VIDEO_H265_PICTURE_TYPE_P) || (pic->pic_type == STD_VIDEO_H265_PICTURE_TYPE_B)) {
1069 radv_enc_code_fixed_bits(cmd_buffer, slice->flags.num_ref_idx_active_override_flag, 1);
1070 if (slice->flags.num_ref_idx_active_override_flag) {
1071 radv_enc_code_ue(cmd_buffer, pic->pRefLists->num_ref_idx_l0_active_minus1);
1072 if (pic->pic_type == STD_VIDEO_H265_PICTURE_TYPE_B)
1073 radv_enc_code_ue(cmd_buffer, pic->pRefLists->num_ref_idx_l1_active_minus1);
1074 }
1075 if (pic->pic_type == STD_VIDEO_H265_PICTURE_TYPE_B)
1076 radv_enc_code_fixed_bits(cmd_buffer, slice->flags.mvd_l1_zero_flag, 1);
1077 if (pps->flags.cabac_init_present_flag)
1078 radv_enc_code_fixed_bits(cmd_buffer, slice->flags.cabac_init_flag, 1);
1079 if (pic->flags.slice_temporal_mvp_enabled_flag) {
1080 if (pic->pic_type == STD_VIDEO_H265_PICTURE_TYPE_B)
1081 radv_enc_code_fixed_bits(cmd_buffer, slice->flags.collocated_from_l0_flag, 1);
1082 }
1083 radv_enc_code_ue(cmd_buffer, 5 - slice->MaxNumMergeCand);
1084 }
1085
1086 radv_enc_flush_headers(cmd_buffer);
1087 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
1088 num_bits[inst_index] = enc->bits_output - bits_copied;
1089 bits_copied = enc->bits_output;
1090 inst_index++;
1091
1092 instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_SLICE_QP_DELTA;
1093 inst_index++;
1094
1095 if (pps->flags.pps_slice_chroma_qp_offsets_present_flag) {
1096 radv_enc_code_se(cmd_buffer, slice->slice_cb_qp_offset);
1097 radv_enc_code_se(cmd_buffer, slice->slice_cr_qp_offset);
1098 }
1099
1100 if (pps->flags.pps_slice_act_qp_offsets_present_flag) {
1101 radv_enc_code_se(cmd_buffer, slice->slice_act_y_qp_offset);
1102 radv_enc_code_se(cmd_buffer, slice->slice_act_cb_qp_offset);
1103 radv_enc_code_se(cmd_buffer, slice->slice_act_cr_qp_offset);
1104 }
1105
1106 if (pps->flags.chroma_qp_offset_list_enabled_flag) {
1107 radv_enc_code_fixed_bits(cmd_buffer, slice->flags.cu_chroma_qp_offset_enabled_flag, 1);
1108 }
1109
1110 if (pps->flags.deblocking_filter_override_enabled_flag) {
1111 radv_enc_code_fixed_bits(cmd_buffer, slice->flags.deblocking_filter_override_flag, 1);
1112 if (slice->flags.deblocking_filter_override_flag) {
1113 radv_enc_code_fixed_bits(cmd_buffer, slice->flags.slice_deblocking_filter_disabled_flag, 1);
1114 if (!slice->flags.slice_deblocking_filter_disabled_flag) {
1115 radv_enc_code_se(cmd_buffer, slice->slice_beta_offset_div2);
1116 radv_enc_code_se(cmd_buffer, slice->slice_tc_offset_div2);
1117 }
1118 }
1119 }
1120 if ((pps->flags.pps_loop_filter_across_slices_enabled_flag) &&
1121 (!slice->flags.slice_deblocking_filter_disabled_flag || slice->flags.slice_sao_luma_flag ||
1122 slice->flags.slice_sao_chroma_flag)) {
1123
1124 if (slice->flags.slice_sao_luma_flag || slice->flags.slice_sao_chroma_flag) {
1125 instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_LOOP_FILTER_ACROSS_SLICES_ENABLE;
1126 inst_index++;
1127 } else {
1128 radv_enc_code_fixed_bits(cmd_buffer, slice->flags.slice_loop_filter_across_slices_enabled_flag, 1);
1129 radv_enc_flush_headers(cmd_buffer);
1130 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
1131 num_bits[inst_index] = enc->bits_output - bits_copied;
1132 bits_copied = enc->bits_output;
1133 inst_index++;
1134 }
1135 }
1136
1137 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_END;
1138
1139 cdw_filled = cs->cdw - cdw_start;
1140 for (int i = 0; i < RENCODE_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS - cdw_filled; i++)
1141 radeon_emit(cs, 0x00000000);
1142 for (int j = 0; j < RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS; j++) {
1143 radeon_emit(cs, instruction[j]);
1144 radeon_emit(cs, num_bits[j]);
1145 }
1146 ENC_END;
1147 }
1148
1149 static void
radv_enc_ctx(struct radv_cmd_buffer * cmd_buffer,const VkVideoEncodeInfoKHR * info)1150 radv_enc_ctx(struct radv_cmd_buffer *cmd_buffer, const VkVideoEncodeInfoKHR *info)
1151 {
1152 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
1153 const struct radv_physical_device *pdev = radv_device_physical(device);
1154 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1155 struct radv_image_view *dpb_iv = NULL;
1156 struct radv_image *dpb = NULL;
1157 struct radv_image_plane *dpb_luma = NULL;
1158 struct radv_image_plane *dpb_chroma = NULL;
1159 uint64_t va = 0;
1160 uint32_t luma_pitch = 0;
1161 int max_ref_slot_idx = 0;
1162
1163 if (info->pSetupReferenceSlot) {
1164 dpb_iv = radv_image_view_from_handle(info->pSetupReferenceSlot->pPictureResource->imageViewBinding);
1165 if (info->pSetupReferenceSlot->slotIndex > max_ref_slot_idx)
1166 max_ref_slot_idx = info->pSetupReferenceSlot->slotIndex;
1167 }
1168
1169 if (info->referenceSlotCount > 0) {
1170 dpb_iv = radv_image_view_from_handle(info->pReferenceSlots[0].pPictureResource->imageViewBinding);
1171 for (unsigned i = 0; i < info->referenceSlotCount; i++) {
1172 if (info->pReferenceSlots[i].slotIndex > max_ref_slot_idx)
1173 max_ref_slot_idx = info->pReferenceSlots[i].slotIndex;
1174 }
1175 }
1176
1177 if (dpb_iv) {
1178 dpb = dpb_iv->image;
1179 dpb_luma = &dpb->planes[0];
1180 dpb_chroma = &dpb->planes[1];
1181 radv_cs_add_buffer(device->ws, cs, dpb->bindings[0].bo);
1182 va = radv_buffer_get_va(dpb->bindings[0].bo) + dpb->bindings[0].offset; // TODO DPB resource
1183 luma_pitch = dpb_luma->surface.u.gfx9.surf_pitch * dpb_luma->surface.blk_w; // rec_luma_pitch
1184 }
1185
1186 uint32_t swizzle_mode = 0;
1187
1188 if (pdev->enc_hw_ver >= RADV_VIDEO_ENC_HW_4)
1189 swizzle_mode = RENCODE_REC_SWIZZLE_MODE_256B_D;
1190 else if (pdev->enc_hw_ver >= RADV_VIDEO_ENC_HW_2)
1191 swizzle_mode = RENCODE_REC_SWIZZLE_MODE_256B_S;
1192 ENC_BEGIN;
1193 radeon_emit(cs, pdev->vcn_enc_cmds.ctx);
1194 radeon_emit(cs, va >> 32);
1195 radeon_emit(cs, va & 0xffffffff);
1196 radeon_emit(cs, swizzle_mode);
1197 radeon_emit(cs, luma_pitch); // rec_luma_pitch
1198 radeon_emit(cs, luma_pitch); // rec_luma_pitch0); //rec_chromma_pitch
1199 radeon_emit(cs, max_ref_slot_idx + 1); // num_reconstructed_pictures
1200
1201 int i;
1202 for (i = 0; i < max_ref_slot_idx + 1; i++) {
1203 radeon_emit(cs, dpb_luma ? dpb_luma->surface.u.gfx9.surf_offset + i * dpb_luma->surface.u.gfx9.surf_slice_size
1204 : 0); // luma offset
1205 radeon_emit(cs, dpb_chroma
1206 ? dpb_chroma->surface.u.gfx9.surf_offset + i * dpb_chroma->surface.u.gfx9.surf_slice_size
1207 : 0); // chroma offset
1208
1209 if (pdev->enc_hw_ver >= RADV_VIDEO_ENC_HW_4) {
1210 radeon_emit(cs, 0); /* unused offset 1 */
1211 radeon_emit(cs, 0); /* unused offset 2 */
1212 }
1213 }
1214
1215 for (; i < RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES; i++) {
1216 radeon_emit(cs, 0);
1217 radeon_emit(cs, 0);
1218 if (pdev->enc_hw_ver >= RADV_VIDEO_ENC_HW_4) {
1219 radeon_emit(cs, 0); /* unused offset 1 */
1220 radeon_emit(cs, 0); /* unused offset 2 */
1221 }
1222 }
1223
1224 if (pdev->enc_hw_ver == RADV_VIDEO_ENC_HW_3) {
1225 radeon_emit(cs, 0); // colloc buffer offset
1226 }
1227 radeon_emit(cs, 0); // enc pic pre encode luma pitch
1228 radeon_emit(cs, 0); // enc pic pre encode chroma pitch
1229
1230 for (i = 0; i < RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES; i++) {
1231 radeon_emit(cs, 0); // pre encode luma offset
1232 radeon_emit(cs, 0); // pre encode chroma offset
1233 if (pdev->enc_hw_ver >= RADV_VIDEO_ENC_HW_4) {
1234 radeon_emit(cs, 0); /* unused offset 1 */
1235 radeon_emit(cs, 0); /* unused offset 2 */
1236 }
1237 }
1238
1239 if (pdev->enc_hw_ver == RADV_VIDEO_ENC_HW_2) {
1240 radeon_emit(cs, 0); // enc pic yuv luma offset
1241 radeon_emit(cs, 0); // enc pic yuv chroma offset
1242
1243 radeon_emit(cs, 0); // two pass search center map offset
1244
1245 // rgboffsets
1246 radeon_emit(cs, 0); // red
1247 radeon_emit(cs, 0); // green
1248 radeon_emit(cs, 0); // blue
1249 } else if (pdev->enc_hw_ver >= RADV_VIDEO_ENC_HW_3) {
1250 radeon_emit(cs, 0); // red
1251 radeon_emit(cs, 0); // green
1252 radeon_emit(cs, 0); // blue
1253 radeon_emit(cs, 0); // v3 two pass search center map offset
1254 radeon_emit(cs, 0);
1255 if (pdev->enc_hw_ver == RADV_VIDEO_ENC_HW_3) {
1256 radeon_emit(cs, 0);
1257 }
1258 }
1259 ENC_END;
1260 }
1261
1262 static void
radv_enc_bitstream(struct radv_cmd_buffer * cmd_buffer,struct radv_buffer * buffer,VkDeviceSize offset)1263 radv_enc_bitstream(struct radv_cmd_buffer *cmd_buffer, struct radv_buffer *buffer, VkDeviceSize offset)
1264 {
1265 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
1266 const struct radv_physical_device *pdev = radv_device_physical(device);
1267 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1268 uint64_t va = radv_buffer_get_va(buffer->bo) + buffer->offset + offset;
1269 radv_cs_add_buffer(device->ws, cs, buffer->bo);
1270
1271 ENC_BEGIN;
1272 radeon_emit(cs, pdev->vcn_enc_cmds.bitstream);
1273 radeon_emit(cs, RENCODE_REC_SWIZZLE_MODE_LINEAR);
1274 radeon_emit(cs, va >> 32);
1275 radeon_emit(cs, va & 0xffffffff);
1276 radeon_emit(cs, buffer->vk.size);
1277 radeon_emit(cs, 0);
1278 ENC_END;
1279 }
1280
1281 static void
radv_enc_feedback(struct radv_cmd_buffer * cmd_buffer,uint64_t feedback_query_va)1282 radv_enc_feedback(struct radv_cmd_buffer *cmd_buffer, uint64_t feedback_query_va)
1283 {
1284 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
1285 const struct radv_physical_device *pdev = radv_device_physical(device);
1286 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1287 ENC_BEGIN;
1288
1289 radeon_emit(cs, pdev->vcn_enc_cmds.feedback);
1290 radeon_emit(cs, RENCODE_FEEDBACK_BUFFER_MODE_LINEAR);
1291 radeon_emit(cs, feedback_query_va >> 32);
1292 radeon_emit(cs, feedback_query_va & 0xffffffff);
1293 radeon_emit(cs, 16); // buffer_size
1294 radeon_emit(cs, 40); // data_size
1295 ENC_END;
1296 }
1297
1298 static void
radv_enc_intra_refresh(struct radv_cmd_buffer * cmd_buffer)1299 radv_enc_intra_refresh(struct radv_cmd_buffer *cmd_buffer)
1300 {
1301 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
1302 const struct radv_physical_device *pdev = radv_device_physical(device);
1303 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1304 ENC_BEGIN;
1305 radeon_emit(cs, pdev->vcn_enc_cmds.intra_refresh);
1306 radeon_emit(cs, 0); // intra refresh mode
1307 radeon_emit(cs, 0); // intra ref offset
1308 radeon_emit(cs, 0); // intra region size
1309 ENC_END;
1310 }
1311
1312 static void
radv_enc_rc_per_pic(struct radv_cmd_buffer * cmd_buffer,const VkVideoEncodeInfoKHR * enc_info,rvcn_enc_rate_ctl_per_picture_t * per_pic)1313 radv_enc_rc_per_pic(struct radv_cmd_buffer *cmd_buffer, const VkVideoEncodeInfoKHR *enc_info,
1314 rvcn_enc_rate_ctl_per_picture_t *per_pic)
1315 {
1316 struct radv_video_session *vid = cmd_buffer->video.vid;
1317 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
1318 const struct radv_physical_device *pdev = radv_device_physical(device);
1319 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1320
1321 unsigned qp = per_pic->qp_i;
1322
1323 if (vid->enc_rate_control_method == RENCODE_RATE_CONTROL_METHOD_NONE && !vid->enc_rate_control_default) {
1324 switch (vid->vk.op) {
1325 case VK_VIDEO_CODEC_OPERATION_ENCODE_H264_BIT_KHR: {
1326 const struct VkVideoEncodeH264PictureInfoKHR *h264_picture_info =
1327 vk_find_struct_const(enc_info->pNext, VIDEO_ENCODE_H264_PICTURE_INFO_KHR);
1328 const VkVideoEncodeH264NaluSliceInfoKHR *h264_slice = &h264_picture_info->pNaluSliceEntries[0];
1329 qp = h264_slice->constantQp;
1330 break;
1331 }
1332 case VK_VIDEO_CODEC_OPERATION_ENCODE_H265_BIT_KHR: {
1333 const struct VkVideoEncodeH265PictureInfoKHR *h265_picture_info =
1334 vk_find_struct_const(enc_info->pNext, VIDEO_ENCODE_H265_PICTURE_INFO_KHR);
1335 const VkVideoEncodeH265NaluSliceSegmentInfoKHR *h265_slice = &h265_picture_info->pNaluSliceSegmentEntries[0];
1336 qp = h265_slice->constantQp;
1337 break;
1338 }
1339 default:
1340 break;
1341 }
1342 }
1343 ENC_BEGIN;
1344 radeon_emit(cs, pdev->vcn_enc_cmds.rc_per_pic);
1345 radeon_emit(cs, qp); // qp_i
1346 radeon_emit(cs, qp); // qp_p
1347 radeon_emit(cs, qp); // qp_b
1348 radeon_emit(cs, per_pic->min_qp_i);
1349 radeon_emit(cs, per_pic->max_qp_i);
1350 radeon_emit(cs, per_pic->min_qp_p);
1351 radeon_emit(cs, per_pic->max_qp_p);
1352 radeon_emit(cs, per_pic->min_qp_b);
1353 radeon_emit(cs, per_pic->max_qp_b);
1354 radeon_emit(cs, per_pic->max_au_size_i);
1355 radeon_emit(cs, per_pic->max_au_size_p);
1356 radeon_emit(cs, per_pic->max_au_size_b);
1357 radeon_emit(cs, per_pic->enabled_filler_data);
1358 radeon_emit(cs, per_pic->skip_frame_enable);
1359 radeon_emit(cs, per_pic->enforce_hrd);
1360 radeon_emit(cs, 0xFFFFFFFF); // reserved_0xff
1361 ENC_END;
1362 }
1363
1364 static void
radv_enc_params(struct radv_cmd_buffer * cmd_buffer,const VkVideoEncodeInfoKHR * enc_info)1365 radv_enc_params(struct radv_cmd_buffer *cmd_buffer, const VkVideoEncodeInfoKHR *enc_info)
1366 {
1367 const struct VkVideoEncodeH264PictureInfoKHR *h264_picture_info =
1368 vk_find_struct_const(enc_info->pNext, VIDEO_ENCODE_H264_PICTURE_INFO_KHR);
1369 const struct VkVideoEncodeH265PictureInfoKHR *h265_picture_info =
1370 vk_find_struct_const(enc_info->pNext, VIDEO_ENCODE_H265_PICTURE_INFO_KHR);
1371 const StdVideoEncodeH264PictureInfo *h264_pic = h264_picture_info ? h264_picture_info->pStdPictureInfo : NULL;
1372 const StdVideoEncodeH265PictureInfo *h265_pic = h265_picture_info ? h265_picture_info->pStdPictureInfo : NULL;
1373 struct radv_image_view *src_iv = radv_image_view_from_handle(enc_info->srcPictureResource.imageViewBinding);
1374 struct radv_image *src_img = src_iv->image;
1375 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
1376 const struct radv_physical_device *pdev = radv_device_physical(device);
1377 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1378 uint64_t va = radv_buffer_get_va(src_img->bindings[0].bo) + src_img->bindings[0].offset;
1379 uint64_t luma_va = va + src_img->planes[0].surface.u.gfx9.surf_offset;
1380 uint64_t chroma_va = va + src_img->planes[1].surface.u.gfx9.surf_offset;
1381 uint32_t pic_type;
1382 unsigned int slot_idx = 0xffffffff;
1383 unsigned int max_layers = cmd_buffer->video.vid->rc_layer_control.max_num_temporal_layers;
1384
1385 radv_cs_add_buffer(device->ws, cs, src_img->bindings[0].bo);
1386 if (h264_pic) {
1387 switch (h264_pic->primary_pic_type) {
1388 case STD_VIDEO_H264_PICTURE_TYPE_P:
1389 slot_idx = enc_info->pReferenceSlots[0].slotIndex;
1390 pic_type = RENCODE_PICTURE_TYPE_P;
1391 break;
1392 case STD_VIDEO_H264_PICTURE_TYPE_B:
1393 slot_idx = enc_info->pReferenceSlots[0].slotIndex;
1394 pic_type = RENCODE_PICTURE_TYPE_B;
1395 break;
1396 case STD_VIDEO_H264_PICTURE_TYPE_I:
1397 case STD_VIDEO_H264_PICTURE_TYPE_IDR:
1398 default:
1399 pic_type = RENCODE_PICTURE_TYPE_I;
1400 break;
1401 }
1402 radv_enc_layer_select(cmd_buffer, MIN2(h264_pic->temporal_id, max_layers));
1403 } else if (h265_pic) {
1404 switch (h265_pic->pic_type) {
1405 case STD_VIDEO_H265_PICTURE_TYPE_P:
1406 slot_idx = enc_info->pReferenceSlots[0].slotIndex;
1407 pic_type = RENCODE_PICTURE_TYPE_P;
1408 break;
1409 case STD_VIDEO_H265_PICTURE_TYPE_B:
1410 slot_idx = enc_info->pReferenceSlots[0].slotIndex;
1411 pic_type = RENCODE_PICTURE_TYPE_B;
1412 break;
1413 case STD_VIDEO_H265_PICTURE_TYPE_I:
1414 case STD_VIDEO_H265_PICTURE_TYPE_IDR:
1415 default:
1416 pic_type = RENCODE_PICTURE_TYPE_I;
1417 break;
1418 }
1419 radv_enc_layer_select(cmd_buffer, MIN2(h265_pic->TemporalId, max_layers));
1420 } else {
1421 assert(0);
1422 return;
1423 }
1424
1425 ENC_BEGIN;
1426 radeon_emit(cs, pdev->vcn_enc_cmds.enc_params);
1427 radeon_emit(cs, pic_type); // pic type
1428 radeon_emit(cs, enc_info->dstBufferRange); // allowed max bitstream size
1429 radeon_emit(cs, luma_va >> 32);
1430 radeon_emit(cs, luma_va & 0xffffffff);
1431 radeon_emit(cs, chroma_va >> 32);
1432 radeon_emit(cs, chroma_va & 0xffffffff);
1433 radeon_emit(cs, src_img->planes[0].surface.u.gfx9.surf_pitch); // luma pitch
1434 radeon_emit(cs, src_img->planes[1].surface.u.gfx9.surf_pitch); // chroma pitch
1435 radeon_emit(cs, src_img->planes[0].surface.u.gfx9.swizzle_mode); // swizzle mode
1436 radeon_emit(cs, slot_idx); // ref0_idx
1437
1438 if (enc_info->pSetupReferenceSlot)
1439 radeon_emit(cs, enc_info->pSetupReferenceSlot->slotIndex); // reconstructed picture index
1440 else
1441 radeon_emit(cs, 0);
1442 ENC_END;
1443 }
1444
1445 static void
radv_enc_params_h264(struct radv_cmd_buffer * cmd_buffer)1446 radv_enc_params_h264(struct radv_cmd_buffer *cmd_buffer)
1447 {
1448 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
1449 const struct radv_physical_device *pdev = radv_device_physical(device);
1450 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1451 ENC_BEGIN;
1452 radeon_emit(cs, pdev->vcn_enc_cmds.enc_params_h264);
1453
1454 if (pdev->enc_hw_ver < RADV_VIDEO_ENC_HW_3) {
1455 radeon_emit(cs, RENCODE_H264_PICTURE_STRUCTURE_FRAME);
1456 radeon_emit(cs, RENCODE_H264_INTERLACING_MODE_PROGRESSIVE);
1457 radeon_emit(cs, RENCODE_H264_PICTURE_STRUCTURE_FRAME);
1458 radeon_emit(cs, 0xffffffff); // reference_picture1_index
1459 } else {
1460 // V3
1461 radeon_emit(cs, RENCODE_H264_PICTURE_STRUCTURE_FRAME);
1462 radeon_emit(cs, 0); // input pic order cnt
1463 radeon_emit(cs, RENCODE_H264_INTERLACING_MODE_PROGRESSIVE);
1464 radeon_emit(cs, 0); // l0 ref pic0 pic_type
1465 radeon_emit(cs, 0); // l0 ref pic0 is long term
1466 radeon_emit(cs, 0); // l0 ref pic0 picture structure
1467 radeon_emit(cs, 0); // l0 ref pic0 pic order cnt
1468 radeon_emit(cs, 0xffffffff); // l0 ref pic1 index
1469 radeon_emit(cs, 0); // l0 ref pic1 pic_type
1470 radeon_emit(cs, 0); // l0 ref pic1 is long term
1471 radeon_emit(cs, 0); // l0 ref pic1 picture structure
1472 radeon_emit(cs, 0); // l0 ref pic1 pic order cnt
1473 radeon_emit(cs, 0xffffffff); // l1 ref pic0 index
1474 radeon_emit(cs, 0); // l1 ref pic0 pic_type
1475 radeon_emit(cs, 0); // l1 ref pic0 is long term
1476 radeon_emit(cs, 0); // l1 ref pic0 picture structure
1477 radeon_emit(cs, 0); // l1 ref pic0 pic order cnt
1478 }
1479 ENC_END;
1480 }
1481
1482 static void
radv_enc_op_init(struct radv_cmd_buffer * cmd_buffer)1483 radv_enc_op_init(struct radv_cmd_buffer *cmd_buffer)
1484 {
1485 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1486 ENC_BEGIN;
1487 radeon_emit(cs, RENCODE_IB_OP_INITIALIZE);
1488 ENC_END;
1489 }
1490
1491 static void
radv_enc_op_enc(struct radv_cmd_buffer * cmd_buffer)1492 radv_enc_op_enc(struct radv_cmd_buffer *cmd_buffer)
1493 {
1494 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1495 ENC_BEGIN;
1496 radeon_emit(cs, RENCODE_IB_OP_ENCODE);
1497 ENC_END;
1498 }
1499
1500 static void
radv_enc_op_init_rc(struct radv_cmd_buffer * cmd_buffer)1501 radv_enc_op_init_rc(struct radv_cmd_buffer *cmd_buffer)
1502 {
1503 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1504 ENC_BEGIN;
1505 radeon_emit(cs, RENCODE_IB_OP_INIT_RC);
1506 ENC_END;
1507 }
1508
1509 static void
radv_enc_op_init_rc_vbv(struct radv_cmd_buffer * cmd_buffer)1510 radv_enc_op_init_rc_vbv(struct radv_cmd_buffer *cmd_buffer)
1511 {
1512 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1513 ENC_BEGIN;
1514 radeon_emit(cs, RENCODE_IB_OP_INIT_RC_VBV_BUFFER_LEVEL);
1515 ENC_END;
1516 }
1517
1518 static void
radv_enc_op_preset(struct radv_cmd_buffer * cmd_buffer,const VkVideoEncodeInfoKHR * enc_info)1519 radv_enc_op_preset(struct radv_cmd_buffer *cmd_buffer, const VkVideoEncodeInfoKHR *enc_info)
1520 {
1521 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1522 struct radv_video_session *vid = cmd_buffer->video.vid;
1523 uint32_t preset_mode;
1524
1525 if (vid->enc_preset_mode == RENCODE_PRESET_MODE_QUALITY)
1526 preset_mode = RENCODE_IB_OP_SET_QUALITY_ENCODING_MODE;
1527 else if (vid->enc_preset_mode == RENCODE_PRESET_MODE_BALANCE)
1528 preset_mode = RENCODE_IB_OP_SET_BALANCE_ENCODING_MODE;
1529 else
1530 preset_mode = RENCODE_IB_OP_SET_SPEED_ENCODING_MODE;
1531
1532 switch (vid->vk.op) {
1533 case VK_VIDEO_CODEC_OPERATION_ENCODE_H265_BIT_KHR: {
1534 const struct VkVideoEncodeH265PictureInfoKHR *h265_picture_info =
1535 vk_find_struct_const(enc_info->pNext, VIDEO_ENCODE_H265_PICTURE_INFO_KHR);
1536 const StdVideoEncodeH265PictureInfo *pic = h265_picture_info->pStdPictureInfo;
1537 const StdVideoH265SequenceParameterSet *sps =
1538 vk_video_find_h265_enc_std_sps(&cmd_buffer->video.params->vk, pic->pps_seq_parameter_set_id);
1539 if (sps->flags.sample_adaptive_offset_enabled_flag && vid->enc_preset_mode == RENCODE_PRESET_MODE_SPEED)
1540 preset_mode = RENCODE_IB_OP_SET_BALANCE_ENCODING_MODE;
1541 break;
1542 }
1543 default:
1544 break;
1545 }
1546
1547 ENC_BEGIN;
1548 radeon_emit(cs, preset_mode);
1549 ENC_END;
1550 }
1551
1552 static void
radv_enc_input_format(struct radv_cmd_buffer * cmd_buffer)1553 radv_enc_input_format(struct radv_cmd_buffer *cmd_buffer)
1554 {
1555 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
1556 const struct radv_physical_device *pdev = radv_device_physical(device);
1557 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1558 struct radv_video_session *vid = cmd_buffer->video.vid;
1559 uint32_t color_bit_depth;
1560 uint32_t color_packing_format;
1561
1562 switch (vid->vk.picture_format) {
1563 case VK_FORMAT_G8_B8R8_2PLANE_420_UNORM:
1564 color_bit_depth = RENCODE_COLOR_BIT_DEPTH_8_BIT;
1565 color_packing_format = RENCODE_COLOR_PACKING_FORMAT_NV12;
1566 break;
1567 case VK_FORMAT_G10X6_B10X6R10X6_2PLANE_420_UNORM_3PACK16:
1568 color_bit_depth = RENCODE_COLOR_BIT_DEPTH_10_BIT;
1569 color_packing_format = RENCODE_COLOR_PACKING_FORMAT_P010;
1570 break;
1571 default:
1572 assert(0);
1573 return;
1574 }
1575
1576 ENC_BEGIN;
1577 radeon_emit(cs, pdev->vcn_enc_cmds.input_format);
1578 radeon_emit(cs, 0); // input color volume
1579 radeon_emit(cs, 0); // input color space
1580 radeon_emit(cs, RENCODE_COLOR_RANGE_STUDIO); // input color range
1581 radeon_emit(cs, 0); // input chroma subsampling
1582 radeon_emit(cs, 0); // input chroma location
1583 radeon_emit(cs, color_bit_depth); // input color bit depth
1584 radeon_emit(cs, color_packing_format); // input color packing format
1585 ENC_END;
1586 }
1587
1588 static void
radv_enc_output_format(struct radv_cmd_buffer * cmd_buffer)1589 radv_enc_output_format(struct radv_cmd_buffer *cmd_buffer)
1590 {
1591 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
1592 const struct radv_physical_device *pdev = radv_device_physical(device);
1593 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1594 struct radv_video_session *vid = cmd_buffer->video.vid;
1595 uint32_t color_bit_depth;
1596
1597 switch (vid->vk.op) {
1598 case VK_VIDEO_CODEC_OPERATION_ENCODE_H264_BIT_KHR:
1599 color_bit_depth = RENCODE_COLOR_BIT_DEPTH_8_BIT;
1600 break;
1601 case VK_VIDEO_CODEC_OPERATION_ENCODE_H265_BIT_KHR:
1602 if (vid->vk.h265.profile_idc == STD_VIDEO_H265_PROFILE_IDC_MAIN_10)
1603 color_bit_depth = RENCODE_COLOR_BIT_DEPTH_10_BIT;
1604 else
1605 color_bit_depth = RENCODE_COLOR_BIT_DEPTH_8_BIT;
1606 break;
1607 default:
1608 assert(0);
1609 return;
1610 }
1611
1612 ENC_BEGIN;
1613 radeon_emit(cs, pdev->vcn_enc_cmds.output_format);
1614 radeon_emit(cs, 0); // output color volume
1615 radeon_emit(cs, RENCODE_COLOR_RANGE_STUDIO); // output color range
1616 radeon_emit(cs, 0); // output chroma location
1617 radeon_emit(cs, color_bit_depth); // output color bit depth
1618 ENC_END;
1619 }
1620
1621 static void
radv_enc_headers_h264(struct radv_cmd_buffer * cmd_buffer,const VkVideoEncodeInfoKHR * enc_info)1622 radv_enc_headers_h264(struct radv_cmd_buffer *cmd_buffer, const VkVideoEncodeInfoKHR *enc_info)
1623 {
1624 radv_enc_slice_header(cmd_buffer, enc_info);
1625 radv_enc_params(cmd_buffer, enc_info);
1626 radv_enc_params_h264(cmd_buffer);
1627 }
1628
1629 static void
radv_enc_headers_hevc(struct radv_cmd_buffer * cmd_buffer,const VkVideoEncodeInfoKHR * enc_info)1630 radv_enc_headers_hevc(struct radv_cmd_buffer *cmd_buffer, const VkVideoEncodeInfoKHR *enc_info)
1631 {
1632 radv_enc_slice_header_hevc(cmd_buffer, enc_info);
1633 radv_enc_params(cmd_buffer, enc_info);
1634 }
1635
1636 static void
begin(struct radv_cmd_buffer * cmd_buffer,const VkVideoEncodeInfoKHR * enc_info)1637 begin(struct radv_cmd_buffer *cmd_buffer, const VkVideoEncodeInfoKHR *enc_info)
1638 {
1639 struct radv_video_session *vid = cmd_buffer->video.vid;
1640
1641 radv_enc_op_init(cmd_buffer);
1642 radv_enc_session_init(cmd_buffer, enc_info);
1643 if (vid->vk.op == VK_VIDEO_CODEC_OPERATION_ENCODE_H264_BIT_KHR) {
1644 radv_enc_slice_control(cmd_buffer, enc_info);
1645 radv_enc_spec_misc_h264(cmd_buffer, enc_info);
1646 radv_enc_deblocking_filter_h264(cmd_buffer, enc_info);
1647 } else if (vid->vk.op == VK_VIDEO_CODEC_OPERATION_ENCODE_H265_BIT_KHR) {
1648 radv_enc_slice_control_hevc(cmd_buffer, enc_info);
1649 radv_enc_spec_misc_hevc(cmd_buffer, enc_info);
1650 radv_enc_deblocking_filter_hevc(cmd_buffer, enc_info);
1651 }
1652 radv_enc_layer_control(cmd_buffer, &vid->rc_layer_control);
1653 radv_enc_rc_session_init(cmd_buffer);
1654 radv_enc_quality_params(cmd_buffer);
1655 // temporal layers init
1656 unsigned i = 0;
1657 do {
1658 radv_enc_layer_select(cmd_buffer, i);
1659 radv_enc_rc_layer_init(cmd_buffer, &vid->rc_layer_init[i]);
1660 radv_enc_layer_select(cmd_buffer, i);
1661 radv_enc_rc_per_pic(cmd_buffer, enc_info, &vid->rc_per_pic[i]);
1662 } while (++i < vid->rc_layer_control.num_temporal_layers);
1663 radv_enc_op_init_rc(cmd_buffer);
1664 radv_enc_op_init_rc_vbv(cmd_buffer);
1665 }
1666
1667 static void
radv_vcn_encode_video(struct radv_cmd_buffer * cmd_buffer,const VkVideoEncodeInfoKHR * enc_info)1668 radv_vcn_encode_video(struct radv_cmd_buffer *cmd_buffer, const VkVideoEncodeInfoKHR *enc_info)
1669 {
1670 VK_FROM_HANDLE(radv_buffer, dst_buffer, enc_info->dstBuffer);
1671 struct radv_video_session *vid = cmd_buffer->video.vid;
1672 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
1673 const struct radv_physical_device *pdev = radv_device_physical(device);
1674 struct radv_enc_state *enc = &cmd_buffer->video.enc;
1675 uint64_t feedback_query_va;
1676 switch (vid->vk.op) {
1677 case VK_VIDEO_CODEC_OPERATION_ENCODE_H264_BIT_KHR:
1678 case VK_VIDEO_CODEC_OPERATION_ENCODE_H265_BIT_KHR:
1679 break;
1680 default:
1681 assert(0);
1682 return;
1683 }
1684
1685 radeon_check_space(device->ws, cmd_buffer->cs, 1024);
1686
1687 if (pdev->enc_hw_ver >= RADV_VIDEO_ENC_HW_4)
1688 radv_vcn_sq_header(cmd_buffer->cs, &cmd_buffer->video.sq, RADEON_VCN_ENGINE_TYPE_ENCODE, false);
1689
1690 const struct VkVideoInlineQueryInfoKHR *inline_queries = NULL;
1691 if (vid->vk.flags & VK_VIDEO_SESSION_CREATE_INLINE_QUERIES_BIT_KHR) {
1692 inline_queries = vk_find_struct_const(enc_info->pNext, VIDEO_INLINE_QUERY_INFO_KHR);
1693
1694 if (inline_queries) {
1695 VK_FROM_HANDLE(radv_query_pool, pool, inline_queries->queryPool);
1696
1697 radv_cs_add_buffer(device->ws, cmd_buffer->cs, pool->bo);
1698
1699 feedback_query_va = radv_buffer_get_va(pool->bo);
1700 feedback_query_va += pool->stride * inline_queries->firstQuery;
1701 }
1702 }
1703
1704 if (!inline_queries)
1705 feedback_query_va = cmd_buffer->video.feedback_query_va;
1706
1707 // before encode
1708 // session info
1709 radv_enc_session_info(cmd_buffer);
1710
1711 cmd_buffer->video.enc.total_task_size = 0;
1712
1713 // task info
1714 radv_enc_task_info(cmd_buffer, true);
1715
1716 if (vid->enc_need_begin) {
1717 begin(cmd_buffer, enc_info);
1718 vid->enc_need_begin = false;
1719 } else {
1720 // temporal layers init
1721 unsigned i = 0;
1722 do {
1723 if (vid->enc_need_rate_control) {
1724 radv_enc_layer_select(cmd_buffer, i);
1725 radv_enc_rc_layer_init(cmd_buffer, &vid->rc_layer_init[i]);
1726 vid->enc_need_rate_control = false;
1727 }
1728 radv_enc_layer_select(cmd_buffer, i);
1729 radv_enc_rc_per_pic(cmd_buffer, enc_info, &vid->rc_per_pic[i]);
1730 } while (++i < vid->rc_layer_control.num_temporal_layers);
1731 }
1732
1733 // encode headers
1734 // ctx
1735 if (vid->vk.op == VK_VIDEO_CODEC_OPERATION_ENCODE_H264_BIT_KHR) {
1736 radv_enc_headers_h264(cmd_buffer, enc_info);
1737 radv_enc_ctx(cmd_buffer, enc_info);
1738 } else if (vid->vk.op == VK_VIDEO_CODEC_OPERATION_ENCODE_H265_BIT_KHR) {
1739 radv_enc_headers_hevc(cmd_buffer, enc_info);
1740 radv_enc_ctx(cmd_buffer, enc_info);
1741 }
1742 // bitstream
1743 radv_enc_bitstream(cmd_buffer, dst_buffer, enc_info->dstBufferOffset);
1744
1745 // feedback
1746 radv_enc_feedback(cmd_buffer, feedback_query_va);
1747
1748 // v2 encode statistics
1749 if (pdev->enc_hw_ver >= RADV_VIDEO_ENC_HW_2) {
1750 }
1751 // intra_refresh
1752 radv_enc_intra_refresh(cmd_buffer);
1753 // v2 input format
1754 if (pdev->enc_hw_ver >= RADV_VIDEO_ENC_HW_2) {
1755 radv_enc_input_format(cmd_buffer);
1756 radv_enc_output_format(cmd_buffer);
1757 }
1758 // v2 output format
1759
1760 // op_preset
1761 radv_enc_op_preset(cmd_buffer, enc_info);
1762 // op_enc
1763 radv_enc_op_enc(cmd_buffer);
1764
1765 radeon_emit_direct(cmd_buffer->cs, enc->task_size_offset, enc->total_task_size);
1766
1767 if (pdev->enc_hw_ver >= RADV_VIDEO_ENC_HW_4)
1768 radv_vcn_sq_tail(cmd_buffer->cs, &cmd_buffer->video.sq);
1769 }
1770
1771 static void
set_rate_control_defaults(struct radv_video_session * vid)1772 set_rate_control_defaults(struct radv_video_session *vid)
1773 {
1774 uint32_t frame_rate_den = 1, frame_rate_num = 30;
1775 vid->enc_rate_control_method = RENCODE_RATE_CONTROL_METHOD_NONE;
1776 vid->enc_vbv_buffer_level = 64;
1777 vid->rc_layer_control.num_temporal_layers = 1;
1778 vid->rc_layer_control.max_num_temporal_layers = 1;
1779 vid->rc_per_pic[0].qp_i = 26;
1780 vid->rc_per_pic[0].qp_p = 26;
1781 vid->rc_per_pic[0].qp_b = 26;
1782 vid->rc_per_pic[0].min_qp_i = 0;
1783 vid->rc_per_pic[0].max_qp_i = 51;
1784 vid->rc_per_pic[0].min_qp_p = 0;
1785 vid->rc_per_pic[0].max_qp_p = 51;
1786 vid->rc_per_pic[0].min_qp_b = 0;
1787 vid->rc_per_pic[0].max_qp_b = 51;
1788 vid->rc_per_pic[0].max_au_size_i = 0;
1789 vid->rc_per_pic[0].max_au_size_p = 0;
1790 vid->rc_per_pic[0].max_au_size_b = 0;
1791 vid->rc_per_pic[0].enabled_filler_data = 1;
1792 vid->rc_per_pic[0].skip_frame_enable = 0;
1793 vid->rc_per_pic[0].enforce_hrd = 1;
1794 vid->rc_layer_init[0].frame_rate_den = frame_rate_den;
1795 vid->rc_layer_init[0].frame_rate_num = frame_rate_num;
1796 vid->rc_layer_init[0].vbv_buffer_size = 20000000; // rate_control->virtualBufferSizeInMs;
1797 vid->rc_layer_init[0].target_bit_rate = 16000;
1798 vid->rc_layer_init[0].peak_bit_rate = 32000;
1799 vid->rc_layer_init[0].avg_target_bits_per_picture =
1800 radv_vcn_per_frame_integer(16000, frame_rate_den, frame_rate_num);
1801 vid->rc_layer_init[0].peak_bits_per_picture_integer =
1802 radv_vcn_per_frame_integer(32000, frame_rate_den, frame_rate_num);
1803 vid->rc_layer_init[0].peak_bits_per_picture_fractional =
1804 radv_vcn_per_frame_frac(32000, frame_rate_den, frame_rate_num);
1805 return;
1806 }
1807
1808 void
radv_video_enc_control_video_coding(struct radv_cmd_buffer * cmd_buffer,const VkVideoCodingControlInfoKHR * control_info)1809 radv_video_enc_control_video_coding(struct radv_cmd_buffer *cmd_buffer, const VkVideoCodingControlInfoKHR *control_info)
1810 {
1811 struct radv_video_session *vid = cmd_buffer->video.vid;
1812
1813 switch (vid->vk.op) {
1814 case VK_VIDEO_CODEC_OPERATION_ENCODE_H264_BIT_KHR:
1815 case VK_VIDEO_CODEC_OPERATION_ENCODE_H265_BIT_KHR:
1816 break;
1817 default:
1818 unreachable("Unsupported\n");
1819 }
1820
1821 if (control_info->flags & VK_VIDEO_CODING_CONTROL_RESET_BIT_KHR) {
1822 set_rate_control_defaults(vid);
1823 vid->enc_need_begin = true;
1824 }
1825
1826 if (control_info->flags & VK_VIDEO_CODING_CONTROL_ENCODE_RATE_CONTROL_BIT_KHR) {
1827 const VkVideoEncodeRateControlInfoKHR *rate_control = (VkVideoEncodeRateControlInfoKHR *)vk_find_struct_const(
1828 control_info->pNext, VIDEO_ENCODE_RATE_CONTROL_INFO_KHR);
1829
1830 assert(rate_control);
1831 const VkVideoEncodeH264RateControlInfoKHR *h264_rate_control =
1832 (VkVideoEncodeH264RateControlInfoKHR *)vk_find_struct_const(rate_control->pNext,
1833 VIDEO_ENCODE_H264_RATE_CONTROL_INFO_KHR);
1834 const VkVideoEncodeH265RateControlInfoKHR *h265_rate_control =
1835 (VkVideoEncodeH265RateControlInfoKHR *)vk_find_struct_const(rate_control->pNext,
1836 VIDEO_ENCODE_H265_RATE_CONTROL_INFO_KHR);
1837
1838 uint32_t rate_control_method = RENCODE_RATE_CONTROL_METHOD_NONE;
1839
1840 vid->enc_rate_control_default = false;
1841
1842 if (rate_control->rateControlMode == VK_VIDEO_ENCODE_RATE_CONTROL_MODE_DEFAULT_KHR) {
1843 vid->enc_rate_control_default = true;
1844 set_rate_control_defaults(vid);
1845 } else if (rate_control->rateControlMode == VK_VIDEO_ENCODE_RATE_CONTROL_MODE_CBR_BIT_KHR)
1846 rate_control_method = RENCODE_RATE_CONTROL_METHOD_CBR;
1847 else if (rate_control->rateControlMode == VK_VIDEO_ENCODE_RATE_CONTROL_MODE_VBR_BIT_KHR)
1848 rate_control_method = RENCODE_RATE_CONTROL_METHOD_PEAK_CONSTRAINED_VBR;
1849
1850 vid->enc_need_rate_control = true;
1851 if (vid->enc_rate_control_method != rate_control_method)
1852 vid->enc_need_begin = true;
1853
1854 vid->enc_rate_control_method = rate_control_method;
1855
1856 if (rate_control->rateControlMode == VK_VIDEO_ENCODE_RATE_CONTROL_MODE_DEFAULT_KHR)
1857 return;
1858
1859 if (h264_rate_control) {
1860 vid->rc_layer_control.max_num_temporal_layers = h264_rate_control->temporalLayerCount;
1861 vid->rc_layer_control.num_temporal_layers = h264_rate_control->temporalLayerCount;
1862 } else if (h265_rate_control) {
1863 vid->rc_layer_control.max_num_temporal_layers = h265_rate_control->subLayerCount;
1864 vid->rc_layer_control.num_temporal_layers = h265_rate_control->subLayerCount;
1865 }
1866
1867 for (unsigned l = 0; l < rate_control->layerCount; l++) {
1868 const VkVideoEncodeRateControlLayerInfoKHR *layer = &rate_control->pLayers[l];
1869 const VkVideoEncodeH264RateControlLayerInfoKHR *h264_layer =
1870 (VkVideoEncodeH264RateControlLayerInfoKHR *)vk_find_struct_const(
1871 layer->pNext, VIDEO_ENCODE_H264_RATE_CONTROL_LAYER_INFO_KHR);
1872 const VkVideoEncodeH265RateControlLayerInfoKHR *h265_layer =
1873 (VkVideoEncodeH265RateControlLayerInfoKHR *)vk_find_struct_const(
1874 layer->pNext, VIDEO_ENCODE_H265_RATE_CONTROL_LAYER_INFO_KHR);
1875 uint32_t frame_rate_den, frame_rate_num;
1876 vid->rc_layer_init[l].target_bit_rate = layer->averageBitrate;
1877 vid->rc_layer_init[l].peak_bit_rate = layer->maxBitrate;
1878 frame_rate_den = layer->frameRateDenominator;
1879 frame_rate_num = layer->frameRateNumerator;
1880 radv_vcn_enc_invalid_frame_rate(&frame_rate_den, &frame_rate_num);
1881 vid->rc_layer_init[l].frame_rate_den = frame_rate_den;
1882 vid->rc_layer_init[l].frame_rate_num = frame_rate_num;
1883 vid->rc_layer_init[l].vbv_buffer_size =
1884 (rate_control->virtualBufferSizeInMs / 1000.) * layer->averageBitrate;
1885 vid->rc_layer_init[l].avg_target_bits_per_picture =
1886 radv_vcn_per_frame_integer(layer->averageBitrate, frame_rate_den, frame_rate_num);
1887 vid->rc_layer_init[l].peak_bits_per_picture_integer =
1888 radv_vcn_per_frame_integer(layer->maxBitrate, frame_rate_den, frame_rate_num);
1889 vid->rc_layer_init[l].peak_bits_per_picture_fractional =
1890 radv_vcn_per_frame_frac(layer->maxBitrate, frame_rate_den, frame_rate_num);
1891
1892 if (h264_layer) {
1893 vid->rc_per_pic[l].min_qp_i = h264_layer->useMinQp ? h264_layer->minQp.qpI : 0;
1894 vid->rc_per_pic[l].min_qp_p = h264_layer->useMinQp ? h264_layer->minQp.qpP : 0;
1895 vid->rc_per_pic[l].min_qp_b = h264_layer->useMinQp ? h264_layer->minQp.qpB : 0;
1896 vid->rc_per_pic[l].max_qp_i = h264_layer->useMaxQp ? h264_layer->maxQp.qpI : 51;
1897 vid->rc_per_pic[l].max_qp_p = h264_layer->useMaxQp ? h264_layer->maxQp.qpP : 51;
1898 vid->rc_per_pic[l].max_qp_b = h264_layer->useMaxQp ? h264_layer->maxQp.qpB : 51;
1899 vid->rc_per_pic[l].max_au_size_i = h264_layer->useMaxFrameSize ? h264_layer->maxFrameSize.frameISize : 0;
1900 vid->rc_per_pic[l].max_au_size_p = h264_layer->useMaxFrameSize ? h264_layer->maxFrameSize.framePSize : 0;
1901 vid->rc_per_pic[l].max_au_size_b = h264_layer->useMaxFrameSize ? h264_layer->maxFrameSize.frameBSize : 0;
1902 } else if (h265_layer) {
1903 vid->rc_per_pic[l].min_qp_i = h265_layer->useMinQp ? h265_layer->minQp.qpI : 0;
1904 vid->rc_per_pic[l].min_qp_p = h265_layer->useMinQp ? h265_layer->minQp.qpP : 0;
1905 vid->rc_per_pic[l].min_qp_b = h265_layer->useMinQp ? h265_layer->minQp.qpB : 0;
1906 vid->rc_per_pic[l].max_qp_i = h265_layer->useMaxQp ? h265_layer->maxQp.qpI : 51;
1907 vid->rc_per_pic[l].max_qp_p = h265_layer->useMaxQp ? h265_layer->maxQp.qpP : 51;
1908 vid->rc_per_pic[l].max_qp_b = h265_layer->useMaxQp ? h265_layer->maxQp.qpB : 51;
1909 vid->rc_per_pic[l].max_au_size_i = h265_layer->useMaxFrameSize ? h265_layer->maxFrameSize.frameISize : 0;
1910 vid->rc_per_pic[l].max_au_size_p = h265_layer->useMaxFrameSize ? h265_layer->maxFrameSize.framePSize : 0;
1911 vid->rc_per_pic[l].max_au_size_b = h265_layer->useMaxFrameSize ? h265_layer->maxFrameSize.frameBSize : 0;
1912 }
1913
1914 vid->rc_per_pic[l].enabled_filler_data = 1;
1915 vid->rc_per_pic[l].skip_frame_enable = 0;
1916 vid->rc_per_pic[l].enforce_hrd = 1;
1917 }
1918
1919 if (rate_control->virtualBufferSizeInMs > 0)
1920 vid->enc_vbv_buffer_level =
1921 lroundf((float)rate_control->initialVirtualBufferSizeInMs / rate_control->virtualBufferSizeInMs * 64);
1922 }
1923 }
1924
1925 VKAPI_ATTR void VKAPI_CALL
radv_CmdEncodeVideoKHR(VkCommandBuffer commandBuffer,const VkVideoEncodeInfoKHR * pEncodeInfo)1926 radv_CmdEncodeVideoKHR(VkCommandBuffer commandBuffer, const VkVideoEncodeInfoKHR *pEncodeInfo)
1927 {
1928 VK_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1929 radv_vcn_encode_video(cmd_buffer, pEncodeInfo);
1930 }
1931
1932 VKAPI_ATTR VkResult VKAPI_CALL
radv_GetPhysicalDeviceVideoEncodeQualityLevelPropertiesKHR(VkPhysicalDevice physicalDevice,const VkPhysicalDeviceVideoEncodeQualityLevelInfoKHR * pQualityLevelInfo,VkVideoEncodeQualityLevelPropertiesKHR * pQualityLevelProperties)1933 radv_GetPhysicalDeviceVideoEncodeQualityLevelPropertiesKHR(
1934 VkPhysicalDevice physicalDevice, const VkPhysicalDeviceVideoEncodeQualityLevelInfoKHR *pQualityLevelInfo,
1935 VkVideoEncodeQualityLevelPropertiesKHR *pQualityLevelProperties)
1936 {
1937 return VK_SUCCESS;
1938 }
1939
1940 void
radv_video_patch_encode_session_parameters(struct vk_video_session_parameters * params)1941 radv_video_patch_encode_session_parameters(struct vk_video_session_parameters *params)
1942 {
1943 switch (params->op) {
1944 case VK_VIDEO_CODEC_OPERATION_ENCODE_H264_BIT_KHR:
1945 for (unsigned i = 0; i < params->h264_enc.h264_pps_count; i++) {
1946 params->h264_enc.h264_pps[i].base.pic_init_qp_minus26 = 0;
1947 }
1948 break;
1949 case VK_VIDEO_CODEC_OPERATION_ENCODE_H265_BIT_KHR: {
1950 /*
1951 * AMD firmware requires these flags to be set in h265 with RC modes,
1952 * VCN 3 need 1.27 and VCN 4 needs 1.7 or newer to pass the CTS tests,
1953 * dEQP-VK.video.encode.h265_rc_*.
1954 */
1955 for (unsigned i = 0; i < params->h265_enc.h265_pps_count; i++) {
1956 params->h265_enc.h265_pps[i].base.flags.cu_qp_delta_enabled_flag = 1;
1957 params->h265_enc.h265_pps[i].base.diff_cu_qp_delta_depth = 0;
1958 params->h265_enc.h265_pps[i].base.init_qp_minus26 = 0;
1959 }
1960 break;
1961 }
1962 default:
1963 break;
1964 }
1965 }
1966
1967 VKAPI_ATTR VkResult VKAPI_CALL
radv_GetEncodedVideoSessionParametersKHR(VkDevice device,const VkVideoEncodeSessionParametersGetInfoKHR * pVideoSessionParametersInfo,VkVideoEncodeSessionParametersFeedbackInfoKHR * pFeedbackInfo,size_t * pDataSize,void * pData)1968 radv_GetEncodedVideoSessionParametersKHR(VkDevice device,
1969 const VkVideoEncodeSessionParametersGetInfoKHR *pVideoSessionParametersInfo,
1970 VkVideoEncodeSessionParametersFeedbackInfoKHR *pFeedbackInfo,
1971 size_t *pDataSize, void *pData)
1972 {
1973 VK_FROM_HANDLE(radv_video_session_params, templ, pVideoSessionParametersInfo->videoSessionParameters);
1974 size_t total_size = 0;
1975 size_t size_limit = 0;
1976
1977 if (pData)
1978 size_limit = *pDataSize;
1979
1980 switch (templ->vk.op) {
1981 case VK_VIDEO_CODEC_OPERATION_ENCODE_H264_BIT_KHR: {
1982 const struct VkVideoEncodeH264SessionParametersGetInfoKHR *h264_get_info =
1983 vk_find_struct_const(pVideoSessionParametersInfo->pNext, VIDEO_ENCODE_H264_SESSION_PARAMETERS_GET_INFO_KHR);
1984 size_t sps_size = 0, pps_size = 0;
1985 if (h264_get_info->writeStdSPS) {
1986 const StdVideoH264SequenceParameterSet *sps =
1987 vk_video_find_h264_enc_std_sps(&templ->vk, h264_get_info->stdSPSId);
1988 assert(sps);
1989 vk_video_encode_h264_sps(sps, size_limit, &sps_size, pData);
1990 }
1991 if (h264_get_info->writeStdPPS) {
1992 const StdVideoH264PictureParameterSet *pps =
1993 vk_video_find_h264_enc_std_pps(&templ->vk, h264_get_info->stdPPSId);
1994 assert(pps);
1995 char *data_ptr = pData ? (char *)pData + sps_size : NULL;
1996 vk_video_encode_h264_pps(pps, templ->vk.h264_enc.profile_idc == STD_VIDEO_H264_PROFILE_IDC_HIGH, size_limit,
1997 &pps_size, data_ptr);
1998 if (pFeedbackInfo) {
1999 struct VkVideoEncodeH264SessionParametersFeedbackInfoKHR *h264_feedback_info =
2000 vk_find_struct(pFeedbackInfo->pNext, VIDEO_ENCODE_H264_SESSION_PARAMETERS_FEEDBACK_INFO_KHR);
2001 pFeedbackInfo->hasOverrides = VK_TRUE;
2002 if (h264_feedback_info)
2003 h264_feedback_info->hasStdPPSOverrides = VK_TRUE;
2004 }
2005 }
2006 total_size = sps_size + pps_size;
2007 break;
2008 }
2009 case VK_VIDEO_CODEC_OPERATION_ENCODE_H265_BIT_KHR: {
2010 const struct VkVideoEncodeH265SessionParametersGetInfoKHR *h265_get_info =
2011 vk_find_struct_const(pVideoSessionParametersInfo->pNext, VIDEO_ENCODE_H265_SESSION_PARAMETERS_GET_INFO_KHR);
2012 size_t sps_size = 0, pps_size = 0, vps_size = 0;
2013 if (h265_get_info->writeStdVPS) {
2014 const StdVideoH265VideoParameterSet *vps = vk_video_find_h265_enc_std_vps(&templ->vk, h265_get_info->stdVPSId);
2015 assert(vps);
2016 vk_video_encode_h265_vps(vps, size_limit, &vps_size, pData);
2017 }
2018 if (h265_get_info->writeStdSPS) {
2019 const StdVideoH265SequenceParameterSet *sps =
2020 vk_video_find_h265_enc_std_sps(&templ->vk, h265_get_info->stdSPSId);
2021 assert(sps);
2022 char *data_ptr = pData ? (char *)pData + vps_size : NULL;
2023 vk_video_encode_h265_sps(sps, size_limit, &sps_size, data_ptr);
2024 }
2025 if (h265_get_info->writeStdPPS) {
2026 const StdVideoH265PictureParameterSet *pps =
2027 vk_video_find_h265_enc_std_pps(&templ->vk, h265_get_info->stdPPSId);
2028 assert(pps);
2029 char *data_ptr = pData ? (char *)pData + vps_size + sps_size : NULL;
2030 vk_video_encode_h265_pps(pps, size_limit, &pps_size, data_ptr);
2031
2032 if (pFeedbackInfo) {
2033 struct VkVideoEncodeH265SessionParametersFeedbackInfoKHR *h265_feedback_info =
2034 vk_find_struct(pFeedbackInfo->pNext, VIDEO_ENCODE_H265_SESSION_PARAMETERS_FEEDBACK_INFO_KHR);
2035 pFeedbackInfo->hasOverrides = VK_TRUE;
2036 if (h265_feedback_info)
2037 h265_feedback_info->hasStdPPSOverrides = VK_TRUE;
2038 }
2039 }
2040 total_size = sps_size + pps_size + vps_size;
2041 break;
2042 }
2043 default:
2044 break;
2045 }
2046
2047 *pDataSize = total_size;
2048 return VK_SUCCESS;
2049 }
2050
2051 #define VCN_ENC_SESSION_SIZE 128 * 1024
2052
2053 VkResult
radv_video_get_encode_session_memory_requirements(struct radv_device * device,struct radv_video_session * vid,uint32_t * pMemoryRequirementsCount,VkVideoSessionMemoryRequirementsKHR * pMemoryRequirements)2054 radv_video_get_encode_session_memory_requirements(struct radv_device *device, struct radv_video_session *vid,
2055 uint32_t *pMemoryRequirementsCount,
2056 VkVideoSessionMemoryRequirementsKHR *pMemoryRequirements)
2057 {
2058 struct radv_physical_device *pdev = radv_device_physical(device);
2059 uint32_t memory_type_bits = (1u << pdev->memory_properties.memoryTypeCount) - 1;
2060
2061 VK_OUTARRAY_MAKE_TYPED(VkVideoSessionMemoryRequirementsKHR, out, pMemoryRequirements, pMemoryRequirementsCount);
2062
2063 vk_outarray_append_typed(VkVideoSessionMemoryRequirementsKHR, &out, m)
2064 {
2065 m->memoryBindIndex = 0;
2066 m->memoryRequirements.size = VCN_ENC_SESSION_SIZE;
2067 m->memoryRequirements.alignment = 0;
2068 m->memoryRequirements.memoryTypeBits = memory_type_bits;
2069 }
2070
2071 return vk_outarray_status(&out);
2072 }
2073