1 /*
2 * Copyright © 2020 Mike Blumenkrantz
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
25 */
26
27 #include "nir.h"
28 #include "nir_builder.h"
29
30 /**
31 * This pass uses the enabled clip planes from the rasterizer state to rewrite
32 * vertex shader store operations and store a 0 to the corresponding gl_ClipDistance[n]
33 * value if the plane is disabled
34 */
35
36 /* vulkan (and some drivers) provides no concept of enabling clip planes through api,
37 * so we rewrite disabled clip planes to a zero value in order to disable them
38 */
39 static bool
lower_clip_plane_store_io(nir_builder * b,nir_intrinsic_instr * intr,void * cb_data)40 lower_clip_plane_store_io(nir_builder *b, nir_intrinsic_instr *intr,
41 void *cb_data)
42 {
43 unsigned clip_plane_enable = *(unsigned *)cb_data;
44
45 switch (intr->intrinsic) {
46 case nir_intrinsic_store_output:
47 case nir_intrinsic_store_per_primitive_output:
48 case nir_intrinsic_store_per_vertex_output:
49 case nir_intrinsic_store_per_view_output:
50 break;
51 default:
52 return false;
53 }
54
55 nir_io_semantics sem = nir_intrinsic_io_semantics(intr);
56 if (sem.location != VARYING_SLOT_CLIP_DIST0 &&
57 sem.location != VARYING_SLOT_CLIP_DIST1)
58 return false;
59
60 b->cursor = nir_before_instr(&intr->instr);
61 nir_src *src_offset = nir_get_io_offset_src(intr);
62 unsigned wrmask = nir_intrinsic_write_mask(intr);
63 unsigned base_index = (sem.location == VARYING_SLOT_CLIP_DIST1 ? 4 : 0) +
64 nir_intrinsic_component(intr);
65 nir_def *zero = nir_imm_int(b, 0);
66
67 if (nir_src_is_const(*src_offset)) {
68 base_index += nir_src_as_uint(*src_offset) * 4;
69
70 u_foreach_bit(bit, wrmask) {
71 if (!(clip_plane_enable & BITFIELD_BIT(base_index + bit))) {
72 nir_def *vec = nir_vector_insert_imm(b, intr->src[0].ssa, zero, bit);
73 nir_src_rewrite(&intr->src[0], vec);
74 }
75 }
76 } else {
77 u_foreach_bit(bit, wrmask) {
78 unsigned index = base_index + bit;
79 nir_def *chan = nir_channel(b, intr->src[0].ssa, bit);
80 nir_def *dist0 = clip_plane_enable & BITFIELD_BIT(index) ? chan : zero;
81 nir_def *dist1 = clip_plane_enable & BITFIELD_BIT(index + 4) ? chan : zero;
82 chan = nir_bcsel(b, nir_ieq_imm(b, src_offset->ssa, 0), dist0, dist1);
83 nir_def *vec = nir_vector_insert_imm(b, intr->src[0].ssa, chan, bit);
84 nir_src_rewrite(&intr->src[0], vec);
85 }
86 }
87 return true;
88 }
89
90 bool
nir_lower_clip_disable(nir_shader * shader,unsigned clip_plane_enable)91 nir_lower_clip_disable(nir_shader *shader, unsigned clip_plane_enable)
92 {
93 assert(shader->info.io_lowered);
94
95 /* if all user planes are enabled in API that are written in the array, always ignore;
96 * this explicitly covers the 2x vec4 case
97 */
98 if (clip_plane_enable == u_bit_consecutive(0, shader->info.clip_distance_array_size))
99 return false;
100
101 return nir_shader_intrinsics_pass(shader, lower_clip_plane_store_io,
102 nir_metadata_control_flow,
103 &clip_plane_enable);
104 }
105