1<?xml version="1.0" encoding="UTF-8"?> 2<!-- 3Copyright © 2023 Igalia S.L. 4SPDX-License-Identifier: MIT 5 --> 6 7<isa> 8 9<template name="INSTR_ALU"> 10 {NAME}{DST_FULL}{SAT}{COND}{SKPHP}{TYPE}{PMODE}{THREAD}{RMODE} 11</template> 12 13<template name="INSTR_TEX"> 14 {NAME} 15</template> 16 17<template name="INSTR_CF"> 18 {NAME}{COND}{TYPE} 19</template> 20 21<template name="INSTR_LOAD_STORE"> 22 {NAME}{SAT}{COND}{SKPHP}{DENORM}{LOCAL}{TYPE}{LEFT_SHIFT}{PMODE} 23</template> 24 25<enum name="#cond"> 26 <value val="0" name=".true" display=""/> 27 <value val="1" display=".gt"/> 28 <value val="2" display=".lt"/> 29 <value val="3" display=".ge"/> 30 <value val="4" display=".le"/> 31 <value val="5" display=".eq"/> 32 <value val="6" display=".ne"/> 33 <value val="7" display=".and"/> 34 <value val="8" display=".or"/> 35 <value val="9" display=".xor"/> 36 <value val="10" display=".not"/> 37 <value val="11" display=".nz"/> 38 <value val="12" display=".gez"/> 39 <value val="13" display=".gz"/> 40 <value val="14" display=".lez"/> 41 <value val="15" display=".lz"/> 42 <value val="22" display=".selmsb"/> 43</enum> 44 45<enum name="#swiz"> 46 <value val="0" display="x"/> 47 <value val="1" display="y"/> 48 <value val="2" display="z"/> 49 <value val="3" display="w"/> 50</enum> 51 52<enum name="#type"> 53 <value val="0" name=".f32" display=""/> 54 <value val="1" display=".s32"/> 55 <value val="2" display=".s8"/> 56 <value val="3" display=".u16"/> 57 <value val="4" display=".f16"/> 58 <value val="5" display=".s16"/> 59 <value val="6" display=".u32"/> 60 <value val="7" display=".u8"/> 61</enum> 62 63<enum name="#reg_group"> 64 <value val="0" name="temp" display="t"/> 65 <value val="1" name="internal" display="i"/> 66 <value val="2" name="uniform_0" display="u"/> 67 <value val="3" name="uniform_1" display="u"/> 68 <value val="4" display="th"/> 69 <value val="7" name="immed" display=""/> 70</enum> 71 72<enum name="#reg_addressing_mode"> 73 <value val="0" name="direct" display=""/> 74 <value val="1" display="[a.x]"/> 75 <value val="2" display="[a.y]"/> 76 <value val="3" display="[a.z]"/> 77 <value val="4" display="[a.w]"/> 78</enum> 79 80<enum name="#rounding"> 81 <value val="0" display=""/> 82 <value val="1" display=".rtz"/> 83 <value val="2" display=".rtne"/> 84 <value val="3" display=".unkown"/> 85 <value val="4" display=".unkown2"/> 86</enum> 87 88<enum name="#wrmask"> 89 <value val="0" display=".____"/> 90 <value val="1" display=".x___"/> 91 <value val="2" display="._y__"/> 92 <value val="3" display=".xy__"/> 93 <value val="4" display=".__z_"/> 94 <value val="5" display=".zx"/> 95 <value val="6" display=".zy"/> 96 <value val="7" display=".xyz_"/> 97 <value val="8" display=".___w"/> 98 <value val="9" display=".x__w"/> 99 <value val="10" display="._y_w"/> 100 <value val="11" display=".xy_w"/> 101 <value val="12" display=".__zw"/> 102 <value val="13" display=".x_zw"/> 103 <value val="14" display="._yzw"/> 104 <value val="15" name="xyzw" display=""/> <!-- xyzw --> 105</enum> 106 107<bitset name="#instruction-dst" size="14"> 108 <override> 109 <expr> 110 {DST_USE} == 0 111 </expr> 112 <display> 113 void 114 </display> 115 </override> 116 117 <display> 118 t{REG}{AMODE}{COMPS} 119 </display> 120 121 <field name="AMODE" low="0" high="2" type="#reg_addressing_mode"/> 122 <field name="REG" low="3" high="9" type="uint"/> 123 <field name="COMPS" low="10" high="13" type="#wrmask"/> 124 125 <encode type="struct etna_inst_dst *"> 126 <map name="DST_USE">p->DST_USE</map> 127 <map name="AMODE">src->amode</map> 128 <map name="REG">src->reg</map> 129 <map name="COMPS">p->COMPS</map> 130 </encode> 131</bitset> 132 133<bitset name="#instruction" size="128"> 134 <field name="COND" low="6" high="10" type="#cond"/> 135 <field name="SAT" pos="11" type="bool" display=".sat"/> 136 137 <field name="TYPE_BIT2" pos="53" type="uint"/> 138 <field name="TYPE_BIT01" low="94" high="95" type="int"/> 139 140 <derived name="TYPE" type="#type"> 141 <expr>{TYPE_BIT2} << 2 | {TYPE_BIT01}</expr> 142 </derived> 143 144 <encode type="struct etna_inst *" case-prefix="ISA_OPC_"> 145 <map name="TYPE_BIT01">src->type & 0x3</map> 146 <map name="TYPE_BIT2">(src->type & 0x4) > 2</map> 147 <map name="LOW_HALF">(src->thread & 0x1)</map> 148 <map name="HIGH_HALF">(src->thread & 0x2) > 1</map> 149 <map name="COND">src->cond</map> 150 <map name="RMODE">src->rounding</map> 151 <map name="SAT">src->sat</map> 152 <map name="PMODE">!src->pmode</map> 153 <map name="SKPHP">src->skphp</map> 154 <map name="DENORM">src->denorm</map> 155 <map name="LOCAL">src->local</map> 156 <map name="LEFT_SHIFT">src->left_shift</map> 157 <map name="DST_USE">src->dst.use</map> 158 <map name="DST">&src->dst</map> 159 <map name="DST_FULL">src->dst_full</map> 160 <map name="COMPS">src->dst.write_mask</map> 161 <map name="SRC0">&src->src[0]</map> 162 <map name="SRC0_USE">src->src[0].use</map> 163 <map name="SRC0_REG">src->src[0].reg</map> 164 <map name="SRC0_RGROUP">src->src[0].rgroup</map> 165 <map name="SRC0_AMODE">src->src[0].amode</map> 166 <map name="SRC1">&src->src[1]</map> 167 <map name="SRC1_USE">src->src[1].use</map> 168 <map name="SRC1_REG">src->src[1].reg</map> 169 <map name="SRC1_RGROUP">src->src[1].rgroup</map> 170 <map name="SRC1_AMODE">src->src[1].amode</map> 171 <map name="SRC2">&src->src[2]</map> 172 <map name="SRC2_USE">src->src[2].use</map> 173 <map name="SRC2_REG">src->src[2].reg</map> 174 <map name="SRC2_RGROUP">src->src[2].rgroup</map> 175 <map name="SRC2_AMODE">src->src[2].amode</map> 176 177 <map name="TEX_ID">src->tex.id</map> 178 <map name="TEX_SWIZ">src->tex.swiz</map> 179 <map name="TARGET">src->imm</map> 180 </encode> 181</bitset> 182 183<bitset name="#src-swizzle" size="8"> 184 <display> 185 .{SWIZ_X}{SWIZ_Y}{SWIZ_Z}{SWIZ_W} 186 </display> 187 188 <field name="SWIZ_X" low="0" high="1" type="#swiz"/> 189 <field name="SWIZ_Y" low="2" high="3" type="#swiz"/> 190 <field name="SWIZ_Z" low="4" high="5" type="#swiz"/> 191 <field name="SWIZ_W" low="6" high="7" type="#swiz"/> 192 193 <encode type="uint8_t"> 194 <map name="SWIZ_X">(src & 0x03) >> 0</map> 195 <map name="SWIZ_Y">(src & 0x0c) >> 2</map> 196 <map name="SWIZ_Z">(src & 0x30) >> 4</map> 197 <map name="SWIZ_W">(src & 0xc0) >> 6</map> 198 </encode> 199</bitset> 200 201<enum name="#thread"> 202 <value val="0" display=""/> 203 <value val="1" display=".t0"/> 204 <value val="2" display=".t1"/> 205</enum> 206 207<bitset name="#instruction-alu" extends="#instruction"> 208 <meta type="alu"/> 209 210 <field name="DST_USE" pos="12" type="bool"/> 211 <field name="DST" low="13" high="26" type="#instruction-dst"> 212 <param name="DST_USE"/> 213 <param name="COMPS"/> 214 </field> 215 <pattern low="27" high="31">00000</pattern> <!-- TEX_ID --> 216 <field name="RMODE" low="32" high="33" type="#rounding"/> 217 <field name="PMODE" pos="34" type="bool_inv" display=".pack"/> 218 219 <pattern low="35" high="38">0000</pattern> 220 <field name="SKPHP" pos="39" type="bool" display=".skpHp"/> 221 <pattern low="40" high="42">000</pattern> 222 223 <field name="LOW_HALF" pos="109" type="bool"/> 224 <field name="HIGH_HALF" pos="120" type="bool"/> 225 226 <derived name="THREAD" type="#thread"> 227 <expr>{HIGH_HALF} << 1 | {LOW_HALF}</expr> 228 </derived> 229 230 <field name="DST_FULL" pos="127" type="bool" display=".hp"/> 231</bitset> 232 233<bitset name="#instruction-src" size="10"> 234 <display> 235 {SRC_NEG}{SRC_ABS}{SRC_RGROUP}{SRC_REG}{SRC_AMODE}{SRC_SWIZ}{SRC_ABS} 236 </display> 237 238 <field name="SRC_SWIZ" low="0" high="7" type="#src-swizzle"/> 239 <field name="SRC_NEG" pos="8" type="bool" display="-"/> 240 <field name="SRC_ABS" pos="9" type="bool" display="|"/> 241 242 <derived name="IMMED_TYPE" type="uint"> 243 <expr>({SRC_AMODE} >> 1)</expr> <!-- lowest bit is the sign bit --> 244 </derived> 245 246 <override> 247 <expr> 248 (({SRC_RGROUP} == 7) & ({IMMED_TYPE} == 0)) 249 </expr> 250 251 <display> 252 {IMMED} 253 </display> 254 255 <derived name="IMMED" type="float" width="32"> 256 <expr> 257 (((({SRC_AMODE} & 0x1) << 19) | 258 ({SRC_ABS} << 18) | 259 ({SRC_NEG} << 17) | 260 ({SRC_SWIZ} << 9) | 261 {SRC_REG}) << 12) 262 </expr> 263 </derived> 264 </override> 265 266 <override> 267 <expr> 268 (({SRC_RGROUP} == 7) & ({IMMED_TYPE} == 1)) 269 </expr> 270 271 <display> 272 {IMMED} 273 </display> 274 275 <derived name="IMMED" type="int" width="20"> 276 <expr> 277 ((({SRC_AMODE} & 0x1) << 19) | 278 ({SRC_ABS} << 18) | 279 ({SRC_NEG} << 17) | 280 ({SRC_SWIZ} << 9) | 281 {SRC_REG}) 282 </expr> 283 </derived> 284 </override> 285 286 <override> 287 <expr> 288 (({SRC_RGROUP} == 7) & ({IMMED_TYPE} == 2)) 289 </expr> 290 291 <display> 292 {IMMED} 293 </display> 294 295 <derived name="IMMED" type="uint" width="20"> 296 <expr> 297 ((({SRC_AMODE} & 0x1) << 19) | 298 ({SRC_ABS} << 18) | 299 ({SRC_NEG} << 17) | 300 ({SRC_SWIZ} << 9) | 301 {SRC_REG}) 302 </expr> 303 </derived> 304 </override> 305 306 <override> 307 <expr> 308 (({SRC_RGROUP} == 7) & ({IMMED_TYPE} == 3)) 309 </expr> 310 311 <display> 312 {IMMED} 313 </display> 314 315 <derived name="IMMED" type="float" width="16"> 316 <expr> 317 ((({SRC_AMODE} & 0x1) << 19) | 318 ({SRC_ABS} << 18) | 319 ({SRC_NEG} << 17) | 320 ({SRC_SWIZ} << 9) | 321 {SRC_REG}) 322 </expr> 323 </derived> 324 </override> 325 326 <encode type="struct etna_inst_src *"> 327 <map name="SRC_SWIZ">src->swiz</map> 328 <map name="SRC_NEG">src->neg</map> 329 <map name="SRC_ABS">src->abs</map> 330 <map name="SRC_RGROUP">p->SRC_RGROUP</map> 331 </encode> 332</bitset> 333 334<bitset name="#instruction-alu-no-src" extends="#instruction-alu"> 335 <display> 336 {NAME} {DST:align=18}{DST_FULL}, void, void, void 337 </display> 338 339 <!-- SRC0 --> 340 <pattern pos="43">0</pattern> <!-- SRC0_USE --> 341 <pattern low="44" high="52">000000000</pattern> <!-- SRC0_REG --> 342 <pattern low="54" high="61">00000000</pattern> <!-- SRC0_SWIZ --> 343 <pattern pos="62">0</pattern> <!-- SRC0_NEG --> 344 <pattern pos="63">0</pattern> <!-- SRC0_ABS --> 345 <pattern low="64" high="66">000</pattern> <!-- SRC0_AMODE --> 346 <pattern low="67" high="69">000</pattern> <!-- SRC0_RGROUP --> 347 348 <!-- SRC1 --> 349 <pattern pos="70">0</pattern> <!-- SRC1_USE --> 350 <pattern low="71" high="79">000000000</pattern> <!-- SRC1_REG --> 351 <pattern low="81" high="88">00000000</pattern> <!-- SRC1_SWIZ --> 352 <pattern pos="89">0</pattern> <!-- SRC1_NEG --> 353 <pattern pos="90">0</pattern> <!-- SRC1_ABS --> 354 <pattern low="91" high="93">000</pattern> <!-- SRC1_AMODE --> 355 <pattern low="96" high="98">000</pattern> <!-- SRC1_RGROUP --> 356 357 <!-- SRC2 --> 358 <pattern pos="99">0</pattern> <!-- SRC2_USE --> 359 <pattern low="100" high="108">000000000</pattern> <!-- SRC2_REG --> 360 <pattern low="110" high="117">00000000</pattern> <!-- SRC2_SWIZ --> 361 <pattern pos="118">0</pattern> <!-- SRC2_NEG --> 362 <pattern pos="119">0</pattern> <!-- SRC2_ABS --> 363 <pattern low="121" high="123">000</pattern> <!-- SRC2_AMODE --> 364 <pattern low="124" high="126">000</pattern> <!-- SRC2_RGROUP --> 365</bitset> 366 367<expr name="#instruction-has-src0-src1"> 368 ({SRC0_USE} != 0) && ({SRC1_USE} != 0) 369</expr> 370 371<expr name="#instruction-has-src2"> 372 ({SRC2_USE} != 0) 373</expr> 374 375<expr name="#instruction-has-src0-src1-src2"> 376 ({SRC0_USE} != 0) && ({SRC1_USE} != 0) && ({SRC2_USE} != 0) 377</expr> 378 379<bitset name="#instruction-alu-no-dst-maybe-src0-src1" extends="#instruction-alu"> 380 <doc>Needed for texkill</doc> 381 <display> 382 {NAME}{COND}{TYPE}{PMODE}{THREAD}{RMODE} {DST:align=18}{DST_FULL}, void, void, void 383 </display> 384 385 <override expr="#instruction-has-src0-src1"> 386 <display> 387 {NAME}{COND}{TYPE}{PMODE}{THREAD}{RMODE} {DST:align=18}, {SRC0}, {SRC1}, void 388 </display> 389 </override> 390 391 <override expr="#instruction-has-src0"> 392 <display> 393 {NAME}{COND}{TYPE}{PMODE}{THREAD}{RMODE} {DST:align=18}, {SRC0}, void, void 394 </display> 395 </override> 396 397 <!-- SRC0 --> 398 <field name="SRC0_USE" pos="43" type="bool"/> 399 <field name="SRC0_REG" low="44" high="52" type="uint"/> 400 <field name="SRC0" low="54" high="63" type="#instruction-src"> 401 <param name="SRC0_REG" as="SRC_REG"/> 402 <param name="SRC0_AMODE" as="SRC_AMODE"/> 403 <param name="SRC0_RGROUP" as="SRC_RGROUP"/> 404 </field> 405 <field name="SRC0_AMODE" low="64" high="66" type="#reg_addressing_mode"/> 406 <field name="SRC0_RGROUP" low="67" high="69" type="#reg_group"/> 407 408 <!-- SRC1 --> 409 <field name="SRC1_USE" pos="70" type="bool"/> 410 <field name="SRC1_REG" low="71" high="79" type="uint"/> 411 <field name="SRC1" low="81" high="90" type="#instruction-src"> 412 <param name="SRC1_REG" as="SRC_REG"/> 413 <param name="SRC1_AMODE" as="SRC_AMODE"/> 414 <param name="SRC1_RGROUP" as="SRC_RGROUP"/> 415 </field> 416 <field name="SRC1_AMODE" low="91" high="93" type="#reg_addressing_mode"/> 417 <field name="SRC1_RGROUP" low="96" high="98" type="#reg_group"/> 418 419 <!-- SRC2 --> 420 <pattern pos="99">0</pattern> <!-- SRC2_USE --> 421 <pattern low="100" high="108">000000000</pattern> <!-- SRC2_REG --> 422 <pattern low="110" high="117">00000000</pattern> <!-- SRC2_SWIZ --> 423 <pattern pos="118">0</pattern> <!-- SRC2_NEG --> 424 <pattern pos="119">0</pattern> <!-- SRC2_ABS --> 425 <pattern low="121" high="123">000</pattern> <!-- SRC2_AMODE --> 426 <pattern low="124" high="126">000</pattern> <!-- SRC2_RGROUP --> 427</bitset> 428 429<bitset name="#instruction-alu-src0" extends="#instruction-alu"> 430 <meta has_dest="true" valid_srcs="0"/> 431 432 <display> 433 {INSTR_ALU} {DST:align=18}, {SRC0}, void, void 434 </display> 435 436 <!-- SRC0 --> 437 <pattern pos="43">1</pattern> <!-- SRC0_USE --> 438 <field name="SRC0_REG" low="44" high="52" type="uint"/> 439 <field name="SRC0" low="54" high="63" type="#instruction-src"> 440 <param name="SRC0_REG" as="SRC_REG"/> 441 <param name="SRC0_AMODE" as="SRC_AMODE"/> 442 <param name="SRC0_RGROUP" as="SRC_RGROUP"/> 443 </field> 444 <field name="SRC0_AMODE" low="64" high="66" type="#reg_addressing_mode"/> 445 <field name="SRC0_RGROUP" low="67" high="69" type="#reg_group"/> 446 447 <!-- SRC1 --> 448 <pattern pos="70">0</pattern> <!-- SRC1_USE --> 449 <pattern low="71" high="79">000000000</pattern> <!-- SRC1_REG --> 450 <pattern low="81" high="88">00000000</pattern> <!-- SRC1_SWIZ --> 451 <pattern pos="89">0</pattern> <!-- SRC1_NEG --> 452 <pattern pos="90">0</pattern> <!-- SRC1_ABS --> 453 <pattern low="91" high="93">000</pattern> <!-- SRC1_AMODE --> 454 <pattern low="96" high="98">000</pattern> <!-- SRC1_RGROUP --> 455 456 <!-- SRC2 --> 457 <pattern pos="99">0</pattern> <!-- SRC2_USE --> 458 <pattern low="100" high="108">000000000</pattern> <!-- SRC2_REG --> 459 <pattern low="110" high="117">00000000</pattern> <!-- SRC2_SWIZ --> 460 <pattern pos="118">0</pattern> <!-- SRC2_NEG --> 461 <pattern pos="119">0</pattern> <!-- SRC2_ABS --> 462 <pattern low="121" high="123">000</pattern> <!-- SRC2_AMODE --> 463 <pattern low="124" high="126">000</pattern> <!-- SRC2_RGROUP --> 464</bitset> 465 466<bitset name="#instruction-alu-src2" extends="#instruction-alu"> 467 <meta has_dest="true" valid_srcs="2"/> 468 469 <display> 470 {INSTR_ALU} {DST:align=18}, void, void, {SRC2} 471 </display> 472 473 <!-- SRC0 --> 474 <pattern pos="43">0</pattern> <!-- SRC0_USE --> 475 <pattern low="44" high="52">000000000</pattern> <!-- SRC0_REG --> 476 <pattern low="54" high="61">00000000</pattern> <!-- SRC0_SWIZ --> 477 <pattern pos="62">0</pattern> <!-- SRC0_NEG --> 478 <pattern pos="63">0</pattern> <!-- SRC0_ABS --> 479 <pattern low="64" high="66">000</pattern> <!-- SRC0_AMODE --> 480 <pattern low="67" high="69">000</pattern> <!-- SRC0_RGROUP --> 481 482 <!-- SRC1 --> 483 <pattern pos="70">0</pattern> <!-- SRC1_USE --> 484 <pattern low="71" high="79">000000000</pattern> <!-- SRC1_REG --> 485 <pattern low="81" high="88">00000000</pattern> <!-- SRC1_SWIZ --> 486 <pattern pos="89">0</pattern> <!-- SRC1_NEG --> 487 <pattern pos="90">0</pattern> <!-- SRC1_ABS --> 488 <pattern low="91" high="93">000</pattern> <!-- SRC1_AMODE --> 489 <pattern low="96" high="98">000</pattern> <!-- SRC1_RGROUP --> 490 491 <!-- SRC2 --> 492 <pattern pos="99">1</pattern> <!-- SRC2_USE --> 493 <field name="SRC2_REG" low="100" high="108" type="uint"/> 494 <field name="SRC2" low="110" high="119" type="#instruction-src"> 495 <param name="SRC2_REG" as="SRC_REG"/> 496 <param name="SRC2_AMODE" as="SRC_AMODE"/> 497 <param name="SRC2_RGROUP" as="SRC_RGROUP"/> 498 </field> 499 <field name="SRC2_AMODE" low="121" high="123" type="#reg_addressing_mode"/> 500 <field name="SRC2_RGROUP" low="124" high="126" type="#reg_group"/> 501 502 <encode type="struct etna_inst *" case-prefix="ISA_OPC_"> 503 <map name="SRC2">&src->src[0]</map> 504 <map name="SRC2_USE">rc->src[0].use</map> 505 <map name="SRC2_REG">src->src[0].reg</map> 506 <map name="SRC2_RGROUP">src->src[0].rgroup</map> 507 <map name="SRC2_AMODE">src->src[0].amode</map> 508 </encode> 509</bitset> 510 511<bitset name="#instruction-alu-src0-src1" extends="#instruction-alu"> 512 <meta has_dest="true" valid_srcs="0|1"/> 513 514 <display> 515 {INSTR_ALU} {DST:align=18}, {SRC0}, {SRC1}, void 516 </display> 517 518 <!-- SRC0 --> 519 <pattern pos="43">1</pattern> <!-- SRC0_USE --> 520 <field name="SRC0_REG" low="44" high="52" type="uint"/> 521 <field name="SRC0" low="54" high="63" type="#instruction-src"> 522 <param name="SRC0_REG" as="SRC_REG"/> 523 <param name="SRC0_AMODE" as="SRC_AMODE"/> 524 <param name="SRC0_RGROUP" as="SRC_RGROUP"/> 525 </field> 526 <field name="SRC0_AMODE" low="64" high="66" type="#reg_addressing_mode"/> 527 <field name="SRC0_RGROUP" low="67" high="69" type="#reg_group"/> 528 529 <!-- SRC1 --> 530 <pattern pos="70">1</pattern> <!-- SRC1_USE --> 531 <field name="SRC1_REG" low="71" high="79" type="uint"/> 532 <field name="SRC1" low="81" high="90" type="#instruction-src"> 533 <param name="SRC1_REG" as="SRC_REG"/> 534 <param name="SRC1_AMODE" as="SRC_AMODE"/> 535 <param name="SRC1_RGROUP" as="SRC_RGROUP"/> 536 </field> 537 <field name="SRC1_AMODE" low="91" high="93" type="#reg_addressing_mode"/> 538 <field name="SRC1_RGROUP" low="96" high="98" type="#reg_group"/> 539 540 <!-- SRC2 --> 541 <pattern pos="99">0</pattern> <!-- SRC2_USE --> 542 <pattern low="100" high="108">000000000</pattern> <!-- SRC2_REG --> 543 <pattern low="110" high="117">00000000</pattern> <!-- SRC2_SWIZ --> 544 <pattern pos="118">0</pattern> <!-- SRC2_NEG --> 545 <pattern pos="119">0</pattern> <!-- SRC2_ABS --> 546 <pattern low="121" high="123">000</pattern> <!-- SRC2_AMODE --> 547 <pattern low="124" high="126">000</pattern> <!-- SRC2_RGROUP --> 548</bitset> 549 550<bitset name="#instruction-alu-src0-src2" extends="#instruction-alu"> 551 <meta has_dest="true" valid_srcs="0|2"/> 552 553 <display> 554 {INSTR_ALU} {DST:align=18}, {SRC0}, void, {SRC2} 555 </display> 556 557 <!-- SRC0 --> 558 <pattern pos="43">1</pattern> <!-- SRC0_USE --> 559 <field name="SRC0_REG" low="44" high="52" type="uint"/> 560 <field name="SRC0" low="54" high="63" type="#instruction-src"> 561 <param name="SRC0_REG" as="SRC_REG"/> 562 <param name="SRC0_AMODE" as="SRC_AMODE"/> 563 <param name="SRC0_RGROUP" as="SRC_RGROUP"/> 564 </field> 565 <field name="SRC0_AMODE" low="64" high="66" type="#reg_addressing_mode"/> 566 <field name="SRC0_RGROUP" low="67" high="69" type="#reg_group"/> 567 568 <!-- SRC1 --> 569 <pattern pos="70">0</pattern> <!-- SRC1_USE --> 570 <pattern low="71" high="79">000000000</pattern> <!-- SRC1_REG --> 571 <pattern low="81" high="88">00000000</pattern> <!-- SRC1_SWIZ --> 572 <pattern pos="89">0</pattern> <!-- SRC1_NEG --> 573 <pattern pos="90">0</pattern> <!-- SRC1_ABS --> 574 <pattern low="91" high="93">000</pattern> <!-- SRC1_AMODE --> 575 <pattern low="96" high="98">000</pattern> <!-- SRC1_RGROUP --> 576 577 <!-- SRC2 --> 578 <pattern pos="99">1</pattern> <!-- SRC2_USE --> 579 <field name="SRC2_REG" low="100" high="108" type="uint"/> 580 <field name="SRC2" low="110" high="119" type="#instruction-src"> 581 <param name="SRC2_REG" as="SRC_REG"/> 582 <param name="SRC2_AMODE" as="SRC_AMODE"/> 583 <param name="SRC2_RGROUP" as="SRC_RGROUP"/> 584 </field> 585 <field name="SRC2_AMODE" low="121" high="123" type="#reg_addressing_mode"/> 586 <field name="SRC2_RGROUP" low="124" high="126" type="#reg_group"/> 587 588 <encode type="struct etna_inst *" case-prefix="ISA_OPC_"> 589 <map name="SRC2">&src->src[1]</map> 590 <map name="SRC2_USE">rc->src[1].use</map> 591 <map name="SRC2_REG">src->src[1].reg</map> 592 <map name="SRC2_RGROUP">src->src[1].rgroup</map> 593 <map name="SRC2_AMODE">src->src[1].amode</map> 594 </encode> 595</bitset> 596 597<bitset name="#instruction-alu-src1-src2" extends="#instruction-alu"> 598 <meta has_dest="true" valid_srcs="1|2"/> 599 600 <display> 601 {INSTR_ALU} {DST:align=18}, void, {SRC1}, {SRC2} 602 </display> 603 604 <!-- SRC0 --> 605 <pattern pos="43">0</pattern> <!-- SRC0_USE --> 606 <pattern low="44" high="52">000000000</pattern> <!-- SRC0_REG --> 607 <pattern low="54" high="61">00000000</pattern> <!-- SRC0_SWIZ --> 608 <pattern pos="62">0</pattern> <!-- SRC0_NEG --> 609 <pattern pos="63">0</pattern> <!-- SRC0_ABS --> 610 <pattern low="64" high="66">000</pattern> <!-- SRC0_AMODE --> 611 <pattern low="67" high="69">000</pattern> <!-- SRC0_RGROUP --> 612 613 <!-- SRC1 --> 614 <pattern pos="70">1</pattern> <!-- SRC1_USE --> 615 <field name="SRC1_REG" low="71" high="79" type="uint"/> 616 <field name="SRC1" low="81" high="90" type="#instruction-src"> 617 <param name="SRC1_REG" as="SRC_REG"/> 618 <param name="SRC1_AMODE" as="SRC_AMODE"/> 619 <param name="SRC1_RGROUP" as="SRC_RGROUP"/> 620 </field> 621 <field name="SRC1_AMODE" low="91" high="93" type="#reg_addressing_mode"/> 622 <field name="SRC1_RGROUP" low="96" high="98" type="#reg_group"/> 623 624 <!-- SRC2 --> 625 <pattern pos="99">1</pattern> <!-- SRC2_USE --> 626 <field name="SRC2_REG" low="100" high="108" type="uint"/> 627 <field name="SRC2" low="110" high="119" type="#instruction-src"> 628 <param name="SRC2_REG" as="SRC_REG"/> 629 <param name="SRC2_AMODE" as="SRC_AMODE"/> 630 <param name="SRC2_RGROUP" as="SRC_RGROUP"/> 631 </field> 632 <field name="SRC2_AMODE" low="121" high="123" type="#reg_addressing_mode"/> 633 <field name="SRC2_RGROUP" low="124" high="126" type="#reg_group"/> 634 635 <encode type="struct etna_inst *" case-prefix="ISA_OPC_"> 636 <map name="SRC1">&src->src[0]</map> 637 <map name="SRC1_USE">rc->src[0].use</map> 638 <map name="SRC1_REG">src->src[0].reg</map> 639 <map name="SRC1_RGROUP">src->src[0].rgroup</map> 640 <map name="SRC1_AMODE">src->src[0].amode</map> 641 <map name="SRC2">&src->src[1]</map> 642 <map name="SRC2_USE">rc->src[1].use</map> 643 <map name="SRC2_REG">src->src[1].reg</map> 644 <map name="SRC2_RGROUP">src->src[1].rgroup</map> 645 <map name="SRC2_AMODE">src->src[1].amode</map> 646 </encode> 647</bitset> 648 649<bitset name="#instruction-alu-src0-src1-src2" extends="#instruction-alu"> 650 <meta has_dest="true" valid_srcs="0|1|2"/> 651 <display> 652 {INSTR_ALU} {DST:align=18}, {SRC0}, {SRC1}, {SRC2} 653 </display> 654 655 <!-- SRC0 --> 656 <pattern pos="43">1</pattern> <!-- SRC0_USE --> 657 <field name="SRC0_REG" low="44" high="52" type="uint"/> 658 <field name="SRC0" low="54" high="63" type="#instruction-src"> 659 <param name="SRC0_REG" as="SRC_REG"/> 660 <param name="SRC0_AMODE" as="SRC_AMODE"/> 661 <param name="SRC0_RGROUP" as="SRC_RGROUP"/> 662 </field> 663 <field name="SRC0_AMODE" low="64" high="66" type="#reg_addressing_mode"/> 664 <field name="SRC0_RGROUP" low="67" high="69" type="#reg_group"/> 665 666 <!-- SRC1 --> 667 <pattern pos="70">1</pattern> <!-- SRC1_USE --> 668 <field name="SRC1_REG" low="71" high="79" type="uint"/> 669 <field name="SRC1" low="81" high="90" type="#instruction-src"> 670 <param name="SRC1_REG" as="SRC_REG"/> 671 <param name="SRC1_AMODE" as="SRC_AMODE"/> 672 <param name="SRC1_RGROUP" as="SRC_RGROUP"/> 673 </field> 674 <field name="SRC1_AMODE" low="91" high="93" type="#reg_addressing_mode"/> 675 <field name="SRC1_RGROUP" low="96" high="98" type="#reg_group"/> 676 677 <!-- SRC2 --> 678 <pattern pos="99">1</pattern> <!-- SRC2_USE --> 679 <field name="SRC2_REG" low="100" high="108" type="uint"/> 680 <field name="SRC2" low="110" high="119" type="#instruction-src"> 681 <param name="SRC2_REG" as="SRC_REG"/> 682 <param name="SRC2_AMODE" as="SRC_AMODE"/> 683 <param name="SRC2_RGROUP" as="SRC_RGROUP"/> 684 </field> 685 <field name="SRC2_AMODE" low="121" high="123" type="#reg_addressing_mode"/> 686 <field name="SRC2_RGROUP" low="124" high="126" type="#reg_group"/> 687</bitset> 688 689<bitset name="#instruction-tex" extends="#instruction"> 690 <meta type="tex"/> 691 692 <field name="DST_USE" pos="12" type="bool"/> 693 <field name="DST" low="13" high="26" type="#instruction-dst"> 694 <param name="DST_USE"/> 695 <param name="COMPS"/> 696 </field> 697 <field name="TEX_ID" low="27" high="31" type="uint"/> 698 <field name="RMODE" low="32" high="34" type="#reg_addressing_mode"/> 699 <field name="TEX_SWIZ" low="35" high="42" type="#src-swizzle"/> 700 701 <pattern pos="109">0</pattern> 702 <pattern pos="120">0</pattern> 703 <pattern pos="127">0</pattern> 704</bitset> 705 706<bitset name="#instruction-tex-src0-maybe-src2" extends="#instruction-tex"> 707 <meta has_dest="true" valid_srcs="0"/> 708 709 <display> 710 {INSTR_TEX} {DST:align=18}, tex{TEX_ID}{TEX_SWIZ}, {SRC0}, void, void 711 </display> 712 713 <override expr="#instruction-has-src2"> 714 <display> 715 {INSTR_TEX} {DST:align=18}, tex{TEX_ID}{TEX_SWIZ}, {SRC0}, void, {SRC2} 716 </display> 717 </override> 718 719 <!-- SRC0 --> 720 <pattern pos="43">1</pattern> <!-- SRC0_USE --> 721 <field name="SRC0_REG" low="44" high="52" type="uint"/> 722 <field name="SRC0" low="54" high="63" type="#instruction-src"> 723 <param name="SRC0_REG" as="SRC_REG"/> 724 <param name="SRC0_AMODE" as="SRC_AMODE"/> 725 <param name="SRC0_RGROUP" as="SRC_RGROUP"/> 726 </field> 727 <field name="SRC0_AMODE" low="64" high="66" type="#reg_addressing_mode"/> 728 <field name="SRC0_RGROUP" low="67" high="69" type="#reg_group"/> 729 730 <!-- SRC1 --> 731 <pattern pos="70">0</pattern> <!-- SRC1_USE --> 732 <pattern low="71" high="79">000000000</pattern> <!-- SRC1_REG --> 733 <pattern low="81" high="88">00000000</pattern> <!-- SRC1_SWIZ --> 734 <pattern pos="89">0</pattern> <!-- SRC1_NEG --> 735 <pattern pos="90">0</pattern> <!-- SRC1_ABS --> 736 <pattern low="91" high="93">000</pattern> <!-- SRC1_AMODE --> 737 <pattern low="96" high="98">000</pattern> <!-- SRC1_RGROUP --> 738 739 <!-- SRC2 --> 740 <field name="SRC2_USE" pos="99" type="bool"/> <!-- SRC2_USE --> 741 <field name="SRC2_REG" low="100" high="108" type="uint"/> 742 <field name="SRC2" low="110" high="119" type="#instruction-src"> 743 <param name="SRC2_REG" as="SRC_REG"/> 744 <param name="SRC2_AMODE" as="SRC_AMODE"/> 745 <param name="SRC2_RGROUP" as="SRC_RGROUP"/> 746 </field> 747 <field name="SRC2_AMODE" low="121" high="123" type="#reg_addressing_mode"/> 748 <field name="SRC2_RGROUP" low="124" high="126" type="#reg_group"/> 749</bitset> 750 751<bitset name="#instruction-tex-src0-src1-src2" extends="#instruction-tex"> 752 <meta has_dest="true" valid_srcs="0|1|2"/> 753 754 <display> 755 {INSTR_TEX} {DST:align=18}, tex{TEX_ID}{TEX_SWIZ}, {SRC0}, {SRC1}, {SRC2} 756 </display> 757 758 <!-- SRC0 --> 759 <pattern pos="43">1</pattern> <!-- SRC0_USE --> 760 <field name="SRC0_REG" low="44" high="52" type="uint"/> 761 <field name="SRC0" low="54" high="63" type="#instruction-src"> 762 <param name="SRC0_REG" as="SRC_REG"/> 763 <param name="SRC0_AMODE" as="SRC_AMODE"/> 764 <param name="SRC0_RGROUP" as="SRC_RGROUP"/> 765 </field> 766 <field name="SRC0_AMODE" low="64" high="66" type="#reg_addressing_mode"/> 767 <field name="SRC0_RGROUP" low="67" high="69" type="#reg_group"/> 768 769 <!-- SRC1 --> 770 <pattern pos="70">1</pattern> <!-- SRC1_USE --> 771 <field name="SRC1_REG" low="71" high="79" type="uint"/> 772 <field name="SRC1" low="81" high="90" type="#instruction-src"> 773 <param name="SRC1_REG" as="SRC_REG"/> 774 <param name="SRC1_AMODE" as="SRC_AMODE"/> 775 <param name="SRC1_RGROUP" as="SRC_RGROUP"/> 776 </field> 777 <field name="SRC1_AMODE" low="91" high="93" type="#reg_addressing_mode"/> 778 <field name="SRC1_RGROUP" low="96" high="98" type="#reg_group"/> 779 780 <!-- SRC2 --> 781 <pattern pos="99">1</pattern> <!-- SRC2_USE --> 782 <field name="SRC2_REG" low="100" high="108" type="uint"/> 783 <field name="SRC2" low="110" high="119" type="#instruction-src"> 784 <param name="SRC2_REG" as="SRC_REG"/> 785 <param name="SRC2_AMODE" as="SRC_AMODE"/> 786 <param name="SRC2_RGROUP" as="SRC_RGROUP"/> 787 </field> 788 <field name="SRC2_AMODE" low="121" high="123" type="#reg_addressing_mode"/> 789 <field name="SRC2_RGROUP" low="124" high="126" type="#reg_group"/> 790</bitset> 791 792<bitset name="#instruction-tex-src0-maybe-src1-src2" extends="#instruction-tex"> 793 <meta has_dest="true" valid_srcs="0|1"/> 794 795 <display> 796 {INSTR_TEX} {DST:align=18}, tex{TEX_ID}{TEX_SWIZ}, {SRC0}, {SRC1}, void 797 </display> 798 799 <override expr="#instruction-has-src0"> 800 <display> 801 {INSTR_TEX} {DST:align=18}, tex{TEX_ID}{TEX_SWIZ}, {SRC0}, void, void 802 </display> 803 </override> 804 805 <override expr="#instruction-has-src0-src1-src2"> 806 <display> 807 {INSTR_TEX} {DST:align=18}, tex{TEX_ID}{TEX_SWIZ}, {SRC0}, {SRC1}, {SRC2} 808 </display> 809 </override> 810 811 <!-- SRC0 --> 812 <field name="SRC0_USE" pos="43" type="bool"/> 813 <field name="SRC0_REG" low="44" high="52" type="uint"/> 814 <field name="SRC0" low="54" high="63" type="#instruction-src"> 815 <param name="SRC0_REG" as="SRC_REG"/> 816 <param name="SRC0_AMODE" as="SRC_AMODE"/> 817 <param name="SRC0_RGROUP" as="SRC_RGROUP"/> 818 </field> 819 <field name="SRC0_AMODE" low="64" high="66" type="#reg_addressing_mode"/> 820 <field name="SRC0_RGROUP" low="67" high="69" type="#reg_group"/> 821 822 <!-- SRC1 --> 823 <field name="SRC1_USE" pos="70" type="bool"/> 824 <field name="SRC1_REG" low="71" high="79" type="uint"/> 825 <field name="SRC1" low="81" high="90" type="#instruction-src"> 826 <param name="SRC1_REG" as="SRC_REG"/> 827 <param name="SRC1_AMODE" as="SRC_AMODE"/> 828 <param name="SRC1_RGROUP" as="SRC_RGROUP"/> 829 </field> 830 <field name="SRC1_AMODE" low="91" high="93" type="#reg_addressing_mode"/> 831 <field name="SRC1_RGROUP" low="96" high="98" type="#reg_group"/> 832 833 <!-- SRC2 --> 834 <field name="SRC2_USE" pos="99" type="bool"/> <!-- SRC2_USE --> 835 <field name="SRC2_REG" low="100" high="108" type="uint"/> 836 <field name="SRC2" low="110" high="119" type="#instruction-src"> 837 <param name="SRC2_REG" as="SRC_REG"/> 838 <param name="SRC2_AMODE" as="SRC_AMODE"/> 839 <param name="SRC2_RGROUP" as="SRC_RGROUP"/> 840 </field> 841 <field name="SRC2_AMODE" low="121" high="123" type="#reg_addressing_mode"/> 842 <field name="SRC2_RGROUP" low="124" high="126" type="#reg_group"/> 843</bitset> 844 845<bitset name="#instruction-cf" extends="#instruction"> 846 <meta type="cf"/> 847 848 <pattern low="12" high="31">00000000000000000000</pattern> 849 850 <pattern low="32" high="33">00</pattern> <!-- RMODE --> 851 <pattern pos="34">x</pattern><!-- PMODE --> 852 <pattern low="35" high="42">00000000</pattern><!-- TEX_SWIZ --> 853 854 <pattern low="99" high="102">0000</pattern> 855 <field name="TARGET" low="103" high="117" type="absbranch"/> 856 <pattern low="118" high="127">0000000000</pattern> 857</bitset> 858 859<bitset name="#instruction-cf-no-src" extends="#instruction-cf"> 860 <display> 861 {INSTR_CF} {:align=18}void, void, void, {TARGET} 862 </display> 863 864 <pattern low="43" high="52">0000000000</pattern> 865 <pattern low="54" high="63">0000000000</pattern> 866 <pattern low="64" high="66">000</pattern> 867 <pattern low="67" high="79">0000000000000</pattern> 868 <pattern low="81" high="93">0000000000000</pattern> 869 <pattern low="96" high="98">000</pattern> 870</bitset> 871 872<expr name="#instruction-has-src0"> 873 ({SRC0_USE} != 0) && ({SRC1_USE} == 0) 874</expr> 875 876<bitset name="#instruction-cf-src0" extends="#instruction-cf"> 877 <meta valid_srcs="0"/> 878 879 <display> 880 {INSTR_CF} {:align=18}void, {SRC0}, void, {TARGET} 881 </display> 882 883 <!-- SRC0 --> 884 <pattern pos="43">1</pattern> <!-- SRC0_USE --> 885 <field name="SRC0_REG" low="44" high="52" type="uint"/> 886 <field name="SRC0" low="54" high="63" type="#instruction-src"> 887 <param name="SRC0_REG" as="SRC_REG"/> 888 <param name="SRC0_AMODE" as="SRC_AMODE"/> 889 <param name="SRC0_RGROUP" as="SRC_RGROUP"/> 890 </field> 891 <field name="SRC0_AMODE" low="64" high="66" type="#reg_addressing_mode"/> 892 <field name="SRC0_RGROUP" low="67" high="69" type="#reg_group"/> 893 894 <!-- SRC1 --> 895 <pattern pos="70">0</pattern> <!-- SRC1_USE --> 896 <pattern low="71" high="79">000000000</pattern> <!-- SRC1_REG --> 897 <pattern low="81" high="88">00000000</pattern> <!-- SRC1_SWIZ --> 898 <pattern pos="89">0</pattern> <!-- SRC1_NEG --> 899 <pattern pos="90">0</pattern> <!-- SRC1_ABS --> 900 <pattern low="91" high="93">000</pattern> <!-- SRC1_AMODE --> 901 <pattern low="96" high="98">000</pattern> <!-- SRC1_RGROUP --> 902</bitset> 903 904<bitset name="#instruction-cf-src0-src1" extends="#instruction-cf"> 905 <meta valid_srcs="0|1"/> 906 907 <display> 908 {INSTR_CF} {:align=18}void, {SRC0}, {SRC1}, {TARGET} 909 </display> 910 911 <!-- SRC0 --> 912 <pattern pos="43">1</pattern> <!-- SRC0_USE --> 913 <field name="SRC0_REG" low="44" high="52" type="uint"/> 914 <field name="SRC0" low="54" high="63" type="#instruction-src"> 915 <param name="SRC0_REG" as="SRC_REG"/> 916 <param name="SRC0_AMODE" as="SRC_AMODE"/> 917 <param name="SRC0_RGROUP" as="SRC_RGROUP"/> 918 </field> 919 <field name="SRC0_AMODE" low="64" high="66" type="#reg_addressing_mode"/> 920 <field name="SRC0_RGROUP" low="67" high="69" type="#reg_group"/> 921 922 <!-- SRC1 --> 923 <pattern pos="70">1</pattern> <!-- SRC1_USE --> 924 <field name="SRC1_REG" low="71" high="79" type="uint"/> 925 <field name="SRC1" low="81" high="90" type="#instruction-src"> 926 <param name="SRC1_REG" as="SRC_REG"/> 927 <param name="SRC1_AMODE" as="SRC_AMODE"/> 928 <param name="SRC1_RGROUP" as="SRC_RGROUP"/> 929 </field> 930 <field name="SRC1_AMODE" low="91" high="93" type="#reg_addressing_mode"/> 931 <field name="SRC1_RGROUP" low="96" high="98" type="#reg_group"/> 932</bitset> 933 934<bitset name="#left-shift" size="3"> 935 <field name="LEFT_SHIFT" low="0" high="2" type="uint"/> 936 937 <override> 938 <expr> 939 {LEFT_SHIFT} != 0 940 </expr> 941 <display> 942 .ls{LEFT_SHIFT} 943 </display> 944 </override> 945 946 <display> 947 </display> 948 949 <encode type="unsigned int"> 950 <map name="LEFT_SHIFT">src</map> 951 </encode> 952</bitset> 953 954<bitset name="#instruction-load" extends="#instruction"> 955 <meta type="load_store"/> 956 <meta has_dest="true" valid_srcs="0|1"/> 957 958 <field name="DST_USE" pos="12" type="bool"/> 959 <field name="DST" low="13" high="26" type="#instruction-dst"> 960 <param name="DST_USE"/> 961 <param name="COMPS"/> 962 </field> 963 964 <pattern low="27" high="31">00000</pattern> <!-- TEX_ID --> 965 <pattern low="32" high="33">00</pattern> <!-- RMODE --> 966 <field name="PMODE" pos="34" type="bool_inv" display=".pack"/> 967 <field name="LEFT_SHIFT" low="35" high="37" type="#left-shift"/> 968 <pattern pos="38">0</pattern> 969 <field name="SKPHP" pos="39" type="bool" display=".skpHp"/> 970 <field name="LOCAL" pos="40" type="bool" display=".local"/> 971 <pattern pos="41">0</pattern> 972 <field name="DENORM" pos="42" type="bool" display=".denorm"/> 973 974 <field name="LOW_HALF" pos="109" type="bool"/> 975 <field name="HIGH_HALF" pos="120" type="bool"/> 976 977 <derived name="THREAD" type="#thread"> 978 <expr>{HIGH_HALF} << 1 | {LOW_HALF}</expr> 979 </derived> 980 981 <field name="DST_FULL" pos="127" type="bool" display=".hp"/> 982 983 <display> 984 {INSTR_LOAD_STORE} {DST:align=18}, {SRC0}, {SRC1}, void 985 </display> 986 987 <!-- SRC0 --> 988 <pattern pos="43">1</pattern> <!-- SRC0_USE --> 989 <field name="SRC0_REG" low="44" high="52" type="uint"/> 990 <field name="SRC0" low="54" high="63" type="#instruction-src"> 991 <param name="SRC0_REG" as="SRC_REG"/> 992 <param name="SRC0_AMODE" as="SRC_AMODE"/> 993 <param name="SRC0_RGROUP" as="SRC_RGROUP"/> 994 </field> 995 <field name="SRC0_AMODE" low="64" high="66" type="#reg_addressing_mode"/> 996 <field name="SRC0_RGROUP" low="67" high="69" type="#reg_group"/> 997 998 <!-- SRC1 --> 999 <pattern pos="70">1</pattern> <!-- SRC1_USE --> 1000 <field name="SRC1_REG" low="71" high="79" type="uint"/> 1001 <field name="SRC1" low="81" high="90" type="#instruction-src"> 1002 <param name="SRC1_REG" as="SRC_REG"/> 1003 <param name="SRC1_AMODE" as="SRC_AMODE"/> 1004 <param name="SRC1_RGROUP" as="SRC_RGROUP"/> 1005 </field> 1006 <field name="SRC1_AMODE" low="91" high="93" type="#reg_addressing_mode"/> 1007 <field name="SRC1_RGROUP" low="96" high="98" type="#reg_group"/> 1008 1009 <!-- SRC2 --> 1010 <pattern pos="99">0</pattern> <!-- SRC2_USE --> 1011 <pattern low="100" high="108">000000000</pattern> <!-- SRC2_REG --> 1012 <pattern low="110" high="117">00000000</pattern> <!-- SRC2_SWIZ --> 1013 <pattern pos="118">0</pattern> <!-- SRC2_NEG --> 1014 <pattern pos="119">0</pattern> <!-- SRC2_ABS --> 1015 <pattern low="121" high="123">000</pattern> <!-- SRC2_AMODE --> 1016 <pattern low="124" high="126">000</pattern> <!-- SRC2_RGROUP --> 1017</bitset> 1018 1019<bitset name="#instruction-store" extends="#instruction"> 1020 <meta type="load_store"/> 1021 <meta has_dest="true" valid_srcs="0|1|2"/> 1022 1023 <pattern low="12" high="16">xxxxx</pattern> 1024 <pattern pos="17">x</pattern> 1025 <pattern low="18" high="22">xxxxx</pattern> 1026 <field name="COMPS" low="23" high="26" type="#wrmask"/> 1027 <pattern low="27" high="31">xxxxx</pattern> 1028 <pattern low="32" high="33">xx</pattern> 1029 <field name="PMODE" pos="34" type="bool_inv" display=".pack"/> 1030 <field name="LEFT_SHIFT" low="35" high="37" type="#left-shift"/> 1031 <pattern pos="38">0</pattern> 1032 <field name="SKPHP" pos="39" type="bool" display=".skpHp"/> 1033 <field name="LOCAL" pos="40" type="bool" display=".local"/> 1034 <pattern low="41" high="41">x</pattern> 1035 <field name="DENORM" pos="42" type="bool" display=".denorm"/> 1036 1037 <field name="LOW_HALF" pos="109" type="bool"/> 1038 <field name="HIGH_HALF" pos="120" type="bool"/> 1039 1040 <derived name="THREAD" type="#thread"> 1041 <expr>{HIGH_HALF} << 1 | {LOW_HALF}</expr> 1042 </derived> 1043 1044 <field name="DST_FULL" pos="127" type="bool" display=".hp"/> 1045 1046 <display> 1047 {INSTR_LOAD_STORE} {:align=18}mem{COMPS}, {SRC0}, {SRC1}, {SRC2} 1048 </display> 1049 1050 <!-- SRC0 --> 1051 <pattern pos="43">1</pattern> <!-- SRC0_USE --> 1052 <field name="SRC0_REG" low="44" high="52" type="uint"/> 1053 <field name="SRC0" low="54" high="63" type="#instruction-src"> 1054 <param name="SRC0_REG" as="SRC_REG"/> 1055 <param name="SRC0_AMODE" as="SRC_AMODE"/> 1056 <param name="SRC0_RGROUP" as="SRC_RGROUP"/> 1057 </field> 1058 <field name="SRC0_AMODE" low="64" high="66" type="#reg_addressing_mode"/> 1059 <field name="SRC0_RGROUP" low="67" high="69" type="#reg_group"/> 1060 1061 <!-- SRC1 --> 1062 <pattern pos="70">1</pattern> <!-- SRC1_USE --> 1063 <field name="SRC1_REG" low="71" high="79" type="uint"/> 1064 <field name="SRC1" low="81" high="90" type="#instruction-src"> 1065 <param name="SRC1_REG" as="SRC_REG"/> 1066 <param name="SRC1_AMODE" as="SRC_AMODE"/> 1067 <param name="SRC1_RGROUP" as="SRC_RGROUP"/> 1068 </field> 1069 <field name="SRC1_AMODE" low="91" high="93" type="#reg_addressing_mode"/> 1070 <field name="SRC1_RGROUP" low="96" high="98" type="#reg_group"/> 1071 1072 <!-- SRC2 --> 1073 <pattern pos="99">1</pattern> <!-- SRC2_USE --> 1074 <field name="SRC2_REG" low="100" high="108" type="uint"/> 1075 <field name="SRC2" low="110" high="119" type="#instruction-src"> 1076 <param name="SRC2_REG" as="SRC_REG"/> 1077 <param name="SRC2_AMODE" as="SRC_AMODE"/> 1078 <param name="SRC2_RGROUP" as="SRC_RGROUP"/> 1079 </field> 1080 <field name="SRC2_AMODE" low="121" high="123" type="#reg_addressing_mode"/> 1081 <field name="SRC2_RGROUP" low="124" high="126" type="#reg_group"/> 1082</bitset> 1083 1084<!-- opcocdes sorted by opc number --> 1085 1086<bitset name="nop" extends="#instruction-alu-no-src"> 1087 <pattern low="0" high="5">000000</pattern> <!-- OPC --> 1088 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 1089</bitset> 1090 1091<bitset name="add" extends="#instruction-alu-src0-src2"> 1092 <pattern low="0" high="5">000001</pattern> <!-- OPC --> 1093 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 1094</bitset> 1095 1096<bitset name="mad" extends="#instruction-alu-src0-src1-src2"> 1097 <pattern low="0" high="5">000010</pattern> <!-- OPC --> 1098 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 1099</bitset> 1100 1101<bitset name="mul" extends="#instruction-alu-src0-src1"> 1102 <pattern low="0" high="5">000011</pattern> <!-- OPC --> 1103 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 1104</bitset> 1105 1106<!-- dst --> 1107 1108<bitset name="dp3" extends="#instruction-alu-src0-src1"> 1109 <pattern low="0" high="5">000101</pattern> <!-- OPC --> 1110 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 1111</bitset> 1112 1113<bitset name="dp4" extends="#instruction-alu-src0-src1"> 1114 <pattern low="0" high="5">000110</pattern> <!-- OPC --> 1115 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 1116</bitset> 1117 1118<bitset name="dsx" extends="#instruction-alu-src0-src2"> 1119 <pattern low="0" high="5">000111</pattern> <!-- OPC --> 1120 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 1121</bitset> 1122 1123<bitset name="dsy" extends="#instruction-alu-src0-src2"> 1124 <pattern low="0" high="5">001000</pattern> <!-- OPC --> 1125 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 1126</bitset> 1127 1128<bitset name="mov" extends="#instruction-alu-src2"> 1129 <pattern low="0" high="5">001001</pattern> <!-- OPC --> 1130 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 1131</bitset> 1132 1133<bitset name="movar" extends="#instruction-alu-src2"> 1134 <pattern low="0" high="5">001010</pattern> <!-- OPC --> 1135 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 1136</bitset> 1137 1138<!-- movaf --> 1139 1140<bitset name="rcp" extends="#instruction-alu-src2"> 1141 <pattern low="0" high="5">001100</pattern> <!-- OPC --> 1142 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 1143</bitset> 1144 1145<bitset name="rsq" extends="#instruction-alu-src2"> 1146 <pattern low="0" high="5">001101</pattern> <!-- OPC --> 1147 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 1148</bitset> 1149 1150<!-- litp --> 1151 1152<bitset name="select" extends="#instruction-alu-src0-src1-src2"> 1153 <pattern low="0" high="5">001111</pattern> <!-- OPC --> 1154 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 1155</bitset> 1156 1157<bitset name="set" extends="#instruction-alu-src0-src1"> 1158 <pattern low="0" high="5">010000</pattern> <!-- OPC --> 1159 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 1160</bitset> 1161 1162<bitset name="exp" extends="#instruction-alu-src2"> 1163 <pattern low="0" high="5">010001</pattern> <!-- OPC --> 1164 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 1165</bitset> 1166 1167<bitset name="log" extends="#instruction-alu-src2"> 1168 <pattern low="0" high="5">010010</pattern> <!-- OPC --> 1169 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 1170</bitset> 1171 1172<bitset name="frc" extends="#instruction-alu-src2"> 1173 <pattern low="0" high="5">010011</pattern> <!-- OPC --> 1174 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 1175</bitset> 1176 1177<bitset name="call" extends="#instruction-cf-no-src"> 1178 <pattern low="0" high="5">010100</pattern> <!-- OPC --> 1179 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 1180</bitset> 1181 1182<bitset name="ret" extends="#instruction-alu-no-src"> 1183 <pattern low="0" high="5">010101</pattern> <!-- OPC --> 1184 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 1185</bitset> 1186 1187<bitset name="branch" extends="#instruction-cf-no-src"> 1188 <pattern low="0" high="5">010110</pattern> <!-- OPC --> 1189 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 1190</bitset> 1191 1192<bitset name="branch_unary" extends="#instruction-cf-src0" displayname="branch"> 1193 <pattern low="0" high="5">010110</pattern> <!-- OPC --> 1194 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 1195</bitset> 1196 1197<bitset name="branch_binary" extends="#instruction-cf-src0-src1" displayname="branch"> 1198 <pattern low="0" high="5">010110</pattern> <!-- OPC --> 1199 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 1200</bitset> 1201 1202<bitset name="texkill" extends="#instruction-alu-no-dst-maybe-src0-src1"> 1203 <pattern low="0" high="5">010111</pattern> <!-- OPC --> 1204 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 1205</bitset> 1206 1207<bitset name="texld" extends="#instruction-tex-src0-maybe-src2"> 1208 <pattern low="0" high="5">011000</pattern> <!-- OPC --> 1209 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 1210</bitset> 1211 1212<bitset name="texldb" extends="#instruction-tex-src0-maybe-src1-src2"> 1213 <pattern low="0" high="5">011001</pattern> <!-- OPC --> 1214 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 1215</bitset> 1216 1217<bitset name="texldd" extends="#instruction-tex-src0-src1-src2"> 1218 <pattern low="0" high="5">011010</pattern> <!-- OPC --> 1219 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 1220</bitset> 1221 1222<bitset name="texldl" extends="#instruction-tex-src0-maybe-src1-src2"> 1223 <pattern low="0" high="5">011011</pattern> <!-- OPC --> 1224 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 1225</bitset> 1226 1227<!-- 0x7800000f 0x9011007c 0x00200804 0x0100100c --> 1228 1229<!-- texldpcf --> 1230<!-- rep --> 1231<!-- endrep --> 1232<!-- loop --> 1233<!-- endloop --> 1234 1235<bitset name="sqrt" extends="#instruction-alu-src2"> 1236 <pattern low="0" high="5">100001</pattern> <!-- OPC --> 1237 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 1238</bitset> 1239 1240<bitset name="sin" extends="#instruction-alu-src2"> 1241 <pattern low="0" high="5">100010</pattern> <!-- OPC --> 1242 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 1243</bitset> 1244 1245<bitset name="cos" extends="#instruction-alu-src2"> 1246 <pattern low="0" high="5">100011</pattern> <!-- OPC --> 1247 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 1248</bitset> 1249 1250<bitset name="branch_any" extends="#instruction-cf-src0-src1"> 1251 <pattern low="0" high="5">100100</pattern> <!-- OPC --> 1252 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 1253</bitset> 1254 1255<bitset name="floor" extends="#instruction-alu-src2"> 1256 <pattern low="0" high="5">100101</pattern> <!-- OPC --> 1257 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 1258</bitset> 1259 1260<bitset name="ceil" extends="#instruction-alu-src2"> 1261 <pattern low="0" high="5">100110</pattern> <!-- OPC --> 1262 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 1263</bitset> 1264 1265<bitset name="sign" extends="#instruction-alu-src2"> 1266 <pattern low="0" high="5">100111</pattern> <!-- OPC --> 1267 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 1268</bitset> 1269 1270<!-- addlo --> 1271<!-- mullo --> 1272 1273<bitset name="barrier" extends="#instruction-alu-no-src"> 1274 <pattern low="0" high="5">101010</pattern> <!-- OPC --> 1275 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 1276</bitset> 1277 1278<!-- swizzle --> 1279 1280<bitset name="i2i" extends="#instruction-alu-src0-src1"> 1281 <pattern low="0" high="5">101100</pattern> <!-- OPC --> 1282 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 1283</bitset> 1284 1285<bitset name="i2f" extends="#instruction-alu-src0"> 1286 <pattern low="0" high="5">101101</pattern> <!-- OPC --> 1287 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 1288</bitset> 1289 1290<bitset name="f2i" extends="#instruction-alu-src0"> 1291 <pattern low="0" high="5">101110</pattern> <!-- OPC --> 1292 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 1293</bitset> 1294 1295<bitset name="f2irnd" extends="#instruction-alu-src0"> 1296 <pattern low="0" high="5">101111</pattern> <!-- OPC --> 1297 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 1298</bitset> 1299 1300<!-- f2i7 --> 1301 1302<bitset name="cmp" extends="#instruction-alu-src0-src1-src2"> 1303 <pattern low="0" high="5">110001</pattern> <!-- OPC --> 1304 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 1305</bitset> 1306 1307<bitset name="load" extends="#instruction-load"> 1308 <pattern low="0" high="5">110010</pattern> <!-- OPC --> 1309 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 1310</bitset> 1311 1312<bitset name="store" extends="#instruction-store"> 1313 <pattern low="0" high="5">110011</pattern> <!-- OPC --> 1314 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 1315</bitset> 1316 1317<bitset name="clamp0_max" extends="#instruction-alu-src0-src1"> 1318 <pattern low="0" high="5">110110</pattern> <!-- OPC --> 1319 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 1320</bitset> 1321 1322<bitset name="iaddsat" extends="#instruction-alu-src0-src2"> 1323 <pattern low="0" high="5">111011</pattern> <!-- OPC --> 1324 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 1325</bitset> 1326 1327<bitset name="imullo0" extends="#instruction-alu-src0-src1"> 1328 <pattern low="0" high="5">111100</pattern> <!-- OPC --> 1329 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 1330</bitset> 1331 1332<!-- imullo1 --> 1333<!-- imullosat0 --> 1334<!-- imullosat1 --> 1335 1336<bitset name="imulhi0" extends="#instruction-alu-src0-src1"> 1337 <pattern low="0" high="5">000000</pattern> <!-- OPC --> 1338 <pattern pos="80">1</pattern> <!-- OPCODE_BIT6 --> 1339</bitset> 1340 1341<!-- imulhi1 --> 1342 1343<bitset name="idiv0" extends="#instruction-alu-src0-src1"> 1344 <pattern low="0" high="5">000100</pattern> <!-- OPC --> 1345 <pattern pos="80">1</pattern> <!-- OPCODE_BIT6 --> 1346</bitset> 1347 1348<bitset name="imod" extends="#instruction-alu-src0-src1"> 1349 <pattern low="0" high="5">001000</pattern> <!-- OPC --> 1350 <pattern pos="80">1</pattern> <!-- OPCODE_BIT6 --> 1351</bitset> 1352 1353<bitset name="imadlo0" extends="#instruction-alu-src0-src1-src2"> 1354 <pattern low="0" high="5">001100</pattern> <!-- OPC --> 1355 <pattern pos="80">1</pattern> <!-- OPCODE_BIT6 --> 1356</bitset> 1357 1358<bitset name="imadlosat0" extends="#instruction-alu-src0-src1-src2"> 1359 <pattern low="0" high="5">001110</pattern> <!-- OPC --> 1360 <pattern pos="80">1</pattern> <!-- OPCODE_BIT6 --> 1361</bitset> 1362 1363<bitset name="movai" extends="#instruction-alu-src2"> 1364 <meta has_dest="false"/> 1365 1366 <pattern low="0" high="5">010110</pattern> <!-- OPC --> 1367 <pattern pos="80">1</pattern> <!-- OPCODE_BIT6 --> 1368</bitset> 1369 1370<bitset name="iabs" extends="#instruction-alu-src2"> 1371 <pattern low="0" high="5">010111</pattern> <!-- OPC --> 1372 <pattern pos="80">1</pattern> <!-- OPCODE_BIT6 --> 1373</bitset> 1374 1375<bitset name="leadzero" extends="#instruction-alu-src2"> 1376 <pattern low="0" high="5">011000</pattern> <!-- OPC --> 1377 <pattern pos="80">1</pattern> <!-- OPCODE_BIT6 --> 1378</bitset> 1379 1380<bitset name="lshift" extends="#instruction-alu-src0-src2"> 1381 <pattern low="0" high="5">011001</pattern> <!-- OPC --> 1382 <pattern pos="80">1</pattern> <!-- OPCODE_BIT6 --> 1383</bitset> 1384 1385<bitset name="rshift" extends="#instruction-alu-src0-src2"> 1386 <pattern low="0" high="5">011010</pattern> <!-- OPC --> 1387 <pattern pos="80">1</pattern> <!-- OPCODE_BIT6 --> 1388</bitset> 1389 1390<bitset name="rotate" extends="#instruction-alu-src0-src2"> 1391 <pattern low="0" high="5">011011</pattern> <!-- OPC --> 1392 <pattern pos="80">1</pattern> <!-- OPCODE_BIT6 --> 1393</bitset> 1394 1395<bitset name="or" extends="#instruction-alu-src0-src2"> 1396 <pattern low="0" high="5">011100</pattern> <!-- OPC --> 1397 <pattern pos="80">1</pattern> <!-- OPCODE_BIT6 --> 1398</bitset> 1399 1400<bitset name="and" extends="#instruction-alu-src0-src2"> 1401 <pattern low="0" high="5">011101</pattern> <!-- OPC --> 1402 <pattern pos="80">1</pattern> <!-- OPCODE_BIT6 --> 1403</bitset> 1404 1405<bitset name="xor" extends="#instruction-alu-src0-src2"> 1406 <pattern low="0" high="5">011110</pattern> <!-- OPC --> 1407 <pattern pos="80">1</pattern> <!-- OPCODE_BIT6 --> 1408</bitset> 1409 1410<bitset name="not" extends="#instruction-alu-src2"> 1411 <pattern low="0" high="5">011111</pattern> <!-- OPC --> 1412 <pattern pos="80">1</pattern> <!-- OPCODE_BIT6 --> 1413</bitset> 1414 1415<bitset name="bit_extract" extends="#instruction-alu-src0-src1-src2"> 1416 <pattern low="0" high="5">100000</pattern> <!-- OPC --> 1417 <pattern pos="80">1</pattern> <!-- OPCODE_BIT6 --> 1418</bitset> 1419 1420<bitset name="popcount" extends="#instruction-alu-src2"> 1421 <pattern low="0" high="5">100001</pattern> <!-- OPC --> 1422 <pattern pos="80">1</pattern> <!-- OPCODE_BIT6 --> 1423</bitset> 1424 1425<bitset name="div" extends="#instruction-alu-src1-src2"> 1426 <pattern low="0" high="5">100100</pattern> <!-- OPC --> 1427 <pattern pos="80">1</pattern> <!-- OPCODE_BIT6 --> 1428</bitset> 1429 1430<bitset name="atomic_add" extends="#instruction-alu-src0-src1-src2"> 1431 <pattern low="0" high="5">100101</pattern> <!-- OPC --> 1432 <pattern pos="80">1</pattern> <!-- OPCODE_BIT6 --> 1433</bitset> 1434 1435<bitset name="atomic_xchg" extends="#instruction-alu-src0-src1-src2"> 1436 <pattern low="0" high="5">100110</pattern> <!-- OPC --> 1437 <pattern pos="80">1</pattern> <!-- OPCODE_BIT6 --> 1438</bitset> 1439 1440<bitset name="atomic_cmp_xchg" extends="#instruction-alu-src0-src1-src2"> 1441 <pattern low="0" high="5">100111</pattern> <!-- OPC --> 1442 <pattern pos="80">1</pattern> <!-- OPCODE_BIT6 --> 1443</bitset> 1444 1445<bitset name="atomic_min" extends="#instruction-alu-src0-src1-src2"> 1446 <pattern low="0" high="5">101000</pattern> <!-- OPC --> 1447 <pattern pos="80">1</pattern> <!-- OPCODE_BIT6 --> 1448</bitset> 1449 1450<bitset name="atomic_max" extends="#instruction-alu-src0-src1-src2"> 1451 <pattern low="0" high="5">101001</pattern> <!-- OPC --> 1452 <pattern pos="80">1</pattern> <!-- OPCODE_BIT6 --> 1453</bitset> 1454 1455<bitset name="atomic_or" extends="#instruction-alu-src0-src1-src2"> 1456 <pattern low="0" high="5">101010</pattern> <!-- OPC --> 1457 <pattern pos="80">1</pattern> <!-- OPCODE_BIT6 --> 1458</bitset> 1459 1460<bitset name="atomic_and" extends="#instruction-alu-src0-src1-src2"> 1461 <pattern low="0" high="5">101011</pattern> <!-- OPC --> 1462 <pattern pos="80">1</pattern> <!-- OPCODE_BIT6 --> 1463</bitset> 1464 1465<bitset name="atomic_xor" extends="#instruction-alu-src0-src1-src2"> 1466 <pattern low="0" high="5">101100</pattern> <!-- OPC --> 1467 <pattern pos="80">1</pattern> <!-- OPCODE_BIT6 --> 1468</bitset> 1469 1470<bitset name="bit_rev" extends="#instruction-alu-src0"> 1471 <pattern low="0" high="5">101101</pattern> <!-- OPC --> 1472 <pattern pos="80">1</pattern> <!-- OPCODE_BIT6 --> 1473</bitset> 1474 1475<bitset name="texldlpcf" extends="#instruction-tex-src0-src1-src2"> 1476 <pattern low="0" high="5">101111</pattern> <!-- OPC --> 1477 <pattern pos="80">1</pattern> <!-- OPCODE_BIT6 --> 1478</bitset> 1479 1480<bitset name="conv" extends="#instruction-alu-src0-src1"> 1481 <pattern low="0" high="5">110010</pattern> <!-- OPC --> 1482 <pattern pos="80">1</pattern> <!-- OPCODE_BIT6 --> 1483</bitset> 1484 1485<bitset name="dp2" extends="#instruction-alu-src0-src1"> 1486 <pattern low="0" high="5">110011</pattern> <!-- OPC --> 1487 <pattern pos="80">1</pattern> <!-- OPCODE_BIT6 --> 1488</bitset> 1489 1490<bitset name="norm_dp2" extends="#instruction-alu-src0"> 1491 <pattern low="0" high="5">110100</pattern> <!-- OPC --> 1492 <pattern pos="80">1</pattern> <!-- OPCODE_BIT6 --> 1493</bitset> 1494 1495<bitset name="norm_dp3" extends="#instruction-alu-src0"> 1496 <pattern low="0" high="5">110101</pattern> <!-- OPC --> 1497 <pattern pos="80">1</pattern> <!-- OPCODE_BIT6 --> 1498</bitset> 1499 1500<bitset name="norm_dp4" extends="#instruction-alu-src0"> 1501 <pattern low="0" high="5">110110</pattern> <!-- OPC --> 1502 <pattern pos="80">1</pattern> <!-- OPCODE_BIT6 --> 1503</bitset> 1504 1505<bitset name="img_load" extends="#instruction-load"> 1506 <pattern low="0" high="5">111001</pattern> <!-- OPC --> 1507 <pattern pos="80">1</pattern> <!-- OPCODE_BIT6 --> 1508</bitset> 1509 1510<bitset name="img_store" extends="#instruction-store"> 1511 <pattern low="0" high="5">111010</pattern> <!-- OPC --> 1512 <pattern pos="80">1</pattern> <!-- OPCODE_BIT6 --> 1513</bitset> 1514 1515<bitset name="#extended-instruction-alu" extends="#instruction-alu"> 1516 <pattern low="0" high="5">111111</pattern> <!-- OPC --> 1517 <pattern pos="80">1</pattern> <!-- OPCODE_BIT6 --> 1518</bitset> 1519 1520<bitset name="#extended-instruction-alu-src0" extends="#extended-instruction-alu"> 1521 <meta has_dest="true" valid_srcs="0"/> 1522 1523 <display> 1524 {INSTR_ALU} {DST:align=18}, {SRC0}, void, void 1525 </display> 1526 1527 <!-- SRC0 --> 1528 <pattern pos="43">1</pattern> <!-- SRC0_USE --> 1529 <field name="SRC0_REG" low="44" high="52" type="uint"/> 1530 <field name="SRC0" low="54" high="63" type="#instruction-src"> 1531 <param name="SRC0_REG" as="SRC_REG"/> 1532 <param name="SRC0_AMODE" as="SRC_AMODE"/> 1533 <param name="SRC0_RGROUP" as="SRC_RGROUP"/> 1534 </field> 1535 <field name="SRC0_AMODE" low="64" high="66" type="#reg_addressing_mode"/> 1536 <field name="SRC0_RGROUP" low="67" high="69" type="#reg_group"/> 1537 1538 <!-- SRC1 --> 1539 <pattern pos="70">0</pattern> <!-- SRC1_USE --> 1540 <pattern low="71" high="79">000000000</pattern> <!-- SRC1_REG --> 1541 <pattern low="81" high="88">00000000</pattern> <!-- SRC1_SWIZ --> 1542 <pattern pos="89">0</pattern> <!-- SRC1_NEG --> 1543 <pattern pos="90">0</pattern> <!-- SRC1_ABS --> 1544 <pattern low="91" high="93">000</pattern> <!-- SRC1_AMODE --> 1545 <pattern low="96" high="98">000</pattern> <!-- SRC1_RGROUP --> 1546 1547 <!-- SRC2 as IMMED (uint 20 bit). SRC2_REG is the extended opcode --> 1548 <pattern pos="99">1</pattern> <!-- SRC2_USE --> 1549 <pattern low="110" high="117">00000000</pattern> <!-- SRC2_SWIZ --> 1550 <pattern pos="118">0</pattern> <!-- SRC2_NEG --> 1551 <pattern pos="119">0</pattern> <!-- SRC2_ABS --> 1552 <pattern low="121" high="123">100</pattern> <!-- SRC2_AMODE --> 1553 <pattern low="124" high="126">111</pattern> <!-- SRC2_RGROUP --> 1554</bitset> 1555 1556<bitset name="bit_findlsb" extends="#extended-instruction-alu-src0"> 1557 <pattern low="100" high="108">000001011</pattern> <!-- OPC --> 1558</bitset> 1559 1560<bitset name="bit_findmsb" extends="#extended-instruction-alu-src0"> 1561 <pattern low="100" high="108">000001100</pattern> <!-- OPC --> 1562</bitset> 1563</isa> 1564