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1; a6xx microcode
2; Version: 016ee001
3
4[016ee001]
5[#jumptbl]
6mov $01, 0x830	; CP_SQE_INSTR_BASE
7mov $02, 0x2
8cwrite $01, [$00 + @REG_READ_ADDR]
9cwrite $02, [$00 + @REG_READ_DWORDS]
10mov $01, $regdata
11mov $02, $regdata
12add $01, $01, 0x4
13addhi $02, $02, 0x0
14mov $03, 0x1
15cwrite $01, [$00 + @MEM_READ_ADDR]
16cwrite $02, [$00 + @MEM_READ_ADDR+0x1]
17cwrite $03, [$00 + @MEM_READ_DWORDS]
18rot $04, $memdata, 0x8
19ushr $04, $04, 0x6
20sub $04, $04, 0x4
21add $01, $01, $04
22addhi $02, $02, 0x0
23mov $rem, 0x80
24cwrite $01, [$00 + @MEM_READ_ADDR]
25cwrite $02, [$00 + @MEM_READ_ADDR+0x1]
26cwrite $02, [$00 + @LOAD_STORE_HI]
27cwrite $rem, [$00 + @MEM_READ_DWORDS]
28cwrite $00, [$00 + @PACKET_TABLE_WRITE_ADDR]
29(rep)cwrite $memdata, [$00 + @PACKET_TABLE_WRITE]
30mov $02, 0x883	; CP_SCRATCH[0].REG
31mov $03, 0xbeef
32mov $04, 0xdead << 16
33or $03, $03, $04
34cwrite $02, [$00 + @REG_WRITE_ADDR]
35cwrite $03, [$00 + @REG_WRITE]
36waitin
37mov $01, $data
38
39CP_ME_INIT:
40mov $02, 0x2
41waitin
42mov $01, $data
43
44CP_MEM_WRITE:
45mov $addr, 0xa0 << 24	; |NRT_ADDR
46mov $02, 0x4
47(xmov1)add $data, $02, $data
48mov $addr, 0xa204 << 16	; |NRT_DATA
49(rep)(xmov3)mov $data, $data
50waitin
51mov $01, $data
52
53CP_SCRATCH_WRITE:
54mov $02, 0xff
55(rep)cwrite $data, [$02 + 0x1]!
56waitin
57mov $01, $data
58
59CP_SET_DRAW_STATE:
60(rep)(sds2)cwrite $data, [$00 + @DRAW_STATE_SET_HDR]
61waitin
62mov $01, $data
63
64CP_SET_BIN_DATA5:
65sread $02, [$00 + %SP]
66swrite $02, [$00 + %SP]
67mov $02, 0x7
68(rep)swrite $data, [$02 + 0x1]!
69waitin
70mov $01, $data
71
72CP_SET_SECURE_MODE:
73mov $02, $data
74setsecure $02, #l61
75
76fxn59:
77l59:
78jump #l59
79nop
80l61:
81waitin
82mov $01, $data
83
84fxn63:
85l63:
86cmp $04, $02, $03
87breq $04, b0, #l70
88brne $04, b1, #l68
89breq $04, b2, #l63
90sub $03, $03, $02
91l68:
92jump #l63
93sub $02, $02, $03
94l70:
95ret
96nop
97
98CP_REG_RMW:
99cwrite $data, [$00 + @REG_READ_ADDR]
100add $02, $regdata, 0x42
101addhi $03, $00, $regdata
102sub $02, $02, $regdata
103call #fxn63
104subhi $03, $03, $regdata
105and $02, $02, $regdata
106or $02, $02, 0x1
107xor $02, $02, 0x1
108not $02, $02
109shl $02, $02, $regdata
110ushr $02, $02, $regdata
111ishr $02, $02, $regdata
112rot $02, $02, $regdata
113min $02, $02, $regdata
114max $02, $02, $regdata
115mul8 $02, $02, $regdata
116msb $02, $02
117mov $usraddr, $data
118mov $data, $02
119waitin
120mov $01, $data
121
122CP_MEMCPY:
123mov $02, $data
124mov $03, $data
125mov $04, $data
126mov $05, $data
127mov $06, $data
128l99:
129breq $06, 0x0, #l105
130cwrite $03, [$00 + @LOAD_STORE_HI]
131load $07, [$02 + 0x4]!
132cwrite $05, [$00 + @LOAD_STORE_HI]
133jump #l99
134store $07, [$04 + 0x4]!
135l105:
136waitin
137mov $01, $data
138
139CP_MEM_TO_MEM:
140cwrite $data, [$00 + @MEM_READ_ADDR]
141cwrite $data, [$00 + @MEM_READ_ADDR+0x1]
142mov $02, $data
143cwrite $data, [$00 + @LOAD_STORE_HI]
144mov $rem, $data
145cwrite $rem, [$00 + @MEM_READ_DWORDS]
146(rep)store $memdata, [$02 + 0x4]!
147waitin
148mov $01, $data
149
150IN_PREEMPT:
151cread $02, [$00 + 0x101]
152brne $02, 0x1, #l125
153nop
154bl #fxn59
155nop
156nop
157nop
158waitin
159mov $01, $data
160l125:
161iret
162nop
163
164CP_BLIT:
165CP_BOOTSTRAP_UCODE:
166CP_COND_EXEC:
167CP_COND_REG_EXEC:
168CP_COND_WRITE5:
169CP_CONTEXT_REG_BUNCH:
170CP_CONTEXT_SWITCH:
171CP_CONTEXT_SWITCH_YIELD:
172CP_CONTEXT_UPDATE:
173CP_DRAW_AUTO:
174CP_DRAW_INDIRECT:
175CP_DRAW_INDIRECT_MULTI:
176CP_DRAW_INDX:
177CP_DRAW_INDX_INDIRECT:
178CP_DRAW_INDX_OFFSET:
179CP_DRAW_PRED_ENABLE_GLOBAL:
180CP_DRAW_PRED_ENABLE_LOCAL:
181CP_DRAW_PRED_SET:
182CP_END_BIN:
183CP_EVENT_WRITE:
184CP_EVENT_WRITE_CFL:
185CP_EVENT_WRITE_SHD:
186CP_EVENT_WRITE_ZPD:
187CP_EXEC_CS:
188CP_EXEC_CS_INDIRECT:
189CP_IM_LOAD:
190CP_IM_LOAD_IMMEDIATE:
191CP_INDIRECT_BUFFER:
192CP_INDIRECT_BUFFER_CHAIN:
193CP_INDIRECT_BUFFER_PFD:
194CP_INTERRUPT:
195CP_INVALIDATE_STATE:
196CP_LOAD_STATE6:
197CP_LOAD_STATE6_FRAG:
198CP_LOAD_STATE6_GEOM:
199CP_MEM_TO_REG:
200CP_MEM_WRITE_CNTR:
201CP_NOP:
202CP_PREEMPT_DISABLE:
203CP_RECORD_PFP_TIMESTAMP:
204CP_REG_TEST:
205CP_REG_TO_MEM:
206CP_REG_TO_MEM_OFFSET_MEM:
207CP_REG_TO_MEM_OFFSET_REG:
208CP_REG_TO_SCRATCH:
209CP_REG_WRITE:
210CP_REG_WR_NO_CTXT:
211CP_RUN_OPENCL:
212CP_SCRATCH_TO_REG:
213CP_SET_AMBLE:
214CP_SET_BIN_DATA5_OFFSET:
215CP_SET_DRAW_INIT_FLAGS:
216CP_SET_MARKER:
217CP_SET_MODE:
218CP_SET_PROTECTED_MODE:
219CP_SET_PSEUDO_REG:
220CP_SET_STATE:
221CP_SET_SUBDRAW_SIZE:
222CP_SET_VISIBILITY_OVERRIDE:
223CP_SKIP_IB2_ENABLE_GLOBAL:
224CP_SKIP_IB2_ENABLE_LOCAL:
225CP_SMMU_TABLE_UPDATE:
226CP_START_BIN:
227CP_TEST_TWO_MEMS:
228CP_WAIT_FOR_IDLE:
229CP_WAIT_FOR_ME:
230CP_WAIT_MEM_GTE:
231CP_WAIT_MEM_WRITES:
232CP_WAIT_REG_EQ:
233CP_WAIT_REG_MEM:
234CP_WAIT_TWO_REGS:
235CP_WHERE_AM_I:
236IN_GMU_INTERRUPT:
237IN_IB_END:
238PKT4:
239UNKN0:
240UNKN1:
241UNKN103:
242UNKN104:
243UNKN105:
244UNKN106:
245UNKN110:
246UNKN118:
247UNKN119:
248UNKN12:
249UNKN121:
250UNKN122:
251UNKN123:
252UNKN124:
253UNKN125:
254UNKN126:
255UNKN127:
256UNKN13:
257UNKN14:
258UNKN2:
259UNKN21:
260UNKN22:
261UNKN23:
262UNKN24:
263UNKN27:
264UNKN28:
265UNKN3:
266UNKN30:
267UNKN31:
268UNKN32:
269UNKN45:
270UNKN48:
271UNKN5:
272UNKN58:
273UNKN6:
274UNKN7:
275UNKN73:
276UNKN8:
277UNKN9:
278UNKN90:
279UNKN93:
280UNKN96:
281UNKN97:
282waitin
283mov $01, $data
284jumptbl:
285.jumptbl
286