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1; Copyright (c) 2020 Valve Corporation
2;
3; Permission is hereby granted, free of charge, to any person obtaining a
4; copy of this software and associated documentation files (the "Software"),
5; to deal in the Software without restriction, including without limitation
6; the rights to use, copy, modify, merge, publish, distribute, sublicense,
7; and/or sell copies of the Software, and to permit persons to whom the
8; Software is furnished to do so, subject to the following conditions:
9;
10; The above copyright notice and this permission notice (including the next
11; paragraph) shall be included in all copies or substantial portions of the
12; Software.
13;
14; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17; THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18; LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
19; OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
20; SOFTWARE.
21;
22;
23; This file is the source for a simple mock firmware used to regression test
24; the afuc assembler/disassembler. This is the a7xx variant, for testing new
25; features introduced in a7xx.
26[01730001]
27[#jumptbl]
28loc02:
29; packet table loading:
30mov $01, 0x0830 ; CP_SQE_INSTR_BASE
31mov $02, 0x0002
32cwrite $01, [$00 + @REG_READ_ADDR]
33cwrite $02, [$00 + @REG_READ_DWORDS]
34; move hi/lo of SQE fw addrs to registers:
35mov $01, $regdata
36mov $02, $regdata
37; skip first dword
38add $01, $01, 0x0004
39addhi $02, $02, 0x0000
40mov $03, 0x0001
41cwrite $01, [$00 + @MEM_READ_ADDR]
42cwrite $02, [$00 + @MEM_READ_ADDR+0x1]
43cwrite $03, [$00 + @MEM_READ_DWORDS]
44; read 2nd dword of fw, and add offset (minus 4 because we skipped first dword)
45; to base address of sqe fw
46rot $04, $memdata, 0x0008
47ushr $04, $04, 0x0006
48sub $04, $04, 0x0004
49add $01, $01, $04
50addhi $02, $02, 0x0000
51
52; load packet table:
53mov $rem, 0x0080
54cwrite $01, [$00 + @MEM_READ_ADDR]
55cwrite $02, [$00 + @MEM_READ_ADDR+0x1]
56cwrite $02, [$00 + @LOAD_STORE_HI]
57cwrite $rem, [$00 + @MEM_READ_DWORDS]
58cwrite $00, [$00 + @PACKET_TABLE_WRITE_ADDR]
59(rep)cwrite $memdata, [$00 + @PACKET_TABLE_WRITE]
60
61; load BV SQE base address, which should be after the packet table:
62add $01, $01, 0x200
63addhi $02, $02, 0x0
64cwrite $01, [$00 + @BV_INSTR_BASE]
65cwrite $02, [$00 + @BV_INSTR_BASE+1]
66
67; kick off the BV
68cwrite $03, [$00 + @BV_CNTL]
69
70; get BV packet table offset:
71add $01, $01, 0x4
72addhi $02, $02, 0
73
74cwrite $01, [$00 + @MEM_READ_ADDR]
75cwrite $02, [$00 + @MEM_READ_ADDR+1]
76cwrite $03, [$00 + @MEM_READ_DWORDS]
77
78rot $04, $memdata, 8
79ushr $04, $04, 6
80sub $04, $04, 4
81add $01, $01, $04
82addhi $02, $02, 0x0
83
84; load LPAC base address, which is after the BV packet table
85add $01, $01, 0x200
86addhi $02, $02, 0x0
87
88cwrite $01, [$00 + @LPAC_INSTR_BASE]
89cwrite $02, [$00 + @LPAC_INSTR_BASE+1]
90
91; kick off the LPAC
92cwrite $03, [$00 + @LPAC_CNTL]
93
94mov $02, 0x883
95mov $03, 0xbeef
96mov $04, 0xdead << 16
97or $03, $03, $04
98cwrite $02, [$00 + @REG_WRITE_ADDR]
99cwrite $03, [$00 + @REG_WRITE]
100waitin
101mov $01, $data
102
103CP_ME_INIT:
104; test label-as-immediate feature
105mov $02, #loc02 ; should be 0x0002
106waitin
107mov $01, $data
108
109CP_MEM_WRITE:
110; test $addr + (rep) + (xmovN) with ALU
111mov $addr, 0xa0 << 24
112mov $02, 4
113(xmov1)add $data, $02, $data
114mov $addr, 0xa204 << 16
115(rep)(xmov3)mov $data, $data
116waitin
117mov $01, $data
118
119CP_SCRATCH_WRITE:
120; test (rep) + preincrement + non-zero offset with cwrite
121mov $02, 0xff
122(rep)cwrite $data, [$02 + 0x001]!
123waitin
124mov $01, $data
125
126CP_SET_DRAW_STATE:
127; test (sds)
128(rep)(sds2) cwrite $data, [$00 + @DRAW_STATE_SET_HDR]
129waitin
130mov $01, $data
131
132CP_SET_BIN_DATA5:
133; test SQE registers
134sread $02, [$00 + %SP]
135swrite $02, [$00 + %SP]
136mov $02, 7
137(rep)swrite $data, [$02 + 1]!
138waitin
139mov $01, $data
140
141CP_SET_SECURE_MODE:
142; test setsecure
143mov $02, $data
144setsecure $02, #setsecure_success
145err:
146jump #err
147nop
148setsecure_success:
149waitin
150mov $01, $data
151
152euclid:
153; Euclid's algorithm in afuc: https://en.wikipedia.org/wiki/Euclidean_algorithm
154; Since afuc doesn't do modulo, we implement the subtraction-based version.
155;
156; Demonstrates/tests comparisons and conditional branches. This also
157; demonstrates the common trick of branching in a delay slot. Note that if a
158; branch is taken and its delay slot includes another branch, the second
159; branch cannot also be taken, which is why the last branch in the sequence
160; cannot be unconditional.
161;
162; Inputs are in $02 and $03, and output is in $02.
163cmp $04, $02, $03
164breq $04, b0, #euclid_exit
165brne $04, b1, #euclid_gt
166breq $04, b2, #euclid
167sub $03, $03, $02
168euclid_gt:
169jump #euclid
170sub $02, $02, $03
171euclid_exit:
172ret
173nop
174
175CP_REG_RMW:
176; Test various ALU instructions, and read/write $regdata
177cwrite $data, [$00 + @REG_READ_ADDR]
178add $02, $regdata, 0x42
179addhi $03, $00, $regdata
180sub $02, $02, $regdata
181call #euclid
182subhi $03, $03, $regdata
183and $02, $02, $regdata
184or $02, $02, 0x1
185xor $02, $02, 0x1
186not $02, $02
187shl $02, $02, $regdata
188ushr $02, $02, $regdata
189ishr $02, $02, $regdata
190rot $02, $02, $regdata
191min $02, $02, $regdata
192max $02, $02, $regdata
193mul8 $02, $02, $regdata
194bic $02, $02, $regdata
195msb $02, $02
196bfi $02, $03, b1, b2
197setbit $02, $02, b3
198clrbit $02, $02, b4
199setbit $02, $02, $03
200ubfx $03, $02, b5, b6
201mov $usraddr, $data
202mov $data, $02
203(peek)mov $00, $data
204waitin
205mov $01, $data
206
207CP_MEMCPY:
208; implement CP_MEMCPY using load/store instructions
209mov $02, $data
210mov $03, $data
211mov $04, $data
212mov $05, $data
213mov $06, $data
214cpy_header:
215breq $06, 0, #cpy_exit
216cwrite $03, [$00 + @LOAD_STORE_HI]
217load $07, [$02 + 0x004]!
218cwrite $05, [$00 + @LOAD_STORE_HI]
219jump #cpy_header
220store $07, [$04 + 0x004]!
221cpy_exit:
222waitin
223mov $01, $data
224
225CP_MEM_TO_MEM:
226; implement CP_MEMCPY using mem read control regs
227; tests @FOO+0x1 for 64-bit control regs, and reading/writing $rem
228cwrite $data, [$00 + @MEM_READ_ADDR]
229cwrite $data, [$00 + @MEM_READ_ADDR+1]
230mov $02, $data
231cwrite $data, [$00 + @LOAD_STORE_HI]
232mov $rem, $data
233cwrite $rem, [$00 + @MEM_READ_DWORDS]
234(rep)store $memdata, [$02 + 0x004]!
235waitin
236mov $01, $data
237
238IN_PREEMPT:
239; test bl + iret + conditional branch w/ immed
240cread $02, [$00 + 0x101]
241brne $02, 0x0001, #exit_iret
242nop
243bl #err
244nop
245nop
246nop
247waitin
248mov $01, $data
249exit_iret:
250iret
251nop
252
253UNKN0:
254UNKN1:
255UNKN2:
256UNKN3:
257PKT4:
258UNKN5:
259UNKN6:
260UNKN7:
261UNKN8:
262UNKN9:
263UNKN10:
264UNKN11:
265UNKN12:
266UNKN13:
267UNKN14:
268CP_NOP:
269CP_RECORD_PFP_TIMESTAMP:
270CP_WAIT_MEM_WRITES:
271CP_WAIT_FOR_ME:
272CP_WAIT_MEM_GTE:
273UNKN21:
274UNKN22:
275UNKN23:
276UNKN24:
277CP_DRAW_PRED_ENABLE_GLOBAL:
278CP_DRAW_PRED_ENABLE_LOCAL:
279UNKN27:
280CP_PREEMPT_ENABLE:
281CP_SKIP_IB2_ENABLE_GLOBAL:
282CP_PREEMPT_TOKEN:
283UNKN31:
284UNKN32:
285CP_DRAW_INDX:
286CP_SKIP_IB2_ENABLE_LOCAL:
287CP_DRAW_AUTO:
288CP_SET_STATE:
289CP_WAIT_FOR_IDLE:
290CP_IM_LOAD:
291CP_DRAW_INDIRECT:
292CP_DRAW_INDX_INDIRECT:
293CP_DRAW_INDIRECT_MULTI:
294CP_IM_LOAD_IMMEDIATE:
295CP_BLIT:
296CP_SET_CONSTANT:
297CP_SET_BIN_DATA5_OFFSET:
298UNKN48:
299CP_RUN_OPENCL:
300CP_LOAD_STATE6_GEOM:
301CP_EXEC_CS:
302CP_LOAD_STATE6_FRAG:
303CP_SET_SUBDRAW_SIZE:
304CP_LOAD_STATE6:
305CP_INDIRECT_BUFFER_PFD:
306CP_DRAW_INDX_OFFSET:
307CP_REG_TEST:
308CP_CCHE_INVALIDATE:
309CP_INVALIDATE_STATE:
310CP_WAIT_REG_MEM:
311CP_REG_TO_MEM:
312CP_INDIRECT_BUFFER:
313CP_INTERRUPT:
314CP_EXEC_CS_INDIRECT:
315CP_MEM_TO_REG:
316CP_COND_EXEC:
317CP_COND_WRITE5:
318CP_EVENT_WRITE:
319CP_COND_REG_EXEC:
320UNKN73:
321CP_REG_TO_SCRATCH:
322CP_SET_DRAW_INIT_FLAGS:
323CP_SCRATCH_TO_REG:
324CP_DRAW_PRED_SET:
325CP_MEM_WRITE_CNTR:
326CP_START_BIN:
327CP_END_BIN:
328CP_WAIT_REG_EQ:
329CP_SMMU_TABLE_UPDATE:
330UNKN84:
331CP_SET_AMBLE:
332CP_SET_PSEUDO_REG:
333CP_INDIRECT_BUFFER_CHAIN:
334CP_EVENT_WRITE_SHD:
335CP_EVENT_WRITE_CFL:
336UNKN90:
337CP_EVENT_WRITE_ZPD:
338CP_CONTEXT_REG_BUNCH:
339CP_WAIT_IB_PFD_COMPLETE:
340CP_CONTEXT_UPDATE:
341CP_SET_PROTECTED_MODE:
342UNKN96:
343UNKN97:
344UNKN98:
345CP_SET_MODE:
346CP_SET_VISIBILITY_OVERRIDE:
347CP_SET_MARKER:
348UNKN103:
349UNKN104:
350UNKN105:
351UNKN106:
352UNKN107:
353UNKN108:
354CP_REG_WRITE:
355UNKN110:
356CP_BOOTSTRAP_UCODE:
357CP_WAIT_TWO_REGS:
358CP_TEST_TWO_MEMS:
359CP_REG_TO_MEM_OFFSET_REG:
360CP_REG_TO_MEM_OFFSET_MEM:
361UNKN118:
362UNKN119:
363CP_REG_WR_NO_CTXT:
364UNKN121:
365UNKN122:
366UNKN123:
367UNKN124:
368UNKN125:
369UNKN126:
370UNKN127:
371        waitin
372        mov $01, $data
373
374.align 32
375jumptbl:
376.jumptbl
377
378.section BV
379; BV microcode
380
381[01000001]
382[#jumptbl]
383
384; read BV fw addr
385cread $01, [$00 + @BV_INSTR_BASE]
386cread $02, [$00 + @BV_INSTR_BASE+1]
387
388; skip first dword
389add $01, $01, 0x0004
390addhi $02, $02, 0x0000
391mov $03, 0x0001
392cwrite $01, [$00 + @MEM_READ_ADDR]
393cwrite $02, [$00 + @MEM_READ_ADDR+0x1]
394cwrite $03, [$00 + @MEM_READ_DWORDS]
395; read 2nd dword of fw, and add offset (minus 4 because we skipped first dword)
396; to base address of sqe fw
397rot $04, $memdata, 0x0008
398ushr $04, $04, 0x0006
399sub $04, $04, 0x0004
400add $01, $01, $04
401addhi $02, $02, 0x0000
402
403; load packet table:
404mov $rem, 0x0080
405cwrite $01, [$00 + @MEM_READ_ADDR]
406cwrite $02, [$00 + @MEM_READ_ADDR+0x1]
407cwrite $02, [$00 + @LOAD_STORE_HI]
408cwrite $rem, [$00 + @MEM_READ_DWORDS]
409cwrite $00, [$00 + @PACKET_TABLE_WRITE_ADDR]
410(rep)cwrite $memdata, [$00 + @PACKET_TABLE_WRITE]
411
412; load LPAC SQE base address, which should be after the packet table:
413add $01, $01, 0x200
414addhi $02, $02, 0x0
415cwrite $01, [$00 + @LPAC_INSTR_BASE]
416cwrite $02, [$00 + @LPAC_INSTR_BASE+1]
417
418waitin
419mov $01, $data
420
421CP_ME_INIT:
422CP_MEM_WRITE:
423CP_SCRATCH_WRITE:
424CP_SET_DRAW_STATE:
425CP_SET_BIN_DATA5:
426CP_SET_SECURE_MODE:
427CP_REG_RMW:
428CP_MEMCPY:
429CP_MEM_TO_MEM:
430IN_PREEMPT:
431UNKN0:
432UNKN1:
433UNKN2:
434UNKN3:
435PKT4:
436UNKN5:
437UNKN6:
438UNKN7:
439UNKN8:
440UNKN9:
441UNKN10:
442UNKN11:
443UNKN12:
444UNKN13:
445UNKN14:
446CP_NOP:
447CP_RECORD_PFP_TIMESTAMP:
448CP_WAIT_MEM_WRITES:
449CP_WAIT_FOR_ME:
450CP_WAIT_MEM_GTE:
451UNKN21:
452UNKN22:
453UNKN23:
454UNKN24:
455CP_DRAW_PRED_ENABLE_GLOBAL:
456CP_DRAW_PRED_ENABLE_LOCAL:
457UNKN27:
458CP_PREEMPT_ENABLE:
459CP_SKIP_IB2_ENABLE_GLOBAL:
460CP_PREEMPT_TOKEN:
461UNKN31:
462UNKN32:
463CP_DRAW_INDX:
464CP_SKIP_IB2_ENABLE_LOCAL:
465CP_DRAW_AUTO:
466CP_SET_STATE:
467CP_WAIT_FOR_IDLE:
468CP_IM_LOAD:
469CP_DRAW_INDIRECT:
470CP_DRAW_INDX_INDIRECT:
471CP_DRAW_INDIRECT_MULTI:
472CP_IM_LOAD_IMMEDIATE:
473CP_BLIT:
474CP_SET_CONSTANT:
475CP_SET_BIN_DATA5_OFFSET:
476UNKN48:
477CP_RUN_OPENCL:
478CP_LOAD_STATE6_GEOM:
479CP_EXEC_CS:
480CP_LOAD_STATE6_FRAG:
481CP_SET_SUBDRAW_SIZE:
482CP_LOAD_STATE6:
483CP_INDIRECT_BUFFER_PFD:
484CP_DRAW_INDX_OFFSET:
485CP_REG_TEST:
486CP_CCHE_INVALIDATE:
487CP_INVALIDATE_STATE:
488CP_WAIT_REG_MEM:
489CP_REG_TO_MEM:
490CP_INDIRECT_BUFFER:
491CP_INTERRUPT:
492CP_EXEC_CS_INDIRECT:
493CP_MEM_TO_REG:
494CP_COND_EXEC:
495CP_COND_WRITE5:
496CP_EVENT_WRITE:
497CP_COND_REG_EXEC:
498UNKN73:
499CP_REG_TO_SCRATCH:
500CP_SET_DRAW_INIT_FLAGS:
501CP_SCRATCH_TO_REG:
502CP_DRAW_PRED_SET:
503CP_MEM_WRITE_CNTR:
504CP_START_BIN:
505CP_END_BIN:
506CP_WAIT_REG_EQ:
507CP_SMMU_TABLE_UPDATE:
508UNKN84:
509CP_SET_AMBLE:
510CP_SET_PSEUDO_REG:
511CP_INDIRECT_BUFFER_CHAIN:
512CP_EVENT_WRITE_SHD:
513CP_EVENT_WRITE_CFL:
514UNKN90:
515CP_EVENT_WRITE_ZPD:
516CP_CONTEXT_REG_BUNCH:
517CP_WAIT_IB_PFD_COMPLETE:
518CP_CONTEXT_UPDATE:
519CP_SET_PROTECTED_MODE:
520UNKN96:
521UNKN97:
522UNKN98:
523CP_SET_MODE:
524CP_SET_VISIBILITY_OVERRIDE:
525CP_SET_MARKER:
526UNKN103:
527UNKN104:
528UNKN105:
529UNKN106:
530UNKN107:
531UNKN108:
532CP_REG_WRITE:
533UNKN110:
534CP_BOOTSTRAP_UCODE:
535CP_WAIT_TWO_REGS:
536CP_TEST_TWO_MEMS:
537CP_REG_TO_MEM_OFFSET_REG:
538CP_REG_TO_MEM_OFFSET_MEM:
539UNKN118:
540UNKN119:
541CP_REG_WR_NO_CTXT:
542UNKN121:
543UNKN122:
544UNKN123:
545UNKN124:
546UNKN125:
547UNKN126:
548UNKN127:
549waitin
550mov $01, $data
551
552.align 32
553jumptbl:
554.jumptbl
555
556.section LPAC
557; LPAC microcode
558[01000001]
559[#jumptbl]
560
561; read LPAC fw addr
562cread $01, [$00 + @LPAC_INSTR_BASE]
563cread $02, [$00 + @LPAC_INSTR_BASE+1]
564
565; skip first dword
566add $01, $01, 0x0004
567addhi $02, $02, 0x0000
568mov $03, 0x0001
569cwrite $01, [$00 + @MEM_READ_ADDR]
570cwrite $02, [$00 + @MEM_READ_ADDR+0x1]
571cwrite $03, [$00 + @MEM_READ_DWORDS]
572; read 2nd dword of fw, and add offset (minus 4 because we skipped first dword)
573; to base address of sqe fw
574rot $04, $memdata, 0x0008
575ushr $04, $04, 0x0006
576sub $04, $04, 0x0004
577add $01, $01, $04
578addhi $02, $02, 0x0000
579
580; load packet table:
581mov $rem, 0x0080
582cwrite $01, [$00 + @MEM_READ_ADDR]
583cwrite $02, [$00 + @MEM_READ_ADDR+0x1]
584cwrite $02, [$00 + @LOAD_STORE_HI]
585cwrite $rem, [$00 + @MEM_READ_DWORDS]
586cwrite $00, [$00 + @PACKET_TABLE_WRITE_ADDR]
587(rep)cwrite $memdata, [$00 + @PACKET_TABLE_WRITE]
588
589CP_ME_INIT:
590CP_MEM_WRITE:
591CP_SCRATCH_WRITE:
592CP_SET_DRAW_STATE:
593CP_SET_BIN_DATA5:
594CP_SET_SECURE_MODE:
595CP_REG_RMW:
596CP_MEMCPY:
597CP_MEM_TO_MEM:
598IN_PREEMPT:
599UNKN0:
600UNKN1:
601UNKN2:
602UNKN3:
603PKT4:
604UNKN5:
605UNKN6:
606UNKN7:
607UNKN8:
608UNKN9:
609UNKN10:
610UNKN11:
611UNKN12:
612UNKN13:
613UNKN14:
614CP_NOP:
615CP_RECORD_PFP_TIMESTAMP:
616CP_WAIT_MEM_WRITES:
617CP_WAIT_FOR_ME:
618CP_WAIT_MEM_GTE:
619UNKN21:
620UNKN22:
621UNKN23:
622UNKN24:
623CP_DRAW_PRED_ENABLE_GLOBAL:
624CP_DRAW_PRED_ENABLE_LOCAL:
625UNKN27:
626CP_PREEMPT_ENABLE:
627CP_SKIP_IB2_ENABLE_GLOBAL:
628CP_PREEMPT_TOKEN:
629UNKN31:
630UNKN32:
631CP_DRAW_INDX:
632CP_SKIP_IB2_ENABLE_LOCAL:
633CP_DRAW_AUTO:
634CP_SET_STATE:
635CP_WAIT_FOR_IDLE:
636CP_IM_LOAD:
637CP_DRAW_INDIRECT:
638CP_DRAW_INDX_INDIRECT:
639CP_DRAW_INDIRECT_MULTI:
640CP_IM_LOAD_IMMEDIATE:
641CP_BLIT:
642CP_SET_CONSTANT:
643CP_SET_BIN_DATA5_OFFSET:
644UNKN48:
645CP_RUN_OPENCL:
646CP_LOAD_STATE6_GEOM:
647CP_EXEC_CS:
648CP_LOAD_STATE6_FRAG:
649CP_SET_SUBDRAW_SIZE:
650CP_LOAD_STATE6:
651CP_INDIRECT_BUFFER_PFD:
652CP_DRAW_INDX_OFFSET:
653CP_REG_TEST:
654CP_CCHE_INVALIDATE:
655CP_INVALIDATE_STATE:
656CP_WAIT_REG_MEM:
657CP_REG_TO_MEM:
658CP_INDIRECT_BUFFER:
659CP_INTERRUPT:
660CP_EXEC_CS_INDIRECT:
661CP_MEM_TO_REG:
662CP_COND_EXEC:
663CP_COND_WRITE5:
664CP_EVENT_WRITE:
665CP_COND_REG_EXEC:
666UNKN73:
667CP_REG_TO_SCRATCH:
668CP_SET_DRAW_INIT_FLAGS:
669CP_SCRATCH_TO_REG:
670CP_DRAW_PRED_SET:
671CP_MEM_WRITE_CNTR:
672CP_START_BIN:
673CP_END_BIN:
674CP_WAIT_REG_EQ:
675CP_SMMU_TABLE_UPDATE:
676UNKN84:
677CP_SET_AMBLE:
678CP_SET_PSEUDO_REG:
679CP_INDIRECT_BUFFER_CHAIN:
680CP_EVENT_WRITE_SHD:
681CP_EVENT_WRITE_CFL:
682UNKN90:
683CP_EVENT_WRITE_ZPD:
684CP_CONTEXT_REG_BUNCH:
685CP_WAIT_IB_PFD_COMPLETE:
686CP_CONTEXT_UPDATE:
687CP_SET_PROTECTED_MODE:
688UNKN96:
689UNKN97:
690UNKN98:
691CP_SET_MODE:
692CP_SET_VISIBILITY_OVERRIDE:
693CP_SET_MARKER:
694UNKN103:
695UNKN104:
696UNKN105:
697UNKN106:
698UNKN107:
699UNKN108:
700CP_REG_WRITE:
701UNKN110:
702CP_BOOTSTRAP_UCODE:
703CP_WAIT_TWO_REGS:
704CP_TEST_TWO_MEMS:
705CP_REG_TO_MEM_OFFSET_REG:
706CP_REG_TO_MEM_OFFSET_MEM:
707UNKN118:
708UNKN119:
709CP_REG_WR_NO_CTXT:
710UNKN121:
711UNKN122:
712UNKN123:
713UNKN124:
714UNKN125:
715UNKN126:
716UNKN127:
717waitin
718mov $01, $data
719
720.align 32
721jumptbl:
722.jumptbl
723
724; test junk data after jump table
725[0100beef]
726