1<?xml version="1.0" encoding="UTF-8"?> 2<!-- 3Copyright © 2020 Google, Inc. 4Copyright © 2023 Valve Corporation 5 6Permission is hereby granted, free of charge, to any person obtaining a 7copy of this software and associated documentation files (the "Software"), 8to deal in the Software without restriction, including without limitation 9the rights to use, copy, modify, merge, publish, distribute, sublicense, 10and/or sell copies of the Software, and to permit persons to whom the 11Software is furnished to do so, subject to the following conditions: 12 13The above copyright notice and this permission notice (including the next 14paragraph) shall be included in all copies or substantial portions of the 15Software. 16 17THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 23SOFTWARE. 24 --> 25 26<isa> 27 28<bitset name="#instruction" size="32"> 29 <doc> 30 Encoding of an afuc instruction. All instructions are 32b. 31 </doc> 32 <encode type="struct afuc_instr *" case-prefix="OPC_"> 33 <map name="XMOV">src->xmov</map> 34 <map name="DST">src->dst</map> 35 <map name="SRC1">src->src1</map> 36 <map name="SRC2">src->src2</map> 37 <map name="IMMED">src->immed</map> 38 <map name="BIT">src->bit</map> 39 <!-- RIMMED is an alias of IMMED for immediates that might be a GPU register --> 40 <map name="RIMMED">src->immed</map> 41 </encode> 42 <decode/> 43</bitset> 44 45<enum name="#specialsrc"> 46 <doc>special registers for operands used as a source</doc> 47 <value val="0x1c" display="$rem"/> 48 <value val="0x1d" display="$memdata"/> 49 <value val="0x1e" display="$regdata"/> 50 <value val="0x1f" display="$data"/> 51</enum> 52 53<enum name="#specialdst"> 54 <doc>special registers for operands used as a destination</doc> 55 <value val="0x1c" display="$rem"/> 56 <value val="0x1d" display="$addr"/> 57 <value val="0x1e" display="$usraddr"/> 58 <value val="0x1f" display="$data"/> 59</enum> 60 61<!-- TODO add support for padding integers so this doesn't have to be an enum --> 62<enum name="#reg"> 63 <value val="0x00" display="$00"/> 64 <value val="0x01" display="$01"/> 65 <value val="0x02" display="$02"/> 66 <value val="0x03" display="$03"/> 67 <value val="0x04" display="$04"/> 68 <value val="0x05" display="$05"/> 69 <value val="0x06" display="$06"/> 70 <value val="0x07" display="$07"/> 71 <value val="0x08" display="$08"/> 72 <value val="0x09" display="$09"/> 73 <value val="0x0a" display="$0a"/> 74 <value val="0x0b" display="$0b"/> 75 <value val="0x0c" display="$0c"/> 76 <value val="0x0d" display="$0d"/> 77 <value val="0x0e" display="$0e"/> 78 <value val="0x0f" display="$0f"/> 79 <value val="0x10" display="$10"/> 80 <value val="0x11" display="$11"/> 81 <value val="0x12" display="$12"/> 82 <value val="0x13" display="$13"/> 83 <value val="0x14" display="$14"/> 84 <value val="0x15" display="$15"/> 85 <value val="0x16" display="$16"/> 86 <value val="0x17" display="$17"/> 87 <value val="0x18" display="$18"/> 88 <value val="0x19" display="$19"/> 89 <value val="0x1a" display="$sp"/> 90 <value val="0x1b" display="$lr"/> 91</enum> 92 93<expr name="#reg-special"> 94 {SPECIALREG} >= 0x1c 95</expr> 96 97<bitset name="#src" size="5"> 98 <override expr="#reg-special"> 99 <display> 100 {SPECIALREG} 101 </display> 102 <field name="SPECIALREG" low="0" high="4" type="#specialsrc"/> 103 </override> 104 <display> 105 {REG} 106 </display> 107 <field name="REG" low="0" high="4" type="#reg"/> 108 109 <encode type="uint8_t"> 110 <map name="REG">src</map> 111 <map name="SPECIALREG">src</map> 112 </encode> 113 <decode/> 114</bitset> 115 116<bitset name="#dst" size="5"> 117 <override expr="#reg-special"> 118 <display> 119 {SPECIALREG} 120 </display> 121 <field name="SPECIALREG" low="0" high="4" type="#specialdst"/> 122 </override> 123 <display> 124 {REG} 125 </display> 126 <field name="REG" low="0" high="4" type="#reg"/> 127 128 <encode type="uint8_t"> 129 <map name="REG">src</map> 130 <map name="SPECIALREG">src</map> 131 </encode> 132 <decode/> 133</bitset> 134 135<bitset name="#instruction-rep" extends="#instruction"> 136 <field name="REP" pos="26" type="bool" display="(rep)"/> 137 138 <encode> 139 <map name="REP">src->rep</map> 140 </encode> 141</bitset> 142 143<enum name="#xmov"> 144 <doc>Execute eXtra mov's based on $rem</doc> 145 <value val="0" display=""/> 146 <value val="1" display="(xmov1)"/> 147 <value val="2" display="(xmov2)"/> 148 <value val="3" display="(xmov3)"/> 149</enum> 150 151<bitset name="#alu-2src" extends="#instruction-rep"> 152 <display> 153 {REP}{XMOV}{PEEK}{NAME} {DST}, {SRC1}, {SRC2} 154 </display> 155 156 <pattern low="5" high="7">xxx</pattern> 157 <field name="PEEK" pos="8" type="bool" display="(peek)"/> 158 <field name="XMOV" low="9" high="10" type="#xmov"/> 159 <field name="DST" low="11" high="15" type="#dst"/> 160 <field name="SRC2" low="16" high="20" type="#src"/> 161 <field name="SRC1" low="21" high="25" type="#src"/> 162 <pattern low="27" high="31">10011</pattern> 163 164 <encode> 165 <map name="PEEK">src->peek</map> 166 </encode> 167</bitset> 168 169<bitset name="#alu-1src" extends="#instruction-rep"> 170 <display> 171 {REP}{XMOV}{NAME} {DST}, {SRC1} 172 </display> 173 174 <pattern low="5" high="8">xxxx</pattern> 175 <field name="XMOV" low="9" high="10" type="#xmov"/> 176 <field name="DST" low="11" high="15" type="#dst"/> 177 <field name="SRC1" low="16" high="20" type="#src"/> 178 <pattern low="21" high="25">xxxxx</pattern> <!-- SRC1 unused --> 179 <pattern low="27" high="31">10011</pattern> 180</bitset> 181 182<bitset name="#alu-2src-immed" extends="#instruction-rep"> 183 <display> 184 {REP}{NAME} {DST}, {SRC1}, 0x{RIMMED} 185 </display> 186 187 <field name="RIMMED" low="0" high="15" type="hex"/> 188 <field name="DST" low="16" high="20" type="#dst"/> 189 <field name="SRC1" low="21" high="25" type="#src"/> 190</bitset> 191 192<bitset name="#alu-2src-immed12" extends="#instruction-rep"> 193 <display> 194 {REP}{NAME} {DST}, {SRC1}, 0x{RIMMED} 195 </display> 196 197 <field name="RIMMED" low="0" high="11" type="hex"/> 198 <field name="DST" low="16" high="20" type="#dst"/> 199 <field name="SRC1" low="21" high="25" type="#src"/> 200 <pattern low="27" high="31">10010</pattern> 201</bitset> 202 203<bitset name="#alu-1src-immed" extends="#instruction-rep"> 204 <display> 205 {REP}{NAME} {DST}, 0x{IMMED} 206 </display> 207 208 <field name="IMMED" low="0" high="15" type="hex"/> 209 <field name="DST" low="16" high="20" type="#dst"/> 210 <pattern low="21" high="25">xxxxx</pattern> <!-- SRC1 unused --> 211</bitset> 212 213<bitset name="add" extends="#alu-2src"> 214 <doc>add and write carry flag</doc> 215 <pattern low="0" high="4">00001</pattern> 216</bitset> 217 218<bitset name="addi" displayname="add" extends="#alu-2src-immed"> 219 <pattern low="27" high="31">00001</pattern> 220</bitset> 221 222<bitset name="addhi" extends="#alu-2src"> 223 <doc>Perform high 32 bits of 64-bit addition, using carry flag written by add</doc> 224 <pattern low="0" high="4">00010</pattern> 225</bitset> 226 227<bitset name="addhii" displayname="addhi" extends="#alu-2src-immed"> 228 <pattern low="27" high="31">00010</pattern> 229</bitset> 230 231<bitset name="sub" extends="#alu-2src"> 232 <doc>subtract and write carry flag</doc> 233 <pattern low="0" high="4">00011</pattern> 234</bitset> 235 236<bitset name="subi" displayname="sub" extends="#alu-2src-immed"> 237 <pattern low="27" high="31">00011</pattern> 238</bitset> 239 240<bitset name="subhi" extends="#alu-2src"> 241 <doc>Perform high 32 bits of 64-bit subtraction, using carry flag written by sub</doc> 242 <pattern low="0" high="4">00100</pattern> 243</bitset> 244 245<bitset name="subhii" displayname="subhi" extends="#alu-2src-immed"> 246 <pattern low="27" high="31">00100</pattern> 247</bitset> 248 249<bitset name="and" extends="#alu-2src"> 250 <pattern low="0" high="4">00101</pattern> 251</bitset> 252 253<bitset name="andi" displayname="and" extends="#alu-2src-immed"> 254 <pattern low="27" high="31">00101</pattern> 255</bitset> 256 257<bitset name="or" extends="#alu-2src"> 258 <!-- mov of a register is encoded as or with $00 --> 259 <override> 260 <expr>{SRC1} == 0</expr> 261 <display> 262 {REP}{XMOV}{PEEK}mov {DST}, {SRC2} 263 </display> 264 </override> 265 <pattern low="0" high="4">00110</pattern> 266</bitset> 267 268<bitset name="ori" displayname="or" extends="#alu-2src-immed"> 269 <pattern low="27" high="31">00110</pattern> 270</bitset> 271 272<bitset name="xor" extends="#alu-2src"> 273 <pattern low="0" high="4">00111</pattern> 274</bitset> 275 276<bitset name="xori" displayname="xor" extends="#alu-2src-immed"> 277 <pattern low="27" high="31">00111</pattern> 278</bitset> 279 280<bitset name="not" extends="#alu-1src"> 281 <pattern low="0" high="4">01000</pattern> 282</bitset> 283 284<bitset name="noti" displayname="not" extends="#alu-1src-immed"> 285 <pattern low="27" high="31">01000</pattern> 286</bitset> 287 288<bitset name="shl" extends="#alu-2src"> 289 <gen max="6"/> 290 <pattern low="0" high="4">01001</pattern> 291</bitset> 292 293<bitset name="shli" displayname="shl" extends="#alu-2src-immed"> 294 <gen max="6"/> 295 <pattern low="27" high="31">01001</pattern> 296</bitset> 297 298<bitset name="shl" extends="#alu-2src"> 299 <gen min="7"/> 300 <pattern low="0" high="4">10010</pattern> 301</bitset> 302 303<bitset name="shli" displayname="shl" extends="#alu-2src-immed12"> 304 <gen min="7"/> 305 <pattern low="12" high="15">0010</pattern> 306</bitset> 307 308<bitset name="ushr" extends="#alu-2src"> 309 <doc>0-extending right shift</doc> 310 <gen max="6"/> 311 <pattern low="0" high="4">01010</pattern> 312</bitset> 313 314<bitset name="ushri" displayname="ushr" extends="#alu-2src-immed"> 315 <gen max="6"/> 316 <pattern low="27" high="31">01010</pattern> 317</bitset> 318 319<bitset name="ushr" extends="#alu-2src"> 320 <gen min="7"/> 321 <pattern low="0" high="4">10011</pattern> 322</bitset> 323 324<bitset name="ushri" displayname="ushr" extends="#alu-2src-immed12"> 325 <gen min="7"/> 326 <pattern low="12" high="15">0011</pattern> 327</bitset> 328 329<bitset name="ishr" extends="#alu-2src"> 330 <doc>sign-extending right shift</doc> 331 <gen max="6"/> 332 <pattern low="0" high="4">01011</pattern> 333</bitset> 334 335<bitset name="ishri" displayname="ishr" extends="#alu-2src-immed"> 336 <gen max="6"/> 337 <pattern low="27" high="31">01011</pattern> 338</bitset> 339 340<bitset name="ishr" extends="#alu-2src"> 341 <gen min="7"/> 342 <pattern low="0" high="4">10100</pattern> 343</bitset> 344 345<bitset name="ishri" displayname="ishr" extends="#alu-2src-immed12"> 346 <gen min="7"/> 347 <pattern low="12" high="15">0100</pattern> 348</bitset> 349 350<bitset name="rot" extends="#alu-2src"> 351 <doc>Rotate left (left shift with wraparound)</doc> 352 <gen max="6"/> 353 <pattern low="0" high="4">01100</pattern> 354</bitset> 355 356<bitset name="roti" displayname="rot" extends="#alu-2src-immed"> 357 <gen max="6"/> 358 <pattern low="27" high="31">01100</pattern> 359</bitset> 360 361<bitset name="rot" extends="#alu-2src"> 362 <gen min="7"/> 363 <pattern low="0" high="4">10101</pattern> 364</bitset> 365 366<bitset name="roti" displayname="rot" extends="#alu-2src-immed12"> 367 <gen min="7"/> 368 <pattern low="12" high="15">0101</pattern> 369</bitset> 370 371<bitset name="mul8" extends="#alu-2src"> 372 <doc>Multiply low 8 bits of each source to produce a 16-bit result</doc> 373 <gen max="6"/> 374 <pattern low="0" high="4">01101</pattern> 375</bitset> 376 377<bitset name="mul8i" displayname="mul8" extends="#alu-2src-immed"> 378 <gen max="6"/> 379 <pattern low="27" high="31">01101</pattern> 380</bitset> 381 382<bitset name="mul8" extends="#alu-2src"> 383 <gen min="7"/> 384 <pattern low="0" high="4">01100</pattern> 385</bitset> 386 387<bitset name="mul8i" displayname="mul8" extends="#alu-2src-immed"> 388 <gen min="7"/> 389 <pattern low="27" high="31">01100</pattern> 390</bitset> 391 392<bitset name="min" extends="#alu-2src"> 393 <doc>Unsigned minimum</doc> 394 <gen max="6"/> 395 <pattern low="0" high="4">01110</pattern> 396</bitset> 397 398<bitset name="mini" displayname="min" extends="#alu-2src-immed"> 399 <gen max="6"/> 400 <pattern low="27" high="31">01110</pattern> 401</bitset> 402 403<bitset name="min" extends="#alu-2src"> 404 <gen min="7"/> 405 <pattern low="0" high="4">01010</pattern> 406</bitset> 407 408<bitset name="mini" displayname="min" extends="#alu-2src-immed"> 409 <gen min="7"/> 410 <pattern low="27" high="31">01010</pattern> 411</bitset> 412 413<bitset name="max" extends="#alu-2src"> 414 <doc>Unsigned maximum</doc> 415 <gen max="6"/> 416 <pattern low="0" high="4">01111</pattern> 417</bitset> 418 419<bitset name="maxi" displayname="max" extends="#alu-2src-immed"> 420 <gen max="6"/> 421 <pattern low="27" high="31">01111</pattern> 422</bitset> 423 424<bitset name="max" extends="#alu-2src"> 425 <gen min="7"/> 426 <pattern low="0" high="4">01011</pattern> 427</bitset> 428 429<bitset name="maxi" displayname="max" extends="#alu-2src-immed"> 430 <gen min="7"/> 431 <pattern low="27" high="31">01011</pattern> 432</bitset> 433 434<bitset name="cmp" extends="#alu-2src"> 435 <doc> 436 Compare two sources and produce a bitfield: 437 - 0x00 if src1 > src2 438 - 0x2b if src1 == src2 439 - 0x1e if src1 < src2 440 Often a "branch on bit set/unset" instruction is used on the 441 result to implement a compare-and-branch macro. 442 </doc> 443 <gen max="6"/> 444 <pattern low="0" high="4">10000</pattern> 445</bitset> 446 447<bitset name="cmpi" displayname="cmp" extends="#alu-2src-immed"> 448 <gen max="6"/> 449 <pattern low="27" high="31">10000</pattern> 450</bitset> 451 452<bitset name="cmp" extends="#alu-2src"> 453 <gen min="7"/> 454 <pattern low="0" high="4">01101</pattern> 455</bitset> 456 457<bitset name="cmpi" displayname="cmp" extends="#alu-2src-immed"> 458 <gen min="7"/> 459 <pattern low="27" high="31">01101</pattern> 460</bitset> 461 462<bitset name="bic" extends="#alu-2src"> 463 <gen min="7"/> 464 <pattern low="0" high="4">01001</pattern> 465</bitset> 466 467<bitset name="bici" displayname="bic" extends="#alu-2src-immed"> 468 <gen min="7"/> 469 <pattern low="27" high="31">01001</pattern> 470</bitset> 471 472<bitset name="msb" extends="#alu-1src"> 473 <doc>Return the most-significant bit of src2, or 0 if src2 == 0</doc> 474 <gen max="6"/> 475 <pattern low="0" high="4">10100</pattern> 476</bitset> 477 478<bitset name="msb" extends="#alu-1src"> 479 <gen min="7"/> 480 <pattern low="0" high="4">11001</pattern> 481</bitset> 482 483<bitset name="#setclrbit6" extends="#instruction-rep"> 484 <display> 485 {REP}{NAME} {DST}, {SRC}, b{BIT} 486 </display> 487 488 <field name="BIT" low="1" high="5" type="uint"/> 489 <pattern low="6" high="15">xxxxxxxxxx</pattern> 490 <field name="DST" low="16" high="20" type="#dst"/> 491 <field name="SRC" low="21" high="25" type="#src"/> 492 <pattern low="27" high="31">10010</pattern> 493 494 <encode> 495 <map name="SRC">src->src1</map> 496 </encode> 497</bitset> 498 499<bitset name="#setclrbit7" extends="#instruction-rep"> 500 <display> 501 {REP}{NAME} {DST}, {SRC}, b{BIT} 502 </display> 503 504 <field name="BIT" low="1" high="5" type="uint"/> 505 <pattern low="6" high="11">xxxxxx</pattern> 506 <pattern low="12" high="15">0110</pattern> 507 <field name="DST" low="16" high="20" type="#dst"/> 508 <field name="SRC" low="21" high="25" type="#src"/> 509 <pattern low="27" high="31">10010</pattern> 510 511 <encode> 512 <map name="SRC">src->src1</map> 513 </encode> 514</bitset> 515 516<bitset name="setbiti" displayname="setbit" extends="#setclrbit6"> 517 <doc>Set a given bit to 1</doc> 518 <gen max="6"/> 519 <pattern pos="0">1</pattern> 520</bitset> 521 522<bitset name="clrbit" extends="#setclrbit6"> 523 <doc>Clear a given bit, i.e. set it to 0</doc> 524 <gen max="6"/> 525 <pattern pos="0">0</pattern> 526</bitset> 527 528<bitset name="setbiti" displayname="setbit" extends="#setclrbit7"> 529 <gen min="7"/> 530 <pattern pos="0">1</pattern> 531</bitset> 532 533<bitset name="clrbit" extends="#setclrbit7"> 534 <gen min="7"/> 535 <pattern pos="0">0</pattern> 536</bitset> 537 538<bitset name="setbit" extends="#alu-2src"> 539 <doc> 540 Set or clear a given bit. This is the non-immediate form of 541 setbit/clrbit. Bits 1-5 of src2 are the bit to set, bit 0 is the 542 value to set it to. 543 </doc> 544 <gen min="7"/> 545 <pattern low="0" high="4">10110</pattern> 546</bitset> 547 548<bitset name="#bitfield-immed" extends="#instruction-rep"> 549 <display> 550 {REP}{NAME} {DST}, {SRC}, b{LO}, b{HI} 551 </display> 552 553 <field name="LO" low="0" high="4" type="uint"/> 554 <field name="HI" low="5" high="9" type="uint"/> 555 <pattern low="10" high="11">xx</pattern> 556 <field name="DST" low="16" high="20" type="#dst"/> 557 <field name="SRC" low="21" high="25" type="#src"/> 558 <pattern low="27" high="31">10010</pattern> 559 560 <encode> 561 <map name="LO">src->bit</map> 562 <map name="HI">src->immed</map> 563 <map name="SRC">src->src1</map> 564 </encode> 565</bitset> 566 567<bitset name="ubfx" extends="#bitfield-immed"> 568 <doc>Unsigned BitField eXtract</doc> 569 <gen min="7"/> 570 <pattern low="12" high="15">0111</pattern> 571</bitset> 572 573<bitset name="bfi" extends="#bitfield-immed"> 574 <doc>BitField Insert</doc> 575 <gen min="7"/> 576 <pattern low="12" high="15">1000</pattern> 577</bitset> 578 579<bitset name="#movi" extends="#instruction-rep"> 580 <doc>Special move-immediate instruction with a shift</doc> 581 <override> 582 <expr>{SHIFT} == 0</expr> 583 <display> 584 {REP}mov {DST}, 0x{RIMMED} 585 </display> 586 </override> 587 <display> 588 {REP}mov {DST}, 0x{RIMMED} << {SHIFT} 589 </display> 590 591 <field name="RIMMED" low="0" high="15" type="hex"/> 592 <field name="DST" low="16" high="20" type="#dst"/> 593 <field name="SHIFT" low="21" high="25" type="uint"/> 594 595 <encode> 596 <map name="SHIFT">src->shift</map> 597 </encode> 598</bitset> 599 600<bitset name="movi" extends="#movi"> 601 <gen max="6"/> 602 <pattern low="27" high="31">10001</pattern> 603</bitset> 604 605<bitset name="movi" extends="#movi"> 606 <gen min="7"/> 607 <pattern low="27" high="31">01110</pattern> 608</bitset> 609 610<enum name="#sds"> 611 <doc> 612 Used in combination with writing @DRAW_STATE_SET, the source is 613 read the specified number of times and used to set the draw 614 state base. 615 </doc> 616 <value val="0" display=""/> 617 <value val="1" display="(sds1)"/> 618 <value val="2" display="(sds2)"/> 619 <value val="3" display="(sds3)"/> 620</enum> 621 622<bitset name="#control" extends="#instruction-rep"> 623 <field name="PREINCREMENT" pos="14" type="bool" display="!"/> 624 <field name="OFFSET" low="21" high="25" type="#src"/> 625 626 <encode> 627 <map name="PREINCREMENT">src->preincrement</map> 628 </encode> 629</bitset> 630 631<bitset name="#store" extends="#control"> 632 <display> 633 {REP}store {SRC}, [{OFFSET} + 0x{IMMED}]{PREINCREMENT} 634 </display> 635 636 <doc> 637 Store to memory directly. Mainly used by preemption to avoid 638 disturbing FIFO state before it is saved and after it is 639 restored. 640 </doc> 641 642 <pattern low="12" high="13">00</pattern> 643 <field name="IMMED" low="0" high="11" type="hex"/> 644 <field name="SRC" low="16" high="20" type="#src"/> 645 646 <encode> 647 <map name="SRC">src->src1</map> 648 <map name="OFFSET">src->src2</map> 649 </encode> 650</bitset> 651 652<bitset name="store" extends="#store"> 653 <gen max="5"/> 654 <pattern low="27" high="31">10101</pattern> 655 <pattern pos="15">0</pattern> 656</bitset> 657 658<bitset name="store" extends="#store"> 659 <gen min="6"/> 660 <pattern pos="15">0</pattern> 661 <pattern low="27" high="31">10100</pattern> 662</bitset> 663 664<expr name="#pre-increment"> 665 {PREINCREMENT} 666</expr> 667 668<bitset name="#control-base" size="12"> 669 <!-- 670 In pre-increment mode, the register is usually in the offset 671 instead of the base, so always print it as an immediate. 672 --> 673 <override expr="#pre-increment"> 674 <display> 675 0x{IMMED} 676 </display> 677 <field name="IMMED" low="0" high="11" type="hex"/> 678 </override> 679 <display> 680 {CONTROLREG} 681 </display> 682 <field name="CONTROLREG" low="0" high="11" type="custom"/> 683 <encode type="uint32_t"> 684 <map name="IMMED">src</map> 685 <map name="CONTROLREG">src</map> 686 </encode> 687 <decode/> 688</bitset> 689 690<bitset name="#cwrite" extends="#control"> 691 <doc>Write to a control register.</doc> 692 <display> 693 {REP}{SDS}cwrite {SRC}, [{OFFSET} + {BASE}]{PREINCREMENT} 694 </display> 695 696 <field name="BASE" low="0" high="11" type="#control-base"> 697 <param name="PREINCREMENT"/> 698 </field> 699 <field name="SDS" low="12" high="13" type="#sds"/> 700 <field name="SRC" low="16" high="20" type="#src"/> 701 <pattern low="27" high="31">10101</pattern> 702 703 <encode> 704 <map name="SDS">src->sds</map> 705 <map name="SRC">src->src1</map> 706 <map name="OFFSET">src->src2</map> 707 <map name="BASE">src->immed</map> 708 </encode> 709</bitset> 710 711<bitset name="cwrite" extends="#cwrite"> 712 <pattern pos="15">1</pattern> 713 <gen max="5"/> 714</bitset> 715 716<bitset name="cwrite" extends="#cwrite"> 717 <pattern pos="15">0</pattern> 718 <gen min="6"/> 719</bitset> 720 721<bitset name="#sqe-base" size="12"> 722 <override expr="#pre-increment"> 723 <display> 724 0x{IMMED} 725 </display> 726 <field name="IMMED" low="0" high="11" type="uint"/> 727 </override> 728 <display> 729 {SQEREG} 730 </display> 731 <field name="SQEREG" low="0" high="11" type="custom"/> 732 <encode type="uint32_t"> 733 <map name="IMMED">src</map> 734 <map name="SQEREG">src</map> 735 </encode> 736</bitset> 737 738<bitset name="swrite" extends="#control"> 739 <doc>Write to a SQE register.</doc> 740 <gen min="6"/> 741 <display> 742 {REP}swrite {SRC}, [{OFFSET} + {BASE}]{PREINCREMENT} 743 </display> 744 745 <field name="BASE" low="0" high="11" type="#sqe-base"> 746 <param name="PREINCREMENT"/> 747 </field> 748 <pattern low="12" high="13">00</pattern> 749 <field name="SRC" low="16" high="20" type="#src"/> 750 <pattern pos="15">1</pattern> 751 <pattern low="27" high="31">10101</pattern> 752 753 <encode> 754 <map name="SRC">src->src1</map> 755 <map name="OFFSET">src->src2</map> 756 <map name="BASE">src->immed</map> 757 </encode> 758</bitset> 759 760<bitset name="load" extends="#control"> 761 <gen min="6"/> 762 <doc> 763 Load from memory directly. Mainly used by preemption to avoid 764 disturbing FIFO state before it is saved and after it is 765 restored. 766 </doc> 767 <display> 768 {REP}load {DST}, [{OFFSET} + 0x{IMMED}]{PREINCREMENT} 769 </display> 770 771 <field name="IMMED" low="0" high="11" type="hex"/> 772 <pattern low="12" high="13">00</pattern> 773 <pattern pos="15">0</pattern> 774 <field name="DST" low="16" high="20" type="#dst"/> 775 <pattern low="27" high="31">10110</pattern> 776 777 <encode> 778 <map name="OFFSET">src->src1</map> 779 </encode> 780</bitset> 781 782<bitset name="#cread" extends="#control"> 783 <doc>Read from a control register.</doc> 784 <display> 785 {REP}cread {DST}, [{OFFSET} + {BASE}]{PREINCREMENT} 786 </display> 787 788 <field name="BASE" low="0" high="11" type="#control-base"> 789 <param name="PREINCREMENT"/> 790 </field> 791 <pattern low="12" high="13">00</pattern> 792 <field name="DST" low="16" high="20" type="#dst"/> 793 794 <encode> 795 <map name="OFFSET">src->src1</map> 796 <map name="BASE">src->immed</map> 797 </encode> 798</bitset> 799 800<bitset name="cread" extends="#cread"> 801 <gen max="5"/> 802 <pattern pos="15">1</pattern> 803 <pattern low="27" high="31">10110</pattern> 804</bitset> 805 806<bitset name="cread" extends="#cread"> 807 <gen min="6"/> 808 <pattern pos="15">0</pattern> 809 <!-- a6xx shuffled around the cread opcode --> 810 <pattern low="27" high="31">10111</pattern> 811</bitset> 812 813<bitset name="sread" extends="#control"> 814 <doc>Read from a SQE register.</doc> 815 <gen min="6"/> 816 <display> 817 {REP}{XREG}sread {DST}, [{OFFSET} + {BASE}]{PREINCREMENT} 818 </display> 819 820 <field name="BASE" low="0" high="11" type="#sqe-base"> 821 <param name="PREINCREMENT"/> 822 </field> 823 <pattern low="12" high="13">00</pattern> 824 <field name="DST" low="16" high="20" type="#dst"/> 825 826 <encode> 827 <map name="OFFSET">src->src1</map> 828 <map name="BASE">src->immed</map> 829 </encode> 830 831 <pattern pos="15">1</pattern> 832 <pattern low="27" high="31">10111</pattern> 833</bitset> 834 835<bitset name="#branch" extends="#instruction"> 836 <field name="OFFSET" low="0" high="15" type="branch"/> 837 <field name="SRC" low="21" high="25" type="#src"/> 838 839 <encode> 840 <map name="OFFSET">src->offset</map> 841 <map name="SRC">src->src1</map> 842 </encode> 843</bitset> 844 845<bitset name="#branch-immed" extends="#branch"> 846 <display> 847 {NAME} {SRC}, 0x{IMMED}, #{OFFSET} 848 </display> 849 <field name="IMMED" low="16" high="20" type="hex"/> 850</bitset> 851 852<bitset name="#branch-bit" extends="#branch"> 853 <display> 854 {NAME} {SRC}, b{BIT}, #{OFFSET} 855 </display> 856 <field name="BIT" low="16" high="20" type="uint"/> 857</bitset> 858 859<bitset name="brnei" displayname="brne" extends="#branch-immed"> 860 <doc>Branch if not equal to an immediate.</doc> 861 <pattern low="26" high="31">110000</pattern> 862</bitset> 863 864<bitset name="breqi" displayname="breq" extends="#branch-immed"> 865 <doc>Branch if equal to an immediate.</doc> 866 <pattern low="26" high="31">110001</pattern> 867</bitset> 868 869<bitset name="brneb" displayname="brne" extends="#branch-bit"> 870 <doc>Branch if a bit is not set.</doc> 871 <override> 872 <!-- jump #label is encoded as brne $00, b0, #label --> 873 <expr> 874 ({BIT} == 0) && ({SRC} == 0) 875 </expr> 876 <display> 877 jump #{OFFSET} 878 </display> 879 </override> 880 <pattern low="26" high="31">110010</pattern> 881</bitset> 882 883<bitset name="breqb" displayname="breq" extends="#branch-bit"> 884 <doc>Branch if a bit is set.</doc> 885 <pattern low="26" high="31">110011</pattern> 886</bitset> 887 888<bitset name="#instruction-no-args" extends="#instruction"> 889 <display> 890 {NAME} 891 </display> 892 <pattern low="0" high="25">xxxxxxxxxxxxxxxxxxxxxxxxxx</pattern> 893</bitset> 894 895<bitset name="#ret" extends="#instruction"> 896 <display> 897 {NAME} 898 </display> 899 <pattern low="26" high="31">110100</pattern> 900 <pattern low="0" high="24">xxxxxxxxxxxxxxxxxxxxxxxxx</pattern> 901</bitset> 902 903<bitset name="ret" extends="#ret"> 904 <pattern low="25" high="25">0</pattern> 905</bitset> 906 907<bitset name="iret" extends="#ret"> 908 <doc>Return from preemption interrupt handler.</doc> 909 <pattern low="25" high="25">1</pattern> 910</bitset> 911 912<bitset name="call" extends="#instruction"> 913 <display> 914 call #{TARGET} 915 </display> 916 917 <field name="TARGET" low="0" high="25" type="absbranch" call="true"/> 918 <pattern low="26" high="31">110101</pattern> 919 920 <encode> 921 <map name="TARGET">src->literal</map> 922 </encode> 923</bitset> 924 925<bitset name="jumpa" extends="#instruction"> 926 <display> 927 jumpa #{TARGET} 928 </display> 929 930 <gen min="7"/> 931 932 <field name="TARGET" low="0" high="25" type="absbranch"/> 933 <pattern low="26" high="31">111001</pattern> 934 935 <encode> 936 <map name="TARGET">src->literal</map> 937 </encode> 938</bitset> 939 940<bitset name="waitin" extends="#instruction-no-args"> 941 <doc> 942 A special branch instruction that parses the next PM4 packet 943 header in $data and jumps to the packet handler routine. By 944 convention the delay slot always contains a "mov $01, $data" 945 instruction, so that $01 contains the packet header when 946 processing the next packet. 947 </doc> 948 <display> 949 waitin 950 </display> 951 <pattern low="26" high="31">110110</pattern> 952</bitset> 953 954<bitset name="bl" extends="#instruction"> 955 <doc> 956 Jump to the target and store a return address in $lr. 957 </doc> 958 <display> 959 bl #{TARGET} 960 </display> 961 962 <field name="TARGET" low="0" high="25" type="absbranch" call="true"/> 963 <pattern low="26" high="31">111000</pattern> 964 965 <encode> 966 <map name="TARGET">src->literal</map> 967 </encode> 968</bitset> 969 970<expr name="#three"> 971 3 972</expr> 973 974<bitset name="setsecure" extends="#instruction-no-args"> 975 <doc> 976 Call the zap shader fw to switch into/out of secure mode. Skips 977 the next two instructions if successful. 978 </doc> 979 <display> 980 setsecure $02, #{TARGET} 981 </display> 982 983 <pattern low="26" high="31">111011</pattern> 984 <derived name="TARGET" expr="#three" width="16" type="branch"/> 985</bitset> 986 987<bitset name="nop" extends="#instruction-rep"> 988 <gen max="5"/> 989 <display> 990 {REP}nop 991 </display> 992 <pattern low="0" high="25">00000000000000000000000000</pattern> 993 <pattern low="27" high="31">00000</pattern> 994</bitset> 995 996<!-- a6xx changed the default nop pattern and all 0's is now illegal --> 997<bitset name="nop" extends="#instruction-rep"> 998 <gen min="6"/> 999 <display> 1000 {REP}nop 1001 </display> 1002 <pattern low="0" high="25">01000000000000000000000000</pattern> 1003 <pattern low="27" high="31">00000</pattern> 1004</bitset> 1005 1006<bitset name="#jump-a7xx" extends="#instruction"> 1007 <gen min="7"/> 1008 <pattern low="26" high="31">110111</pattern> 1009</bitset> 1010 1011<bitset name="jumpr" extends="#jump-a7xx"> 1012 <doc> 1013 Indirect jump instruction. Jump to the given offset. 1014 Used as a return instruction together with bl: 1015 1016 bl #fxn 1017 ... 1018 1019 fxn: 1020 ... 1021 jump $lr 1022 nop 1023 1024 However this is only used by hand-crafted assembly 1025 routines that make sure to never use any stack space. Otherwise 1026 sret is used. 1027 </doc> 1028 1029 <display> 1030 jump {SRC1} 1031 </display> 1032 1033 <pattern low="20" high="25">110111</pattern> 1034 <pattern low="5" high="19">000000000000000</pattern> 1035 <field name="SRC1" low="0" high="4" type="#src"/> 1036</bitset> 1037 1038<bitset name="sret" extends="#jump-a7xx"> 1039 <doc> 1040 Seems to be equivalent to "jump $lr". This seems to be used by 1041 the compiled code, and is always immediately followed by a 1042 "sub $sp, $sp, imm" instruction to restore the stack frame. It's 1043 therefore possible this also includes a stack overflow check. 1044 </doc> 1045 1046 <display> 1047 sret 1048 </display> 1049 1050 <pattern low="20" high="25">110110</pattern> 1051 <pattern low="0" high="19">00000000000000000000</pattern> 1052</bitset> 1053 1054</isa> 1055