1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 * SPDX-License-Identifier: MIT
5 *
6 * based in part on anv driver which is:
7 * Copyright © 2015 Intel Corporation
8 */
9
10 #include "tu_cmd_buffer.h"
11
12 #include "vk_common_entrypoints.h"
13 #include "vk_render_pass.h"
14 #include "vk_util.h"
15
16 #include "tu_buffer.h"
17 #include "tu_clear_blit.h"
18 #include "tu_cs.h"
19 #include "tu_event.h"
20 #include "tu_image.h"
21 #include "tu_tracepoints.h"
22
23 #include "common/freedreno_gpu_event.h"
24 #include "common/freedreno_lrz.h"
25
26 static void
tu_clone_trace_range(struct tu_cmd_buffer * cmd,struct tu_cs * cs,struct u_trace_iterator begin,struct u_trace_iterator end)27 tu_clone_trace_range(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
28 struct u_trace_iterator begin, struct u_trace_iterator end)
29 {
30 if (u_trace_iterator_equal(begin, end))
31 return;
32
33 tu_cs_emit_wfi(cs);
34 tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
35 u_trace_clone_append(begin, end, &cmd->trace, cs, tu_copy_buffer);
36 }
37
38 static void
tu_clone_trace(struct tu_cmd_buffer * cmd,struct tu_cs * cs,struct u_trace * trace)39 tu_clone_trace(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
40 struct u_trace *trace)
41 {
42 tu_clone_trace_range(cmd, cs, u_trace_begin_iterator(trace),
43 u_trace_end_iterator(trace));
44 }
45
46 template <chip CHIP>
47 void
tu_emit_raw_event_write(struct tu_cmd_buffer * cmd,struct tu_cs * cs,enum vgt_event_type event,bool needs_seqno)48 tu_emit_raw_event_write(struct tu_cmd_buffer *cmd,
49 struct tu_cs *cs,
50 enum vgt_event_type event,
51 bool needs_seqno)
52 {
53 if (CHIP == A6XX) {
54 tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, needs_seqno ? 4 : 1);
55 tu_cs_emit(cs, CP_EVENT_WRITE_0_EVENT(event));
56 } else {
57 tu_cs_emit_pkt7(cs, CP_EVENT_WRITE7, needs_seqno ? 4 : 1);
58 tu_cs_emit(cs,
59 CP_EVENT_WRITE7_0(.event = event,
60 .write_src = EV_WRITE_USER_32B,
61 .write_dst = EV_DST_RAM,
62 .write_enabled = needs_seqno).value);
63 }
64
65 if (needs_seqno) {
66 tu_cs_emit_qw(cs, global_iova(cmd, seqno_dummy));
67 tu_cs_emit(cs, 0);
68 }
69 }
70 TU_GENX(tu_emit_raw_event_write);
71
72 template <chip CHIP>
73 void
tu_emit_event_write(struct tu_cmd_buffer * cmd,struct tu_cs * cs,enum fd_gpu_event event)74 tu_emit_event_write(struct tu_cmd_buffer *cmd,
75 struct tu_cs *cs,
76 enum fd_gpu_event event)
77 {
78 struct fd_gpu_event_info event_info = fd_gpu_events<CHIP>[event];
79 tu_emit_raw_event_write<CHIP>(cmd, cs, event_info.raw_event,
80 event_info.needs_seqno);
81 }
82 TU_GENX(tu_emit_event_write);
83
84 /* Emits the tessfactor address to the top-level CS if it hasn't been already.
85 * Updating this register requires a WFI if outstanding drawing is using it, but
86 * tu6_init_hardware() will have WFIed before we started and no other draws
87 * could be using the tessfactor address yet since we only emit one per cmdbuf.
88 */
89 template <chip CHIP>
90 static void
tu6_lazy_emit_tessfactor_addr(struct tu_cmd_buffer * cmd)91 tu6_lazy_emit_tessfactor_addr(struct tu_cmd_buffer *cmd)
92 {
93 if (cmd->state.tessfactor_addr_set)
94 return;
95
96 tu_cs_emit_regs(&cmd->cs, PC_TESSFACTOR_ADDR(CHIP, .qword = cmd->device->tess_bo->iova));
97 /* Updating PC_TESSFACTOR_ADDR could race with the next draw which uses it. */
98 cmd->state.cache.flush_bits |= TU_CMD_FLAG_WAIT_FOR_IDLE;
99 cmd->state.tessfactor_addr_set = true;
100 }
101
102 static void
tu6_lazy_init_vsc(struct tu_cmd_buffer * cmd)103 tu6_lazy_init_vsc(struct tu_cmd_buffer *cmd)
104 {
105 struct tu_device *dev = cmd->device;
106 uint32_t num_vsc_pipes = dev->physical_device->info->num_vsc_pipes;
107
108 /* VSC buffers:
109 * use vsc pitches from the largest values used so far with this device
110 * if there hasn't been overflow, there will already be a scratch bo
111 * allocated for these sizes
112 *
113 * if overflow is detected, the stream size is increased by 2x
114 */
115 mtx_lock(&dev->mutex);
116
117 struct tu6_global *global = dev->global_bo_map;
118
119 uint32_t vsc_draw_overflow = global->vsc_draw_overflow;
120 uint32_t vsc_prim_overflow = global->vsc_prim_overflow;
121
122 if (vsc_draw_overflow >= dev->vsc_draw_strm_pitch)
123 dev->vsc_draw_strm_pitch = (dev->vsc_draw_strm_pitch - VSC_PAD) * 2 + VSC_PAD;
124
125 if (vsc_prim_overflow >= dev->vsc_prim_strm_pitch)
126 dev->vsc_prim_strm_pitch = (dev->vsc_prim_strm_pitch - VSC_PAD) * 2 + VSC_PAD;
127
128 cmd->vsc_prim_strm_pitch = dev->vsc_prim_strm_pitch;
129 cmd->vsc_draw_strm_pitch = dev->vsc_draw_strm_pitch;
130
131 mtx_unlock(&dev->mutex);
132
133 struct tu_bo *vsc_bo;
134 uint32_t size0 = cmd->vsc_prim_strm_pitch * num_vsc_pipes +
135 cmd->vsc_draw_strm_pitch * num_vsc_pipes;
136
137 tu_get_scratch_bo(dev, size0 + num_vsc_pipes * 4, &vsc_bo);
138
139 cmd->vsc_draw_strm_va = vsc_bo->iova + cmd->vsc_prim_strm_pitch * num_vsc_pipes;
140 cmd->vsc_draw_strm_size_va = vsc_bo->iova + size0;
141 cmd->vsc_prim_strm_va = vsc_bo->iova;
142 }
143
144 template <chip CHIP>
145 static void
tu_emit_vsc(struct tu_cmd_buffer * cmd,struct tu_cs * cs)146 tu_emit_vsc(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
147 {
148 if (CHIP == A6XX) {
149 tu_cs_emit_regs(cs,
150 A6XX_VSC_DRAW_STRM_SIZE_ADDRESS(.qword = cmd->vsc_draw_strm_size_va));
151 tu_cs_emit_regs(cs,
152 A6XX_VSC_PRIM_STRM_ADDRESS(.qword = cmd->vsc_prim_strm_va));
153 tu_cs_emit_regs(
154 cs, A6XX_VSC_DRAW_STRM_ADDRESS(.qword = cmd->vsc_draw_strm_va));
155 } else {
156 tu_cs_emit_pkt7(cs, CP_SET_PSEUDO_REG, 3 * 3);
157 tu_cs_emit(cs, A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG(DRAW_STRM_ADDRESS));
158 tu_cs_emit_qw(cs, cmd->vsc_draw_strm_va);
159 tu_cs_emit(cs, A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG(DRAW_STRM_SIZE_ADDRESS));
160 tu_cs_emit_qw(cs, cmd->vsc_draw_strm_size_va);
161 tu_cs_emit(cs, A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG(PRIM_STRM_ADDRESS));
162 tu_cs_emit_qw(cs, cmd->vsc_prim_strm_va);
163 }
164
165 cmd->vsc_initialized = true;
166 }
167
168 /* This workaround, copied from the blob, seems to ensure that the BVH node
169 * cache is invalidated so that we don't read stale values when multiple BVHs
170 * share the same address.
171 */
172 static void
tu_emit_rt_workaround(struct tu_cmd_buffer * cmd,struct tu_cs * cs)173 tu_emit_rt_workaround(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
174 {
175 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
176 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_RT_WA_START);
177
178 tu_cs_emit_regs(cs, A7XX_SP_CS_UNKNOWN_A9BE(.dword = 0x10000));
179 tu_cs_emit_regs(cs, A7XX_SP_FS_UNKNOWN_A9AB(.dword = 0x10000));
180 tu_emit_event_write<A7XX>(cmd, cs, FD_DUMMY_EVENT);
181 tu_cs_emit_regs(cs, A7XX_SP_CS_UNKNOWN_A9BE(.dword = 0));
182 tu_cs_emit_regs(cs, A7XX_SP_FS_UNKNOWN_A9AB(.dword = 0));
183 tu_emit_event_write<A7XX>(cmd, cs, FD_DUMMY_EVENT);
184 tu_emit_event_write<A7XX>(cmd, cs, FD_DUMMY_EVENT);
185 tu_emit_event_write<A7XX>(cmd, cs, FD_DUMMY_EVENT);
186 tu_emit_event_write<A7XX>(cmd, cs, FD_DUMMY_EVENT);
187
188 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
189 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_RT_WA_END);
190 }
191
192 template <chip CHIP>
193 static void
tu6_emit_flushes(struct tu_cmd_buffer * cmd_buffer,struct tu_cs * cs,struct tu_cache_state * cache)194 tu6_emit_flushes(struct tu_cmd_buffer *cmd_buffer,
195 struct tu_cs *cs,
196 struct tu_cache_state *cache)
197 {
198 BITMASK_ENUM(tu_cmd_flush_bits) flushes = cache->flush_bits;
199 cache->flush_bits = 0;
200
201 if (TU_DEBUG(FLUSHALL))
202 flushes |= TU_CMD_FLAG_ALL_CLEAN | TU_CMD_FLAG_ALL_INVALIDATE;
203
204 if (TU_DEBUG(SYNCDRAW))
205 flushes |= TU_CMD_FLAG_WAIT_MEM_WRITES |
206 TU_CMD_FLAG_WAIT_FOR_IDLE |
207 TU_CMD_FLAG_WAIT_FOR_ME;
208
209 /* Experiments show that invalidating CCU while it still has data in it
210 * doesn't work, so make sure to always flush before invalidating in case
211 * any data remains that hasn't yet been made available through a barrier.
212 * However it does seem to work for UCHE.
213 */
214 if (flushes & (TU_CMD_FLAG_CCU_CLEAN_COLOR |
215 TU_CMD_FLAG_CCU_INVALIDATE_COLOR))
216 tu_emit_event_write<CHIP>(cmd_buffer, cs, FD_CCU_CLEAN_COLOR);
217 if (flushes & (TU_CMD_FLAG_CCU_CLEAN_DEPTH |
218 TU_CMD_FLAG_CCU_INVALIDATE_DEPTH))
219 tu_emit_event_write<CHIP>(cmd_buffer, cs, FD_CCU_CLEAN_DEPTH);
220 if (flushes & TU_CMD_FLAG_CCU_INVALIDATE_COLOR)
221 tu_emit_event_write<CHIP>(cmd_buffer, cs, FD_CCU_INVALIDATE_COLOR);
222 if (flushes & TU_CMD_FLAG_CCU_INVALIDATE_DEPTH)
223 tu_emit_event_write<CHIP>(cmd_buffer, cs, FD_CCU_INVALIDATE_DEPTH);
224 if (flushes & TU_CMD_FLAG_CACHE_CLEAN)
225 tu_emit_event_write<CHIP>(cmd_buffer, cs, FD_CACHE_CLEAN);
226 if (flushes & TU_CMD_FLAG_CACHE_INVALIDATE)
227 tu_emit_event_write<CHIP>(cmd_buffer, cs, FD_CACHE_INVALIDATE);
228 if (flushes & TU_CMD_FLAG_BINDLESS_DESCRIPTOR_INVALIDATE) {
229 tu_cs_emit_regs(cs, HLSQ_INVALIDATE_CMD(CHIP,
230 .cs_bindless = CHIP == A6XX ? 0x1f : 0xff,
231 .gfx_bindless = CHIP == A6XX ? 0x1f : 0xff,
232 ));
233 }
234 if (CHIP >= A7XX && flushes & TU_CMD_FLAG_BLIT_CACHE_CLEAN)
235 /* On A7XX, blit cache flushes are required to ensure blit writes are visible
236 * via UCHE. This isn't necessary on A6XX, all writes should be visible implictly.
237 */
238 tu_emit_event_write<CHIP>(cmd_buffer, cs, FD_CCU_CLEAN_BLIT_CACHE);
239 if (CHIP >= A7XX && (flushes & TU_CMD_FLAG_CCHE_INVALIDATE) &&
240 /* Invalidating UCHE seems to also invalidate CCHE */
241 !(flushes & TU_CMD_FLAG_CACHE_INVALIDATE))
242 tu_cs_emit_pkt7(cs, CP_CCHE_INVALIDATE, 0);
243 if (CHIP >= A7XX && (flushes & TU_CMD_FLAG_RTU_INVALIDATE) &&
244 cmd_buffer->device->physical_device->info->a7xx.has_rt_workaround)
245 tu_emit_rt_workaround(cmd_buffer, cs);
246 if (flushes & TU_CMD_FLAG_WAIT_MEM_WRITES)
247 tu_cs_emit_pkt7(cs, CP_WAIT_MEM_WRITES, 0);
248 if (flushes & TU_CMD_FLAG_WAIT_FOR_IDLE)
249 tu_cs_emit_wfi(cs);
250 if (flushes & TU_CMD_FLAG_WAIT_FOR_ME)
251 tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
252 }
253
254 /* "Normal" cache flushes outside the renderpass, that don't require any special handling */
255 template <chip CHIP>
256 void
tu_emit_cache_flush(struct tu_cmd_buffer * cmd_buffer)257 tu_emit_cache_flush(struct tu_cmd_buffer *cmd_buffer)
258 {
259 tu6_emit_flushes<CHIP>(cmd_buffer, &cmd_buffer->cs, &cmd_buffer->state.cache);
260 }
261 TU_GENX(tu_emit_cache_flush);
262
263 /* Renderpass cache flushes inside the draw_cs */
264 template <chip CHIP>
265 void
tu_emit_cache_flush_renderpass(struct tu_cmd_buffer * cmd_buffer)266 tu_emit_cache_flush_renderpass(struct tu_cmd_buffer *cmd_buffer)
267 {
268 if (!cmd_buffer->state.renderpass_cache.flush_bits &&
269 likely(!tu_env.debug))
270 return;
271 tu6_emit_flushes<CHIP>(cmd_buffer, &cmd_buffer->draw_cs,
272 &cmd_buffer->state.renderpass_cache);
273 if (cmd_buffer->state.renderpass_cache.flush_bits &
274 TU_CMD_FLAG_BLIT_CACHE_CLEAN) {
275 cmd_buffer->state.blit_cache_cleaned = true;
276 }
277 }
278 TU_GENX(tu_emit_cache_flush_renderpass);
279
280 template <chip CHIP>
281 static void
emit_rb_ccu_cntl(struct tu_cs * cs,struct tu_device * dev,bool gmem)282 emit_rb_ccu_cntl(struct tu_cs *cs, struct tu_device *dev, bool gmem)
283 {
284 /* The CCUs are a cache that allocates memory from GMEM while facilitating
285 * framebuffer caching for sysmem rendering. The CCU is split into two parts,
286 * one for color and one for depth. The size and offset of these in GMEM can
287 * be configured separately.
288 *
289 * The most common configuration for the CCU is to occupy as much as possible
290 * of GMEM (CACHE_SIZE_FULL) during sysmem rendering as GMEM is unused. On
291 * the other hand, when rendering to GMEM, the CCUs can be left enabled at
292 * any configuration as they don't interfere with GMEM rendering and only
293 * overwrite GMEM when sysmem operations are performed.
294 *
295 * The vast majority of GMEM rendering doesn't need any sysmem operations
296 * but there are some cases where it is required. For example, when the
297 * framebuffer isn't aligned to the tile size or with certain MSAA resolves.
298 *
299 * To correctly handle these cases, we need to be able to switch between
300 * sysmem and GMEM rendering. We do this by allocating a carveout at the
301 * end of GMEM for the color CCU (as none of these operations are depth)
302 * which the color CCU offset is set to and the GMEM size available to the
303 * GMEM layout calculations is adjusted accordingly.
304 */
305 uint32_t color_offset = gmem ? dev->physical_device->ccu_offset_gmem
306 : dev->physical_device->ccu_offset_bypass;
307
308 uint32_t color_offset_hi = color_offset >> 21;
309 color_offset &= 0x1fffff;
310
311 uint32_t depth_offset = gmem ? 0
312 : dev->physical_device->ccu_depth_offset_bypass;
313
314 uint32_t depth_offset_hi = depth_offset >> 21;
315 depth_offset &= 0x1fffff;
316
317 enum a6xx_ccu_cache_size color_cache_size = !gmem ? CCU_CACHE_SIZE_FULL : !gmem ? CCU_CACHE_SIZE_FULL :
318 (a6xx_ccu_cache_size)(dev->physical_device->info->a6xx.gmem_ccu_color_cache_fraction);
319
320 if (CHIP == A7XX) {
321 tu_cs_emit_regs(cs, A7XX_RB_CCU_CNTL2(
322 .depth_offset_hi = depth_offset_hi,
323 .color_offset_hi = color_offset_hi,
324 .depth_cache_size = CCU_CACHE_SIZE_FULL,
325 .depth_offset = depth_offset,
326 .color_cache_size = color_cache_size,
327 .color_offset = color_offset
328 ));
329
330 if (dev->physical_device->info->a7xx.has_gmem_vpc_attr_buf) {
331 tu_cs_emit_regs(cs,
332 A7XX_VPC_ATTR_BUF_SIZE_GMEM(
333 .size_gmem =
334 gmem ? dev->physical_device->vpc_attr_buf_size_gmem
335 : dev->physical_device->vpc_attr_buf_size_bypass),
336 A7XX_VPC_ATTR_BUF_BASE_GMEM(
337 .base_gmem =
338 gmem ? dev->physical_device->vpc_attr_buf_offset_gmem
339 : dev->physical_device->vpc_attr_buf_offset_bypass), );
340 tu_cs_emit_regs(cs,
341 A7XX_PC_ATTR_BUF_SIZE_GMEM(
342 .size_gmem =
343 gmem ? dev->physical_device->vpc_attr_buf_size_gmem
344 : dev->physical_device->vpc_attr_buf_size_bypass), );
345 }
346 } else {
347 tu_cs_emit_regs(cs, RB_CCU_CNTL(CHIP,
348 .gmem_fast_clear_disable =
349 !dev->physical_device->info->a6xx.has_gmem_fast_clear,
350 .concurrent_resolve =
351 dev->physical_device->info->a6xx.concurrent_resolve,
352 .depth_offset_hi = 0,
353 .color_offset_hi = color_offset_hi,
354 .depth_cache_size = CCU_CACHE_SIZE_FULL,
355 .depth_offset = 0,
356 .color_cache_size = color_cache_size,
357 .color_offset = color_offset
358 ));
359 }
360 }
361
362 /* Cache flushes for things that use the color/depth read/write path (i.e.
363 * blits and draws). This deals with changing CCU state as well as the usual
364 * cache flushing.
365 */
366 template <chip CHIP>
367 void
tu_emit_cache_flush_ccu(struct tu_cmd_buffer * cmd_buffer,struct tu_cs * cs,enum tu_cmd_ccu_state ccu_state)368 tu_emit_cache_flush_ccu(struct tu_cmd_buffer *cmd_buffer,
369 struct tu_cs *cs,
370 enum tu_cmd_ccu_state ccu_state)
371 {
372 assert(ccu_state != TU_CMD_CCU_UNKNOWN);
373 /* It's unsafe to flush inside condition because we clear flush_bits */
374 assert(!cs->cond_stack_depth);
375
376 /* Changing CCU state must involve invalidating the CCU. In sysmem mode,
377 * the CCU may also contain data that we haven't flushed out yet, so we
378 * also need to flush. Also, in order to program RB_CCU_CNTL, we need to
379 * emit a WFI as it isn't pipelined.
380 *
381 * Note: On A7XX, with the introduction of RB_CCU_CNTL2, we no longer need
382 * to emit a WFI when changing a subset of CCU state.
383 */
384 if (ccu_state != cmd_buffer->state.ccu_state) {
385 if (cmd_buffer->state.ccu_state != TU_CMD_CCU_GMEM) {
386 cmd_buffer->state.cache.flush_bits |=
387 TU_CMD_FLAG_CCU_CLEAN_COLOR |
388 TU_CMD_FLAG_CCU_CLEAN_DEPTH;
389 cmd_buffer->state.cache.pending_flush_bits &= ~(
390 TU_CMD_FLAG_CCU_CLEAN_COLOR |
391 TU_CMD_FLAG_CCU_CLEAN_DEPTH);
392 }
393 cmd_buffer->state.cache.flush_bits |=
394 TU_CMD_FLAG_CCU_INVALIDATE_COLOR |
395 TU_CMD_FLAG_CCU_INVALIDATE_DEPTH |
396 (CHIP == A6XX ? TU_CMD_FLAG_WAIT_FOR_IDLE : 0);
397 cmd_buffer->state.cache.pending_flush_bits &= ~(
398 TU_CMD_FLAG_CCU_INVALIDATE_COLOR |
399 TU_CMD_FLAG_CCU_INVALIDATE_DEPTH |
400 (CHIP == A6XX ? TU_CMD_FLAG_WAIT_FOR_IDLE : 0));
401 }
402
403 tu6_emit_flushes<CHIP>(cmd_buffer, cs, &cmd_buffer->state.cache);
404
405 if (ccu_state != cmd_buffer->state.ccu_state) {
406 emit_rb_ccu_cntl<CHIP>(cs, cmd_buffer->device,
407 ccu_state == TU_CMD_CCU_GMEM);
408 cmd_buffer->state.ccu_state = ccu_state;
409 }
410 }
411 TU_GENX(tu_emit_cache_flush_ccu);
412
413 template <chip CHIP>
414 static void
tu6_emit_zs(struct tu_cmd_buffer * cmd,const struct tu_subpass * subpass,struct tu_cs * cs)415 tu6_emit_zs(struct tu_cmd_buffer *cmd,
416 const struct tu_subpass *subpass,
417 struct tu_cs *cs)
418 {
419 const uint32_t a = subpass->depth_stencil_attachment.attachment;
420 if (a == VK_ATTACHMENT_UNUSED) {
421 tu_cs_emit_regs(cs,
422 RB_DEPTH_BUFFER_INFO(CHIP, .depth_format = DEPTH6_NONE),
423 A6XX_RB_DEPTH_BUFFER_PITCH(0),
424 A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(0),
425 A6XX_RB_DEPTH_BUFFER_BASE(0),
426 A6XX_RB_DEPTH_BUFFER_BASE_GMEM(0));
427
428 tu_cs_emit_regs(cs,
429 A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format = DEPTH6_NONE));
430
431 tu_cs_emit_regs(cs, RB_STENCIL_INFO(CHIP, 0));
432
433 return;
434 }
435
436 const struct tu_image_view *iview = cmd->state.attachments[a];
437 const struct tu_render_pass_attachment *attachment =
438 &cmd->state.pass->attachments[a];
439 enum a6xx_depth_format fmt = tu6_pipe2depth(attachment->format);
440
441 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_BUFFER_INFO, 6);
442 tu_cs_emit(cs, RB_DEPTH_BUFFER_INFO(CHIP,
443 .depth_format = fmt,
444 .tilemode = TILE6_3,
445 .losslesscompen = iview->view.ubwc_enabled,
446 ).value);
447 if (attachment->format == VK_FORMAT_D32_SFLOAT_S8_UINT)
448 tu_cs_image_depth_ref(cs, iview, 0);
449 else
450 tu_cs_image_ref(cs, &iview->view, 0);
451 tu_cs_emit(cs, tu_attachment_gmem_offset(cmd, attachment, 0));
452
453 tu_cs_emit_regs(cs,
454 A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format = fmt));
455
456 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE, 3);
457 tu_cs_image_flag_ref(cs, &iview->view, 0);
458
459 if (attachment->format == VK_FORMAT_D32_SFLOAT_S8_UINT ||
460 attachment->format == VK_FORMAT_S8_UINT) {
461
462 tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCIL_INFO, 6);
463 tu_cs_emit(cs, RB_STENCIL_INFO(CHIP,
464 .separate_stencil = true,
465 .tilemode = TILE6_3,
466 ).value);
467 if (attachment->format == VK_FORMAT_D32_SFLOAT_S8_UINT) {
468 tu_cs_image_stencil_ref(cs, iview, 0);
469 tu_cs_emit(cs, tu_attachment_gmem_offset_stencil(cmd, attachment, 0));
470 } else {
471 tu_cs_image_ref(cs, &iview->view, 0);
472 tu_cs_emit(cs, tu_attachment_gmem_offset(cmd, attachment, 0));
473 }
474 } else {
475 tu_cs_emit_regs(cs,
476 RB_STENCIL_INFO(CHIP, 0));
477 }
478 }
479
480 template <chip CHIP>
481 static void
tu6_emit_mrt(struct tu_cmd_buffer * cmd,const struct tu_subpass * subpass,struct tu_cs * cs)482 tu6_emit_mrt(struct tu_cmd_buffer *cmd,
483 const struct tu_subpass *subpass,
484 struct tu_cs *cs)
485 {
486 const struct tu_framebuffer *fb = cmd->state.framebuffer;
487
488 enum a6xx_format mrt0_format = FMT6_NONE;
489
490 uint32_t written = 0;
491 for (uint32_t i = 0; i < subpass->color_count; ++i) {
492 uint32_t a = subpass->color_attachments[i].attachment;
493 unsigned remapped = cmd->vk.dynamic_graphics_state.cal.color_map[i];
494 if (a == VK_ATTACHMENT_UNUSED ||
495 remapped == MESA_VK_ATTACHMENT_UNUSED)
496 continue;
497
498 const struct tu_image_view *iview = cmd->state.attachments[a];
499
500 tu_cs_emit_regs(cs,
501 RB_MRT_BUF_INFO(CHIP, remapped, .dword = iview->view.RB_MRT_BUF_INFO),
502 A6XX_RB_MRT_PITCH(remapped, iview->view.pitch),
503 A6XX_RB_MRT_ARRAY_PITCH(remapped, iview->view.layer_size),
504 A6XX_RB_MRT_BASE(remapped, .qword = tu_layer_address(&iview->view, 0)),
505 A6XX_RB_MRT_BASE_GMEM(remapped,
506 tu_attachment_gmem_offset(cmd, &cmd->state.pass->attachments[a], 0)
507 ),
508 );
509
510 tu_cs_emit_regs(cs,
511 A6XX_SP_FS_MRT_REG(remapped, .dword = iview->view.SP_FS_MRT_REG));
512
513 tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR(remapped), 3);
514 tu_cs_image_flag_ref(cs, &iview->view, 0);
515
516 if (remapped == 0)
517 mrt0_format = (enum a6xx_format) (iview->view.SP_FS_MRT_REG & 0xff);
518
519 written |= 1u << remapped;
520 }
521
522 u_foreach_bit (i, ~written) {
523 if (i >= subpass->color_count)
524 break;
525
526 /* From the VkPipelineRenderingCreateInfo definition:
527 *
528 * Valid formats indicate that an attachment can be used - but it
529 * is still valid to set the attachment to NULL when beginning
530 * rendering.
531 *
532 * This means that with dynamic rendering, pipelines may write to
533 * some attachments that are UNUSED here. Setting the format to 0
534 * here should prevent them from writing to anything. This also seems
535 * to also be required for alpha-to-coverage which can use the alpha
536 * value for an otherwise-unused attachment.
537 */
538 tu_cs_emit_regs(cs,
539 RB_MRT_BUF_INFO(CHIP, i),
540 A6XX_RB_MRT_PITCH(i),
541 A6XX_RB_MRT_ARRAY_PITCH(i),
542 A6XX_RB_MRT_BASE(i),
543 A6XX_RB_MRT_BASE_GMEM(i),
544 );
545
546 tu_cs_emit_regs(cs,
547 A6XX_SP_FS_MRT_REG(i, .dword = 0));
548 }
549
550 tu_cs_emit_regs(cs, A6XX_GRAS_LRZ_MRT_BUF_INFO_0(.color_format = mrt0_format));
551
552 const bool dither = subpass->legacy_dithering_enabled;
553 const uint32_t dither_cntl =
554 A6XX_RB_DITHER_CNTL(
555 .dither_mode_mrt0 = dither ? DITHER_ALWAYS : DITHER_DISABLE,
556 .dither_mode_mrt1 = dither ? DITHER_ALWAYS : DITHER_DISABLE,
557 .dither_mode_mrt2 = dither ? DITHER_ALWAYS : DITHER_DISABLE,
558 .dither_mode_mrt3 = dither ? DITHER_ALWAYS : DITHER_DISABLE,
559 .dither_mode_mrt4 = dither ? DITHER_ALWAYS : DITHER_DISABLE,
560 .dither_mode_mrt5 = dither ? DITHER_ALWAYS : DITHER_DISABLE,
561 .dither_mode_mrt6 = dither ? DITHER_ALWAYS : DITHER_DISABLE,
562 .dither_mode_mrt7 = dither ? DITHER_ALWAYS : DITHER_DISABLE, )
563 .value;
564 tu_cs_emit_regs(cs, A6XX_RB_DITHER_CNTL(.dword = dither_cntl));
565 if (CHIP >= A7XX) {
566 tu_cs_emit_regs(cs, A7XX_SP_DITHER_CNTL(.dword = dither_cntl));
567 }
568
569 tu_cs_emit_regs(cs,
570 A6XX_RB_SRGB_CNTL(.dword = subpass->srgb_cntl));
571 tu_cs_emit_regs(cs,
572 A6XX_SP_SRGB_CNTL(.dword = subpass->srgb_cntl));
573
574 unsigned layers = MAX2(fb->layers, util_logbase2(subpass->multiview_mask) + 1);
575 tu_cs_emit_regs(cs, A6XX_GRAS_MAX_LAYER_INDEX(layers - 1));
576 }
577
578 struct tu_bin_size_params {
579 enum a6xx_render_mode render_mode;
580 bool force_lrz_write_dis;
581 enum a6xx_buffers_location buffers_location;
582 enum a6xx_lrz_feedback_mask lrz_feedback_zmode_mask;
583 };
584
585 template <chip CHIP>
586 static void
tu6_emit_bin_size(struct tu_cs * cs,uint32_t bin_w,uint32_t bin_h,struct tu_bin_size_params && p)587 tu6_emit_bin_size(struct tu_cs *cs,
588 uint32_t bin_w,
589 uint32_t bin_h,
590 struct tu_bin_size_params &&p)
591 {
592 if (CHIP == A6XX) {
593 tu_cs_emit_regs(
594 cs, A6XX_GRAS_BIN_CONTROL(.binw = bin_w,
595 .binh = bin_h,
596 .render_mode = p.render_mode,
597 .force_lrz_write_dis = p.force_lrz_write_dis,
598 .buffers_location = p.buffers_location,
599 .lrz_feedback_zmode_mask = p.lrz_feedback_zmode_mask, ));
600 } else {
601 tu_cs_emit_regs(cs,
602 A6XX_GRAS_BIN_CONTROL(.binw = bin_w,
603 .binh = bin_h,
604 .render_mode = p.render_mode,
605 .force_lrz_write_dis = p.force_lrz_write_dis,
606 .lrz_feedback_zmode_mask =
607 p.lrz_feedback_zmode_mask, ));
608 }
609
610 tu_cs_emit_regs(cs, RB_BIN_CONTROL(CHIP,
611 .binw = bin_w,
612 .binh = bin_h,
613 .render_mode = p.render_mode,
614 .force_lrz_write_dis = p.force_lrz_write_dis,
615 .buffers_location = p.buffers_location,
616 .lrz_feedback_zmode_mask = p.lrz_feedback_zmode_mask, ));
617
618 /* no flag for RB_BIN_CONTROL2... */
619 tu_cs_emit_regs(cs,
620 A6XX_RB_BIN_CONTROL2(.binw = bin_w,
621 .binh = bin_h));
622 }
623
624 template <chip CHIP>
625 static void
626 tu6_emit_render_cntl(struct tu_cmd_buffer *cmd,
627 const struct tu_subpass *subpass,
628 struct tu_cs *cs,
629 bool binning);
630
631 template <>
632 void
tu6_emit_render_cntl(struct tu_cmd_buffer * cmd,const struct tu_subpass * subpass,struct tu_cs * cs,bool binning)633 tu6_emit_render_cntl<A6XX>(struct tu_cmd_buffer *cmd,
634 const struct tu_subpass *subpass,
635 struct tu_cs *cs,
636 bool binning)
637 {
638 /* doesn't RB_RENDER_CNTL set differently for binning pass: */
639 bool no_track = !cmd->device->physical_device->info->a6xx.has_cp_reg_write;
640 uint32_t cntl = 0;
641 cntl |= A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE(2);
642 if (binning) {
643 if (no_track)
644 return;
645 cntl |= A6XX_RB_RENDER_CNTL_BINNING;
646 } else {
647 uint32_t mrts_ubwc_enable = 0;
648 for (uint32_t i = 0; i < subpass->color_count; ++i) {
649 uint32_t a = subpass->color_attachments[i].attachment;
650 unsigned remapped = cmd->vk.dynamic_graphics_state.cal.color_map[i];
651 if (a == VK_ATTACHMENT_UNUSED ||
652 remapped == MESA_VK_ATTACHMENT_UNUSED)
653 continue;
654
655 const struct tu_image_view *iview = cmd->state.attachments[a];
656 if (iview->view.ubwc_enabled)
657 mrts_ubwc_enable |= 1 << remapped;
658 }
659
660 cntl |= A6XX_RB_RENDER_CNTL_FLAG_MRTS(mrts_ubwc_enable);
661
662 const uint32_t a = subpass->depth_stencil_attachment.attachment;
663 if (a != VK_ATTACHMENT_UNUSED) {
664 const struct tu_image_view *iview = cmd->state.attachments[a];
665 if (iview->view.ubwc_enabled)
666 cntl |= A6XX_RB_RENDER_CNTL_FLAG_DEPTH;
667 }
668
669 if (no_track) {
670 tu_cs_emit_pkt4(cs, REG_A6XX_RB_RENDER_CNTL, 1);
671 tu_cs_emit(cs, cntl);
672 return;
673 }
674
675 /* In the !binning case, we need to set RB_RENDER_CNTL in the draw_cs
676 * in order to set it correctly for the different subpasses. However,
677 * that means the packets we're emitting also happen during binning. So
678 * we need to guard the write on !BINNING at CP execution time.
679 */
680 tu_cs_reserve(cs, 3 + 4);
681 tu_cs_emit_pkt7(cs, CP_COND_REG_EXEC, 2);
682 tu_cs_emit(cs, CP_COND_REG_EXEC_0_MODE(RENDER_MODE) |
683 CP_COND_REG_EXEC_0_GMEM | CP_COND_REG_EXEC_0_SYSMEM);
684 tu_cs_emit(cs, RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS(4));
685 }
686
687 tu_cs_emit_pkt7(cs, CP_REG_WRITE, 3);
688 tu_cs_emit(cs, CP_REG_WRITE_0_TRACKER(TRACK_RENDER_CNTL));
689 tu_cs_emit(cs, REG_A6XX_RB_RENDER_CNTL);
690 tu_cs_emit(cs, cntl);
691 }
692
693 template <>
694 void
tu6_emit_render_cntl(struct tu_cmd_buffer * cmd,const struct tu_subpass * subpass,struct tu_cs * cs,bool binning)695 tu6_emit_render_cntl<A7XX>(struct tu_cmd_buffer *cmd,
696 const struct tu_subpass *subpass,
697 struct tu_cs *cs,
698 bool binning)
699 {
700 }
701
702 static void
tu6_emit_blit_scissor(struct tu_cmd_buffer * cmd,struct tu_cs * cs,bool align)703 tu6_emit_blit_scissor(struct tu_cmd_buffer *cmd, struct tu_cs *cs, bool align)
704 {
705 struct tu_physical_device *phys_dev = cmd->device->physical_device;
706 const VkRect2D *render_area = &cmd->state.render_area;
707
708 /* Avoid assertion fails with an empty render area at (0, 0) where the
709 * subtraction below wraps around. Empty render areas should be forced to
710 * the sysmem path by use_sysmem_rendering(). It's not even clear whether
711 * an empty scissor here works, and the blob seems to force sysmem too as
712 * it sets something wrong (non-empty) for the scissor.
713 */
714 if (render_area->extent.width == 0 ||
715 render_area->extent.height == 0)
716 return;
717
718 uint32_t x1 = render_area->offset.x;
719 uint32_t y1 = render_area->offset.y;
720 uint32_t x2 = x1 + render_area->extent.width - 1;
721 uint32_t y2 = y1 + render_area->extent.height - 1;
722
723 if (align) {
724 x1 = x1 & ~(phys_dev->info->gmem_align_w - 1);
725 y1 = y1 & ~(phys_dev->info->gmem_align_h - 1);
726 x2 = ALIGN_POT(x2 + 1, phys_dev->info->gmem_align_w) - 1;
727 y2 = ALIGN_POT(y2 + 1, phys_dev->info->gmem_align_h) - 1;
728 }
729
730 tu_cs_emit_regs(cs,
731 A6XX_RB_BLIT_SCISSOR_TL(.x = x1, .y = y1),
732 A6XX_RB_BLIT_SCISSOR_BR(.x = x2, .y = y2));
733 }
734
735 void
tu6_emit_window_scissor(struct tu_cs * cs,uint32_t x1,uint32_t y1,uint32_t x2,uint32_t y2)736 tu6_emit_window_scissor(struct tu_cs *cs,
737 uint32_t x1,
738 uint32_t y1,
739 uint32_t x2,
740 uint32_t y2)
741 {
742 tu_cs_emit_regs(cs,
743 A6XX_GRAS_SC_WINDOW_SCISSOR_TL(.x = x1, .y = y1),
744 A6XX_GRAS_SC_WINDOW_SCISSOR_BR(.x = x2, .y = y2));
745
746 tu_cs_emit_regs(cs,
747 A6XX_GRAS_2D_RESOLVE_CNTL_1(.x = x1, .y = y1),
748 A6XX_GRAS_2D_RESOLVE_CNTL_2(.x = x2, .y = y2));
749 }
750
751 template <chip CHIP>
752 void
tu6_emit_window_offset(struct tu_cs * cs,uint32_t x1,uint32_t y1)753 tu6_emit_window_offset(struct tu_cs *cs, uint32_t x1, uint32_t y1)
754 {
755 tu_cs_emit_regs(cs,
756 A6XX_RB_WINDOW_OFFSET(.x = x1, .y = y1));
757
758 tu_cs_emit_regs(cs,
759 A6XX_RB_WINDOW_OFFSET2(.x = x1, .y = y1));
760
761 tu_cs_emit_regs(cs,
762 SP_WINDOW_OFFSET(CHIP, .x = x1, .y = y1));
763
764 tu_cs_emit_regs(cs,
765 A6XX_SP_TP_WINDOW_OFFSET(.x = x1, .y = y1));
766
767 tu_cs_emit_regs(cs,
768 A7XX_SP_PS_2D_WINDOW_OFFSET(.x = x1, .y = y1));
769 }
770
771 void
tu6_apply_depth_bounds_workaround(struct tu_device * device,uint32_t * rb_depth_cntl)772 tu6_apply_depth_bounds_workaround(struct tu_device *device,
773 uint32_t *rb_depth_cntl)
774 {
775 if (!device->physical_device->info->a6xx.depth_bounds_require_depth_test_quirk)
776 return;
777
778 /* On some GPUs it is necessary to enable z test for depth bounds test when
779 * UBWC is enabled. Otherwise, the GPU would hang. FUNC_ALWAYS is required to
780 * pass z test. Relevant tests:
781 * dEQP-VK.pipeline.extended_dynamic_state.two_draws_dynamic.depth_bounds_test_disable
782 * dEQP-VK.dynamic_state.ds_state.depth_bounds_1
783 */
784 *rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE |
785 A6XX_RB_DEPTH_CNTL_ZFUNC(FUNC_ALWAYS);
786 }
787
788 static void
tu_cs_emit_draw_state(struct tu_cs * cs,uint32_t id,struct tu_draw_state state)789 tu_cs_emit_draw_state(struct tu_cs *cs, uint32_t id, struct tu_draw_state state)
790 {
791 uint32_t enable_mask;
792 switch (id) {
793 case TU_DRAW_STATE_VS:
794 case TU_DRAW_STATE_FS:
795 case TU_DRAW_STATE_VPC:
796 /* The blob seems to not enable this (DESC_SETS_LOAD) for binning, even
797 * when resources would actually be used in the binning shader.
798 * Presumably the overhead of prefetching the resources isn't
799 * worth it.
800 */
801 case TU_DRAW_STATE_DESC_SETS_LOAD:
802 enable_mask = CP_SET_DRAW_STATE__0_GMEM |
803 CP_SET_DRAW_STATE__0_SYSMEM;
804 break;
805 case TU_DRAW_STATE_VS_BINNING:
806 case TU_DRAW_STATE_GS_BINNING:
807 enable_mask = CP_SET_DRAW_STATE__0_BINNING;
808 break;
809 case TU_DRAW_STATE_INPUT_ATTACHMENTS_GMEM:
810 enable_mask = CP_SET_DRAW_STATE__0_GMEM;
811 break;
812 case TU_DRAW_STATE_PRIM_MODE_GMEM:
813 /* On a7xx the prim mode is the same for gmem and sysmem, and it no
814 * longer depends on dynamic state, so we reuse the gmem state for
815 * everything:
816 */
817 if (cs->device->physical_device->info->a6xx.has_coherent_ubwc_flag_caches) {
818 enable_mask = CP_SET_DRAW_STATE__0_GMEM |
819 CP_SET_DRAW_STATE__0_SYSMEM |
820 CP_SET_DRAW_STATE__0_BINNING;
821 } else {
822 enable_mask = CP_SET_DRAW_STATE__0_GMEM;
823 }
824 break;
825 case TU_DRAW_STATE_INPUT_ATTACHMENTS_SYSMEM:
826 enable_mask = CP_SET_DRAW_STATE__0_SYSMEM;
827 break;
828 case TU_DRAW_STATE_DYNAMIC + TU_DYNAMIC_STATE_PRIM_MODE_SYSMEM:
829 if (!cs->device->physical_device->info->a6xx.has_coherent_ubwc_flag_caches) {
830 /* By also applying the state during binning we ensure that there
831 * is no rotation applied, by previous A6XX_GRAS_SC_CNTL::rotation.
832 */
833 enable_mask =
834 CP_SET_DRAW_STATE__0_SYSMEM | CP_SET_DRAW_STATE__0_BINNING;
835 } else {
836 static_assert(TU_DYNAMIC_STATE_PRIM_MODE_SYSMEM ==
837 TU_DYNAMIC_STATE_A7XX_FRAGMENT_SHADING_RATE);
838 enable_mask = CP_SET_DRAW_STATE__0_GMEM |
839 CP_SET_DRAW_STATE__0_SYSMEM |
840 CP_SET_DRAW_STATE__0_BINNING;
841 }
842
843 break;
844 default:
845 enable_mask = CP_SET_DRAW_STATE__0_GMEM |
846 CP_SET_DRAW_STATE__0_SYSMEM |
847 CP_SET_DRAW_STATE__0_BINNING;
848 break;
849 }
850
851 STATIC_ASSERT(TU_DRAW_STATE_COUNT <= 32);
852
853 /* We need to reload the descriptors every time the descriptor sets
854 * change. However, the commands we send only depend on the pipeline
855 * because the whole point is to cache descriptors which are used by the
856 * pipeline. There's a problem here, in that the firmware has an
857 * "optimization" which skips executing groups that are set to the same
858 * value as the last draw. This means that if the descriptor sets change
859 * but not the pipeline, we'd try to re-execute the same buffer which
860 * the firmware would ignore and we wouldn't pre-load the new
861 * descriptors. Set the DIRTY bit to avoid this optimization.
862 *
863 * We set the dirty bit for shader draw states because they contain
864 * CP_LOAD_STATE packets that are invalidated by the PROGRAM_CONFIG draw
865 * state, so if PROGRAM_CONFIG changes but one of the shaders stays the
866 * same then we still need to re-emit everything. The GLES blob which
867 * implements separate shader draw states does the same thing.
868 *
869 * We also need to set this bit for draw states which may be patched by the
870 * GPU, because their underlying memory may change between setting the draw
871 * state.
872 */
873 if (id == TU_DRAW_STATE_DESC_SETS_LOAD ||
874 id == TU_DRAW_STATE_VS ||
875 id == TU_DRAW_STATE_VS_BINNING ||
876 id == TU_DRAW_STATE_HS ||
877 id == TU_DRAW_STATE_DS ||
878 id == TU_DRAW_STATE_GS ||
879 id == TU_DRAW_STATE_GS_BINNING ||
880 id == TU_DRAW_STATE_FS ||
881 state.writeable)
882 enable_mask |= CP_SET_DRAW_STATE__0_DIRTY;
883
884 tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(state.size) |
885 enable_mask |
886 CP_SET_DRAW_STATE__0_GROUP_ID(id) |
887 COND(!state.size || !state.iova, CP_SET_DRAW_STATE__0_DISABLE));
888 tu_cs_emit_qw(cs, state.iova);
889 }
890
891 void
tu6_emit_msaa(struct tu_cs * cs,VkSampleCountFlagBits vk_samples,bool msaa_disable)892 tu6_emit_msaa(struct tu_cs *cs, VkSampleCountFlagBits vk_samples,
893 bool msaa_disable)
894 {
895 const enum a3xx_msaa_samples samples = tu_msaa_samples(vk_samples);
896 msaa_disable |= (samples == MSAA_ONE);
897 tu_cs_emit_regs(cs,
898 A6XX_SP_TP_RAS_MSAA_CNTL(samples),
899 A6XX_SP_TP_DEST_MSAA_CNTL(.samples = samples,
900 .msaa_disable = msaa_disable));
901
902 tu_cs_emit_regs(cs,
903 A6XX_GRAS_RAS_MSAA_CNTL(samples),
904 A6XX_GRAS_DEST_MSAA_CNTL(.samples = samples,
905 .msaa_disable = msaa_disable));
906
907 tu_cs_emit_regs(cs,
908 A6XX_RB_RAS_MSAA_CNTL(samples),
909 A6XX_RB_DEST_MSAA_CNTL(.samples = samples,
910 .msaa_disable = msaa_disable));
911 }
912
913 static void
tu6_update_msaa(struct tu_cmd_buffer * cmd)914 tu6_update_msaa(struct tu_cmd_buffer *cmd)
915 {
916 VkSampleCountFlagBits samples =
917 cmd->vk.dynamic_graphics_state.ms.rasterization_samples;;
918
919 /* The samples may not be set by the pipeline or dynamically if raster
920 * discard is enabled. We can set any valid value, but don't set the
921 * default invalid value of 0.
922 */
923 if (samples == 0)
924 samples = VK_SAMPLE_COUNT_1_BIT;
925 tu6_emit_msaa(&cmd->draw_cs, samples, cmd->state.msaa_disable);
926 }
927
928 static void
tu6_update_msaa_disable(struct tu_cmd_buffer * cmd)929 tu6_update_msaa_disable(struct tu_cmd_buffer *cmd)
930 {
931 VkPrimitiveTopology topology =
932 (VkPrimitiveTopology)cmd->vk.dynamic_graphics_state.ia.primitive_topology;
933 bool is_line =
934 topology == VK_PRIMITIVE_TOPOLOGY_LINE_LIST ||
935 topology == VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY ||
936 topology == VK_PRIMITIVE_TOPOLOGY_LINE_STRIP ||
937 topology == VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY ||
938 (topology == VK_PRIMITIVE_TOPOLOGY_PATCH_LIST &&
939 cmd->state.shaders[MESA_SHADER_TESS_EVAL] &&
940 cmd->state.shaders[MESA_SHADER_TESS_EVAL]->variant &&
941 cmd->state.shaders[MESA_SHADER_TESS_EVAL]->variant->key.tessellation == IR3_TESS_ISOLINES);
942 bool msaa_disable = is_line &&
943 cmd->vk.dynamic_graphics_state.rs.line.mode == VK_LINE_RASTERIZATION_MODE_BRESENHAM_KHR;
944
945 if (cmd->state.msaa_disable != msaa_disable) {
946 cmd->state.msaa_disable = msaa_disable;
947 tu6_update_msaa(cmd);
948 }
949 }
950
951 static bool
use_hw_binning(struct tu_cmd_buffer * cmd)952 use_hw_binning(struct tu_cmd_buffer *cmd)
953 {
954 const struct tu_framebuffer *fb = cmd->state.framebuffer;
955 const struct tu_tiling_config *tiling = &fb->tiling[cmd->state.gmem_layout];
956
957 /* XFB commands are emitted for BINNING || SYSMEM, which makes it
958 * incompatible with non-hw binning GMEM rendering. this is required because
959 * some of the XFB commands need to only be executed once.
960 * use_sysmem_rendering() should have made sure we only ended up here if no
961 * XFB was used.
962 */
963 if (cmd->state.rp.xfb_used) {
964 assert(tiling->binning_possible);
965 return true;
966 }
967
968 /* VK_QUERY_TYPE_PRIMITIVES_GENERATED_EXT emulates GL_PRIMITIVES_GENERATED,
969 * which wasn't designed to care about tilers and expects the result not to
970 * be multiplied by tile count.
971 * See https://gitlab.khronos.org/vulkan/vulkan/-/issues/3131
972 */
973 if (cmd->state.rp.has_prim_generated_query_in_rp ||
974 cmd->state.prim_generated_query_running_before_rp) {
975 assert(tiling->binning_possible);
976 return true;
977 }
978
979 return tiling->binning;
980 }
981
982 static bool
use_sysmem_rendering(struct tu_cmd_buffer * cmd,struct tu_renderpass_result ** autotune_result)983 use_sysmem_rendering(struct tu_cmd_buffer *cmd,
984 struct tu_renderpass_result **autotune_result)
985 {
986 if (TU_DEBUG(SYSMEM))
987 return true;
988
989 /* can't fit attachments into gmem */
990 if (!cmd->state.tiling->possible)
991 return true;
992
993 if (cmd->state.framebuffer->layers > 1)
994 return true;
995
996 /* Use sysmem for empty render areas */
997 if (cmd->state.render_area.extent.width == 0 ||
998 cmd->state.render_area.extent.height == 0)
999 return true;
1000
1001 if (cmd->state.rp.has_tess)
1002 return true;
1003
1004 if (cmd->state.rp.disable_gmem)
1005 return true;
1006
1007 /* XFB is incompatible with non-hw binning GMEM rendering, see use_hw_binning */
1008 if (cmd->state.rp.xfb_used && !cmd->state.tiling->binning_possible)
1009 return true;
1010
1011 /* QUERY_TYPE_PRIMITIVES_GENERATED is incompatible with non-hw binning
1012 * GMEM rendering, see use_hw_binning.
1013 */
1014 if ((cmd->state.rp.has_prim_generated_query_in_rp ||
1015 cmd->state.prim_generated_query_running_before_rp) &&
1016 !cmd->state.tiling->binning_possible)
1017 return true;
1018
1019 if (TU_DEBUG(GMEM))
1020 return false;
1021
1022 bool use_sysmem = tu_autotune_use_bypass(&cmd->device->autotune,
1023 cmd, autotune_result);
1024 if (*autotune_result) {
1025 list_addtail(&(*autotune_result)->node, &cmd->renderpass_autotune_results);
1026 }
1027
1028 return use_sysmem;
1029 }
1030
1031 /* Optimization: there is no reason to load gmem if there is no
1032 * geometry to process. COND_REG_EXEC predicate is set here,
1033 * but the actual skip happens in tu_load_gmem_attachment() and tile_store_cs,
1034 * for each blit separately.
1035 */
1036 static void
tu6_emit_cond_for_load_stores(struct tu_cmd_buffer * cmd,struct tu_cs * cs,uint32_t pipe,uint32_t slot,bool skip_wfm)1037 tu6_emit_cond_for_load_stores(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
1038 uint32_t pipe, uint32_t slot, bool skip_wfm)
1039 {
1040 if (cmd->state.tiling->binning_possible &&
1041 cmd->state.pass->has_cond_load_store) {
1042 tu_cs_emit_pkt7(cs, CP_REG_TEST, 1);
1043 tu_cs_emit(cs, A6XX_CP_REG_TEST_0_REG(REG_A6XX_VSC_STATE_REG(pipe)) |
1044 A6XX_CP_REG_TEST_0_BIT(slot) |
1045 COND(skip_wfm, A6XX_CP_REG_TEST_0_SKIP_WAIT_FOR_ME));
1046 } else {
1047 /* COND_REG_EXECs are not emitted in non-binning case */
1048 }
1049 }
1050
1051 template <chip CHIP>
1052 static void
tu6_emit_tile_select(struct tu_cmd_buffer * cmd,struct tu_cs * cs,uint32_t tx,uint32_t ty,uint32_t pipe,uint32_t slot,const struct tu_image_view * fdm)1053 tu6_emit_tile_select(struct tu_cmd_buffer *cmd,
1054 struct tu_cs *cs,
1055 uint32_t tx, uint32_t ty, uint32_t pipe, uint32_t slot,
1056 const struct tu_image_view *fdm)
1057 {
1058 struct tu_physical_device *phys_dev = cmd->device->physical_device;
1059 const struct tu_tiling_config *tiling = cmd->state.tiling;
1060 bool hw_binning = use_hw_binning(cmd);
1061
1062 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
1063 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_BIN_RENDER_START) |
1064 A6XX_CP_SET_MARKER_0_USES_GMEM);
1065
1066 tu6_emit_bin_size<CHIP>(
1067 cs, tiling->tile0.width, tiling->tile0.height,
1068 {
1069 .render_mode = RENDERING_PASS,
1070 .force_lrz_write_dis = !phys_dev->info->a6xx.has_lrz_feedback,
1071 .buffers_location = BUFFERS_IN_GMEM,
1072 .lrz_feedback_zmode_mask =
1073 phys_dev->info->a6xx.has_lrz_feedback
1074 ? (hw_binning ? LRZ_FEEDBACK_EARLY_Z_OR_EARLY_LRZ_LATE_Z :
1075 LRZ_FEEDBACK_EARLY_LRZ_LATE_Z)
1076 : LRZ_FEEDBACK_NONE,
1077 });
1078
1079 tu_cs_emit_regs(cs,
1080 A6XX_VFD_MODE_CNTL(RENDERING_PASS));
1081
1082 const uint32_t x1 = tiling->tile0.width * tx;
1083 const uint32_t y1 = tiling->tile0.height * ty;
1084 const uint32_t x2 = MIN2(x1 + tiling->tile0.width, MAX_VIEWPORT_SIZE);
1085 const uint32_t y2 = MIN2(y1 + tiling->tile0.height, MAX_VIEWPORT_SIZE);
1086 tu6_emit_window_scissor(cs, x1, y1, x2 - 1, y2 - 1);
1087 tu6_emit_window_offset<CHIP>(cs, x1, y1);
1088
1089 if (hw_binning) {
1090 tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
1091
1092 tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
1093 tu_cs_emit(cs, 0x0);
1094
1095 tu_cs_emit_pkt7(cs, CP_SET_BIN_DATA5_OFFSET, 4);
1096 tu_cs_emit(cs, tiling->pipe_sizes[pipe] |
1097 CP_SET_BIN_DATA5_0_VSC_N(slot));
1098 tu_cs_emit(cs, pipe * cmd->vsc_draw_strm_pitch);
1099 tu_cs_emit(cs, pipe * 4);
1100 tu_cs_emit(cs, pipe * cmd->vsc_prim_strm_pitch);
1101 }
1102
1103 tu6_emit_cond_for_load_stores(cmd, cs, pipe, slot, hw_binning);
1104
1105 tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
1106 tu_cs_emit(cs, !hw_binning);
1107
1108 tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
1109 tu_cs_emit(cs, 0x0);
1110
1111 if (fdm || (TU_DEBUG(FDM) && cmd->state.pass->has_fdm)) {
1112 unsigned views =
1113 cmd->state.pass->num_views ? cmd->state.pass->num_views : 1;
1114 const struct tu_framebuffer *fb = cmd->state.framebuffer;
1115 struct tu_frag_area raw_areas[views];
1116 if (fdm) {
1117 tu_fragment_density_map_sample(fdm,
1118 (x1 + MIN2(x2, fb->width)) / 2,
1119 (y1 + MIN2(y2, fb->height)) / 2,
1120 fb->width, fb->height, views,
1121 raw_areas);
1122 } else {
1123 for (unsigned i = 0; i < views; i++)
1124 raw_areas[i].width = raw_areas[i].height = 1.0f;
1125 }
1126
1127 VkExtent2D frag_areas[views];
1128 for (unsigned i = 0; i < views; i++) {
1129 float floor_x, floor_y;
1130 float area = raw_areas[i].width * raw_areas[i].height;
1131 float frac_x = modff(raw_areas[i].width, &floor_x);
1132 float frac_y = modff(raw_areas[i].height, &floor_y);
1133 /* The spec allows rounding up one of the axes as long as the total
1134 * area is less than or equal to the original area. Take advantage of
1135 * this to try rounding up the number with the largest fraction.
1136 */
1137 if ((frac_x > frac_y ? (floor_x + 1.f) * floor_y :
1138 floor_x * (floor_y + 1.f)) <= area) {
1139 if (frac_x > frac_y)
1140 floor_x += 1.f;
1141 else
1142 floor_y += 1.f;
1143 }
1144 frag_areas[i].width = floor_x;
1145 frag_areas[i].height = floor_y;
1146
1147 /* Make sure that the width/height divides the tile width/height so
1148 * we don't have to do extra awkward clamping of the edges of each
1149 * bin when resolving. Note that because the tile width is rounded to
1150 * a multiple of 32 any power of two 32 or less will work.
1151 *
1152 * TODO: Try to take advantage of the total area allowance here, too.
1153 */
1154 while (tiling->tile0.width % frag_areas[i].width != 0)
1155 frag_areas[i].width--;
1156 while (tiling->tile0.height % frag_areas[i].height != 0)
1157 frag_areas[i].height--;
1158 }
1159
1160 /* If at any point we were forced to use the same scaling for all
1161 * viewports, we need to make sure that any users *not* using shared
1162 * scaling, including loads/stores, also consistently share the scaling.
1163 */
1164 if (cmd->state.rp.shared_viewport) {
1165 VkExtent2D frag_area = { UINT32_MAX, UINT32_MAX };
1166 for (unsigned i = 0; i < views; i++) {
1167 frag_area.width = MIN2(frag_area.width, frag_areas[i].width);
1168 frag_area.height = MIN2(frag_area.height, frag_areas[i].height);
1169 }
1170
1171 for (unsigned i = 0; i < views; i++)
1172 frag_areas[i] = frag_area;
1173 }
1174
1175 VkRect2D bin = { { x1, y1 }, { x2 - x1, y2 - y1 } };
1176 util_dynarray_foreach (&cmd->fdm_bin_patchpoints,
1177 struct tu_fdm_bin_patchpoint, patch) {
1178 tu_cs_emit_pkt7(cs, CP_MEM_WRITE, 2 + patch->size);
1179 tu_cs_emit_qw(cs, patch->iova);
1180 patch->apply(cmd, cs, patch->data, bin, views, frag_areas);
1181 }
1182
1183 /* Make the CP wait until the CP_MEM_WRITE's to the command buffers
1184 * land. When loading FS params via UBOs, we also need to invalidate
1185 * UCHE because the FS param patchpoint is read through UCHE.
1186 */
1187 tu_cs_emit_pkt7(cs, CP_WAIT_MEM_WRITES, 0);
1188 if (cmd->device->compiler->load_shader_consts_via_preamble) {
1189 tu_emit_event_write<CHIP>(cmd, cs, FD_CACHE_INVALIDATE);
1190 tu_cs_emit_wfi(cs);
1191 }
1192 tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
1193 }
1194 }
1195
1196 template <chip CHIP>
1197 static void
tu6_emit_sysmem_resolve(struct tu_cmd_buffer * cmd,struct tu_cs * cs,uint32_t layer_mask,uint32_t a,uint32_t gmem_a)1198 tu6_emit_sysmem_resolve(struct tu_cmd_buffer *cmd,
1199 struct tu_cs *cs,
1200 uint32_t layer_mask,
1201 uint32_t a,
1202 uint32_t gmem_a)
1203 {
1204 const struct tu_framebuffer *fb = cmd->state.framebuffer;
1205 const struct tu_image_view *dst = cmd->state.attachments[a];
1206 const struct tu_image_view *src = cmd->state.attachments[gmem_a];
1207
1208 tu_resolve_sysmem<CHIP>(cmd, cs, src, dst, layer_mask, fb->layers, &cmd->state.render_area);
1209 }
1210
1211 template <chip CHIP>
1212 static void
tu6_emit_sysmem_resolves(struct tu_cmd_buffer * cmd,struct tu_cs * cs,const struct tu_subpass * subpass)1213 tu6_emit_sysmem_resolves(struct tu_cmd_buffer *cmd,
1214 struct tu_cs *cs,
1215 const struct tu_subpass *subpass)
1216 {
1217 if (subpass->resolve_attachments) {
1218 /* From the documentation for vkCmdNextSubpass, section 7.4 "Render Pass
1219 * Commands":
1220 *
1221 * End-of-subpass multisample resolves are treated as color
1222 * attachment writes for the purposes of synchronization.
1223 * This applies to resolve operations for both color and
1224 * depth/stencil attachments. That is, they are considered to
1225 * execute in the VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT
1226 * pipeline stage and their writes are synchronized with
1227 * VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT. Synchronization between
1228 * rendering within a subpass and any resolve operations at the end
1229 * of the subpass occurs automatically, without need for explicit
1230 * dependencies or pipeline barriers. However, if the resolve
1231 * attachment is also used in a different subpass, an explicit
1232 * dependency is needed.
1233 *
1234 * We use the CP_BLIT path for sysmem resolves, which is really a
1235 * transfer command, so we have to manually flush similar to the gmem
1236 * resolve case. However, a flush afterwards isn't needed because of the
1237 * last sentence and the fact that we're in sysmem mode.
1238 */
1239 tu_emit_event_write<CHIP>(cmd, cs, FD_CCU_CLEAN_COLOR);
1240 if (subpass->resolve_depth_stencil)
1241 tu_emit_event_write<CHIP>(cmd, cs, FD_CCU_CLEAN_DEPTH);
1242
1243 tu_emit_event_write<CHIP>(cmd, cs, FD_CACHE_INVALIDATE);
1244
1245 /* Wait for the flushes to land before using the 2D engine */
1246 tu_cs_emit_wfi(cs);
1247
1248 for (unsigned i = 0; i < subpass->resolve_count; i++) {
1249 uint32_t a = subpass->resolve_attachments[i].attachment;
1250 if (a == VK_ATTACHMENT_UNUSED)
1251 continue;
1252
1253 uint32_t gmem_a = tu_subpass_get_attachment_to_resolve(subpass, i);
1254
1255 tu6_emit_sysmem_resolve<CHIP>(cmd, cs, subpass->multiview_mask, a, gmem_a);
1256 }
1257 }
1258 }
1259
1260 template <chip CHIP>
1261 static void
tu6_emit_tile_store(struct tu_cmd_buffer * cmd,struct tu_cs * cs)1262 tu6_emit_tile_store(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1263 {
1264 const struct tu_render_pass *pass = cmd->state.pass;
1265 const struct tu_subpass *subpass = &pass->subpasses[pass->subpass_count-1];
1266 const struct tu_framebuffer *fb = cmd->state.framebuffer;
1267
1268 if (pass->has_fdm)
1269 tu_cs_set_writeable(cs, true);
1270
1271 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
1272 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_BIN_RESOLVE) |
1273 A6XX_CP_SET_MARKER_0_USES_GMEM);
1274
1275 tu6_emit_blit_scissor(cmd, cs, true);
1276
1277 struct tu_resolve_group resolve_group = {};
1278
1279 /* Resolve should happen before store in case BLIT_EVENT_STORE_AND_CLEAR is
1280 * used for a store.
1281 */
1282 if (subpass->resolve_attachments) {
1283 for (unsigned i = 0; i < subpass->resolve_count; i++) {
1284 uint32_t a = subpass->resolve_attachments[i].attachment;
1285 if (a != VK_ATTACHMENT_UNUSED) {
1286 uint32_t gmem_a = tu_subpass_get_attachment_to_resolve(subpass, i);
1287 tu_store_gmem_attachment<CHIP>(cmd, cs, &resolve_group, a, gmem_a,
1288 fb->layers, subpass->multiview_mask, false);
1289 }
1290 }
1291 }
1292
1293 for (uint32_t a = 0; a < pass->attachment_count; ++a) {
1294 if (pass->attachments[a].gmem) {
1295 const bool cond_exec_allowed = cmd->state.tiling->binning_possible &&
1296 cmd->state.pass->has_cond_load_store;
1297 tu_store_gmem_attachment<CHIP>(cmd, cs, &resolve_group, a, a,
1298 fb->layers, subpass->multiview_mask,
1299 cond_exec_allowed);
1300 }
1301 }
1302
1303 tu_emit_resolve_group<CHIP>(cmd, cs, &resolve_group);
1304
1305 if (pass->has_fdm)
1306 tu_cs_set_writeable(cs, false);
1307 }
1308
1309 void
tu_disable_draw_states(struct tu_cmd_buffer * cmd,struct tu_cs * cs)1310 tu_disable_draw_states(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1311 {
1312 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
1313 tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(0) |
1314 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
1315 CP_SET_DRAW_STATE__0_GROUP_ID(0));
1316 tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1317 tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1318
1319 cmd->state.dirty |= TU_CMD_DIRTY_DRAW_STATE;
1320 }
1321
1322 template <chip CHIP>
1323 static void
tu6_init_static_regs(struct tu_device * dev,struct tu_cs * cs)1324 tu6_init_static_regs(struct tu_device *dev, struct tu_cs *cs)
1325 {
1326 const struct tu_physical_device *phys_dev = dev->physical_device;
1327
1328 if (CHIP >= A7XX) {
1329 /* On A7XX, RB_CCU_CNTL was broken into two registers, RB_CCU_CNTL which has
1330 * static properties that can be set once, this requires a WFI to take effect.
1331 * While the newly introduced register RB_CCU_CNTL2 has properties that may
1332 * change per-RP and don't require a WFI to take effect, only CCU inval/flush
1333 * events are required.
1334 */
1335
1336 enum a7xx_concurrent_resolve_mode resolve_mode = CONCURRENT_RESOLVE_MODE_2;
1337 if (TU_DEBUG(NO_CONCURRENT_RESOLVES))
1338 resolve_mode = CONCURRENT_RESOLVE_MODE_DISABLED;
1339
1340 enum a7xx_concurrent_unresolve_mode unresolve_mode = CONCURRENT_UNRESOLVE_MODE_FULL;
1341 if (TU_DEBUG(NO_CONCURRENT_UNRESOLVES))
1342 unresolve_mode = CONCURRENT_UNRESOLVE_MODE_DISABLED;
1343
1344 tu_cs_emit_regs(cs, RB_CCU_CNTL(A7XX,
1345 .gmem_fast_clear_disable =
1346 !dev->physical_device->info->a6xx.has_gmem_fast_clear,
1347 .concurrent_resolve_mode = resolve_mode,
1348 .concurrent_unresolve_mode = unresolve_mode,
1349 ));
1350 }
1351
1352 for (size_t i = 0; i < ARRAY_SIZE(phys_dev->info->a6xx.magic_raw); i++) {
1353 auto magic_reg = phys_dev->info->a6xx.magic_raw[i];
1354 if (!magic_reg.reg)
1355 break;
1356
1357 uint32_t value = magic_reg.value;
1358 switch(magic_reg.reg) {
1359 case REG_A6XX_TPL1_DBG_ECO_CNTL1:
1360 value = (value & ~A6XX_TPL1_DBG_ECO_CNTL1_TP_UBWC_FLAG_HINT) |
1361 (phys_dev->info->a7xx.enable_tp_ubwc_flag_hint
1362 ? A6XX_TPL1_DBG_ECO_CNTL1_TP_UBWC_FLAG_HINT
1363 : 0);
1364 break;
1365 }
1366
1367 tu_cs_emit_write_reg(cs, magic_reg.reg, value);
1368 }
1369
1370 tu_cs_emit_write_reg(cs, REG_A6XX_RB_DBG_ECO_CNTL,
1371 phys_dev->info->a6xx.magic.RB_DBG_ECO_CNTL);
1372 tu_cs_emit_write_reg(cs, REG_A6XX_SP_FLOAT_CNTL, 0);
1373 tu_cs_emit_write_reg(cs, REG_A6XX_SP_DBG_ECO_CNTL,
1374 phys_dev->info->a6xx.magic.SP_DBG_ECO_CNTL);
1375 tu_cs_emit_write_reg(cs, REG_A6XX_SP_PERFCTR_ENABLE, 0x3f);
1376 if (CHIP == A6XX)
1377 tu_cs_emit_write_reg(cs, REG_A6XX_TPL1_UNKNOWN_B605, 0x44);
1378 tu_cs_emit_write_reg(cs, REG_A6XX_TPL1_DBG_ECO_CNTL,
1379 phys_dev->info->a6xx.magic.TPL1_DBG_ECO_CNTL);
1380 if (CHIP == A6XX) {
1381 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE00, 0x80);
1382 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE01, 0);
1383 }
1384
1385 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_DBG_ECO_CNTL,
1386 phys_dev->info->a6xx.magic.VPC_DBG_ECO_CNTL);
1387 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_DBG_ECO_CNTL,
1388 phys_dev->info->a6xx.magic.GRAS_DBG_ECO_CNTL);
1389 if (CHIP == A6XX) {
1390 tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_DBG_ECO_CNTL,
1391 phys_dev->info->a6xx.magic.HLSQ_DBG_ECO_CNTL);
1392 }
1393 tu_cs_emit_write_reg(cs, REG_A6XX_SP_CHICKEN_BITS,
1394 phys_dev->info->a6xx.magic.SP_CHICKEN_BITS);
1395 tu_cs_emit_write_reg(cs, REG_A6XX_SP_IBO_COUNT, 0); // 2 on a740 ???
1396 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B182, 0);
1397 if (CHIP == A6XX)
1398 tu_cs_emit_regs(cs, A6XX_HLSQ_SHARED_CONSTS(.enable = false));
1399 tu_cs_emit_write_reg(cs, REG_A6XX_UCHE_UNKNOWN_0E12,
1400 phys_dev->info->a6xx.magic.UCHE_UNKNOWN_0E12);
1401 tu_cs_emit_write_reg(cs, REG_A6XX_UCHE_CLIENT_PF,
1402 phys_dev->info->a6xx.magic.UCHE_CLIENT_PF);
1403 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8E01,
1404 phys_dev->info->a6xx.magic.RB_UNKNOWN_8E01);
1405 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_A9A8, 0);
1406 tu_cs_emit_regs(cs, A6XX_SP_MODE_CONTROL(.constant_demotion_enable = true,
1407 .isammode = ISAMMODE_GL,
1408 .shared_consts_enable = false));
1409
1410 /* TODO: set A6XX_VFD_ADD_OFFSET_INSTANCE and fix ir3 to avoid adding base instance */
1411 tu_cs_emit_write_reg(cs, REG_A6XX_VFD_ADD_OFFSET, A6XX_VFD_ADD_OFFSET_VERTEX);
1412 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8811, 0x00000010);
1413 tu_cs_emit_write_reg(cs, REG_A6XX_PC_MODE_CNTL,
1414 phys_dev->info->a6xx.magic.PC_MODE_CNTL);
1415
1416 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8110, 0);
1417
1418 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8818, 0);
1419
1420 if (CHIP == A6XX) {
1421 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8819, 0);
1422 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881A, 0);
1423 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881B, 0);
1424 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881C, 0);
1425 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881D, 0);
1426 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_881E, 0);
1427 }
1428
1429 tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_88F0, 0);
1430
1431 tu_cs_emit_regs(cs, A6XX_VPC_POINT_COORD_INVERT(false));
1432 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9300, 0);
1433
1434 tu_cs_emit_regs(cs, A6XX_VPC_SO_DISABLE(true));
1435
1436 tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B183, 0);
1437
1438 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80AF, 0);
1439 if (CHIP == A6XX) {
1440 tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL, 0);
1441 tu_cs_emit_regs(cs, A6XX_PC_DGEN_SU_CONSERVATIVE_RAS_CNTL());
1442
1443 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9210, 0);
1444 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9211, 0);
1445 }
1446 tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9602, 0);
1447 tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9E72, 0);
1448 tu_cs_emit_write_reg(cs, REG_A6XX_SP_TP_MODE_CNTL,
1449 0x000000a0 |
1450 A6XX_SP_TP_MODE_CNTL_ISAMMODE(ISAMMODE_GL));
1451 tu_cs_emit_regs(cs, HLSQ_CONTROL_5_REG(CHIP, .dword = 0xfc));
1452
1453 tu_cs_emit_write_reg(cs, REG_A6XX_VFD_MODE_CNTL, 0x00000000);
1454
1455 tu_cs_emit_write_reg(cs, REG_A6XX_PC_MODE_CNTL, phys_dev->info->a6xx.magic.PC_MODE_CNTL);
1456
1457 tu_cs_emit_regs(cs, A6XX_RB_ALPHA_CONTROL()); /* always disable alpha test */
1458
1459 tu_cs_emit_regs(cs,
1460 A6XX_SP_TP_BORDER_COLOR_BASE_ADDR(.bo = dev->global_bo,
1461 .bo_offset = gb_offset(bcolor_builtin)));
1462 tu_cs_emit_regs(cs,
1463 A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR(.bo = dev->global_bo,
1464 .bo_offset = gb_offset(bcolor_builtin)));
1465
1466 if (CHIP == A7XX) {
1467 tu_cs_emit_regs(cs, TPL1_BICUBIC_WEIGHTS_TABLE_0(CHIP, 0),
1468 TPL1_BICUBIC_WEIGHTS_TABLE_1(CHIP, 0x3fe05ff4),
1469 TPL1_BICUBIC_WEIGHTS_TABLE_2(CHIP, 0x3fa0ebee),
1470 TPL1_BICUBIC_WEIGHTS_TABLE_3(CHIP, 0x3f5193ed),
1471 TPL1_BICUBIC_WEIGHTS_TABLE_4(CHIP, 0x3f0243f0), );
1472 }
1473
1474 if (CHIP >= A7XX) {
1475 /* Blob sets these two per draw. */
1476 tu_cs_emit_regs(cs, A7XX_PC_TESS_PARAM_SIZE(TU_TESS_PARAM_SIZE));
1477 /* Blob adds a bit more space ({0x10, 0x20, 0x30, 0x40} bytes)
1478 * but the meaning of this additional space is not known,
1479 * so we play safe and don't add it.
1480 */
1481 tu_cs_emit_regs(cs, A7XX_PC_TESS_FACTOR_SIZE(TU_TESS_FACTOR_SIZE));
1482 }
1483
1484 /* There is an optimization to skip executing draw states for draws with no
1485 * instances. Instead of simply skipping the draw, internally the firmware
1486 * sets a bit in PC_DRAW_INITIATOR that seemingly skips the draw. However
1487 * there is a hardware bug where this bit does not always cause the FS
1488 * early preamble to be skipped. Because the draw states were skipped,
1489 * SP_FS_CTRL_REG0, SP_FS_OBJ_START and so on are never updated and a
1490 * random FS preamble from the last draw is executed. If the last visible
1491 * draw is from the same submit, it shouldn't be a problem because we just
1492 * re-execute the same preamble and preambles don't have side effects, but
1493 * if it's from another process then we could execute a garbage preamble
1494 * leading to hangs and faults. To make sure this doesn't happen, we reset
1495 * SP_FS_CTRL_REG0 here, making sure that the EARLYPREAMBLE bit isn't set
1496 * so any leftover early preamble doesn't get executed. Other stages don't
1497 * seem to be affected.
1498 */
1499 if (phys_dev->info->a6xx.has_early_preamble) {
1500 tu_cs_emit_regs(cs, A6XX_SP_FS_CTRL_REG0());
1501 }
1502
1503 /* Workaround for draw state with constlen not being applied for
1504 * zero-instance draw calls. See IR3_CONST_ALLOC_DRIVER_PARAMS allocation
1505 * for more info.
1506 */
1507 tu_cs_emit_pkt4(
1508 cs, CHIP == A6XX ? REG_A6XX_HLSQ_VS_CNTL : REG_A7XX_HLSQ_VS_CNTL, 1);
1509 tu_cs_emit(cs, A6XX_HLSQ_VS_CNTL_CONSTLEN(8) | A6XX_HLSQ_VS_CNTL_ENABLED);
1510 }
1511
1512 /* Set always-identical registers used specifically for GMEM */
1513 static void
tu7_emit_tile_render_begin_regs(struct tu_cs * cs)1514 tu7_emit_tile_render_begin_regs(struct tu_cs *cs)
1515 {
1516 tu_cs_emit_regs(cs,
1517 A7XX_RB_UNKNOWN_8812(0x0));
1518 tu_cs_emit_regs(cs,
1519 A7XX_RB_UNKNOWN_8E06(0x0));
1520
1521 tu_cs_emit_regs(cs, A7XX_GRAS_UNKNOWN_8007(0x0));
1522
1523 tu_cs_emit_regs(cs, A6XX_GRAS_UNKNOWN_8110(0x2));
1524 tu_cs_emit_regs(cs, A7XX_RB_UNKNOWN_8E09(0x4));
1525
1526 tu_cs_emit_regs(cs, A7XX_RB_BLIT_CLEAR_MODE(.clear_mode = CLEAR_MODE_GMEM));
1527 }
1528
1529 /* Emit the bin restore preamble, which runs in between bins when L1
1530 * preemption with skipsaverestore happens and we switch back to this context.
1531 * We need to restore static registers normally programmed at cmdbuf start
1532 * which weren't saved, and we need to program the CCU state which is normally
1533 * programmed before rendering the bins and isn't saved/restored by the CP
1534 * because it is always the same for GMEM render passes.
1535 */
1536 template <chip CHIP>
1537 static void
tu_emit_bin_preamble(struct tu_device * dev,struct tu_cs * cs)1538 tu_emit_bin_preamble(struct tu_device *dev, struct tu_cs *cs)
1539 {
1540 struct tu_physical_device *phys_dev = dev->physical_device;
1541
1542 tu6_init_static_regs<CHIP>(dev, cs);
1543 emit_rb_ccu_cntl<CHIP>(cs, dev, true);
1544
1545 if (CHIP == A6XX) {
1546 tu_cs_emit_regs(cs,
1547 A6XX_PC_POWER_CNTL(phys_dev->info->a6xx.magic.PC_POWER_CNTL));
1548
1549 tu_cs_emit_regs(cs,
1550 A6XX_VFD_POWER_CNTL(phys_dev->info->a6xx.magic.PC_POWER_CNTL));
1551 }
1552
1553 if (CHIP == A7XX) {
1554 tu7_emit_tile_render_begin_regs(cs);
1555 }
1556
1557 /* TODO use CP_MEM_TO_SCRATCH_MEM on a7xx. The VSC scratch mem should be
1558 * automatically saved, unlike GPU registers, so we wouldn't have to
1559 * manually restore this state.
1560 */
1561 tu_cs_emit_pkt7(cs, CP_MEM_TO_REG, 3);
1562 tu_cs_emit(cs, CP_MEM_TO_REG_0_REG(REG_A6XX_VSC_STATE(0)) |
1563 CP_MEM_TO_REG_0_CNT(32));
1564 tu_cs_emit_qw(cs, dev->global_bo->iova + gb_offset(vsc_state));
1565 }
1566
1567 VkResult
tu_init_bin_preamble(struct tu_device * device)1568 tu_init_bin_preamble(struct tu_device *device)
1569 {
1570 struct tu_cs preamble_cs;
1571 VkResult result = tu_cs_begin_sub_stream(&device->sub_cs, 256, &preamble_cs);
1572 if (result != VK_SUCCESS)
1573 return vk_startup_errorf(device->instance, result, "bin restore");
1574
1575 TU_CALLX(device, tu_emit_bin_preamble)(device, &preamble_cs);
1576
1577 device->bin_preamble_entry = tu_cs_end_sub_stream(&device->sub_cs, &preamble_cs);
1578
1579 return VK_SUCCESS;
1580 }
1581
1582 template <chip CHIP>
1583 static void
tu6_init_hw(struct tu_cmd_buffer * cmd,struct tu_cs * cs)1584 tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1585 {
1586 struct tu_device *dev = cmd->device;
1587 const struct tu_physical_device *phys_dev = dev->physical_device;
1588
1589 if (CHIP == A6XX) {
1590 tu_emit_event_write<CHIP>(cmd, cs, FD_CACHE_INVALIDATE);
1591 } else {
1592 tu_cs_emit_pkt7(cs, CP_THREAD_CONTROL, 1);
1593 tu_cs_emit(cs, CP_THREAD_CONTROL_0_THREAD(CP_SET_THREAD_BR) |
1594 CP_THREAD_CONTROL_0_CONCURRENT_BIN_DISABLE);
1595
1596 tu_emit_event_write<CHIP>(cmd, cs, FD_CCU_INVALIDATE_COLOR);
1597 tu_emit_event_write<CHIP>(cmd, cs, FD_CCU_INVALIDATE_DEPTH);
1598 tu_emit_raw_event_write<CHIP>(cmd, cs, UNK_40, false);
1599 tu_emit_event_write<CHIP>(cmd, cs, FD_CACHE_INVALIDATE);
1600 tu_cs_emit_wfi(cs);
1601 }
1602
1603 tu_cs_emit_regs(cs, HLSQ_INVALIDATE_CMD(CHIP,
1604 .vs_state = true,
1605 .hs_state = true,
1606 .ds_state = true,
1607 .gs_state = true,
1608 .fs_state = true,
1609 .cs_state = true,
1610 .cs_ibo = true,
1611 .gfx_ibo = true,
1612 .cs_shared_const = true,
1613 .gfx_shared_const = true,
1614 .cs_bindless = CHIP == A6XX ? 0x1f : 0xff,
1615 .gfx_bindless = CHIP == A6XX ? 0x1f : 0xff,));
1616
1617 tu_cs_emit_wfi(cs);
1618
1619 if (dev->dbg_cmdbuf_stomp_cs) {
1620 tu_cs_emit_call(cs, dev->dbg_cmdbuf_stomp_cs);
1621 }
1622
1623 cmd->state.cache.pending_flush_bits &=
1624 ~(TU_CMD_FLAG_WAIT_FOR_IDLE | TU_CMD_FLAG_CACHE_INVALIDATE);
1625
1626 tu6_init_static_regs<CHIP>(cmd->device, cs);
1627
1628 emit_rb_ccu_cntl<CHIP>(cs, cmd->device, false);
1629 cmd->state.ccu_state = TU_CMD_CCU_SYSMEM;
1630
1631 tu_disable_draw_states(cmd, cs);
1632
1633 if (phys_dev->info->a7xx.cmdbuf_start_a725_quirk) {
1634 tu_cs_reserve(cs, 3 + 4);
1635 tu_cs_emit_pkt7(cs, CP_COND_REG_EXEC, 2);
1636 tu_cs_emit(cs, CP_COND_REG_EXEC_0_MODE(THREAD_MODE) |
1637 CP_COND_REG_EXEC_0_BR | CP_COND_REG_EXEC_0_LPAC);
1638 tu_cs_emit(cs, RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS(4));
1639 tu_cs_emit_ib(cs, &dev->cmdbuf_start_a725_quirk_entry);
1640 }
1641
1642 tu_cs_emit_pkt7(cs, CP_SET_AMBLE, 3);
1643 tu_cs_emit_qw(cs, cmd->device->bin_preamble_entry.bo->iova +
1644 cmd->device->bin_preamble_entry.offset);
1645 tu_cs_emit(cs, CP_SET_AMBLE_2_DWORDS(cmd->device->bin_preamble_entry.size /
1646 sizeof(uint32_t)) |
1647 CP_SET_AMBLE_2_TYPE(BIN_PREAMBLE_AMBLE_TYPE));
1648
1649 tu_cs_emit_pkt7(cs, CP_SET_AMBLE, 3);
1650 tu_cs_emit_qw(cs, 0);
1651 tu_cs_emit(cs, CP_SET_AMBLE_2_TYPE(PREAMBLE_AMBLE_TYPE));
1652
1653 tu_cs_emit_pkt7(cs, CP_SET_AMBLE, 3);
1654 tu_cs_emit_qw(cs, 0);
1655 tu_cs_emit(cs, CP_SET_AMBLE_2_TYPE(POSTAMBLE_AMBLE_TYPE));
1656
1657 tu_cs_sanity_check(cs);
1658 }
1659
1660 static void
update_vsc_pipe(struct tu_cmd_buffer * cmd,struct tu_cs * cs,uint32_t num_vsc_pipes)1661 update_vsc_pipe(struct tu_cmd_buffer *cmd,
1662 struct tu_cs *cs,
1663 uint32_t num_vsc_pipes)
1664 {
1665 const struct tu_tiling_config *tiling = cmd->state.tiling;
1666
1667 tu_cs_emit_regs(cs,
1668 A6XX_VSC_BIN_SIZE(.width = tiling->tile0.width,
1669 .height = tiling->tile0.height));
1670
1671 tu_cs_emit_regs(cs,
1672 A6XX_VSC_BIN_COUNT(.nx = tiling->tile_count.width,
1673 .ny = tiling->tile_count.height));
1674
1675 tu_cs_emit_pkt4(cs, REG_A6XX_VSC_PIPE_CONFIG_REG(0), num_vsc_pipes);
1676 tu_cs_emit_array(cs, tiling->pipe_config, num_vsc_pipes);
1677
1678 tu_cs_emit_regs(cs,
1679 A6XX_VSC_PRIM_STRM_PITCH(cmd->vsc_prim_strm_pitch),
1680 A6XX_VSC_PRIM_STRM_LIMIT(cmd->vsc_prim_strm_pitch - VSC_PAD));
1681
1682 tu_cs_emit_regs(cs,
1683 A6XX_VSC_DRAW_STRM_PITCH(cmd->vsc_draw_strm_pitch),
1684 A6XX_VSC_DRAW_STRM_LIMIT(cmd->vsc_draw_strm_pitch - VSC_PAD));
1685
1686 tu_cs_emit_regs(cs, A7XX_VSC_UNKNOWN_0D08(0));
1687 }
1688
1689 static void
emit_vsc_overflow_test(struct tu_cmd_buffer * cmd,struct tu_cs * cs)1690 emit_vsc_overflow_test(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1691 {
1692 const struct tu_tiling_config *tiling = cmd->state.tiling;
1693 const uint32_t used_pipe_count =
1694 tiling->pipe_count.width * tiling->pipe_count.height;
1695
1696 for (int i = 0; i < used_pipe_count; i++) {
1697 tu_cs_emit_pkt7(cs, CP_COND_WRITE5, 8);
1698 tu_cs_emit(cs, CP_COND_WRITE5_0_FUNCTION(WRITE_GE) |
1699 CP_COND_WRITE5_0_WRITE_MEMORY);
1700 tu_cs_emit(cs, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_DRAW_STRM_SIZE_REG(i)));
1701 tu_cs_emit(cs, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
1702 tu_cs_emit(cs, CP_COND_WRITE5_3_REF(cmd->vsc_draw_strm_pitch - VSC_PAD));
1703 tu_cs_emit(cs, CP_COND_WRITE5_4_MASK(~0));
1704 tu_cs_emit_qw(cs, global_iova(cmd, vsc_draw_overflow));
1705 tu_cs_emit(cs, CP_COND_WRITE5_7_WRITE_DATA(cmd->vsc_draw_strm_pitch));
1706
1707 tu_cs_emit_pkt7(cs, CP_COND_WRITE5, 8);
1708 tu_cs_emit(cs, CP_COND_WRITE5_0_FUNCTION(WRITE_GE) |
1709 CP_COND_WRITE5_0_WRITE_MEMORY);
1710 tu_cs_emit(cs, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_PRIM_STRM_SIZE_REG(i)));
1711 tu_cs_emit(cs, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
1712 tu_cs_emit(cs, CP_COND_WRITE5_3_REF(cmd->vsc_prim_strm_pitch - VSC_PAD));
1713 tu_cs_emit(cs, CP_COND_WRITE5_4_MASK(~0));
1714 tu_cs_emit_qw(cs, global_iova(cmd, vsc_prim_overflow));
1715 tu_cs_emit(cs, CP_COND_WRITE5_7_WRITE_DATA(cmd->vsc_prim_strm_pitch));
1716 }
1717
1718 tu_cs_emit_pkt7(cs, CP_WAIT_MEM_WRITES, 0);
1719 }
1720
1721 template <chip CHIP>
1722 static void
tu6_emit_binning_pass(struct tu_cmd_buffer * cmd,struct tu_cs * cs)1723 tu6_emit_binning_pass(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
1724 {
1725 struct tu_physical_device *phys_dev = cmd->device->physical_device;
1726 const struct tu_framebuffer *fb = cmd->state.framebuffer;
1727
1728 /* If this command buffer may be executed multiple times, then
1729 * viewports/scissor states may have been changed by previous executions
1730 * and we need to reset them before executing the binning IB.
1731 */
1732 if (!(cmd->usage_flags & VK_COMMAND_BUFFER_USAGE_ONE_TIME_SUBMIT_BIT) &&
1733 cmd->fdm_bin_patchpoints.size != 0) {
1734 unsigned num_views = MAX2(cmd->state.pass->num_views, 1);
1735 VkExtent2D unscaled_frag_areas[num_views];
1736 for (unsigned i = 0; i < num_views; i++)
1737 unscaled_frag_areas[i] = (VkExtent2D) { 1, 1 };
1738 VkRect2D bin = { { 0, 0 }, { fb->width, fb->height } };
1739 util_dynarray_foreach (&cmd->fdm_bin_patchpoints,
1740 struct tu_fdm_bin_patchpoint, patch) {
1741 tu_cs_emit_pkt7(cs, CP_MEM_WRITE, 2 + patch->size);
1742 tu_cs_emit_qw(cs, patch->iova);
1743 patch->apply(cmd, cs, patch->data, bin, num_views, unscaled_frag_areas);
1744 }
1745
1746 tu_cs_emit_pkt7(cs, CP_WAIT_MEM_WRITES, 0);
1747 tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
1748 }
1749
1750 tu6_emit_window_scissor(cs, 0, 0, fb->width - 1, fb->height - 1);
1751
1752 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
1753 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_BIN_VISIBILITY));
1754
1755 tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
1756 tu_cs_emit(cs, 0x1);
1757
1758 tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
1759 tu_cs_emit(cs, 0x1);
1760
1761 tu_cs_emit_wfi(cs);
1762
1763 tu_cs_emit_regs(cs,
1764 A6XX_VFD_MODE_CNTL(.render_mode = BINNING_PASS));
1765
1766 update_vsc_pipe(cmd, cs, phys_dev->info->num_vsc_pipes);
1767
1768 if (CHIP == A6XX) {
1769 tu_cs_emit_regs(cs,
1770 A6XX_PC_POWER_CNTL(phys_dev->info->a6xx.magic.PC_POWER_CNTL));
1771
1772 tu_cs_emit_regs(cs,
1773 A6XX_VFD_POWER_CNTL(phys_dev->info->a6xx.magic.PC_POWER_CNTL));
1774 }
1775
1776 tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, 1);
1777 tu_cs_emit(cs, UNK_2C);
1778
1779 tu_cs_emit_regs(cs,
1780 A6XX_RB_WINDOW_OFFSET(.x = 0, .y = 0));
1781
1782 tu_cs_emit_regs(cs,
1783 A6XX_SP_TP_WINDOW_OFFSET(.x = 0, .y = 0));
1784
1785 trace_start_binning_ib(&cmd->trace, cs);
1786
1787 /* emit IB to binning drawcmds: */
1788 tu_cs_emit_call(cs, &cmd->draw_cs);
1789
1790 trace_end_binning_ib(&cmd->trace, cs);
1791
1792 /* switching from binning pass to GMEM pass will cause a switch from
1793 * PROGRAM_BINNING to PROGRAM, which invalidates const state (XS_CONST states)
1794 * so make sure these states are re-emitted
1795 * (eventually these states shouldn't exist at all with shader prologue)
1796 * only VS and GS are invalidated, as FS isn't emitted in binning pass,
1797 * and we don't use HW binning when tesselation is used
1798 */
1799 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
1800 tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(0) |
1801 CP_SET_DRAW_STATE__0_DISABLE |
1802 CP_SET_DRAW_STATE__0_GROUP_ID(TU_DRAW_STATE_CONST));
1803 tu_cs_emit(cs, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1804 tu_cs_emit(cs, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1805
1806 tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, 1);
1807 tu_cs_emit(cs, UNK_2D);
1808
1809 /* This flush is probably required because the VSC, which produces the
1810 * visibility stream, is a client of UCHE, whereas the CP needs to read the
1811 * visibility stream (without caching) to do draw skipping. The
1812 * WFI+WAIT_FOR_ME combination guarantees that the binning commands
1813 * submitted are finished before reading the VSC regs (in
1814 * emit_vsc_overflow_test) or the VSC_DATA buffer directly (implicitly as
1815 * part of draws).
1816 */
1817 tu_emit_event_write<CHIP>(cmd, cs, FD_CACHE_CLEAN);
1818
1819 tu_cs_emit_wfi(cs);
1820
1821 tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
1822
1823 emit_vsc_overflow_test(cmd, cs);
1824
1825 tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
1826 tu_cs_emit(cs, 0x0);
1827
1828 tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
1829 tu_cs_emit(cs, 0x0);
1830 }
1831
1832 static struct tu_draw_state
tu_emit_input_attachments(struct tu_cmd_buffer * cmd,const struct tu_subpass * subpass,bool gmem)1833 tu_emit_input_attachments(struct tu_cmd_buffer *cmd,
1834 const struct tu_subpass *subpass,
1835 bool gmem)
1836 {
1837 const struct tu_tiling_config *tiling = cmd->state.tiling;
1838
1839 /* note: we can probably emit input attachments just once for the whole
1840 * renderpass, this would avoid emitting both sysmem/gmem versions
1841 *
1842 * emit two texture descriptors for each input, as a workaround for
1843 * d24s8/d32s8, which can be sampled as both float (depth) and integer (stencil)
1844 * tu_shader lowers uint input attachment loads to use the 2nd descriptor
1845 * in the pair
1846 * TODO: a smarter workaround
1847 */
1848
1849 if (!subpass->input_count)
1850 return (struct tu_draw_state) {};
1851
1852 struct tu_cs_memory texture;
1853 VkResult result = tu_cs_alloc(&cmd->sub_cs, subpass->input_count * 2,
1854 A6XX_TEX_CONST_DWORDS, &texture);
1855 if (result != VK_SUCCESS) {
1856 vk_command_buffer_set_error(&cmd->vk, result);
1857 return (struct tu_draw_state) {};
1858 }
1859
1860 for (unsigned i = 0; i < subpass->input_count * 2; i++) {
1861 uint32_t a = subpass->input_attachments[i / 2].attachment;
1862 if (a == VK_ATTACHMENT_UNUSED)
1863 continue;
1864
1865 const struct tu_image_view *iview = cmd->state.attachments[a];
1866 const struct tu_render_pass_attachment *att =
1867 &cmd->state.pass->attachments[a];
1868 uint32_t *dst = &texture.map[A6XX_TEX_CONST_DWORDS * i];
1869 uint32_t gmem_offset = tu_attachment_gmem_offset(cmd, att, 0);
1870 uint32_t cpp = att->cpp;
1871
1872 memcpy(dst, iview->view.descriptor, A6XX_TEX_CONST_DWORDS * 4);
1873
1874 /* Cube descriptors require a different sampling instruction in shader,
1875 * however we don't know whether image is a cube or not until the start
1876 * of a renderpass. We have to patch the descriptor to make it compatible
1877 * with how it is sampled in shader.
1878 */
1879 enum a6xx_tex_type tex_type =
1880 (enum a6xx_tex_type)((dst[2] & A6XX_TEX_CONST_2_TYPE__MASK) >>
1881 A6XX_TEX_CONST_2_TYPE__SHIFT);
1882 if (tex_type == A6XX_TEX_CUBE) {
1883 dst[2] &= ~A6XX_TEX_CONST_2_TYPE__MASK;
1884 dst[2] |= A6XX_TEX_CONST_2_TYPE(A6XX_TEX_2D);
1885
1886 uint32_t depth = (dst[5] & A6XX_TEX_CONST_5_DEPTH__MASK) >>
1887 A6XX_TEX_CONST_5_DEPTH__SHIFT;
1888 dst[5] &= ~A6XX_TEX_CONST_5_DEPTH__MASK;
1889 dst[5] |= A6XX_TEX_CONST_5_DEPTH(depth * 6);
1890 }
1891
1892 if (i % 2 == 1 && att->format == VK_FORMAT_D24_UNORM_S8_UINT) {
1893 /* note this works because spec says fb and input attachments
1894 * must use identity swizzle
1895 *
1896 * Also we clear swap to WZYX. This is because the view might have
1897 * picked XYZW to work better with border colors.
1898 */
1899 dst[0] &= ~(A6XX_TEX_CONST_0_FMT__MASK |
1900 A6XX_TEX_CONST_0_SWAP__MASK |
1901 A6XX_TEX_CONST_0_SWIZ_X__MASK | A6XX_TEX_CONST_0_SWIZ_Y__MASK |
1902 A6XX_TEX_CONST_0_SWIZ_Z__MASK | A6XX_TEX_CONST_0_SWIZ_W__MASK);
1903 if (!cmd->device->physical_device->info->a6xx.has_z24uint_s8uint) {
1904 dst[0] |= A6XX_TEX_CONST_0_FMT(FMT6_8_8_8_8_UINT) |
1905 A6XX_TEX_CONST_0_SWIZ_X(A6XX_TEX_W) |
1906 A6XX_TEX_CONST_0_SWIZ_Y(A6XX_TEX_ZERO) |
1907 A6XX_TEX_CONST_0_SWIZ_Z(A6XX_TEX_ZERO) |
1908 A6XX_TEX_CONST_0_SWIZ_W(A6XX_TEX_ONE);
1909 } else {
1910 dst[0] |= A6XX_TEX_CONST_0_FMT(FMT6_Z24_UINT_S8_UINT) |
1911 A6XX_TEX_CONST_0_SWIZ_X(A6XX_TEX_Y) |
1912 A6XX_TEX_CONST_0_SWIZ_Y(A6XX_TEX_ZERO) |
1913 A6XX_TEX_CONST_0_SWIZ_Z(A6XX_TEX_ZERO) |
1914 A6XX_TEX_CONST_0_SWIZ_W(A6XX_TEX_ONE);
1915 }
1916 }
1917
1918 if (i % 2 == 1 && att->format == VK_FORMAT_D32_SFLOAT_S8_UINT) {
1919 dst[0] &= ~A6XX_TEX_CONST_0_FMT__MASK;
1920 dst[0] |= A6XX_TEX_CONST_0_FMT(FMT6_8_UINT);
1921 dst[2] &= ~(A6XX_TEX_CONST_2_PITCHALIGN__MASK | A6XX_TEX_CONST_2_PITCH__MASK);
1922 dst[2] |= A6XX_TEX_CONST_2_PITCH(iview->stencil_pitch);
1923 dst[3] = 0;
1924 dst[4] = iview->stencil_base_addr;
1925 dst[5] = (dst[5] & 0xffff) | iview->stencil_base_addr >> 32;
1926
1927 cpp = att->samples;
1928 gmem_offset = att->gmem_offset_stencil[cmd->state.gmem_layout];
1929 }
1930
1931 if (!gmem || !subpass->input_attachments[i / 2].patch_input_gmem)
1932 continue;
1933
1934 /* patched for gmem */
1935 dst[0] &= ~A6XX_TEX_CONST_0_TILE_MODE__MASK;
1936 if (!iview->view.is_mutable)
1937 dst[0] &= ~A6XX_TEX_CONST_0_SWAP__MASK;
1938 dst[0] |= A6XX_TEX_CONST_0_TILE_MODE(TILE6_2);
1939 dst[2] =
1940 A6XX_TEX_CONST_2_TYPE(A6XX_TEX_2D) |
1941 A6XX_TEX_CONST_2_PITCH(tiling->tile0.width * cpp);
1942 /* Note: it seems the HW implicitly calculates the array pitch with the
1943 * GMEM tiling, so we don't need to specify the pitch ourselves.
1944 */
1945 dst[3] = 0;
1946 dst[4] = cmd->device->physical_device->gmem_base + gmem_offset;
1947 dst[5] &= A6XX_TEX_CONST_5_DEPTH__MASK;
1948 for (unsigned i = 6; i < A6XX_TEX_CONST_DWORDS; i++)
1949 dst[i] = 0;
1950 }
1951
1952 struct tu_cs cs;
1953 struct tu_draw_state ds = tu_cs_draw_state(&cmd->sub_cs, &cs, 9);
1954
1955 tu_cs_emit_pkt7(&cs, CP_LOAD_STATE6_FRAG, 3);
1956 tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(0) |
1957 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
1958 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
1959 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_FS_TEX) |
1960 CP_LOAD_STATE6_0_NUM_UNIT(subpass->input_count * 2));
1961 tu_cs_emit_qw(&cs, texture.iova);
1962
1963 tu_cs_emit_regs(&cs, A6XX_SP_FS_TEX_CONST(.qword = texture.iova));
1964
1965 tu_cs_emit_regs(&cs, A6XX_SP_FS_TEX_COUNT(subpass->input_count * 2));
1966
1967 assert(cs.cur == cs.end); /* validate draw state size */
1968
1969 return ds;
1970 }
1971
1972 static void
tu_set_input_attachments(struct tu_cmd_buffer * cmd,const struct tu_subpass * subpass)1973 tu_set_input_attachments(struct tu_cmd_buffer *cmd, const struct tu_subpass *subpass)
1974 {
1975 struct tu_cs *cs = &cmd->draw_cs;
1976
1977 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 6);
1978 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_INPUT_ATTACHMENTS_GMEM,
1979 tu_emit_input_attachments(cmd, subpass, true));
1980 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_INPUT_ATTACHMENTS_SYSMEM,
1981 tu_emit_input_attachments(cmd, subpass, false));
1982 }
1983
1984 static void
tu_trace_start_render_pass(struct tu_cmd_buffer * cmd)1985 tu_trace_start_render_pass(struct tu_cmd_buffer *cmd)
1986 {
1987 if (!u_trace_enabled(&cmd->device->trace_context))
1988 return;
1989
1990 uint32_t load_cpp = 0;
1991 uint32_t store_cpp = 0;
1992 uint32_t clear_cpp = 0;
1993 bool has_depth = false;
1994 char ubwc[MAX_RTS + 3];
1995 for (uint32_t i = 0; i < cmd->state.pass->attachment_count; i++) {
1996 const struct tu_render_pass_attachment *attachment =
1997 &cmd->state.pass->attachments[i];
1998 if (attachment->load) {
1999 load_cpp += attachment->cpp;
2000 }
2001
2002 if (attachment->store) {
2003 store_cpp += attachment->cpp;
2004 }
2005
2006 if (attachment->clear_mask) {
2007 clear_cpp += attachment->cpp;
2008 }
2009
2010 has_depth |= vk_format_has_depth(attachment->format);
2011 }
2012
2013 uint8_t ubwc_len = 0;
2014 const struct tu_subpass *subpass = &cmd->state.pass->subpasses[0];
2015 for (uint32_t i = 0; i < subpass->color_count; i++) {
2016 uint32_t att = subpass->color_attachments[i].attachment;
2017 ubwc[ubwc_len++] = att == VK_ATTACHMENT_UNUSED ? '-'
2018 : cmd->state.attachments[att]->view.ubwc_enabled
2019 ? 'y'
2020 : 'n';
2021 }
2022 if (subpass->depth_used) {
2023 ubwc[ubwc_len++] = '|';
2024 ubwc[ubwc_len++] =
2025 cmd->state.attachments[subpass->depth_stencil_attachment.attachment]
2026 ->view.ubwc_enabled
2027 ? 'y'
2028 : 'n';
2029 }
2030 ubwc[ubwc_len] = '\0';
2031
2032 uint32_t max_samples = 0;
2033 for (uint32_t i = 0; i < cmd->state.pass->subpass_count; i++) {
2034 max_samples = MAX2(max_samples, cmd->state.pass->subpasses[i].samples);
2035 }
2036
2037 trace_start_render_pass(&cmd->trace, &cmd->cs, cmd->state.framebuffer,
2038 cmd->state.tiling, max_samples, clear_cpp,
2039 load_cpp, store_cpp, has_depth, ubwc);
2040 }
2041
2042 template <chip CHIP>
2043 static void
tu_trace_end_render_pass(struct tu_cmd_buffer * cmd,bool gmem)2044 tu_trace_end_render_pass(struct tu_cmd_buffer *cmd, bool gmem)
2045 {
2046 if (!u_trace_enabled(&cmd->device->trace_context))
2047 return;
2048
2049 uint32_t avg_per_sample_bandwidth =
2050 cmd->state.rp.drawcall_bandwidth_per_sample_sum /
2051 MAX2(cmd->state.rp.drawcall_count, 1);
2052
2053 struct u_trace_address addr = {};
2054 if (cmd->state.lrz.image_view) {
2055 struct tu_image *image = cmd->state.lrz.image_view->image;
2056 addr.bo = image->bo;
2057 addr.offset = (image->iova - image->bo->iova) +
2058 image->lrz_layout.lrz_fc_offset +
2059 offsetof(fd_lrzfc_layout<CHIP>, dir_track);
2060 }
2061
2062 trace_end_render_pass(&cmd->trace, &cmd->cs, gmem,
2063 cmd->state.rp.drawcall_count,
2064 avg_per_sample_bandwidth, cmd->state.lrz.valid,
2065 cmd->state.rp.lrz_disable_reason,
2066 cmd->state.rp.lrz_disabled_at_draw, addr);
2067 }
2068
2069 static void
tu_emit_renderpass_begin(struct tu_cmd_buffer * cmd)2070 tu_emit_renderpass_begin(struct tu_cmd_buffer *cmd)
2071 {
2072 /* We need to re-emit any draw states that are patched in order for them to
2073 * be correctly added to the per-renderpass patchpoint list, even if they
2074 * are the same as before.
2075 */
2076 if (cmd->state.pass->has_fdm)
2077 cmd->state.dirty |= TU_CMD_DIRTY_FDM;
2078
2079 /* We need to re-emit MSAA at the beginning of every renderpass because it
2080 * isn't part of a draw state that gets automatically re-emitted.
2081 */
2082 BITSET_SET(cmd->vk.dynamic_graphics_state.dirty,
2083 MESA_VK_DYNAMIC_MS_RASTERIZATION_SAMPLES);
2084 /* PC_PRIMITIVE_CNTL_0 isn't a part of a draw state and may be changed
2085 * by blits.
2086 */
2087 BITSET_SET(cmd->vk.dynamic_graphics_state.dirty,
2088 MESA_VK_DYNAMIC_IA_PRIMITIVE_RESTART_ENABLE);
2089 }
2090
2091 template <chip CHIP>
2092 static void
tu6_sysmem_render_begin(struct tu_cmd_buffer * cmd,struct tu_cs * cs,struct tu_renderpass_result * autotune_result)2093 tu6_sysmem_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
2094 struct tu_renderpass_result *autotune_result)
2095 {
2096 const struct tu_framebuffer *fb = cmd->state.framebuffer;
2097
2098 tu_lrz_sysmem_begin<CHIP>(cmd, cs);
2099
2100 assert(fb->width > 0 && fb->height > 0);
2101 tu6_emit_window_scissor(cs, 0, 0, fb->width - 1, fb->height - 1);
2102 tu6_emit_window_offset<CHIP>(cs, 0, 0);
2103
2104 tu6_emit_bin_size<CHIP>(cs, 0, 0, {
2105 .render_mode = RENDERING_PASS,
2106 .force_lrz_write_dis =
2107 !cmd->device->physical_device->info->a6xx.has_lrz_feedback,
2108 .buffers_location = BUFFERS_IN_SYSMEM,
2109 .lrz_feedback_zmode_mask =
2110 cmd->device->physical_device->info->a6xx.has_lrz_feedback
2111 ? LRZ_FEEDBACK_EARLY_Z_OR_EARLY_LRZ_LATE_Z
2112 : LRZ_FEEDBACK_NONE,
2113 });
2114
2115 if (CHIP == A7XX) {
2116 tu_cs_emit_regs(cs,
2117 A7XX_RB_UNKNOWN_8812(0x3ff)); // all buffers in sysmem
2118 tu_cs_emit_regs(cs,
2119 A7XX_RB_UNKNOWN_8E06(cmd->device->physical_device->info->a6xx.magic.RB_UNKNOWN_8E06));
2120
2121 tu_cs_emit_regs(cs, A7XX_GRAS_UNKNOWN_8007(0x0));
2122
2123 tu_cs_emit_regs(cs, A6XX_GRAS_UNKNOWN_8110(0x2));
2124 tu_cs_emit_regs(cs, A7XX_RB_UNKNOWN_8E09(0x4));
2125
2126 tu_cs_emit_regs(cs, A7XX_RB_BLIT_CLEAR_MODE(.clear_mode = CLEAR_MODE_SYSMEM));
2127 }
2128
2129 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
2130 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_DIRECT_RENDER));
2131
2132 /* A7XX TODO: blob doesn't use CP_SKIP_IB2_ENABLE_* */
2133 tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
2134 tu_cs_emit(cs, 0x0);
2135
2136 tu_emit_cache_flush_ccu<CHIP>(cmd, cs, TU_CMD_CCU_SYSMEM);
2137
2138 tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
2139 tu_cs_emit(cs, 0x1);
2140
2141 tu_cs_emit_pkt7(cs, CP_SET_MODE, 1);
2142 tu_cs_emit(cs, 0x0);
2143
2144 tu_autotune_begin_renderpass<CHIP>(cmd, cs, autotune_result);
2145
2146 tu_cs_sanity_check(cs);
2147 }
2148
2149 template <chip CHIP>
2150 static void
tu6_sysmem_render_end(struct tu_cmd_buffer * cmd,struct tu_cs * cs,struct tu_renderpass_result * autotune_result)2151 tu6_sysmem_render_end(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
2152 struct tu_renderpass_result *autotune_result)
2153 {
2154 tu_autotune_end_renderpass<CHIP>(cmd, cs, autotune_result);
2155
2156 /* Do any resolves of the last subpass. These are handled in the
2157 * tile_store_cs in the gmem path.
2158 */
2159 tu6_emit_sysmem_resolves<CHIP>(cmd, cs, cmd->state.subpass);
2160
2161 tu_cs_emit_call(cs, &cmd->draw_epilogue_cs);
2162
2163 tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
2164 tu_cs_emit(cs, 0x0);
2165
2166 tu_lrz_sysmem_end<CHIP>(cmd, cs);
2167
2168 tu_cs_sanity_check(cs);
2169 }
2170
2171 template <chip CHIP>
2172 static void
tu6_tile_render_begin(struct tu_cmd_buffer * cmd,struct tu_cs * cs,struct tu_renderpass_result * autotune_result)2173 tu6_tile_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
2174 struct tu_renderpass_result *autotune_result)
2175 {
2176 struct tu_physical_device *phys_dev = cmd->device->physical_device;
2177 const struct tu_tiling_config *tiling = cmd->state.tiling;
2178 tu_lrz_tiling_begin<CHIP>(cmd, cs);
2179
2180 tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
2181 tu_cs_emit(cs, 0x0);
2182
2183 if (CHIP >= A7XX) {
2184 tu7_emit_tile_render_begin_regs(cs);
2185 }
2186
2187 tu_emit_cache_flush_ccu<CHIP>(cmd, cs, TU_CMD_CCU_GMEM);
2188
2189 if (use_hw_binning(cmd)) {
2190 if (!cmd->vsc_initialized) {
2191 tu6_lazy_init_vsc(cmd);
2192 }
2193
2194 /* We always emit VSC before each renderpass, because due to
2195 * skipsaverestore the underlying VSC registers may have become
2196 * invalid. Normally we'd need to WFI before setting these non-context
2197 * registers, but we should be safe because we're only setting it to the
2198 * same value it had before.
2199 *
2200 * TODO: On a6xx, we have to emit this per-bin or make the amble include
2201 * these registers, because CP_SET_BIN_DATA5_OFFSET will use the
2202 * register instead of the pseudo register and its value won't survive
2203 * across preemptions. The blob seems to take the second approach and
2204 * emits the preamble lazily.
2205 */
2206 tu_emit_vsc<CHIP>(cmd, cs);
2207
2208 tu6_emit_bin_size<CHIP>(cs, tiling->tile0.width, tiling->tile0.height,
2209 {
2210 .render_mode = BINNING_PASS,
2211 .buffers_location = BUFFERS_IN_GMEM,
2212 .lrz_feedback_zmode_mask =
2213 phys_dev->info->a6xx.has_lrz_feedback
2214 ? LRZ_FEEDBACK_EARLY_LRZ_LATE_Z
2215 : LRZ_FEEDBACK_NONE
2216 });
2217
2218 tu6_emit_render_cntl<CHIP>(cmd, cmd->state.subpass, cs, true);
2219
2220 tu6_emit_binning_pass<CHIP>(cmd, cs);
2221
2222 if (CHIP == A6XX) {
2223 tu_cs_emit_regs(cs,
2224 A6XX_PC_POWER_CNTL(phys_dev->info->a6xx.magic.PC_POWER_CNTL));
2225
2226 tu_cs_emit_regs(cs,
2227 A6XX_VFD_POWER_CNTL(phys_dev->info->a6xx.magic.PC_POWER_CNTL));
2228 }
2229
2230 tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
2231 tu_cs_emit(cs, 0x1);
2232 tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_LOCAL, 1);
2233 tu_cs_emit(cs, 0x1);
2234 } else {
2235 if (tiling->binning_possible) {
2236 /* Mark all tiles as visible for tu6_emit_cond_for_load_stores(), since
2237 * the actual binner didn't run.
2238 */
2239 int pipe_count = tiling->pipe_count.width * tiling->pipe_count.height;
2240 tu_cs_emit_pkt4(cs, REG_A6XX_VSC_STATE_REG(0), pipe_count);
2241 for (int i = 0; i < pipe_count; i++)
2242 tu_cs_emit(cs, ~0);
2243 }
2244 }
2245
2246 if (tiling->binning_possible) {
2247 /* Upload state regs to memory to be restored on skipsaverestore
2248 * preemption.
2249 */
2250 tu_cs_emit_pkt7(cs, CP_REG_TO_MEM, 3);
2251 tu_cs_emit(cs, CP_REG_TO_MEM_0_REG(REG_A6XX_VSC_STATE_REG(0)) |
2252 CP_REG_TO_MEM_0_CNT(32));
2253 tu_cs_emit_qw(cs, global_iova(cmd, vsc_state));
2254 }
2255
2256 tu_autotune_begin_renderpass<CHIP>(cmd, cs, autotune_result);
2257
2258 tu_cs_sanity_check(cs);
2259 }
2260
2261 template <chip CHIP>
2262 static void
tu6_render_tile(struct tu_cmd_buffer * cmd,struct tu_cs * cs,uint32_t tx,uint32_t ty,uint32_t pipe,uint32_t slot,const struct tu_image_view * fdm)2263 tu6_render_tile(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
2264 uint32_t tx, uint32_t ty, uint32_t pipe, uint32_t slot,
2265 const struct tu_image_view *fdm)
2266 {
2267 tu6_emit_tile_select<CHIP>(cmd, &cmd->cs, tx, ty, pipe, slot, fdm);
2268 tu_lrz_before_tile<CHIP>(cmd, &cmd->cs);
2269
2270 trace_start_draw_ib_gmem(&cmd->trace, &cmd->cs);
2271
2272 /* Primitives that passed all tests are still counted in in each
2273 * tile even with HW binning beforehand. Do not permit it.
2274 */
2275 if (cmd->state.prim_generated_query_running_before_rp)
2276 tu_emit_event_write<CHIP>(cmd, cs, FD_STOP_PRIMITIVE_CTRS);
2277
2278 tu_cs_emit_call(cs, &cmd->draw_cs);
2279
2280 if (cmd->state.prim_generated_query_running_before_rp)
2281 tu_emit_event_write<CHIP>(cmd, cs, FD_START_PRIMITIVE_CTRS);
2282
2283 if (use_hw_binning(cmd)) {
2284 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
2285 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_BIN_END_OF_DRAWS) |
2286 A6XX_CP_SET_MARKER_0_USES_GMEM);
2287 }
2288
2289 /* Predicate is changed in draw_cs so we have to re-emit it */
2290 if (cmd->state.rp.draw_cs_writes_to_cond_pred)
2291 tu6_emit_cond_for_load_stores(cmd, cs, pipe, slot, false);
2292
2293 tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
2294 tu_cs_emit(cs, 0x0);
2295
2296 tu_cs_emit_call(cs, &cmd->tile_store_cs);
2297
2298 tu_clone_trace_range(cmd, cs, cmd->trace_renderpass_start,
2299 cmd->trace_renderpass_end);
2300
2301 tu_cs_emit_wfi(cs);
2302
2303 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
2304 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_BIN_RENDER_END));
2305
2306 tu_cs_sanity_check(cs);
2307
2308 trace_end_draw_ib_gmem(&cmd->trace, &cmd->cs);
2309 }
2310
2311 template <chip CHIP>
2312 static void
tu6_tile_render_end(struct tu_cmd_buffer * cmd,struct tu_cs * cs,struct tu_renderpass_result * autotune_result)2313 tu6_tile_render_end(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
2314 struct tu_renderpass_result *autotune_result)
2315 {
2316 tu_autotune_end_renderpass<CHIP>(cmd, cs, autotune_result);
2317
2318 tu_cs_emit_call(cs, &cmd->draw_epilogue_cs);
2319
2320 tu_lrz_tiling_end<CHIP>(cmd, cs);
2321
2322 tu_emit_event_write<CHIP>(cmd, cs, FD_CCU_CLEAN_BLIT_CACHE);
2323
2324 tu_cs_sanity_check(cs);
2325 }
2326
2327 template <chip CHIP>
2328 static void
tu_cmd_render_tiles(struct tu_cmd_buffer * cmd,struct tu_renderpass_result * autotune_result)2329 tu_cmd_render_tiles(struct tu_cmd_buffer *cmd,
2330 struct tu_renderpass_result *autotune_result)
2331 {
2332 const struct tu_tiling_config *tiling = cmd->state.tiling;
2333 const struct tu_image_view *fdm = NULL;
2334
2335 if (cmd->state.pass->fragment_density_map.attachment != VK_ATTACHMENT_UNUSED) {
2336 fdm = cmd->state.attachments[cmd->state.pass->fragment_density_map.attachment];
2337 }
2338
2339 /* Create gmem stores now (at EndRenderPass time)) because they needed to
2340 * know whether to allow their conditional execution, which was tied to a
2341 * state that was known only at the end of the renderpass. They will be
2342 * called from tu6_render_tile().
2343 */
2344 tu_cs_begin(&cmd->tile_store_cs);
2345 tu6_emit_tile_store<CHIP>(cmd, &cmd->tile_store_cs);
2346 tu_cs_end(&cmd->tile_store_cs);
2347
2348 cmd->trace_renderpass_end = u_trace_end_iterator(&cmd->trace);
2349
2350 tu6_tile_render_begin<CHIP>(cmd, &cmd->cs, autotune_result);
2351
2352 /* Note: we reverse the order of walking the pipes and tiles on every
2353 * other row, to improve texture cache locality compared to raster order.
2354 */
2355 for (uint32_t py = 0; py < tiling->pipe_count.height; py++) {
2356 uint32_t pipe_row = py * tiling->pipe_count.width;
2357 for (uint32_t pipe_row_i = 0; pipe_row_i < tiling->pipe_count.width; pipe_row_i++) {
2358 uint32_t px;
2359 if (py & 1)
2360 px = tiling->pipe_count.width - 1 - pipe_row_i;
2361 else
2362 px = pipe_row_i;
2363 uint32_t pipe = pipe_row + px;
2364 uint32_t tx1 = px * tiling->pipe0.width;
2365 uint32_t ty1 = py * tiling->pipe0.height;
2366 uint32_t tx2 = MIN2(tx1 + tiling->pipe0.width, tiling->tile_count.width);
2367 uint32_t ty2 = MIN2(ty1 + tiling->pipe0.height, tiling->tile_count.height);
2368 uint32_t tile_row_stride = tx2 - tx1;
2369 uint32_t slot_row = 0;
2370 for (uint32_t ty = ty1; ty < ty2; ty++) {
2371 for (uint32_t tile_row_i = 0; tile_row_i < tile_row_stride; tile_row_i++) {
2372 uint32_t tx;
2373 if (ty & 1)
2374 tx = tile_row_stride - 1 - tile_row_i;
2375 else
2376 tx = tile_row_i;
2377 uint32_t slot = slot_row + tx;
2378 tu6_render_tile<CHIP>(cmd, &cmd->cs, tx1 + tx, ty, pipe, slot, fdm);
2379 }
2380 slot_row += tile_row_stride;
2381 }
2382 }
2383 }
2384
2385 tu6_tile_render_end<CHIP>(cmd, &cmd->cs, autotune_result);
2386
2387 tu_trace_end_render_pass<CHIP>(cmd, true);
2388
2389 /* We have trashed the dynamically-emitted viewport, scissor, and FS params
2390 * via the patchpoints, so we need to re-emit them if they are reused for a
2391 * later render pass.
2392 */
2393 if (cmd->state.pass->has_fdm)
2394 cmd->state.dirty |= TU_CMD_DIRTY_FDM;
2395
2396 /* tu6_render_tile has cloned these tracepoints for each tile */
2397 if (!u_trace_iterator_equal(cmd->trace_renderpass_start, cmd->trace_renderpass_end))
2398 u_trace_disable_event_range(cmd->trace_renderpass_start,
2399 cmd->trace_renderpass_end);
2400
2401 /* Reset the gmem store CS entry lists so that the next render pass
2402 * does its own stores.
2403 */
2404 tu_cs_discard_entries(&cmd->tile_store_cs);
2405 }
2406
2407 template <chip CHIP>
2408 static void
tu_cmd_render_sysmem(struct tu_cmd_buffer * cmd,struct tu_renderpass_result * autotune_result)2409 tu_cmd_render_sysmem(struct tu_cmd_buffer *cmd,
2410 struct tu_renderpass_result *autotune_result)
2411 {
2412 cmd->trace_renderpass_end = u_trace_end_iterator(&cmd->trace);
2413
2414 tu6_sysmem_render_begin<CHIP>(cmd, &cmd->cs, autotune_result);
2415
2416 trace_start_draw_ib_sysmem(&cmd->trace, &cmd->cs);
2417
2418 tu_cs_emit_call(&cmd->cs, &cmd->draw_cs);
2419
2420 trace_end_draw_ib_sysmem(&cmd->trace, &cmd->cs);
2421
2422 tu6_sysmem_render_end<CHIP>(cmd, &cmd->cs, autotune_result);
2423
2424 tu_trace_end_render_pass<CHIP>(cmd, false);
2425 }
2426
2427 template <chip CHIP>
2428 void
tu_cmd_render(struct tu_cmd_buffer * cmd_buffer)2429 tu_cmd_render(struct tu_cmd_buffer *cmd_buffer)
2430 {
2431 if (cmd_buffer->state.rp.has_tess)
2432 tu6_lazy_emit_tessfactor_addr<CHIP>(cmd_buffer);
2433
2434 struct tu_renderpass_result *autotune_result = NULL;
2435 if (use_sysmem_rendering(cmd_buffer, &autotune_result))
2436 tu_cmd_render_sysmem<CHIP>(cmd_buffer, autotune_result);
2437 else
2438 tu_cmd_render_tiles<CHIP>(cmd_buffer, autotune_result);
2439
2440 /* Outside of renderpasses we assume all draw states are disabled. We do
2441 * this outside the draw CS for the normal case where 3d gmem stores aren't
2442 * used.
2443 */
2444 tu_disable_draw_states(cmd_buffer, &cmd_buffer->cs);
2445
2446 }
2447
tu_reset_render_pass(struct tu_cmd_buffer * cmd_buffer)2448 static void tu_reset_render_pass(struct tu_cmd_buffer *cmd_buffer)
2449 {
2450 /* discard draw_cs and draw_epilogue_cs entries now that the tiles are
2451 rendered */
2452 tu_cs_discard_entries(&cmd_buffer->draw_cs);
2453 tu_cs_begin(&cmd_buffer->draw_cs);
2454 tu_cs_discard_entries(&cmd_buffer->draw_epilogue_cs);
2455 tu_cs_begin(&cmd_buffer->draw_epilogue_cs);
2456
2457 cmd_buffer->state.pass = NULL;
2458 cmd_buffer->state.subpass = NULL;
2459 cmd_buffer->state.framebuffer = NULL;
2460 cmd_buffer->state.attachments = NULL;
2461 cmd_buffer->state.clear_values = NULL;
2462 cmd_buffer->state.gmem_layout = TU_GMEM_LAYOUT_COUNT; /* invalid value to prevent looking up gmem offsets */
2463 memset(&cmd_buffer->state.rp, 0, sizeof(cmd_buffer->state.rp));
2464
2465 /* LRZ is not valid next time we use it */
2466 cmd_buffer->state.lrz.valid = false;
2467 cmd_buffer->state.dirty |= TU_CMD_DIRTY_LRZ;
2468
2469 /* Patchpoints have been executed */
2470 util_dynarray_clear(&cmd_buffer->fdm_bin_patchpoints);
2471 ralloc_free(cmd_buffer->patchpoints_ctx);
2472 cmd_buffer->patchpoints_ctx = NULL;
2473 }
2474
2475 static VkResult
tu_create_cmd_buffer(struct vk_command_pool * pool,VkCommandBufferLevel level,struct vk_command_buffer ** cmd_buffer_out)2476 tu_create_cmd_buffer(struct vk_command_pool *pool,
2477 VkCommandBufferLevel level,
2478 struct vk_command_buffer **cmd_buffer_out)
2479 {
2480 struct tu_device *device =
2481 container_of(pool->base.device, struct tu_device, vk);
2482 struct tu_cmd_buffer *cmd_buffer;
2483
2484 cmd_buffer = (struct tu_cmd_buffer *) vk_zalloc2(
2485 &device->vk.alloc, NULL, sizeof(*cmd_buffer), 8,
2486 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2487
2488 if (cmd_buffer == NULL)
2489 return vk_error(device, VK_ERROR_OUT_OF_HOST_MEMORY);
2490
2491 VkResult result = vk_command_buffer_init(pool, &cmd_buffer->vk,
2492 &tu_cmd_buffer_ops, level);
2493 if (result != VK_SUCCESS) {
2494 vk_free2(&device->vk.alloc, NULL, cmd_buffer);
2495 return result;
2496 }
2497
2498 cmd_buffer->device = device;
2499
2500 u_trace_init(&cmd_buffer->trace, &device->trace_context);
2501 list_inithead(&cmd_buffer->renderpass_autotune_results);
2502
2503 tu_cs_init(&cmd_buffer->cs, device, TU_CS_MODE_GROW, 4096, "cmd cs");
2504 tu_cs_init(&cmd_buffer->draw_cs, device, TU_CS_MODE_GROW, 4096, "draw cs");
2505 tu_cs_init(&cmd_buffer->tile_store_cs, device, TU_CS_MODE_GROW, 2048, "tile store cs");
2506 tu_cs_init(&cmd_buffer->draw_epilogue_cs, device, TU_CS_MODE_GROW, 4096, "draw epilogue cs");
2507 tu_cs_init(&cmd_buffer->sub_cs, device, TU_CS_MODE_SUB_STREAM, 2048, "draw sub cs");
2508 tu_cs_init(&cmd_buffer->pre_chain.draw_cs, device, TU_CS_MODE_GROW, 4096, "prechain draw cs");
2509 tu_cs_init(&cmd_buffer->pre_chain.draw_epilogue_cs, device, TU_CS_MODE_GROW, 4096, "prechain draw epiligoue cs");
2510
2511 for (unsigned i = 0; i < MAX_BIND_POINTS; i++)
2512 cmd_buffer->descriptors[i].push_set.base.type = VK_OBJECT_TYPE_DESCRIPTOR_SET;
2513
2514 *cmd_buffer_out = &cmd_buffer->vk;
2515
2516 return VK_SUCCESS;
2517 }
2518
2519 static void
tu_cmd_buffer_destroy(struct vk_command_buffer * vk_cmd_buffer)2520 tu_cmd_buffer_destroy(struct vk_command_buffer *vk_cmd_buffer)
2521 {
2522 struct tu_cmd_buffer *cmd_buffer =
2523 container_of(vk_cmd_buffer, struct tu_cmd_buffer, vk);
2524
2525 tu_cs_finish(&cmd_buffer->cs);
2526 tu_cs_finish(&cmd_buffer->draw_cs);
2527 tu_cs_finish(&cmd_buffer->tile_store_cs);
2528 tu_cs_finish(&cmd_buffer->draw_epilogue_cs);
2529 tu_cs_finish(&cmd_buffer->sub_cs);
2530 tu_cs_finish(&cmd_buffer->pre_chain.draw_cs);
2531 tu_cs_finish(&cmd_buffer->pre_chain.draw_epilogue_cs);
2532
2533 u_trace_fini(&cmd_buffer->trace);
2534
2535 tu_autotune_free_results(cmd_buffer->device, &cmd_buffer->renderpass_autotune_results);
2536
2537 for (unsigned i = 0; i < MAX_BIND_POINTS; i++) {
2538 if (cmd_buffer->descriptors[i].push_set.layout)
2539 vk_descriptor_set_layout_unref(&cmd_buffer->device->vk,
2540 &cmd_buffer->descriptors[i].push_set.layout->vk);
2541 vk_free(&cmd_buffer->device->vk.alloc,
2542 cmd_buffer->descriptors[i].push_set.mapped_ptr);
2543 }
2544
2545 ralloc_free(cmd_buffer->patchpoints_ctx);
2546 ralloc_free(cmd_buffer->pre_chain.patchpoints_ctx);
2547 util_dynarray_fini(&cmd_buffer->fdm_bin_patchpoints);
2548 util_dynarray_fini(&cmd_buffer->pre_chain.fdm_bin_patchpoints);
2549
2550 vk_command_buffer_finish(&cmd_buffer->vk);
2551 vk_free2(&cmd_buffer->device->vk.alloc, &cmd_buffer->vk.pool->alloc,
2552 cmd_buffer);
2553 }
2554
2555 static void
tu_reset_cmd_buffer(struct vk_command_buffer * vk_cmd_buffer,UNUSED VkCommandBufferResetFlags flags)2556 tu_reset_cmd_buffer(struct vk_command_buffer *vk_cmd_buffer,
2557 UNUSED VkCommandBufferResetFlags flags)
2558 {
2559 struct tu_cmd_buffer *cmd_buffer =
2560 container_of(vk_cmd_buffer, struct tu_cmd_buffer, vk);
2561
2562 vk_command_buffer_reset(&cmd_buffer->vk);
2563
2564 tu_cs_reset(&cmd_buffer->cs);
2565 tu_cs_reset(&cmd_buffer->draw_cs);
2566 tu_cs_reset(&cmd_buffer->tile_store_cs);
2567 tu_cs_reset(&cmd_buffer->draw_epilogue_cs);
2568 tu_cs_reset(&cmd_buffer->sub_cs);
2569 tu_cs_reset(&cmd_buffer->pre_chain.draw_cs);
2570 tu_cs_reset(&cmd_buffer->pre_chain.draw_epilogue_cs);
2571
2572 tu_autotune_free_results(cmd_buffer->device, &cmd_buffer->renderpass_autotune_results);
2573
2574 for (unsigned i = 0; i < MAX_BIND_POINTS; i++) {
2575 memset(&cmd_buffer->descriptors[i].sets, 0, sizeof(cmd_buffer->descriptors[i].sets));
2576 if (cmd_buffer->descriptors[i].push_set.layout) {
2577 vk_descriptor_set_layout_unref(&cmd_buffer->device->vk,
2578 &cmd_buffer->descriptors[i].push_set.layout->vk);
2579 }
2580 vk_free(&cmd_buffer->device->vk.alloc, cmd_buffer->descriptors[i].push_set.mapped_ptr);
2581 memset(&cmd_buffer->descriptors[i].push_set, 0, sizeof(cmd_buffer->descriptors[i].push_set));
2582 cmd_buffer->descriptors[i].push_set.base.type = VK_OBJECT_TYPE_DESCRIPTOR_SET;
2583 cmd_buffer->descriptors[i].max_sets_bound = 0;
2584 cmd_buffer->descriptors[i].max_dynamic_offset_size = 0;
2585 }
2586
2587 u_trace_fini(&cmd_buffer->trace);
2588 u_trace_init(&cmd_buffer->trace, &cmd_buffer->device->trace_context);
2589
2590 cmd_buffer->state.max_vbs_bound = 0;
2591
2592 cmd_buffer->vsc_initialized = false;
2593 cmd_buffer->prev_fsr_is_null = false;
2594
2595 ralloc_free(cmd_buffer->patchpoints_ctx);
2596 ralloc_free(cmd_buffer->pre_chain.patchpoints_ctx);
2597 cmd_buffer->patchpoints_ctx = NULL;
2598 cmd_buffer->pre_chain.patchpoints_ctx = NULL;
2599 util_dynarray_clear(&cmd_buffer->fdm_bin_patchpoints);
2600 util_dynarray_clear(&cmd_buffer->pre_chain.fdm_bin_patchpoints);
2601 }
2602
2603 const struct vk_command_buffer_ops tu_cmd_buffer_ops = {
2604 .create = tu_create_cmd_buffer,
2605 .reset = tu_reset_cmd_buffer,
2606 .destroy = tu_cmd_buffer_destroy,
2607 };
2608
2609 /* Initialize the cache, assuming all necessary flushes have happened but *not*
2610 * invalidations.
2611 */
2612 static void
tu_cache_init(struct tu_cache_state * cache)2613 tu_cache_init(struct tu_cache_state *cache)
2614 {
2615 cache->flush_bits = 0;
2616 cache->pending_flush_bits = TU_CMD_FLAG_ALL_INVALIDATE;
2617 }
2618
2619 /* Unlike the public entrypoint, this doesn't handle cache tracking, and
2620 * tracking the CCU state. It's used for the driver to insert its own command
2621 * buffer in the middle of a submit.
2622 */
2623 VkResult
tu_cmd_buffer_begin(struct tu_cmd_buffer * cmd_buffer,const VkCommandBufferBeginInfo * pBeginInfo)2624 tu_cmd_buffer_begin(struct tu_cmd_buffer *cmd_buffer,
2625 const VkCommandBufferBeginInfo *pBeginInfo)
2626 {
2627 vk_command_buffer_begin(&cmd_buffer->vk, pBeginInfo);
2628
2629 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2630 vk_dynamic_graphics_state_init(&cmd_buffer->vk.dynamic_graphics_state);
2631 cmd_buffer->vk.dynamic_graphics_state.vi = &cmd_buffer->state.vi;
2632 cmd_buffer->vk.dynamic_graphics_state.ms.sample_locations = &cmd_buffer->state.sl;
2633 cmd_buffer->state.index_size = 0xff; /* dirty restart index */
2634 cmd_buffer->state.gmem_layout = TU_GMEM_LAYOUT_COUNT; /* dirty value */
2635
2636 tu_cache_init(&cmd_buffer->state.cache);
2637 tu_cache_init(&cmd_buffer->state.renderpass_cache);
2638 cmd_buffer->usage_flags = pBeginInfo->flags;
2639
2640 tu_cs_begin(&cmd_buffer->cs);
2641 tu_cs_begin(&cmd_buffer->draw_cs);
2642 tu_cs_begin(&cmd_buffer->draw_epilogue_cs);
2643
2644 return VK_SUCCESS;
2645 }
2646
2647 VKAPI_ATTR VkResult VKAPI_CALL
tu_BeginCommandBuffer(VkCommandBuffer commandBuffer,const VkCommandBufferBeginInfo * pBeginInfo)2648 tu_BeginCommandBuffer(VkCommandBuffer commandBuffer,
2649 const VkCommandBufferBeginInfo *pBeginInfo)
2650 {
2651 VK_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
2652 VkResult result = tu_cmd_buffer_begin(cmd_buffer, pBeginInfo);
2653 if (result != VK_SUCCESS)
2654 return result;
2655
2656 /* setup initial configuration into command buffer */
2657 if (cmd_buffer->vk.level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
2658 trace_start_cmd_buffer(&cmd_buffer->trace, &cmd_buffer->cs, cmd_buffer);
2659
2660 switch (cmd_buffer->queue_family_index) {
2661 case TU_QUEUE_GENERAL:
2662 TU_CALLX(cmd_buffer->device, tu6_init_hw)(cmd_buffer, &cmd_buffer->cs);
2663 break;
2664 default:
2665 break;
2666 }
2667 } else if (cmd_buffer->vk.level == VK_COMMAND_BUFFER_LEVEL_SECONDARY) {
2668 const bool pass_continue =
2669 pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT;
2670
2671 trace_start_cmd_buffer(&cmd_buffer->trace,
2672 pass_continue ? &cmd_buffer->draw_cs : &cmd_buffer->cs, cmd_buffer);
2673
2674 assert(pBeginInfo->pInheritanceInfo);
2675
2676 cmd_buffer->inherited_pipeline_statistics =
2677 pBeginInfo->pInheritanceInfo->pipelineStatistics;
2678
2679 vk_foreach_struct_const(ext, pBeginInfo->pInheritanceInfo) {
2680 switch (ext->sType) {
2681 case VK_STRUCTURE_TYPE_COMMAND_BUFFER_INHERITANCE_CONDITIONAL_RENDERING_INFO_EXT: {
2682 const VkCommandBufferInheritanceConditionalRenderingInfoEXT *cond_rend =
2683 (VkCommandBufferInheritanceConditionalRenderingInfoEXT *) ext;
2684 cmd_buffer->state.predication_active = cond_rend->conditionalRenderingEnable;
2685 break;
2686 }
2687 default:
2688 break;
2689 }
2690 }
2691
2692 if (pass_continue) {
2693 const VkCommandBufferInheritanceRenderingInfo *rendering_info =
2694 vk_find_struct_const(pBeginInfo->pInheritanceInfo->pNext,
2695 COMMAND_BUFFER_INHERITANCE_RENDERING_INFO);
2696
2697 if (TU_DEBUG(DYNAMIC)) {
2698 rendering_info =
2699 vk_get_command_buffer_inheritance_rendering_info(cmd_buffer->vk.level,
2700 pBeginInfo);
2701 }
2702
2703 if (rendering_info) {
2704 tu_setup_dynamic_inheritance(cmd_buffer, rendering_info);
2705 cmd_buffer->state.pass = &cmd_buffer->dynamic_pass;
2706 cmd_buffer->state.subpass = &cmd_buffer->dynamic_subpass;
2707
2708 const VkRenderingAttachmentLocationInfoKHR *location_info =
2709 vk_find_struct_const(pBeginInfo->pInheritanceInfo->pNext,
2710 RENDERING_ATTACHMENT_LOCATION_INFO_KHR);
2711 if (location_info) {
2712 vk_common_CmdSetRenderingAttachmentLocationsKHR(commandBuffer,
2713 location_info);
2714 }
2715 } else {
2716 cmd_buffer->state.pass = tu_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2717 cmd_buffer->state.subpass =
2718 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2719 }
2720 tu_fill_render_pass_state(&cmd_buffer->state.vk_rp,
2721 cmd_buffer->state.pass,
2722 cmd_buffer->state.subpass);
2723 vk_cmd_set_cb_attachment_count(&cmd_buffer->vk,
2724 cmd_buffer->state.subpass->color_count);
2725 cmd_buffer->state.dirty |= TU_CMD_DIRTY_SUBPASS;
2726
2727 cmd_buffer->patchpoints_ctx = ralloc_context(NULL);
2728
2729 /* We can't set the gmem layout here, because the state.pass only has
2730 * to be compatible (same formats/sample counts) with the primary's
2731 * renderpass, rather than exactly equal.
2732 */
2733
2734 tu_lrz_begin_secondary_cmdbuf(cmd_buffer);
2735 } else {
2736 /* When executing in the middle of another command buffer, the CCU
2737 * state is unknown.
2738 */
2739 cmd_buffer->state.ccu_state = TU_CMD_CCU_UNKNOWN;
2740 }
2741 }
2742
2743 return VK_SUCCESS;
2744 }
2745
2746 static struct tu_cs
tu_cmd_dynamic_state(struct tu_cmd_buffer * cmd,uint32_t id,uint32_t size)2747 tu_cmd_dynamic_state(struct tu_cmd_buffer *cmd, uint32_t id, uint32_t size)
2748 {
2749 struct tu_cs cs;
2750
2751 assert(id < ARRAY_SIZE(cmd->state.dynamic_state));
2752 cmd->state.dynamic_state[id] = tu_cs_draw_state(&cmd->sub_cs, &cs, size);
2753
2754 /* note: this also avoids emitting draw states before renderpass clears,
2755 * which may use the 3D clear path (for MSAA cases)
2756 */
2757 if (cmd->state.dirty & TU_CMD_DIRTY_DRAW_STATE)
2758 return cs;
2759
2760 tu_cs_emit_pkt7(&cmd->draw_cs, CP_SET_DRAW_STATE, 3);
2761 tu_cs_emit_draw_state(&cmd->draw_cs, TU_DRAW_STATE_DYNAMIC + id, cmd->state.dynamic_state[id]);
2762
2763 return cs;
2764 }
2765
2766 static void
tu_cmd_end_dynamic_state(struct tu_cmd_buffer * cmd,struct tu_cs * cs,uint32_t id)2767 tu_cmd_end_dynamic_state(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
2768 uint32_t id)
2769 {
2770 assert(id < ARRAY_SIZE(cmd->state.dynamic_state));
2771 cmd->state.dynamic_state[id] = tu_cs_end_draw_state(&cmd->sub_cs, cs);
2772
2773 /* note: this also avoids emitting draw states before renderpass clears,
2774 * which may use the 3D clear path (for MSAA cases)
2775 */
2776 if (cmd->state.dirty & TU_CMD_DIRTY_DRAW_STATE)
2777 return;
2778
2779 tu_cs_emit_pkt7(&cmd->draw_cs, CP_SET_DRAW_STATE, 3);
2780 tu_cs_emit_draw_state(&cmd->draw_cs, TU_DRAW_STATE_DYNAMIC + id, cmd->state.dynamic_state[id]);
2781 }
2782
2783 VKAPI_ATTR void VKAPI_CALL
tu_CmdBindVertexBuffers2(VkCommandBuffer commandBuffer,uint32_t firstBinding,uint32_t bindingCount,const VkBuffer * pBuffers,const VkDeviceSize * pOffsets,const VkDeviceSize * pSizes,const VkDeviceSize * pStrides)2784 tu_CmdBindVertexBuffers2(VkCommandBuffer commandBuffer,
2785 uint32_t firstBinding,
2786 uint32_t bindingCount,
2787 const VkBuffer *pBuffers,
2788 const VkDeviceSize *pOffsets,
2789 const VkDeviceSize *pSizes,
2790 const VkDeviceSize *pStrides)
2791 {
2792 VK_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2793 struct tu_cs cs;
2794
2795 cmd->state.max_vbs_bound = MAX2(
2796 cmd->state.max_vbs_bound, firstBinding + bindingCount);
2797
2798 if (pStrides) {
2799 vk_cmd_set_vertex_binding_strides(&cmd->vk, firstBinding, bindingCount,
2800 pStrides);
2801 }
2802
2803 cmd->state.vertex_buffers.iova =
2804 tu_cs_draw_state(&cmd->sub_cs, &cs, 4 * cmd->state.max_vbs_bound).iova;
2805
2806 for (uint32_t i = 0; i < bindingCount; i++) {
2807 if (pBuffers[i] == VK_NULL_HANDLE) {
2808 cmd->state.vb[firstBinding + i].base = 0;
2809 cmd->state.vb[firstBinding + i].size = 0;
2810 } else {
2811 struct tu_buffer *buf = tu_buffer_from_handle(pBuffers[i]);
2812 cmd->state.vb[firstBinding + i].base = buf->iova + pOffsets[i];
2813 cmd->state.vb[firstBinding + i].size =
2814 vk_buffer_range(&buf->vk, pOffsets[i], pSizes ? pSizes[i] : VK_WHOLE_SIZE);
2815 }
2816 }
2817
2818 for (uint32_t i = 0; i < cmd->state.max_vbs_bound; i++) {
2819 tu_cs_emit_regs(&cs,
2820 A6XX_VFD_FETCH_BASE(i, .qword = cmd->state.vb[i].base),
2821 A6XX_VFD_FETCH_SIZE(i, cmd->state.vb[i].size));
2822 }
2823
2824 cmd->state.dirty |= TU_CMD_DIRTY_VERTEX_BUFFERS;
2825 }
2826
2827 VKAPI_ATTR void VKAPI_CALL
tu_CmdBindIndexBuffer2KHR(VkCommandBuffer commandBuffer,VkBuffer buffer,VkDeviceSize offset,VkDeviceSize size,VkIndexType indexType)2828 tu_CmdBindIndexBuffer2KHR(VkCommandBuffer commandBuffer,
2829 VkBuffer buffer,
2830 VkDeviceSize offset,
2831 VkDeviceSize size,
2832 VkIndexType indexType)
2833 {
2834 VK_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
2835 VK_FROM_HANDLE(tu_buffer, buf, buffer);
2836
2837 size = buf ? vk_buffer_range(&buf->vk, offset, size) : 0;
2838
2839 uint32_t index_size, index_shift;
2840 uint32_t restart_index = vk_index_to_restart(indexType);
2841
2842 switch (indexType) {
2843 case VK_INDEX_TYPE_UINT16:
2844 index_size = INDEX4_SIZE_16_BIT;
2845 index_shift = 1;
2846 break;
2847 case VK_INDEX_TYPE_UINT32:
2848 index_size = INDEX4_SIZE_32_BIT;
2849 index_shift = 2;
2850 break;
2851 case VK_INDEX_TYPE_UINT8_KHR:
2852 index_size = INDEX4_SIZE_8_BIT;
2853 index_shift = 0;
2854 break;
2855 default:
2856 unreachable("invalid VkIndexType");
2857 }
2858
2859 if (buf) {
2860 /* initialize/update the restart index */
2861 if (cmd->state.index_size != index_size)
2862 tu_cs_emit_regs(&cmd->draw_cs, A6XX_PC_RESTART_INDEX(restart_index));
2863
2864 cmd->state.index_va = buf->iova + offset;
2865 cmd->state.max_index_count = size >> index_shift;
2866 cmd->state.index_size = index_size;
2867 } else {
2868 cmd->state.index_va = 0;
2869 cmd->state.max_index_count = 0;
2870 cmd->state.index_size = 0;
2871 }
2872 }
2873
2874 template <chip CHIP>
2875 static void
tu6_emit_descriptor_sets(struct tu_cmd_buffer * cmd,VkPipelineBindPoint bind_point)2876 tu6_emit_descriptor_sets(struct tu_cmd_buffer *cmd,
2877 VkPipelineBindPoint bind_point)
2878 {
2879 struct tu_descriptor_state *descriptors_state =
2880 tu_get_descriptors_state(cmd, bind_point);
2881 uint32_t sp_bindless_base_reg, hlsq_bindless_base_reg;
2882 struct tu_cs *cs, state_cs;
2883
2884 if (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS) {
2885 sp_bindless_base_reg = __SP_BINDLESS_BASE_DESCRIPTOR<CHIP>(0, {}).reg;
2886 hlsq_bindless_base_reg = REG_A6XX_HLSQ_BINDLESS_BASE(0);
2887
2888 if (CHIP == A6XX) {
2889 cmd->state.desc_sets =
2890 tu_cs_draw_state(&cmd->sub_cs, &state_cs,
2891 4 + 4 * descriptors_state->max_sets_bound +
2892 (descriptors_state->max_dynamic_offset_size ? 6 : 0));
2893 } else {
2894 cmd->state.desc_sets =
2895 tu_cs_draw_state(&cmd->sub_cs, &state_cs,
2896 3 + 2 * descriptors_state->max_sets_bound +
2897 (descriptors_state->max_dynamic_offset_size ? 3 : 0));
2898 }
2899 cs = &state_cs;
2900 } else {
2901 assert(bind_point == VK_PIPELINE_BIND_POINT_COMPUTE);
2902
2903 sp_bindless_base_reg = __SP_CS_BINDLESS_BASE_DESCRIPTOR<CHIP>(0, {}).reg;
2904 hlsq_bindless_base_reg = REG_A6XX_HLSQ_CS_BINDLESS_BASE(0);
2905
2906 cs = &cmd->cs;
2907 }
2908
2909 tu_cs_emit_pkt4(cs, sp_bindless_base_reg, 2 * descriptors_state->max_sets_bound);
2910 tu_cs_emit_array(cs, (const uint32_t*)descriptors_state->set_iova, 2 * descriptors_state->max_sets_bound);
2911 if (CHIP == A6XX) {
2912 tu_cs_emit_pkt4(cs, hlsq_bindless_base_reg, 2 * descriptors_state->max_sets_bound);
2913 tu_cs_emit_array(cs, (const uint32_t*)descriptors_state->set_iova, 2 * descriptors_state->max_sets_bound);
2914 }
2915
2916 /* Dynamic descriptors get the reserved descriptor set. */
2917 if (descriptors_state->max_dynamic_offset_size) {
2918 int reserved_set_idx = cmd->device->physical_device->reserved_set_idx;
2919 assert(reserved_set_idx >= 0); /* reserved set must be bound */
2920
2921 tu_cs_emit_pkt4(cs, sp_bindless_base_reg + reserved_set_idx * 2, 2);
2922 tu_cs_emit_qw(cs, descriptors_state->set_iova[reserved_set_idx]);
2923 if (CHIP == A6XX) {
2924 tu_cs_emit_pkt4(cs, hlsq_bindless_base_reg + reserved_set_idx * 2, 2);
2925 tu_cs_emit_qw(cs, descriptors_state->set_iova[reserved_set_idx]);
2926 }
2927 }
2928
2929 tu_cs_emit_regs(cs, HLSQ_INVALIDATE_CMD(CHIP,
2930 .cs_bindless = bind_point == VK_PIPELINE_BIND_POINT_COMPUTE ? CHIP == A6XX ? 0x1f : 0xff : 0,
2931 .gfx_bindless = bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS ? CHIP == A6XX ? 0x1f : 0xff : 0,
2932 ));
2933
2934 if (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS) {
2935 assert(cs->cur == cs->end); /* validate draw state size */
2936 /* note: this also avoids emitting draw states before renderpass clears,
2937 * which may use the 3D clear path (for MSAA cases)
2938 */
2939 if (!(cmd->state.dirty & TU_CMD_DIRTY_DRAW_STATE)) {
2940 tu_cs_emit_pkt7(&cmd->draw_cs, CP_SET_DRAW_STATE, 3);
2941 tu_cs_emit_draw_state(&cmd->draw_cs, TU_DRAW_STATE_DESC_SETS, cmd->state.desc_sets);
2942 }
2943 }
2944 }
2945
2946 /* We lazily emit the draw state for desciptor sets at draw time, so that we can
2947 * batch together multiple tu_CmdBindDescriptorSets() calls. ANGLE and zink
2948 * will often emit multiple bind calls in a draw.
2949 */
2950 static void
tu_dirty_desc_sets(struct tu_cmd_buffer * cmd,VkPipelineBindPoint pipelineBindPoint)2951 tu_dirty_desc_sets(struct tu_cmd_buffer *cmd,
2952 VkPipelineBindPoint pipelineBindPoint)
2953 {
2954 if (pipelineBindPoint == VK_PIPELINE_BIND_POINT_COMPUTE) {
2955 cmd->state.dirty |= TU_CMD_DIRTY_COMPUTE_DESC_SETS;
2956 } else {
2957 assert(pipelineBindPoint == VK_PIPELINE_BIND_POINT_GRAPHICS);
2958 cmd->state.dirty |= TU_CMD_DIRTY_DESC_SETS;
2959 }
2960 }
2961
2962 static void
tu_bind_descriptor_sets(struct tu_cmd_buffer * cmd,const VkBindDescriptorSetsInfoKHR * info,VkPipelineBindPoint bind_point)2963 tu_bind_descriptor_sets(struct tu_cmd_buffer *cmd,
2964 const VkBindDescriptorSetsInfoKHR *info,
2965 VkPipelineBindPoint bind_point)
2966 {
2967 VK_FROM_HANDLE(tu_pipeline_layout, layout, info->layout);
2968 unsigned dyn_idx = 0;
2969
2970 struct tu_descriptor_state *descriptors_state =
2971 tu_get_descriptors_state(cmd, bind_point);
2972
2973 descriptors_state->max_sets_bound =
2974 MAX2(descriptors_state->max_sets_bound,
2975 info->firstSet + info->descriptorSetCount);
2976
2977 unsigned dynamic_offset_offset = 0;
2978 for (unsigned i = 0; i < info->firstSet; i++) {
2979 dynamic_offset_offset += layout->set[i].layout->dynamic_offset_size;
2980 }
2981
2982 for (unsigned i = 0; i < info->descriptorSetCount; ++i) {
2983 unsigned idx = i + info->firstSet;
2984 VK_FROM_HANDLE(tu_descriptor_set, set, info->pDescriptorSets[i]);
2985
2986 descriptors_state->sets[idx] = set;
2987 descriptors_state->set_iova[idx] = set ?
2988 (set->va | BINDLESS_DESCRIPTOR_64B) : 0;
2989
2990 if (!set)
2991 continue;
2992
2993 if (set->layout->has_inline_uniforms)
2994 cmd->state.dirty |= TU_CMD_DIRTY_SHADER_CONSTS;
2995
2996 if (!set->layout->dynamic_offset_size)
2997 continue;
2998
2999 uint32_t *src = set->dynamic_descriptors;
3000 uint32_t *dst = descriptors_state->dynamic_descriptors +
3001 dynamic_offset_offset / 4;
3002 for (unsigned j = 0; j < set->layout->binding_count; j++) {
3003 struct tu_descriptor_set_binding_layout *binding =
3004 &set->layout->binding[j];
3005 if (vk_descriptor_type_is_dynamic(binding->type)) {
3006 for (unsigned k = 0; k < binding->array_size; k++, dyn_idx++) {
3007 assert(dyn_idx < info->dynamicOffsetCount);
3008 uint32_t offset = info->pDynamicOffsets[dyn_idx];
3009 memcpy(dst, src, binding->size);
3010
3011 if (binding->type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC) {
3012 /* Note: we can assume here that the addition won't roll
3013 * over and change the SIZE field.
3014 */
3015 uint64_t va = src[0] | ((uint64_t)src[1] << 32);
3016 va += offset;
3017 dst[0] = va;
3018 dst[1] = va >> 32;
3019 } else {
3020 uint32_t *dst_desc = dst;
3021 for (unsigned i = 0;
3022 i < binding->size / (4 * A6XX_TEX_CONST_DWORDS);
3023 i++, dst_desc += A6XX_TEX_CONST_DWORDS) {
3024 /* Note: A6XX_TEX_CONST_5_DEPTH is always 0 */
3025 uint64_t va = dst_desc[4] | ((uint64_t)dst_desc[5] << 32);
3026 uint32_t desc_offset =
3027 (dst_desc[2] &
3028 A6XX_TEX_CONST_2_STARTOFFSETTEXELS__MASK) >>
3029 A6XX_TEX_CONST_2_STARTOFFSETTEXELS__SHIFT;
3030
3031 /* Use descriptor's format to determine the shift amount
3032 * that's to be used on the offset value.
3033 */
3034 uint32_t format = (dst_desc[0] &
3035 A6XX_TEX_CONST_0_FMT__MASK) >>
3036 A6XX_TEX_CONST_0_FMT__SHIFT;
3037 unsigned offset_shift;
3038 switch (format) {
3039 case FMT6_16_UINT:
3040 offset_shift = 1;
3041 break;
3042 case FMT6_32_UINT:
3043 offset_shift = 2;
3044 break;
3045 case FMT6_8_UINT:
3046 default:
3047 offset_shift = 0;
3048 break;
3049 }
3050
3051 va += desc_offset << offset_shift;
3052 va += offset;
3053 unsigned new_offset = (va & 0x3f) >> offset_shift;
3054 va &= ~0x3full;
3055 dst_desc[4] = va;
3056 dst_desc[5] = va >> 32;
3057 dst_desc[2] =
3058 (dst_desc[2] & ~A6XX_TEX_CONST_2_STARTOFFSETTEXELS__MASK) |
3059 A6XX_TEX_CONST_2_STARTOFFSETTEXELS(new_offset);
3060 }
3061 }
3062
3063 dst += binding->size / 4;
3064 src += binding->size / 4;
3065 }
3066 }
3067 }
3068
3069 dynamic_offset_offset += layout->set[idx].layout->dynamic_offset_size;
3070 }
3071 assert(dyn_idx == info->dynamicOffsetCount);
3072
3073 if (dynamic_offset_offset) {
3074 descriptors_state->max_dynamic_offset_size =
3075 MAX2(descriptors_state->max_dynamic_offset_size, dynamic_offset_offset);
3076
3077 /* allocate and fill out dynamic descriptor set */
3078 struct tu_cs_memory dynamic_desc_set;
3079 int reserved_set_idx = cmd->device->physical_device->reserved_set_idx;
3080 VkResult result =
3081 tu_cs_alloc(&cmd->sub_cs,
3082 descriptors_state->max_dynamic_offset_size /
3083 (4 * A6XX_TEX_CONST_DWORDS),
3084 A6XX_TEX_CONST_DWORDS, &dynamic_desc_set);
3085 if (result != VK_SUCCESS) {
3086 vk_command_buffer_set_error(&cmd->vk, result);
3087 return;
3088 }
3089
3090 memcpy(dynamic_desc_set.map, descriptors_state->dynamic_descriptors,
3091 descriptors_state->max_dynamic_offset_size);
3092 assert(reserved_set_idx >= 0); /* reserved set must be bound */
3093 descriptors_state->set_iova[reserved_set_idx] = dynamic_desc_set.iova | BINDLESS_DESCRIPTOR_64B;
3094 }
3095
3096 tu_dirty_desc_sets(cmd, bind_point);
3097 }
3098
3099 VKAPI_ATTR void VKAPI_CALL
tu_CmdBindDescriptorSets2KHR(VkCommandBuffer commandBuffer,const VkBindDescriptorSetsInfoKHR * pBindDescriptorSetsInfo)3100 tu_CmdBindDescriptorSets2KHR(
3101 VkCommandBuffer commandBuffer,
3102 const VkBindDescriptorSetsInfoKHR *pBindDescriptorSetsInfo)
3103 {
3104 VK_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
3105
3106 if (pBindDescriptorSetsInfo->stageFlags & VK_SHADER_STAGE_COMPUTE_BIT) {
3107 tu_bind_descriptor_sets(cmd, pBindDescriptorSetsInfo,
3108 VK_PIPELINE_BIND_POINT_COMPUTE);
3109 }
3110
3111 if (pBindDescriptorSetsInfo->stageFlags & VK_SHADER_STAGE_ALL_GRAPHICS) {
3112 tu_bind_descriptor_sets(cmd, pBindDescriptorSetsInfo,
3113 VK_PIPELINE_BIND_POINT_GRAPHICS);
3114 }
3115 }
3116
3117 VKAPI_ATTR void VKAPI_CALL
tu_CmdBindDescriptorBuffersEXT(VkCommandBuffer commandBuffer,uint32_t bufferCount,const VkDescriptorBufferBindingInfoEXT * pBindingInfos)3118 tu_CmdBindDescriptorBuffersEXT(
3119 VkCommandBuffer commandBuffer,
3120 uint32_t bufferCount,
3121 const VkDescriptorBufferBindingInfoEXT *pBindingInfos)
3122 {
3123 VK_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
3124
3125 for (unsigned i = 0; i < bufferCount; i++)
3126 cmd->state.descriptor_buffer_iova[i] = pBindingInfos[i].address;
3127 }
3128
3129 static void
tu_set_descriptor_buffer_offsets(struct tu_cmd_buffer * cmd,const VkSetDescriptorBufferOffsetsInfoEXT * info,VkPipelineBindPoint bind_point)3130 tu_set_descriptor_buffer_offsets(
3131 struct tu_cmd_buffer *cmd,
3132 const VkSetDescriptorBufferOffsetsInfoEXT *info,
3133 VkPipelineBindPoint bind_point)
3134 {
3135 VK_FROM_HANDLE(tu_pipeline_layout, layout, info->layout);
3136
3137 struct tu_descriptor_state *descriptors_state =
3138 tu_get_descriptors_state(cmd, bind_point);
3139
3140 descriptors_state->max_sets_bound = MAX2(descriptors_state->max_sets_bound,
3141 info->firstSet + info->setCount);
3142
3143 for (unsigned i = 0; i < info->setCount; ++i) {
3144 unsigned idx = i + info->firstSet;
3145 struct tu_descriptor_set_layout *set_layout = layout->set[idx].layout;
3146
3147 descriptors_state->set_iova[idx] =
3148 (cmd->state.descriptor_buffer_iova[info->pBufferIndices[i]] +
3149 info->pOffsets[i]) |
3150 BINDLESS_DESCRIPTOR_64B;
3151
3152 if (set_layout->has_inline_uniforms)
3153 cmd->state.dirty |= TU_CMD_DIRTY_SHADER_CONSTS;
3154 }
3155
3156 tu_dirty_desc_sets(cmd, bind_point);
3157 }
3158
3159 VKAPI_ATTR void VKAPI_CALL
tu_CmdSetDescriptorBufferOffsets2EXT(VkCommandBuffer commandBuffer,const VkSetDescriptorBufferOffsetsInfoEXT * pSetDescriptorBufferOffsetsInfo)3160 tu_CmdSetDescriptorBufferOffsets2EXT(
3161 VkCommandBuffer commandBuffer,
3162 const VkSetDescriptorBufferOffsetsInfoEXT *pSetDescriptorBufferOffsetsInfo)
3163 {
3164 VK_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
3165
3166 if (pSetDescriptorBufferOffsetsInfo->stageFlags &
3167 VK_SHADER_STAGE_COMPUTE_BIT) {
3168 tu_set_descriptor_buffer_offsets(cmd, pSetDescriptorBufferOffsetsInfo,
3169 VK_PIPELINE_BIND_POINT_COMPUTE);
3170 }
3171
3172 if (pSetDescriptorBufferOffsetsInfo->stageFlags &
3173 VK_SHADER_STAGE_ALL_GRAPHICS) {
3174 tu_set_descriptor_buffer_offsets(cmd, pSetDescriptorBufferOffsetsInfo,
3175 VK_PIPELINE_BIND_POINT_GRAPHICS);
3176 }
3177 }
3178
3179 static void
tu_bind_descriptor_buffer_embedded_samplers(struct tu_cmd_buffer * cmd,const VkBindDescriptorBufferEmbeddedSamplersInfoEXT * info,VkPipelineBindPoint bind_point)3180 tu_bind_descriptor_buffer_embedded_samplers(
3181 struct tu_cmd_buffer *cmd,
3182 const VkBindDescriptorBufferEmbeddedSamplersInfoEXT *info,
3183 VkPipelineBindPoint bind_point)
3184 {
3185 VK_FROM_HANDLE(tu_pipeline_layout, layout, info->layout);
3186
3187 struct tu_descriptor_set_layout *set_layout =
3188 layout->set[info->set].layout;
3189
3190 struct tu_descriptor_state *descriptors_state =
3191 tu_get_descriptors_state(cmd, bind_point);
3192
3193 descriptors_state->max_sets_bound =
3194 MAX2(descriptors_state->max_sets_bound, info->set + 1);
3195
3196 descriptors_state->set_iova[info->set] =
3197 set_layout->embedded_samplers->iova | BINDLESS_DESCRIPTOR_64B;
3198
3199 tu_dirty_desc_sets(cmd, bind_point);
3200 }
3201
3202 VKAPI_ATTR void VKAPI_CALL
tu_CmdBindDescriptorBufferEmbeddedSamplers2EXT(VkCommandBuffer commandBuffer,const VkBindDescriptorBufferEmbeddedSamplersInfoEXT * pBindDescriptorBufferEmbeddedSamplersInfo)3203 tu_CmdBindDescriptorBufferEmbeddedSamplers2EXT(
3204 VkCommandBuffer commandBuffer,
3205 const VkBindDescriptorBufferEmbeddedSamplersInfoEXT
3206 *pBindDescriptorBufferEmbeddedSamplersInfo)
3207 {
3208 VK_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
3209
3210 if (pBindDescriptorBufferEmbeddedSamplersInfo->stageFlags &
3211 VK_SHADER_STAGE_COMPUTE_BIT) {
3212 tu_bind_descriptor_buffer_embedded_samplers(
3213 cmd, pBindDescriptorBufferEmbeddedSamplersInfo,
3214 VK_PIPELINE_BIND_POINT_COMPUTE);
3215 }
3216
3217 if (pBindDescriptorBufferEmbeddedSamplersInfo->stageFlags &
3218 VK_SHADER_STAGE_ALL_GRAPHICS) {
3219 tu_bind_descriptor_buffer_embedded_samplers(
3220 cmd, pBindDescriptorBufferEmbeddedSamplersInfo,
3221 VK_PIPELINE_BIND_POINT_GRAPHICS);
3222 }
3223 }
3224
3225 static VkResult
tu_push_descriptor_set_update_layout(struct tu_device * device,struct tu_descriptor_set * set,struct tu_descriptor_set_layout * layout)3226 tu_push_descriptor_set_update_layout(struct tu_device *device,
3227 struct tu_descriptor_set *set,
3228 struct tu_descriptor_set_layout *layout)
3229 {
3230 if (set->layout == layout)
3231 return VK_SUCCESS;
3232
3233 if (set->layout)
3234 vk_descriptor_set_layout_unref(&device->vk, &set->layout->vk);
3235 vk_descriptor_set_layout_ref(&layout->vk);
3236 set->layout = layout;
3237
3238 if (set->host_size < layout->size) {
3239 void *new_buf =
3240 vk_realloc(&device->vk.alloc, set->mapped_ptr, layout->size, 8,
3241 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3242 if (!new_buf)
3243 return VK_ERROR_OUT_OF_HOST_MEMORY;
3244 set->mapped_ptr = (uint32_t *) new_buf;
3245 set->host_size = layout->size;
3246 }
3247 return VK_SUCCESS;
3248 }
3249
3250 static void
tu_push_descriptor_set(struct tu_cmd_buffer * cmd,const VkPushDescriptorSetInfoKHR * info,VkPipelineBindPoint bind_point)3251 tu_push_descriptor_set(struct tu_cmd_buffer *cmd,
3252 const VkPushDescriptorSetInfoKHR *info,
3253 VkPipelineBindPoint bind_point)
3254 {
3255 VK_FROM_HANDLE(tu_pipeline_layout, pipe_layout, info->layout);
3256 struct tu_descriptor_set_layout *layout =
3257 pipe_layout->set[info->set].layout;
3258 struct tu_descriptor_set *set =
3259 &tu_get_descriptors_state(cmd, bind_point)->push_set;
3260
3261 struct tu_cs_memory set_mem;
3262 VkResult result = tu_cs_alloc(&cmd->sub_cs,
3263 DIV_ROUND_UP(layout->size, A6XX_TEX_CONST_DWORDS * 4),
3264 A6XX_TEX_CONST_DWORDS, &set_mem);
3265 if (result != VK_SUCCESS) {
3266 vk_command_buffer_set_error(&cmd->vk, result);
3267 return;
3268 }
3269
3270 result = tu_push_descriptor_set_update_layout(cmd->device, set, layout);
3271 if (result != VK_SUCCESS) {
3272 vk_command_buffer_set_error(&cmd->vk, result);
3273 return;
3274 }
3275
3276 tu_update_descriptor_sets(cmd->device, tu_descriptor_set_to_handle(set),
3277 info->descriptorWriteCount,
3278 info->pDescriptorWrites, 0, NULL);
3279
3280 memcpy(set_mem.map, set->mapped_ptr, layout->size);
3281 set->va = set_mem.iova;
3282
3283 const VkDescriptorSet desc_set[] = { tu_descriptor_set_to_handle(set) };
3284 vk_common_CmdBindDescriptorSets(tu_cmd_buffer_to_handle(cmd), bind_point,
3285 info->layout, info->set, 1, desc_set, 0,
3286 NULL);
3287 }
3288
3289 VKAPI_ATTR void VKAPI_CALL
tu_CmdPushDescriptorSet2KHR(VkCommandBuffer commandBuffer,const VkPushDescriptorSetInfoKHR * pPushDescriptorSetInfo)3290 tu_CmdPushDescriptorSet2KHR(
3291 VkCommandBuffer commandBuffer,
3292 const VkPushDescriptorSetInfoKHR *pPushDescriptorSetInfo)
3293 {
3294 VK_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
3295
3296 if (pPushDescriptorSetInfo->stageFlags & VK_SHADER_STAGE_COMPUTE_BIT) {
3297 tu_push_descriptor_set(cmd, pPushDescriptorSetInfo,
3298 VK_PIPELINE_BIND_POINT_COMPUTE);
3299 }
3300
3301 if (pPushDescriptorSetInfo->stageFlags & VK_SHADER_STAGE_ALL_GRAPHICS) {
3302 tu_push_descriptor_set(cmd, pPushDescriptorSetInfo,
3303 VK_PIPELINE_BIND_POINT_GRAPHICS);
3304 }
3305 }
3306
3307 VKAPI_ATTR void VKAPI_CALL
tu_CmdPushDescriptorSetWithTemplate2KHR(VkCommandBuffer commandBuffer,const VkPushDescriptorSetWithTemplateInfoKHR * pPushDescriptorSetWithTemplateInfo)3308 tu_CmdPushDescriptorSetWithTemplate2KHR(
3309 VkCommandBuffer commandBuffer,
3310 const VkPushDescriptorSetWithTemplateInfoKHR
3311 *pPushDescriptorSetWithTemplateInfo)
3312 {
3313 VK_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
3314 VK_FROM_HANDLE(tu_pipeline_layout, pipe_layout,
3315 pPushDescriptorSetWithTemplateInfo->layout);
3316 VK_FROM_HANDLE(
3317 tu_descriptor_update_template, templ,
3318 pPushDescriptorSetWithTemplateInfo->descriptorUpdateTemplate);
3319 struct tu_descriptor_set_layout *layout =
3320 pipe_layout->set[pPushDescriptorSetWithTemplateInfo->set].layout;
3321 struct tu_descriptor_set *set =
3322 &tu_get_descriptors_state(cmd, templ->bind_point)->push_set;
3323
3324 struct tu_cs_memory set_mem;
3325 VkResult result = tu_cs_alloc(&cmd->sub_cs,
3326 DIV_ROUND_UP(layout->size, A6XX_TEX_CONST_DWORDS * 4),
3327 A6XX_TEX_CONST_DWORDS, &set_mem);
3328 if (result != VK_SUCCESS) {
3329 vk_command_buffer_set_error(&cmd->vk, result);
3330 return;
3331 }
3332
3333 result = tu_push_descriptor_set_update_layout(cmd->device, set, layout);
3334 if (result != VK_SUCCESS) {
3335 vk_command_buffer_set_error(&cmd->vk, result);
3336 return;
3337 }
3338
3339 tu_update_descriptor_set_with_template(
3340 cmd->device, set,
3341 pPushDescriptorSetWithTemplateInfo->descriptorUpdateTemplate,
3342 pPushDescriptorSetWithTemplateInfo->pData);
3343
3344 memcpy(set_mem.map, set->mapped_ptr, layout->size);
3345 set->va = set_mem.iova;
3346
3347 const VkDescriptorSet desc_set[] = { tu_descriptor_set_to_handle(set) };
3348 vk_common_CmdBindDescriptorSets(
3349 tu_cmd_buffer_to_handle(cmd), templ->bind_point,
3350 pPushDescriptorSetWithTemplateInfo->layout,
3351 pPushDescriptorSetWithTemplateInfo->set, 1, desc_set, 0, NULL);
3352 }
3353
3354 VKAPI_ATTR void VKAPI_CALL
tu_CmdBindTransformFeedbackBuffersEXT(VkCommandBuffer commandBuffer,uint32_t firstBinding,uint32_t bindingCount,const VkBuffer * pBuffers,const VkDeviceSize * pOffsets,const VkDeviceSize * pSizes)3355 tu_CmdBindTransformFeedbackBuffersEXT(VkCommandBuffer commandBuffer,
3356 uint32_t firstBinding,
3357 uint32_t bindingCount,
3358 const VkBuffer *pBuffers,
3359 const VkDeviceSize *pOffsets,
3360 const VkDeviceSize *pSizes)
3361 {
3362 VK_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
3363 struct tu_cs *cs = &cmd->draw_cs;
3364
3365 /* using COND_REG_EXEC for xfb commands matches the blob behavior
3366 * presumably there isn't any benefit using a draw state when the
3367 * condition is (SYSMEM | BINNING)
3368 */
3369 tu_cond_exec_start(cs, CP_COND_REG_EXEC_0_MODE(RENDER_MODE) |
3370 CP_COND_REG_EXEC_0_SYSMEM |
3371 CP_COND_REG_EXEC_0_BINNING);
3372
3373 for (uint32_t i = 0; i < bindingCount; i++) {
3374 VK_FROM_HANDLE(tu_buffer, buf, pBuffers[i]);
3375 uint64_t iova = buf->iova + pOffsets[i];
3376 uint32_t size = buf->bo->size - (iova - buf->bo->iova);
3377 uint32_t idx = i + firstBinding;
3378
3379 if (pSizes && pSizes[i] != VK_WHOLE_SIZE)
3380 size = pSizes[i];
3381
3382 /* BUFFER_BASE is 32-byte aligned, add remaining offset to BUFFER_OFFSET */
3383 uint32_t offset = iova & 0x1f;
3384 iova &= ~(uint64_t) 0x1f;
3385
3386 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_BUFFER_BASE(idx), 3);
3387 tu_cs_emit_qw(cs, iova);
3388 tu_cs_emit(cs, size + offset);
3389
3390 cmd->state.streamout_offset[idx] = offset;
3391 }
3392
3393 tu_cond_exec_end(cs);
3394 }
3395
3396 VKAPI_ATTR void VKAPI_CALL
tu_CmdBeginTransformFeedbackEXT(VkCommandBuffer commandBuffer,uint32_t firstCounterBuffer,uint32_t counterBufferCount,const VkBuffer * pCounterBuffers,const VkDeviceSize * pCounterBufferOffsets)3397 tu_CmdBeginTransformFeedbackEXT(VkCommandBuffer commandBuffer,
3398 uint32_t firstCounterBuffer,
3399 uint32_t counterBufferCount,
3400 const VkBuffer *pCounterBuffers,
3401 const VkDeviceSize *pCounterBufferOffsets)
3402 {
3403 VK_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
3404 struct tu_cs *cs = &cmd->draw_cs;
3405
3406 tu_cond_exec_start(cs, CP_COND_REG_EXEC_0_MODE(RENDER_MODE) |
3407 CP_COND_REG_EXEC_0_SYSMEM |
3408 CP_COND_REG_EXEC_0_BINNING);
3409
3410 tu_cs_emit_regs(cs, A6XX_VPC_SO_DISABLE(false));
3411
3412 /* TODO: only update offset for active buffers */
3413 for (uint32_t i = 0; i < IR3_MAX_SO_BUFFERS; i++)
3414 tu_cs_emit_regs(cs, A6XX_VPC_SO_BUFFER_OFFSET(i, cmd->state.streamout_offset[i]));
3415
3416 for (uint32_t i = 0; i < (pCounterBuffers ? counterBufferCount : 0); i++) {
3417 uint32_t idx = firstCounterBuffer + i;
3418 uint32_t offset = cmd->state.streamout_offset[idx];
3419 uint64_t counter_buffer_offset = pCounterBufferOffsets ? pCounterBufferOffsets[i] : 0u;
3420
3421 if (!pCounterBuffers[i])
3422 continue;
3423
3424 VK_FROM_HANDLE(tu_buffer, buf, pCounterBuffers[i]);
3425
3426 tu_cs_emit_pkt7(cs, CP_MEM_TO_REG, 3);
3427 tu_cs_emit(cs, CP_MEM_TO_REG_0_REG(REG_A6XX_VPC_SO_BUFFER_OFFSET(idx)) |
3428 CP_MEM_TO_REG_0_UNK31 |
3429 CP_MEM_TO_REG_0_CNT(1));
3430 tu_cs_emit_qw(cs, buf->iova + counter_buffer_offset);
3431
3432 if (offset) {
3433 tu_cs_emit_pkt7(cs, CP_REG_RMW, 3);
3434 tu_cs_emit(cs, CP_REG_RMW_0_DST_REG(REG_A6XX_VPC_SO_BUFFER_OFFSET(idx)) |
3435 CP_REG_RMW_0_SRC1_ADD);
3436 tu_cs_emit(cs, 0xffffffff);
3437 tu_cs_emit(cs, offset);
3438 }
3439 }
3440
3441 tu_cond_exec_end(cs);
3442 }
3443
3444 template <chip CHIP>
3445 VKAPI_ATTR void VKAPI_CALL
tu_CmdEndTransformFeedbackEXT(VkCommandBuffer commandBuffer,uint32_t firstCounterBuffer,uint32_t counterBufferCount,const VkBuffer * pCounterBuffers,const VkDeviceSize * pCounterBufferOffsets)3446 tu_CmdEndTransformFeedbackEXT(VkCommandBuffer commandBuffer,
3447 uint32_t firstCounterBuffer,
3448 uint32_t counterBufferCount,
3449 const VkBuffer *pCounterBuffers,
3450 const VkDeviceSize *pCounterBufferOffsets)
3451 {
3452 VK_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
3453 struct tu_cs *cs = &cmd->draw_cs;
3454
3455 tu_cond_exec_start(cs, CP_COND_REG_EXEC_0_MODE(RENDER_MODE) |
3456 CP_COND_REG_EXEC_0_SYSMEM |
3457 CP_COND_REG_EXEC_0_BINNING);
3458
3459 tu_cs_emit_regs(cs, A6XX_VPC_SO_DISABLE(true));
3460
3461 /* TODO: only flush buffers that need to be flushed */
3462 for (uint32_t i = 0; i < IR3_MAX_SO_BUFFERS; i++) {
3463 /* note: FLUSH_BASE is always the same, so it could go in init_hw()? */
3464 tu_cs_emit_pkt4(cs, REG_A6XX_VPC_SO_FLUSH_BASE(i), 2);
3465 tu_cs_emit_qw(cs, global_iova_arr(cmd, flush_base, i));
3466 tu_emit_event_write<CHIP>(cmd, cs, (enum fd_gpu_event) (FD_FLUSH_SO_0 + i));
3467 }
3468
3469 for (uint32_t i = 0; i < (pCounterBuffers ? counterBufferCount : 0); i++) {
3470 uint32_t idx = firstCounterBuffer + i;
3471 uint32_t offset = cmd->state.streamout_offset[idx];
3472 uint64_t counter_buffer_offset = pCounterBufferOffsets ? pCounterBufferOffsets[i] : 0u;
3473
3474 if (!pCounterBuffers[i])
3475 continue;
3476
3477 VK_FROM_HANDLE(tu_buffer, buf, pCounterBuffers[i]);
3478
3479 /* VPC_SO_FLUSH_BASE has dwords counter, but counter should be in bytes */
3480 tu_cs_emit_pkt7(cs, CP_MEM_TO_REG, 3);
3481 tu_cs_emit(cs, CP_MEM_TO_REG_0_REG(REG_A6XX_CP_SCRATCH_REG(0)) |
3482 COND(CHIP == A6XX, CP_MEM_TO_REG_0_SHIFT_BY_2) |
3483 0x40000 | /* ??? */
3484 CP_MEM_TO_REG_0_UNK31 |
3485 CP_MEM_TO_REG_0_CNT(1));
3486 tu_cs_emit_qw(cs, global_iova_arr(cmd, flush_base, idx));
3487
3488 if (offset) {
3489 tu_cs_emit_pkt7(cs, CP_REG_RMW, 3);
3490 tu_cs_emit(cs, CP_REG_RMW_0_DST_REG(REG_A6XX_CP_SCRATCH_REG(0)) |
3491 CP_REG_RMW_0_SRC1_ADD);
3492 tu_cs_emit(cs, 0xffffffff);
3493 tu_cs_emit(cs, -offset);
3494 }
3495
3496 tu_cs_emit_pkt7(cs, CP_REG_TO_MEM, 3);
3497 tu_cs_emit(cs, CP_REG_TO_MEM_0_REG(REG_A6XX_CP_SCRATCH_REG(0)) |
3498 CP_REG_TO_MEM_0_CNT(1));
3499 tu_cs_emit_qw(cs, buf->iova + counter_buffer_offset);
3500 }
3501
3502 tu_cond_exec_end(cs);
3503
3504 cmd->state.rp.xfb_used = true;
3505 }
3506 TU_GENX(tu_CmdEndTransformFeedbackEXT);
3507
3508 VKAPI_ATTR void VKAPI_CALL
tu_CmdPushConstants2KHR(VkCommandBuffer commandBuffer,const VkPushConstantsInfoKHR * pPushConstantsInfo)3509 tu_CmdPushConstants2KHR(VkCommandBuffer commandBuffer,
3510 const VkPushConstantsInfoKHR *pPushConstantsInfo)
3511 {
3512 VK_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
3513 memcpy((char *) cmd->push_constants + pPushConstantsInfo->offset,
3514 pPushConstantsInfo->pValues, pPushConstantsInfo->size);
3515 cmd->state.dirty |= TU_CMD_DIRTY_SHADER_CONSTS;
3516 }
3517
3518 /* Clean everything which has been made available but we haven't actually
3519 * cleaned yet.
3520 */
3521 static void
tu_clean_all_pending(struct tu_cache_state * cache)3522 tu_clean_all_pending(struct tu_cache_state *cache)
3523 {
3524 cache->flush_bits |= cache->pending_flush_bits & TU_CMD_FLAG_ALL_CLEAN;
3525 cache->pending_flush_bits &= ~TU_CMD_FLAG_ALL_CLEAN;
3526 }
3527
3528 template <chip CHIP>
3529 VKAPI_ATTR VkResult VKAPI_CALL
tu_EndCommandBuffer(VkCommandBuffer commandBuffer)3530 tu_EndCommandBuffer(VkCommandBuffer commandBuffer)
3531 {
3532 VK_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
3533
3534 /* We currently flush CCU at the end of the command buffer, like
3535 * what the blob does. There's implicit synchronization around every
3536 * vkQueueSubmit, but the kernel only flushes the UCHE, and we don't
3537 * know yet if this command buffer will be the last in the submit so we
3538 * have to defensively flush everything else.
3539 *
3540 * TODO: We could definitely do better than this, since these flushes
3541 * aren't required by Vulkan, but we'd need kernel support to do that.
3542 * Ideally, we'd like the kernel to flush everything afterwards, so that we
3543 * wouldn't have to do any flushes here, and when submitting multiple
3544 * command buffers there wouldn't be any unnecessary flushes in between.
3545 */
3546 if (cmd_buffer->state.pass) {
3547 tu_clean_all_pending(&cmd_buffer->state.renderpass_cache);
3548 tu_emit_cache_flush_renderpass<CHIP>(cmd_buffer);
3549
3550 trace_end_cmd_buffer(&cmd_buffer->trace, &cmd_buffer->draw_cs);
3551 } else {
3552 tu_clean_all_pending(&cmd_buffer->state.cache);
3553 cmd_buffer->state.cache.flush_bits |=
3554 TU_CMD_FLAG_CCU_CLEAN_COLOR |
3555 TU_CMD_FLAG_CCU_CLEAN_DEPTH;
3556 tu_emit_cache_flush<CHIP>(cmd_buffer);
3557
3558 trace_end_cmd_buffer(&cmd_buffer->trace, &cmd_buffer->cs);
3559 }
3560
3561 tu_cs_end(&cmd_buffer->cs);
3562 tu_cs_end(&cmd_buffer->draw_cs);
3563 tu_cs_end(&cmd_buffer->draw_epilogue_cs);
3564
3565 return vk_command_buffer_end(&cmd_buffer->vk);
3566 }
3567 TU_GENX(tu_EndCommandBuffer);
3568
3569 static void
tu_bind_vs(struct tu_cmd_buffer * cmd,struct tu_shader * vs)3570 tu_bind_vs(struct tu_cmd_buffer *cmd, struct tu_shader *vs)
3571 {
3572 cmd->state.shaders[MESA_SHADER_VERTEX] = vs;
3573 }
3574
3575 static void
tu_bind_tcs(struct tu_cmd_buffer * cmd,struct tu_shader * tcs)3576 tu_bind_tcs(struct tu_cmd_buffer *cmd, struct tu_shader *tcs)
3577 {
3578 cmd->state.shaders[MESA_SHADER_TESS_CTRL] = tcs;
3579 }
3580
3581 static void
tu_bind_tes(struct tu_cmd_buffer * cmd,struct tu_shader * tes)3582 tu_bind_tes(struct tu_cmd_buffer *cmd, struct tu_shader *tes)
3583 {
3584 if (cmd->state.shaders[MESA_SHADER_TESS_EVAL] != tes) {
3585 cmd->state.shaders[MESA_SHADER_TESS_EVAL] = tes;
3586 cmd->state.dirty |= TU_CMD_DIRTY_TES;
3587
3588 if (!cmd->state.tess_params.valid ||
3589 cmd->state.tess_params.output_upper_left !=
3590 tes->tes.tess_output_upper_left ||
3591 cmd->state.tess_params.output_lower_left !=
3592 tes->tes.tess_output_lower_left ||
3593 cmd->state.tess_params.spacing != tes->tes.tess_spacing) {
3594 cmd->state.tess_params.output_upper_left =
3595 tes->tes.tess_output_upper_left;
3596 cmd->state.tess_params.output_lower_left =
3597 tes->tes.tess_output_lower_left;
3598 cmd->state.tess_params.spacing = tes->tes.tess_spacing;
3599 cmd->state.tess_params.valid = true;
3600 cmd->state.dirty |= TU_CMD_DIRTY_TESS_PARAMS;
3601 }
3602 }
3603 }
3604
3605 static void
tu_bind_gs(struct tu_cmd_buffer * cmd,struct tu_shader * gs)3606 tu_bind_gs(struct tu_cmd_buffer *cmd, struct tu_shader *gs)
3607 {
3608 cmd->state.shaders[MESA_SHADER_GEOMETRY] = gs;
3609 }
3610
3611 static void
tu_bind_fs(struct tu_cmd_buffer * cmd,struct tu_shader * fs)3612 tu_bind_fs(struct tu_cmd_buffer *cmd, struct tu_shader *fs)
3613 {
3614 if (cmd->state.shaders[MESA_SHADER_FRAGMENT] != fs) {
3615 cmd->state.shaders[MESA_SHADER_FRAGMENT] = fs;
3616 cmd->state.dirty |= TU_CMD_DIRTY_LRZ | TU_CMD_DIRTY_FS;
3617 }
3618 }
3619
3620 /* We cannot do this only at pipeline bind time since pipeline
3621 * could have been bound at any time before current renderpass,
3622 * e.g. in the previous renderpass.
3623 */
3624 static void
tu_pipeline_update_rp_state(struct tu_cmd_state * cmd_state)3625 tu_pipeline_update_rp_state(struct tu_cmd_state *cmd_state)
3626 {
3627 if (cmd_state->pipeline_disable_gmem &&
3628 !cmd_state->rp.disable_gmem) {
3629 /* VK_EXT_attachment_feedback_loop_layout allows feedback loop to involve
3630 * not only input attachments but also sampled images or image resources.
3631 * But we cannot just patch gmem for image in the descriptors.
3632 *
3633 * At the moment, in context of DXVK, it is expected that only a few
3634 * drawcalls in a frame would use feedback loop and they would be wrapped
3635 * in their own renderpasses, so it should be ok to force sysmem.
3636 *
3637 * However, there are two further possible optimizations if need would
3638 * arise for other translation layer:
3639 * - Tiling could be enabled if we ensure that there is no barrier in
3640 * the renderpass;
3641 * - Check that both pipeline and attachments agree that feedback loop
3642 * is needed.
3643 */
3644 perf_debug(
3645 cmd->device,
3646 "Disabling gmem due to VK_EXT_attachment_feedback_loop_layout");
3647 cmd_state->rp.disable_gmem = true;
3648 }
3649
3650 if (cmd_state->pipeline_sysmem_single_prim_mode &&
3651 !cmd_state->rp.sysmem_single_prim_mode) {
3652 perf_debug(cmd->device, "single_prim_mode due to pipeline settings");
3653 cmd_state->rp.sysmem_single_prim_mode = true;
3654 }
3655
3656 if (cmd_state->pipeline_has_tess) {
3657 cmd_state->rp.has_tess = true;
3658 }
3659 }
3660
3661 VKAPI_ATTR void VKAPI_CALL
tu_CmdBindPipeline(VkCommandBuffer commandBuffer,VkPipelineBindPoint pipelineBindPoint,VkPipeline _pipeline)3662 tu_CmdBindPipeline(VkCommandBuffer commandBuffer,
3663 VkPipelineBindPoint pipelineBindPoint,
3664 VkPipeline _pipeline)
3665 {
3666 VK_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
3667 VK_FROM_HANDLE(tu_pipeline, pipeline, _pipeline);
3668
3669 if (pipelineBindPoint == VK_PIPELINE_BIND_POINT_COMPUTE) {
3670 cmd->state.shaders[MESA_SHADER_COMPUTE] =
3671 pipeline->shaders[MESA_SHADER_COMPUTE];
3672 tu_cs_emit_state_ib(&cmd->cs,
3673 pipeline->shaders[MESA_SHADER_COMPUTE]->state);
3674 cmd->state.compute_load_state = pipeline->load_state;
3675 return;
3676 }
3677
3678 assert(pipelineBindPoint == VK_PIPELINE_BIND_POINT_GRAPHICS);
3679
3680 struct tu_graphics_pipeline *gfx_pipeline = tu_pipeline_to_graphics(pipeline);
3681 cmd->state.dirty |= TU_CMD_DIRTY_DESC_SETS | TU_CMD_DIRTY_SHADER_CONSTS |
3682 TU_CMD_DIRTY_VS_PARAMS | TU_CMD_DIRTY_PROGRAM;
3683
3684 tu_bind_vs(cmd, pipeline->shaders[MESA_SHADER_VERTEX]);
3685 tu_bind_tcs(cmd, pipeline->shaders[MESA_SHADER_TESS_CTRL]);
3686 tu_bind_tes(cmd, pipeline->shaders[MESA_SHADER_TESS_EVAL]);
3687 tu_bind_gs(cmd, pipeline->shaders[MESA_SHADER_GEOMETRY]);
3688 tu_bind_fs(cmd, pipeline->shaders[MESA_SHADER_FRAGMENT]);
3689
3690 /* We precompile static state and count it as dynamic, so we have to
3691 * manually clear bitset that tells which dynamic state is set, in order to
3692 * make sure that future dynamic state will be emitted. The issue is that
3693 * framework remembers only a past REAL dynamic state and compares a new
3694 * dynamic state against it, and not against our static state masquaraded
3695 * as dynamic.
3696 */
3697 BITSET_ANDNOT(cmd->vk.dynamic_graphics_state.set,
3698 cmd->vk.dynamic_graphics_state.set,
3699 pipeline->static_state_mask);
3700
3701 vk_cmd_set_dynamic_graphics_state(&cmd->vk,
3702 &gfx_pipeline->dynamic_state);
3703 cmd->state.program = pipeline->program;
3704
3705 cmd->state.load_state = pipeline->load_state;
3706 cmd->state.prim_order_gmem = pipeline->prim_order.state_gmem;
3707 cmd->state.pipeline_sysmem_single_prim_mode = pipeline->prim_order.sysmem_single_prim_mode;
3708 cmd->state.pipeline_has_tess = pipeline->active_stages & VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT;
3709 cmd->state.pipeline_disable_gmem = gfx_pipeline->feedback_loop_may_involve_textures;
3710
3711 tu_pipeline_update_rp_state(&cmd->state);
3712
3713 if (pipeline->lrz_blend.valid) {
3714 if (cmd->state.blend_reads_dest != pipeline->lrz_blend.reads_dest) {
3715 cmd->state.blend_reads_dest = pipeline->lrz_blend.reads_dest;
3716 cmd->state.dirty |= TU_CMD_DIRTY_LRZ;
3717 }
3718 }
3719 cmd->state.pipeline_blend_lrz = pipeline->lrz_blend.valid;
3720
3721 if (pipeline->bandwidth.valid)
3722 cmd->state.bandwidth = pipeline->bandwidth;
3723 cmd->state.pipeline_bandwidth = pipeline->bandwidth.valid;
3724
3725 struct tu_cs *cs = &cmd->draw_cs;
3726
3727 /* note: this also avoids emitting draw states before renderpass clears,
3728 * which may use the 3D clear path (for MSAA cases)
3729 */
3730 if (!(cmd->state.dirty & TU_CMD_DIRTY_DRAW_STATE)) {
3731 uint32_t mask = pipeline->set_state_mask;
3732
3733 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3 * (10 + util_bitcount(mask)));
3734 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_PROGRAM_CONFIG, pipeline->program.config_state);
3735 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VS, pipeline->program.vs_state);
3736 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VS_BINNING, pipeline->program.vs_binning_state);
3737 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_HS, pipeline->program.hs_state);
3738 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_DS, pipeline->program.ds_state);
3739 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_GS, pipeline->program.gs_state);
3740 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_GS_BINNING, pipeline->program.gs_binning_state);
3741 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_FS, pipeline->program.fs_state);
3742 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VPC, pipeline->program.vpc_state);
3743 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_PRIM_MODE_GMEM, pipeline->prim_order.state_gmem);
3744
3745 u_foreach_bit(i, mask)
3746 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_DYNAMIC + i, pipeline->dynamic_state[i]);
3747 }
3748
3749 cmd->state.pipeline_draw_states = pipeline->set_state_mask;
3750 u_foreach_bit(i, pipeline->set_state_mask)
3751 cmd->state.dynamic_state[i] = pipeline->dynamic_state[i];
3752
3753 if (pipeline->program.per_view_viewport != cmd->state.per_view_viewport) {
3754 cmd->state.per_view_viewport = pipeline->program.per_view_viewport;
3755 cmd->state.dirty |= TU_CMD_DIRTY_PER_VIEW_VIEWPORT;
3756 }
3757
3758 if (gfx_pipeline->feedback_loops != cmd->state.pipeline_feedback_loops) {
3759 cmd->state.pipeline_feedback_loops = gfx_pipeline->feedback_loops;
3760 cmd->state.dirty |= TU_CMD_DIRTY_FEEDBACK_LOOPS | TU_CMD_DIRTY_LRZ;
3761 }
3762
3763 if (pipeline->program.writes_shading_rate !=
3764 cmd->state.pipeline_writes_shading_rate ||
3765 pipeline->program.reads_shading_rate !=
3766 cmd->state.pipeline_reads_shading_rate ||
3767 pipeline->program.accesses_smask !=
3768 cmd->state.pipeline_accesses_smask) {
3769 cmd->state.pipeline_writes_shading_rate =
3770 pipeline->program.writes_shading_rate;
3771 cmd->state.pipeline_reads_shading_rate =
3772 pipeline->program.reads_shading_rate;
3773 cmd->state.pipeline_accesses_smask =
3774 pipeline->program.accesses_smask;
3775 cmd->state.dirty |= TU_CMD_DIRTY_SHADING_RATE;
3776 }
3777
3778 bool raster_order_attachment_access =
3779 pipeline->output.raster_order_attachment_access ||
3780 pipeline->ds.raster_order_attachment_access;
3781 if (!cmd->state.raster_order_attachment_access_valid ||
3782 raster_order_attachment_access !=
3783 cmd->state.raster_order_attachment_access) {
3784 cmd->state.raster_order_attachment_access =
3785 raster_order_attachment_access;
3786 cmd->state.dirty |= TU_CMD_DIRTY_RAST_ORDER;
3787 cmd->state.raster_order_attachment_access_valid = true;
3788 }
3789 }
3790
3791 void
tu_flush_for_access(struct tu_cache_state * cache,enum tu_cmd_access_mask src_mask,enum tu_cmd_access_mask dst_mask)3792 tu_flush_for_access(struct tu_cache_state *cache,
3793 enum tu_cmd_access_mask src_mask,
3794 enum tu_cmd_access_mask dst_mask)
3795 {
3796 BITMASK_ENUM(tu_cmd_flush_bits) flush_bits = 0;
3797
3798 if (src_mask & TU_ACCESS_SYSMEM_WRITE) {
3799 cache->pending_flush_bits |= TU_CMD_FLAG_ALL_INVALIDATE;
3800 }
3801
3802 if (src_mask & TU_ACCESS_CP_WRITE) {
3803 /* Flush the CP write queue.
3804 */
3805 cache->pending_flush_bits |=
3806 TU_CMD_FLAG_WAIT_MEM_WRITES |
3807 TU_CMD_FLAG_ALL_INVALIDATE;
3808 }
3809
3810 #define SRC_FLUSH(domain, clean, invalidate) \
3811 if (src_mask & TU_ACCESS_##domain##_WRITE) { \
3812 cache->pending_flush_bits |= TU_CMD_FLAG_##clean | \
3813 (TU_CMD_FLAG_ALL_INVALIDATE & ~TU_CMD_FLAG_##invalidate); \
3814 }
3815
3816 SRC_FLUSH(UCHE, CACHE_CLEAN, CACHE_INVALIDATE)
3817 SRC_FLUSH(CCU_COLOR, CCU_CLEAN_COLOR, CCU_INVALIDATE_COLOR)
3818 SRC_FLUSH(CCU_DEPTH, CCU_CLEAN_DEPTH, CCU_INVALIDATE_DEPTH)
3819
3820 #undef SRC_FLUSH
3821
3822 #define SRC_INCOHERENT_FLUSH(domain, clean, invalidate) \
3823 if (src_mask & TU_ACCESS_##domain##_INCOHERENT_WRITE) { \
3824 flush_bits |= TU_CMD_FLAG_##clean; \
3825 cache->pending_flush_bits |= \
3826 (TU_CMD_FLAG_ALL_INVALIDATE & ~TU_CMD_FLAG_##invalidate); \
3827 }
3828
3829 SRC_INCOHERENT_FLUSH(CCU_COLOR, CCU_CLEAN_COLOR, CCU_INVALIDATE_COLOR)
3830 SRC_INCOHERENT_FLUSH(CCU_DEPTH, CCU_CLEAN_DEPTH, CCU_INVALIDATE_DEPTH)
3831
3832 #undef SRC_INCOHERENT_FLUSH
3833
3834 /* Treat host & sysmem write accesses the same, since the kernel implicitly
3835 * drains the queue before signalling completion to the host.
3836 */
3837 if (dst_mask & (TU_ACCESS_SYSMEM_READ | TU_ACCESS_SYSMEM_WRITE)) {
3838 flush_bits |= cache->pending_flush_bits & TU_CMD_FLAG_ALL_CLEAN;
3839 }
3840
3841 #define DST_FLUSH(domain, clean, invalidate) \
3842 if (dst_mask & (TU_ACCESS_##domain##_READ | \
3843 TU_ACCESS_##domain##_WRITE)) { \
3844 flush_bits |= cache->pending_flush_bits & \
3845 (TU_CMD_FLAG_##invalidate | \
3846 (TU_CMD_FLAG_ALL_CLEAN & ~TU_CMD_FLAG_##clean)); \
3847 }
3848
3849 DST_FLUSH(UCHE, CACHE_CLEAN, CACHE_INVALIDATE)
3850 DST_FLUSH(CCU_COLOR, CCU_CLEAN_COLOR, CCU_INVALIDATE_COLOR)
3851 DST_FLUSH(CCU_DEPTH, CCU_CLEAN_DEPTH, CCU_INVALIDATE_DEPTH)
3852
3853 #undef DST_FLUSH
3854
3855 #define DST_INCOHERENT_FLUSH(domain, flush, invalidate) \
3856 if (dst_mask & (TU_ACCESS_##domain##_INCOHERENT_READ | \
3857 TU_ACCESS_##domain##_INCOHERENT_WRITE)) { \
3858 flush_bits |= TU_CMD_FLAG_##invalidate | \
3859 (cache->pending_flush_bits & \
3860 (TU_CMD_FLAG_ALL_CLEAN & ~TU_CMD_FLAG_##flush)); \
3861 }
3862
3863 DST_INCOHERENT_FLUSH(CCU_COLOR, CCU_CLEAN_COLOR, CCU_INVALIDATE_COLOR)
3864 DST_INCOHERENT_FLUSH(CCU_DEPTH, CCU_CLEAN_DEPTH, CCU_INVALIDATE_DEPTH)
3865
3866 if (dst_mask & TU_ACCESS_BINDLESS_DESCRIPTOR_READ) {
3867 flush_bits |= TU_CMD_FLAG_BINDLESS_DESCRIPTOR_INVALIDATE;
3868 }
3869
3870 /* There are multiple incoherent copies of CCHE, so any read through it may
3871 * require invalidating it and we cannot optimize away invalidates.
3872 */
3873 if (dst_mask & TU_ACCESS_CCHE_READ) {
3874 flush_bits |= TU_CMD_FLAG_CCHE_INVALIDATE;
3875 }
3876
3877 /* The blit cache is a special case dependency between CP_EVENT_WRITE::BLIT
3878 * (from GMEM loads/clears) to any GMEM attachment reads done via the UCHE
3879 * (Eg: Input attachments/CP_BLIT) which needs an explicit BLIT_CACHE_CLEAN
3880 * for the event blit writes to land, it has the following properties:
3881 * - Set on reads rather than on writes, like flushes.
3882 * - Not executed automatically if pending, like invalidates.
3883 * - Pending bits passed through to secondary command buffers, if they're
3884 * continuing the render pass.
3885 */
3886 if (src_mask & TU_ACCESS_BLIT_WRITE_GMEM) {
3887 cache->pending_flush_bits |= TU_CMD_FLAG_BLIT_CACHE_CLEAN;
3888 }
3889
3890 if ((dst_mask & TU_ACCESS_UCHE_READ_GMEM) &&
3891 (cache->pending_flush_bits & TU_CMD_FLAG_BLIT_CACHE_CLEAN)) {
3892 flush_bits |= TU_CMD_FLAG_BLIT_CACHE_CLEAN;
3893 }
3894
3895 /* Nothing writes through the RTU cache so there's no point trying to
3896 * optimize this. Just always invalidate.
3897 */
3898 if (dst_mask & TU_ACCESS_RTU_READ)
3899 flush_bits |= TU_CMD_FLAG_RTU_INVALIDATE;
3900
3901 #undef DST_INCOHERENT_FLUSH
3902
3903 cache->flush_bits |= flush_bits;
3904 cache->pending_flush_bits &= ~flush_bits;
3905 }
3906
3907 /* When translating Vulkan access flags to which cache is accessed
3908 * (CCU/UCHE/sysmem), we should take into account both the access flags and
3909 * the stage so that accesses with MEMORY_READ_BIT/MEMORY_WRITE_BIT + a
3910 * specific stage return something sensible. The specification for
3911 * VK_KHR_synchronization2 says that we should do this:
3912 *
3913 * Additionally, scoping the pipeline stages into the barrier structs
3914 * allows the use of the MEMORY_READ and MEMORY_WRITE flags without
3915 * sacrificing precision. The per-stage access flags should be used to
3916 * disambiguate specific accesses in a given stage or set of stages - for
3917 * instance, between uniform reads and sampling operations.
3918 *
3919 * Note that while in all known cases the stage is actually enough, we should
3920 * still narrow things down based on the access flags to handle "old-style"
3921 * barriers that may specify a wider range of stages but more precise access
3922 * flags. These helpers allow us to do both.
3923 */
3924
3925 static bool
filter_read_access(VkAccessFlags2 flags,VkPipelineStageFlags2 stages,VkAccessFlags2 tu_flags,VkPipelineStageFlags2 tu_stages)3926 filter_read_access(VkAccessFlags2 flags, VkPipelineStageFlags2 stages,
3927 VkAccessFlags2 tu_flags, VkPipelineStageFlags2 tu_stages)
3928 {
3929 return (flags & (tu_flags | VK_ACCESS_2_MEMORY_READ_BIT)) &&
3930 (stages & (tu_stages | VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT));
3931 }
3932
3933 static bool
filter_write_access(VkAccessFlags2 flags,VkPipelineStageFlags2 stages,VkAccessFlags2 tu_flags,VkPipelineStageFlags2 tu_stages)3934 filter_write_access(VkAccessFlags2 flags, VkPipelineStageFlags2 stages,
3935 VkAccessFlags2 tu_flags, VkPipelineStageFlags2 tu_stages)
3936 {
3937 return (flags & (tu_flags | VK_ACCESS_2_MEMORY_WRITE_BIT)) &&
3938 (stages & (tu_stages | VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT));
3939 }
3940
3941 static bool
gfx_read_access(VkAccessFlags2 flags,VkPipelineStageFlags2 stages,VkAccessFlags2 tu_flags,VkPipelineStageFlags2 tu_stages)3942 gfx_read_access(VkAccessFlags2 flags, VkPipelineStageFlags2 stages,
3943 VkAccessFlags2 tu_flags, VkPipelineStageFlags2 tu_stages)
3944 {
3945 return filter_read_access(flags, stages, tu_flags,
3946 tu_stages | VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT);
3947 }
3948
3949 static bool
gfx_write_access(VkAccessFlags2 flags,VkPipelineStageFlags2 stages,VkAccessFlags2 tu_flags,VkPipelineStageFlags2 tu_stages)3950 gfx_write_access(VkAccessFlags2 flags, VkPipelineStageFlags2 stages,
3951 VkAccessFlags2 tu_flags, VkPipelineStageFlags2 tu_stages)
3952 {
3953 return filter_write_access(flags, stages, tu_flags,
3954 tu_stages | VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT);
3955 }
3956
3957 static enum tu_cmd_access_mask
vk2tu_access(VkAccessFlags2 flags,VkPipelineStageFlags2 stages,bool image_only,bool gmem)3958 vk2tu_access(VkAccessFlags2 flags, VkPipelineStageFlags2 stages, bool image_only, bool gmem)
3959 {
3960 BITMASK_ENUM(tu_cmd_access_mask) mask = 0;
3961
3962 if (gfx_read_access(flags, stages,
3963 VK_ACCESS_2_INDIRECT_COMMAND_READ_BIT |
3964 VK_ACCESS_2_CONDITIONAL_RENDERING_READ_BIT_EXT |
3965 VK_ACCESS_2_TRANSFORM_FEEDBACK_COUNTER_READ_BIT_EXT |
3966 VK_ACCESS_2_HOST_READ_BIT,
3967 VK_PIPELINE_STAGE_2_DRAW_INDIRECT_BIT |
3968 VK_PIPELINE_STAGE_2_CONDITIONAL_RENDERING_BIT_EXT |
3969 VK_PIPELINE_STAGE_2_TRANSFORM_FEEDBACK_BIT_EXT |
3970 VK_PIPELINE_STAGE_2_HOST_BIT))
3971 mask |= TU_ACCESS_SYSMEM_READ;
3972
3973 if (gfx_write_access(flags, stages,
3974 VK_ACCESS_2_TRANSFORM_FEEDBACK_COUNTER_READ_BIT_EXT,
3975 VK_PIPELINE_STAGE_2_TRANSFORM_FEEDBACK_BIT_EXT))
3976 mask |= TU_ACCESS_CP_WRITE;
3977
3978 if (gfx_write_access(flags, stages,
3979 VK_ACCESS_2_HOST_WRITE_BIT,
3980 VK_PIPELINE_STAGE_2_HOST_BIT))
3981 mask |= TU_ACCESS_SYSMEM_WRITE;
3982
3983 #define SHADER_STAGES \
3984 (VK_PIPELINE_STAGE_2_VERTEX_SHADER_BIT | \
3985 VK_PIPELINE_STAGE_2_TESSELLATION_CONTROL_SHADER_BIT | \
3986 VK_PIPELINE_STAGE_2_TESSELLATION_EVALUATION_SHADER_BIT | \
3987 VK_PIPELINE_STAGE_2_GEOMETRY_SHADER_BIT | \
3988 VK_PIPELINE_STAGE_2_PRE_RASTERIZATION_SHADERS_BIT | \
3989 VK_PIPELINE_STAGE_2_FRAGMENT_SHADER_BIT | \
3990 VK_PIPELINE_STAGE_2_COMPUTE_SHADER_BIT)
3991
3992
3993 if (gfx_read_access(flags, stages,
3994 VK_ACCESS_2_INDEX_READ_BIT |
3995 VK_ACCESS_2_VERTEX_ATTRIBUTE_READ_BIT |
3996 VK_ACCESS_2_UNIFORM_READ_BIT |
3997 VK_ACCESS_2_INPUT_ATTACHMENT_READ_BIT |
3998 VK_ACCESS_2_SHADER_READ_BIT |
3999 VK_ACCESS_2_SHADER_SAMPLED_READ_BIT |
4000 VK_ACCESS_2_SHADER_STORAGE_READ_BIT |
4001 VK_ACCESS_2_SHADER_BINDING_TABLE_READ_BIT_KHR |
4002 VK_ACCESS_2_ACCELERATION_STRUCTURE_READ_BIT_KHR,
4003 VK_PIPELINE_STAGE_2_INDEX_INPUT_BIT |
4004 VK_PIPELINE_STAGE_2_VERTEX_INPUT_BIT |
4005 VK_PIPELINE_STAGE_2_VERTEX_ATTRIBUTE_INPUT_BIT |
4006 VK_PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR |
4007 VK_PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_COPY_BIT_KHR |
4008 SHADER_STAGES))
4009 mask |= TU_ACCESS_UCHE_READ | TU_ACCESS_CCHE_READ;
4010
4011 if (gfx_read_access(flags, stages,
4012 VK_ACCESS_2_ACCELERATION_STRUCTURE_READ_BIT_KHR,
4013 SHADER_STAGES))
4014 mask |= TU_ACCESS_UCHE_READ | TU_ACCESS_CCHE_READ | TU_ACCESS_RTU_READ;
4015
4016 /* Reading the AS for copying involves doing CmdDispatchIndirect with the
4017 * copy size as a parameter, so it's read by the CP as well as a shader.
4018 */
4019 if (gfx_read_access(flags, stages,
4020 VK_ACCESS_2_ACCELERATION_STRUCTURE_READ_BIT_KHR,
4021 VK_PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR |
4022 VK_PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_COPY_BIT_KHR))
4023 mask |= TU_ACCESS_SYSMEM_READ | TU_ACCESS_UCHE_READ |
4024 TU_ACCESS_CCHE_READ;
4025
4026
4027 if (gfx_read_access(flags, stages,
4028 VK_ACCESS_2_INPUT_ATTACHMENT_READ_BIT,
4029 SHADER_STAGES))
4030 mask |= TU_ACCESS_UCHE_READ_GMEM;
4031
4032 if (gfx_read_access(flags, stages,
4033 VK_ACCESS_2_DESCRIPTOR_BUFFER_READ_BIT_EXT,
4034 SHADER_STAGES)) {
4035 mask |= TU_ACCESS_UCHE_READ | TU_ACCESS_BINDLESS_DESCRIPTOR_READ |
4036 TU_ACCESS_CCHE_READ;
4037 }
4038
4039 if (gfx_write_access(flags, stages,
4040 VK_ACCESS_2_SHADER_WRITE_BIT |
4041 VK_ACCESS_2_SHADER_STORAGE_WRITE_BIT |
4042 VK_ACCESS_2_TRANSFORM_FEEDBACK_WRITE_BIT_EXT,
4043 VK_PIPELINE_STAGE_2_TRANSFORM_FEEDBACK_BIT_EXT |
4044 SHADER_STAGES))
4045 mask |= TU_ACCESS_UCHE_WRITE;
4046
4047 if (gfx_write_access(flags, stages,
4048 VK_ACCESS_2_ACCELERATION_STRUCTURE_WRITE_BIT_KHR,
4049 VK_PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR))
4050 mask |= TU_ACCESS_UCHE_WRITE | TU_ACCESS_CP_WRITE;
4051
4052 /* When using GMEM, the CCU is always flushed automatically to GMEM, and
4053 * then GMEM is flushed to sysmem. Furthermore, we already had to flush any
4054 * previous writes in sysmem mode when transitioning to GMEM. Therefore we
4055 * can ignore CCU and pretend that color attachments and transfers use
4056 * sysmem directly.
4057 */
4058
4059 if (gfx_read_access(flags, stages,
4060 VK_ACCESS_2_COLOR_ATTACHMENT_READ_BIT |
4061 VK_ACCESS_2_COLOR_ATTACHMENT_READ_NONCOHERENT_BIT_EXT,
4062 VK_PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT)) {
4063 if (gmem)
4064 mask |= TU_ACCESS_SYSMEM_READ;
4065 else
4066 mask |= TU_ACCESS_CCU_COLOR_INCOHERENT_READ;
4067 }
4068
4069 if (gfx_read_access(flags, stages,
4070 VK_ACCESS_2_DEPTH_STENCIL_ATTACHMENT_READ_BIT,
4071 VK_PIPELINE_STAGE_2_EARLY_FRAGMENT_TESTS_BIT |
4072 VK_PIPELINE_STAGE_2_LATE_FRAGMENT_TESTS_BIT)) {
4073 if (gmem)
4074 mask |= TU_ACCESS_SYSMEM_READ;
4075 else
4076 mask |= TU_ACCESS_CCU_DEPTH_INCOHERENT_READ;
4077 }
4078
4079 if (gfx_write_access(flags, stages,
4080 VK_ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT,
4081 VK_PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT)) {
4082 if (gmem) {
4083 mask |= TU_ACCESS_SYSMEM_WRITE;
4084 } else {
4085 mask |= TU_ACCESS_CCU_COLOR_INCOHERENT_WRITE;
4086 }
4087 }
4088
4089 if (gfx_write_access(flags, stages,
4090 VK_ACCESS_2_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT,
4091 VK_PIPELINE_STAGE_2_EARLY_FRAGMENT_TESTS_BIT |
4092 VK_PIPELINE_STAGE_2_LATE_FRAGMENT_TESTS_BIT)) {
4093 if (gmem) {
4094 mask |= TU_ACCESS_SYSMEM_WRITE;
4095 } else {
4096 mask |= TU_ACCESS_CCU_DEPTH_INCOHERENT_WRITE;
4097 }
4098 }
4099
4100 if (filter_write_access(flags, stages,
4101 VK_ACCESS_2_TRANSFER_WRITE_BIT,
4102 VK_PIPELINE_STAGE_2_COPY_BIT |
4103 VK_PIPELINE_STAGE_2_BLIT_BIT |
4104 VK_PIPELINE_STAGE_2_CLEAR_BIT |
4105 VK_PIPELINE_STAGE_2_RESOLVE_BIT |
4106 VK_PIPELINE_STAGE_2_ALL_TRANSFER_BIT)) {
4107 if (gmem) {
4108 mask |= TU_ACCESS_SYSMEM_WRITE;
4109 } else if (image_only) {
4110 /* Because we always split up blits/copies of images involving
4111 * multiple layers, we always access each layer in the same way, with
4112 * the same base address, same format, etc. This means we can avoid
4113 * flushing between multiple writes to the same image. This elides
4114 * flushes between e.g. multiple blits to the same image.
4115 */
4116 mask |= TU_ACCESS_CCU_COLOR_WRITE;
4117 } else {
4118 mask |= TU_ACCESS_CCU_COLOR_INCOHERENT_WRITE;
4119 }
4120 }
4121
4122 if (filter_read_access(flags, stages,
4123 VK_ACCESS_2_TRANSFER_READ_BIT,
4124 VK_PIPELINE_STAGE_2_COPY_BIT |
4125 VK_PIPELINE_STAGE_2_BLIT_BIT |
4126 VK_PIPELINE_STAGE_2_RESOLVE_BIT |
4127 VK_PIPELINE_STAGE_2_ALL_TRANSFER_BIT)) {
4128 mask |= TU_ACCESS_UCHE_READ | TU_ACCESS_CCHE_READ;
4129 }
4130
4131 return mask;
4132 }
4133
4134 /* These helpers deal with legacy BOTTOM_OF_PIPE/TOP_OF_PIPE stages.
4135 */
4136
4137 static VkPipelineStageFlags2
sanitize_src_stage(VkPipelineStageFlags2 stage_mask)4138 sanitize_src_stage(VkPipelineStageFlags2 stage_mask)
4139 {
4140 /* From the Vulkan spec:
4141 *
4142 * VK_PIPELINE_STAGE_2_TOP_OF_PIPE_BIT is ... equivalent to
4143 * VK_PIPELINE_STAGE_2_NONE in the first scope.
4144 *
4145 * VK_PIPELINE_STAGE_2_BOTTOM_OF_PIPE_BIT is equivalent to
4146 * VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT with VkAccessFlags2 set to 0
4147 * when specified in the first synchronization scope, ...
4148 */
4149 if (stage_mask & VK_PIPELINE_STAGE_2_BOTTOM_OF_PIPE_BIT)
4150 return VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT;
4151
4152 return stage_mask & ~VK_PIPELINE_STAGE_2_TOP_OF_PIPE_BIT;
4153 }
4154
4155 static VkPipelineStageFlags2
sanitize_dst_stage(VkPipelineStageFlags2 stage_mask)4156 sanitize_dst_stage(VkPipelineStageFlags2 stage_mask)
4157 {
4158 /* From the Vulkan spec:
4159 *
4160 * VK_PIPELINE_STAGE_2_TOP_OF_PIPE_BIT is equivalent to
4161 * VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT with VkAccessFlags2 set to 0
4162 * when specified in the second synchronization scope, ...
4163 *
4164 * VK_PIPELINE_STAGE_2_BOTTOM_OF_PIPE_BIT is ... equivalent to
4165 * VK_PIPELINE_STAGE_2_NONE in the second scope.
4166 *
4167 */
4168 if (stage_mask & VK_PIPELINE_STAGE_2_TOP_OF_PIPE_BIT)
4169 return VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT;
4170
4171 return stage_mask & ~VK_PIPELINE_STAGE_2_BOTTOM_OF_PIPE_BIT;
4172 }
4173
4174 static enum tu_stage
vk2tu_single_stage(VkPipelineStageFlags2 vk_stage,bool dst)4175 vk2tu_single_stage(VkPipelineStageFlags2 vk_stage, bool dst)
4176 {
4177 /* If the destination stage is executed on the CP, then the CP also has to
4178 * wait for any WFI's to finish. This is already done for draw calls,
4179 * including before indirect param reads, for the most part, so we just
4180 * need to WFI and can use TU_STAGE_GPU.
4181 *
4182 * However, some indirect draw opcodes, depending on firmware, don't have
4183 * implicit CP_WAIT_FOR_ME so we have to handle it manually.
4184 *
4185 * Transform feedback counters are read via CP_MEM_TO_REG, which implicitly
4186 * does CP_WAIT_FOR_ME, so we don't include them here.
4187 *
4188 * Currently we read the draw predicate using CP_MEM_TO_MEM, which
4189 * also implicitly does CP_WAIT_FOR_ME. However CP_DRAW_PRED_SET does *not*
4190 * implicitly do CP_WAIT_FOR_ME, it seems to only wait for counters to
4191 * complete since it's written for DX11 where you can only predicate on the
4192 * result of a query object. So if we implement 64-bit comparisons in the
4193 * future, or if CP_DRAW_PRED_SET grows the capability to do 32-bit
4194 * comparisons, then this will have to be dealt with.
4195 */
4196 if (vk_stage == VK_PIPELINE_STAGE_2_DRAW_INDIRECT_BIT ||
4197 vk_stage == VK_PIPELINE_STAGE_2_CONDITIONAL_RENDERING_BIT_EXT ||
4198 vk_stage == VK_PIPELINE_STAGE_2_FRAGMENT_DENSITY_PROCESS_BIT_EXT)
4199 return TU_STAGE_CP;
4200
4201 if (vk_stage == VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT ||
4202 vk_stage == VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT)
4203 return dst ? TU_STAGE_CP : TU_STAGE_GPU;
4204
4205 if (vk_stage == VK_PIPELINE_STAGE_2_HOST_BIT)
4206 return dst ? TU_STAGE_BOTTOM : TU_STAGE_CP;
4207
4208 return TU_STAGE_GPU;
4209 }
4210
4211 static enum tu_stage
vk2tu_src_stage(VkPipelineStageFlags2 vk_stages)4212 vk2tu_src_stage(VkPipelineStageFlags2 vk_stages)
4213 {
4214 enum tu_stage stage = TU_STAGE_CP;
4215 u_foreach_bit64 (bit, vk_stages) {
4216 enum tu_stage new_stage = vk2tu_single_stage(1ull << bit, false);
4217 stage = MAX2(stage, new_stage);
4218 }
4219
4220 return stage;
4221 }
4222
4223 static enum tu_stage
vk2tu_dst_stage(VkPipelineStageFlags2 vk_stages)4224 vk2tu_dst_stage(VkPipelineStageFlags2 vk_stages)
4225 {
4226 enum tu_stage stage = TU_STAGE_BOTTOM;
4227 u_foreach_bit64 (bit, vk_stages) {
4228 enum tu_stage new_stage = vk2tu_single_stage(1ull << bit, true);
4229 stage = MIN2(stage, new_stage);
4230 }
4231
4232 return stage;
4233 }
4234
4235 static void
tu_flush_for_stage(struct tu_cache_state * cache,enum tu_stage src_stage,enum tu_stage dst_stage)4236 tu_flush_for_stage(struct tu_cache_state *cache,
4237 enum tu_stage src_stage, enum tu_stage dst_stage)
4238 {
4239 /* Even if the source is the host or CP, the destination access could
4240 * generate invalidates that we have to wait to complete.
4241 */
4242 if (src_stage == TU_STAGE_CP &&
4243 (cache->flush_bits & TU_CMD_FLAG_ALL_INVALIDATE))
4244 src_stage = TU_STAGE_GPU;
4245
4246 if (src_stage >= dst_stage) {
4247 cache->flush_bits |= TU_CMD_FLAG_WAIT_FOR_IDLE;
4248 if (dst_stage == TU_STAGE_CP)
4249 cache->pending_flush_bits |= TU_CMD_FLAG_WAIT_FOR_ME;
4250 }
4251 }
4252
4253 void
tu_render_pass_state_merge(struct tu_render_pass_state * dst,const struct tu_render_pass_state * src)4254 tu_render_pass_state_merge(struct tu_render_pass_state *dst,
4255 const struct tu_render_pass_state *src)
4256 {
4257 dst->xfb_used |= src->xfb_used;
4258 dst->has_tess |= src->has_tess;
4259 dst->has_prim_generated_query_in_rp |= src->has_prim_generated_query_in_rp;
4260 dst->has_zpass_done_sample_count_write_in_rp |= src->has_zpass_done_sample_count_write_in_rp;
4261 dst->disable_gmem |= src->disable_gmem;
4262 dst->sysmem_single_prim_mode |= src->sysmem_single_prim_mode;
4263 dst->draw_cs_writes_to_cond_pred |= src->draw_cs_writes_to_cond_pred;
4264 dst->shared_viewport |= src->shared_viewport;
4265
4266 dst->drawcall_count += src->drawcall_count;
4267 dst->drawcall_bandwidth_per_sample_sum +=
4268 src->drawcall_bandwidth_per_sample_sum;
4269 if (!dst->lrz_disable_reason && src->lrz_disable_reason) {
4270 dst->lrz_disable_reason = src->lrz_disable_reason;
4271 dst->lrz_disabled_at_draw =
4272 dst->drawcall_count + src->lrz_disabled_at_draw;
4273 }
4274 }
4275
4276 void
tu_restore_suspended_pass(struct tu_cmd_buffer * cmd,struct tu_cmd_buffer * suspended)4277 tu_restore_suspended_pass(struct tu_cmd_buffer *cmd,
4278 struct tu_cmd_buffer *suspended)
4279 {
4280 cmd->state.pass = suspended->state.suspended_pass.pass;
4281 cmd->state.subpass = suspended->state.suspended_pass.subpass;
4282 cmd->state.framebuffer = suspended->state.suspended_pass.framebuffer;
4283 cmd->state.attachments = suspended->state.suspended_pass.attachments;
4284 cmd->state.clear_values = suspended->state.suspended_pass.clear_values;
4285 cmd->state.render_area = suspended->state.suspended_pass.render_area;
4286 cmd->state.gmem_layout = suspended->state.suspended_pass.gmem_layout;
4287 cmd->state.tiling = &cmd->state.framebuffer->tiling[cmd->state.gmem_layout];
4288 cmd->state.lrz = suspended->state.suspended_pass.lrz;
4289 }
4290
4291 /* Take the saved pre-chain in "secondary" and copy its commands to "cmd",
4292 * appending it after any saved-up commands in "cmd".
4293 */
4294 void
tu_append_pre_chain(struct tu_cmd_buffer * cmd,struct tu_cmd_buffer * secondary)4295 tu_append_pre_chain(struct tu_cmd_buffer *cmd,
4296 struct tu_cmd_buffer *secondary)
4297 {
4298 tu_cs_add_entries(&cmd->draw_cs, &secondary->pre_chain.draw_cs);
4299 tu_cs_add_entries(&cmd->draw_epilogue_cs,
4300 &secondary->pre_chain.draw_epilogue_cs);
4301
4302 tu_render_pass_state_merge(&cmd->state.rp,
4303 &secondary->pre_chain.state);
4304 tu_clone_trace_range(cmd, &cmd->draw_cs, secondary->pre_chain.trace_renderpass_start,
4305 secondary->pre_chain.trace_renderpass_end);
4306 util_dynarray_append_dynarray(&cmd->fdm_bin_patchpoints,
4307 &secondary->pre_chain.fdm_bin_patchpoints);
4308 }
4309
4310 /* Take the saved post-chain in "secondary" and copy it to "cmd".
4311 */
4312 void
tu_append_post_chain(struct tu_cmd_buffer * cmd,struct tu_cmd_buffer * secondary)4313 tu_append_post_chain(struct tu_cmd_buffer *cmd,
4314 struct tu_cmd_buffer *secondary)
4315 {
4316 tu_cs_add_entries(&cmd->draw_cs, &secondary->draw_cs);
4317 tu_cs_add_entries(&cmd->draw_epilogue_cs, &secondary->draw_epilogue_cs);
4318
4319 tu_clone_trace_range(cmd, &cmd->draw_cs, secondary->trace_renderpass_start,
4320 secondary->trace_renderpass_end);
4321 cmd->state.rp = secondary->state.rp;
4322 util_dynarray_append_dynarray(&cmd->fdm_bin_patchpoints,
4323 &secondary->fdm_bin_patchpoints);
4324 }
4325
4326 /* Assuming "secondary" is just a sequence of suspended and resuming passes,
4327 * copy its state to "cmd". This also works instead of tu_append_post_chain(),
4328 * but it's a bit slower because we don't assume that the chain begins in
4329 * "secondary" and therefore have to care about the command buffer's
4330 * renderpass state.
4331 */
4332 void
tu_append_pre_post_chain(struct tu_cmd_buffer * cmd,struct tu_cmd_buffer * secondary)4333 tu_append_pre_post_chain(struct tu_cmd_buffer *cmd,
4334 struct tu_cmd_buffer *secondary)
4335 {
4336 tu_cs_add_entries(&cmd->draw_cs, &secondary->draw_cs);
4337 tu_cs_add_entries(&cmd->draw_epilogue_cs, &secondary->draw_epilogue_cs);
4338
4339 tu_clone_trace_range(cmd, &cmd->draw_cs, secondary->trace_renderpass_start,
4340 secondary->trace_renderpass_end);
4341 tu_render_pass_state_merge(&cmd->state.rp,
4342 &secondary->state.rp);
4343 util_dynarray_append_dynarray(&cmd->fdm_bin_patchpoints,
4344 &secondary->fdm_bin_patchpoints);
4345 }
4346
4347 /* Take the current render pass state and save it to "pre_chain" to be
4348 * combined later.
4349 */
4350 static void
tu_save_pre_chain(struct tu_cmd_buffer * cmd)4351 tu_save_pre_chain(struct tu_cmd_buffer *cmd)
4352 {
4353 tu_cs_add_entries(&cmd->pre_chain.draw_cs,
4354 &cmd->draw_cs);
4355 tu_cs_add_entries(&cmd->pre_chain.draw_epilogue_cs,
4356 &cmd->draw_epilogue_cs);
4357 cmd->pre_chain.trace_renderpass_start =
4358 cmd->trace_renderpass_start;
4359 cmd->pre_chain.trace_renderpass_end =
4360 cmd->trace_renderpass_end;
4361 cmd->pre_chain.state = cmd->state.rp;
4362 util_dynarray_append_dynarray(&cmd->pre_chain.fdm_bin_patchpoints,
4363 &cmd->fdm_bin_patchpoints);
4364 cmd->pre_chain.patchpoints_ctx = cmd->patchpoints_ctx;
4365 cmd->patchpoints_ctx = NULL;
4366 }
4367
4368 VKAPI_ATTR void VKAPI_CALL
tu_CmdExecuteCommands(VkCommandBuffer commandBuffer,uint32_t commandBufferCount,const VkCommandBuffer * pCmdBuffers)4369 tu_CmdExecuteCommands(VkCommandBuffer commandBuffer,
4370 uint32_t commandBufferCount,
4371 const VkCommandBuffer *pCmdBuffers)
4372 {
4373 VK_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
4374 VkResult result;
4375
4376 assert(commandBufferCount > 0);
4377
4378 /* Emit any pending flushes. */
4379 if (cmd->state.pass) {
4380 tu_clean_all_pending(&cmd->state.renderpass_cache);
4381 TU_CALLX(cmd->device, tu_emit_cache_flush_renderpass)(cmd);
4382 } else {
4383 tu_clean_all_pending(&cmd->state.cache);
4384 TU_CALLX(cmd->device, tu_emit_cache_flush)(cmd);
4385 }
4386
4387 for (uint32_t i = 0; i < commandBufferCount; i++) {
4388 VK_FROM_HANDLE(tu_cmd_buffer, secondary, pCmdBuffers[i]);
4389
4390 if (secondary->usage_flags &
4391 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
4392 assert(tu_cs_is_empty(&secondary->cs));
4393
4394 TU_CALLX(cmd->device, tu_lrz_flush_valid_during_renderpass)
4395 (cmd, &cmd->draw_cs);
4396
4397 result = tu_cs_add_entries(&cmd->draw_cs, &secondary->draw_cs);
4398 if (result != VK_SUCCESS) {
4399 vk_command_buffer_set_error(&cmd->vk, result);
4400 break;
4401 }
4402
4403 result = tu_cs_add_entries(&cmd->draw_epilogue_cs,
4404 &secondary->draw_epilogue_cs);
4405 if (result != VK_SUCCESS) {
4406 vk_command_buffer_set_error(&cmd->vk, result);
4407 break;
4408 }
4409
4410 /* If LRZ was made invalid in secondary - we should disable
4411 * LRZ retroactively for the whole renderpass.
4412 */
4413 if (!secondary->state.lrz.valid)
4414 cmd->state.lrz.valid = false;
4415
4416 tu_clone_trace(cmd, &cmd->draw_cs, &secondary->trace);
4417 tu_render_pass_state_merge(&cmd->state.rp, &secondary->state.rp);
4418 util_dynarray_append_dynarray(&cmd->fdm_bin_patchpoints,
4419 &secondary->fdm_bin_patchpoints);
4420 } else {
4421 switch (secondary->state.suspend_resume) {
4422 case SR_NONE:
4423 assert(tu_cs_is_empty(&secondary->draw_cs));
4424 assert(tu_cs_is_empty(&secondary->draw_epilogue_cs));
4425 tu_cs_add_entries(&cmd->cs, &secondary->cs);
4426 tu_clone_trace(cmd, &cmd->cs, &secondary->trace);
4427 break;
4428
4429 case SR_IN_PRE_CHAIN:
4430 /* cmd may be empty, which means that the chain begins before cmd
4431 * in which case we have to update its state.
4432 */
4433 if (cmd->state.suspend_resume == SR_NONE) {
4434 cmd->state.suspend_resume = SR_IN_PRE_CHAIN;
4435 cmd->trace_renderpass_start = u_trace_end_iterator(&cmd->trace);
4436 }
4437
4438 /* The secondary is just a continuous suspend/resume chain so we
4439 * just have to append it to the the command buffer.
4440 */
4441 assert(tu_cs_is_empty(&secondary->cs));
4442 tu_append_pre_post_chain(cmd, secondary);
4443 break;
4444
4445 case SR_AFTER_PRE_CHAIN:
4446 case SR_IN_CHAIN:
4447 case SR_IN_CHAIN_AFTER_PRE_CHAIN:
4448 if (secondary->state.suspend_resume == SR_AFTER_PRE_CHAIN ||
4449 secondary->state.suspend_resume == SR_IN_CHAIN_AFTER_PRE_CHAIN) {
4450 /* In thse cases there is a `pre_chain` in the secondary which
4451 * ends that we need to append to the primary.
4452 */
4453
4454 if (cmd->state.suspend_resume == SR_NONE)
4455 cmd->trace_renderpass_start = u_trace_end_iterator(&cmd->trace);
4456
4457 tu_append_pre_chain(cmd, secondary);
4458
4459 /* We're about to render, so we need to end the command stream
4460 * in case there were any extra commands generated by copying
4461 * the trace.
4462 */
4463 tu_cs_end(&cmd->draw_cs);
4464 tu_cs_end(&cmd->draw_epilogue_cs);
4465
4466 switch (cmd->state.suspend_resume) {
4467 case SR_NONE:
4468 case SR_IN_PRE_CHAIN:
4469 /* The renderpass chain ends in the secondary but isn't
4470 * started in the primary, so we have to move the state to
4471 * `pre_chain`.
4472 */
4473 cmd->trace_renderpass_end = u_trace_end_iterator(&cmd->trace);
4474 tu_save_pre_chain(cmd);
4475 cmd->state.suspend_resume = SR_AFTER_PRE_CHAIN;
4476 break;
4477 case SR_IN_CHAIN:
4478 case SR_IN_CHAIN_AFTER_PRE_CHAIN:
4479 /* The renderpass ends in the secondary and starts somewhere
4480 * earlier in this primary. Since the last render pass in
4481 * the chain is in the secondary, we are technically outside
4482 * of a render pass. Fix that here by reusing the dynamic
4483 * render pass that was setup for the last suspended render
4484 * pass before the secondary.
4485 */
4486 tu_restore_suspended_pass(cmd, cmd);
4487
4488 TU_CALLX(cmd->device, tu_cmd_render)(cmd);
4489 if (cmd->state.suspend_resume == SR_IN_CHAIN)
4490 cmd->state.suspend_resume = SR_NONE;
4491 else
4492 cmd->state.suspend_resume = SR_AFTER_PRE_CHAIN;
4493 break;
4494 case SR_AFTER_PRE_CHAIN:
4495 unreachable("resuming render pass is not preceded by suspending one");
4496 }
4497
4498 tu_reset_render_pass(cmd);
4499 }
4500
4501 tu_cs_add_entries(&cmd->cs, &secondary->cs);
4502
4503 if (secondary->state.suspend_resume == SR_IN_CHAIN_AFTER_PRE_CHAIN ||
4504 secondary->state.suspend_resume == SR_IN_CHAIN) {
4505 /* The secondary ends in a "post-chain" (the opposite of a
4506 * pre-chain) that we need to copy into the current command
4507 * buffer.
4508 */
4509 cmd->trace_renderpass_start = u_trace_end_iterator(&cmd->trace);
4510 tu_append_post_chain(cmd, secondary);
4511 cmd->trace_renderpass_end = u_trace_end_iterator(&cmd->trace);
4512 cmd->state.suspended_pass = secondary->state.suspended_pass;
4513
4514 switch (cmd->state.suspend_resume) {
4515 case SR_NONE:
4516 cmd->state.suspend_resume = SR_IN_CHAIN;
4517 break;
4518 case SR_AFTER_PRE_CHAIN:
4519 cmd->state.suspend_resume = SR_IN_CHAIN_AFTER_PRE_CHAIN;
4520 break;
4521 default:
4522 unreachable("suspending render pass is followed by a not resuming one");
4523 }
4524 }
4525 }
4526 }
4527
4528 cmd->state.index_size = secondary->state.index_size; /* for restart index update */
4529 }
4530 cmd->state.dirty = ~0u; /* TODO: set dirty only what needs to be */
4531
4532 if (!cmd->state.lrz.gpu_dir_tracking && cmd->state.pass) {
4533 /* After a secondary command buffer is executed, LRZ is not valid
4534 * until it is cleared again.
4535 */
4536 cmd->state.lrz.valid = false;
4537 }
4538
4539 /* After executing secondary command buffers, there may have been arbitrary
4540 * flushes executed, so when we encounter a pipeline barrier with a
4541 * srcMask, we have to assume that we need to invalidate. Therefore we need
4542 * to re-initialize the cache with all pending invalidate bits set.
4543 */
4544 if (cmd->state.pass) {
4545 struct tu_cache_state *cache = &cmd->state.renderpass_cache;
4546 BITMASK_ENUM(tu_cmd_flush_bits) retained_pending_flush_bits =
4547 cache->pending_flush_bits & TU_CMD_FLAG_BLIT_CACHE_CLEAN;
4548 tu_cache_init(cache);
4549 cache->pending_flush_bits |= retained_pending_flush_bits;
4550 } else {
4551 tu_cache_init(&cmd->state.cache);
4552 }
4553 }
4554
4555 static void
tu_subpass_barrier(struct tu_cmd_buffer * cmd_buffer,const struct tu_subpass_barrier * barrier,bool external)4556 tu_subpass_barrier(struct tu_cmd_buffer *cmd_buffer,
4557 const struct tu_subpass_barrier *barrier,
4558 bool external)
4559 {
4560 /* Note: we don't know until the end of the subpass whether we'll use
4561 * sysmem, so assume sysmem here to be safe.
4562 */
4563 struct tu_cache_state *cache =
4564 external ? &cmd_buffer->state.cache : &cmd_buffer->state.renderpass_cache;
4565 VkPipelineStageFlags2 src_stage_vk =
4566 sanitize_src_stage(barrier->src_stage_mask);
4567 VkPipelineStageFlags2 dst_stage_vk =
4568 sanitize_dst_stage(barrier->dst_stage_mask);
4569 BITMASK_ENUM(tu_cmd_access_mask) src_flags =
4570 vk2tu_access(barrier->src_access_mask, src_stage_vk, false, false);
4571 BITMASK_ENUM(tu_cmd_access_mask) dst_flags =
4572 vk2tu_access(barrier->dst_access_mask, dst_stage_vk, false, false);
4573
4574 if (barrier->incoherent_ccu_color)
4575 src_flags |= TU_ACCESS_CCU_COLOR_INCOHERENT_WRITE;
4576 if (barrier->incoherent_ccu_depth)
4577 src_flags |= TU_ACCESS_CCU_DEPTH_INCOHERENT_WRITE;
4578
4579 tu_flush_for_access(cache, src_flags, dst_flags);
4580
4581 enum tu_stage src_stage = vk2tu_src_stage(src_stage_vk);
4582 enum tu_stage dst_stage = vk2tu_dst_stage(dst_stage_vk);
4583 tu_flush_for_stage(cache, src_stage, dst_stage);
4584 }
4585
4586 template <chip CHIP>
4587 static void
tu_emit_subpass_begin_gmem(struct tu_cmd_buffer * cmd,struct tu_resolve_group * resolve_group)4588 tu_emit_subpass_begin_gmem(struct tu_cmd_buffer *cmd, struct tu_resolve_group *resolve_group)
4589 {
4590 struct tu_cs *cs = &cmd->draw_cs;
4591 uint32_t subpass_idx = cmd->state.subpass - cmd->state.pass->subpasses;
4592
4593 /* If we might choose to bin, then put the loads under a check for geometry
4594 * having been binned to this tile. If we don't choose to bin in the end,
4595 * then we will have manually set those registers to say geometry is present.
4596 *
4597 * However, if the draw CS has a write to the condition for some other reason
4598 * (perf queries), then we can't do this optimization since the
4599 * start-of-the-CS geometry condition will have been overwritten.
4600 */
4601 bool cond_load_allowed = cmd->state.tiling->binning &&
4602 cmd->state.pass->has_cond_load_store &&
4603 !cmd->state.rp.draw_cs_writes_to_cond_pred;
4604
4605 if (cmd->state.pass->has_fdm)
4606 tu_cs_set_writeable(cs, true);
4607
4608 tu_cond_exec_start(cs, CP_COND_EXEC_0_RENDER_MODE_GMEM);
4609
4610 /* Emit gmem loads that are first used in this subpass. */
4611 bool emitted_scissor = false;
4612 for (uint32_t i = 0; i < cmd->state.pass->attachment_count; ++i) {
4613 struct tu_render_pass_attachment *att = &cmd->state.pass->attachments[i];
4614 if ((att->load || att->load_stencil) && att->first_subpass_idx == subpass_idx) {
4615 if (!emitted_scissor) {
4616 tu6_emit_blit_scissor(cmd, cs, true);
4617 emitted_scissor = true;
4618 }
4619 tu_load_gmem_attachment<CHIP>(cmd, cs, resolve_group, i,
4620 cond_load_allowed, false);
4621 }
4622 }
4623
4624 if (!cmd->device->physical_device->info->a7xx.has_generic_clear) {
4625 /* Emit gmem clears that are first used in this subpass. */
4626 emitted_scissor = false;
4627 for (uint32_t i = 0; i < cmd->state.pass->attachment_count; ++i) {
4628 struct tu_render_pass_attachment *att =
4629 &cmd->state.pass->attachments[i];
4630 if (att->clear_mask && att->first_subpass_idx == subpass_idx) {
4631 if (!emitted_scissor) {
4632 tu6_emit_blit_scissor(cmd, cs, false);
4633 emitted_scissor = true;
4634 }
4635 tu_clear_gmem_attachment<CHIP>(cmd, cs, resolve_group, i);
4636 }
4637 }
4638 }
4639
4640 tu_cond_exec_end(cs); /* CP_COND_EXEC_0_RENDER_MODE_GMEM */
4641
4642 if (cmd->state.pass->has_fdm)
4643 tu_cs_set_writeable(cs, false);
4644
4645 }
4646
4647 /* Emits sysmem clears that are first used in this subpass. */
4648 template <chip CHIP>
4649 static void
tu_emit_subpass_begin_sysmem(struct tu_cmd_buffer * cmd)4650 tu_emit_subpass_begin_sysmem(struct tu_cmd_buffer *cmd)
4651 {
4652 if (cmd->device->physical_device->info->a7xx.has_generic_clear)
4653 return;
4654
4655 struct tu_cs *cs = &cmd->draw_cs;
4656 uint32_t subpass_idx = cmd->state.subpass - cmd->state.pass->subpasses;
4657
4658 tu_cond_exec_start(cs, CP_COND_EXEC_0_RENDER_MODE_SYSMEM);
4659 for (uint32_t i = 0; i < cmd->state.pass->attachment_count; ++i) {
4660 struct tu_render_pass_attachment *att = &cmd->state.pass->attachments[i];
4661 if (att->clear_mask && att->first_subpass_idx == subpass_idx)
4662 tu_clear_sysmem_attachment<CHIP>(cmd, cs, i);
4663 }
4664 tu_cond_exec_end(cs); /* sysmem */
4665 }
4666
4667 static void
tu7_emit_subpass_clear(struct tu_cmd_buffer * cmd,struct tu_resolve_group * resolve_group)4668 tu7_emit_subpass_clear(struct tu_cmd_buffer *cmd, struct tu_resolve_group *resolve_group)
4669 {
4670 if (cmd->state.render_area.extent.width == 0 ||
4671 cmd->state.render_area.extent.height == 0)
4672 return;
4673
4674 struct tu_cs *cs = &cmd->draw_cs;
4675 uint32_t subpass_idx = cmd->state.subpass - cmd->state.pass->subpasses;
4676
4677 bool emitted_scissor = false;
4678 for (uint32_t i = 0; i < cmd->state.pass->attachment_count; ++i) {
4679 struct tu_render_pass_attachment *att =
4680 &cmd->state.pass->attachments[i];
4681 if (att->clear_mask && att->first_subpass_idx == subpass_idx) {
4682 if (!emitted_scissor) {
4683 tu6_emit_blit_scissor(cmd, cs, false);
4684 emitted_scissor = true;
4685 }
4686 tu7_generic_clear_attachment(cmd, cs, resolve_group, i);
4687 }
4688 }
4689 }
4690
4691 static void
tu7_emit_subpass_shading_rate(struct tu_cmd_buffer * cmd,const struct tu_subpass * subpass,struct tu_cs * cs)4692 tu7_emit_subpass_shading_rate(struct tu_cmd_buffer *cmd,
4693 const struct tu_subpass *subpass,
4694 struct tu_cs *cs)
4695 {
4696 if (subpass->fsr_attachment == VK_ATTACHMENT_UNUSED) {
4697 tu_cs_emit_regs(cs, A7XX_GRAS_FSR_BUFFER_DESC(),
4698 A7XX_GRAS_FSR_BUFFER_SIZE());
4699 tu_cs_emit_regs(cs, A7XX_GRAS_FSR_BUFFER_PITCH());
4700 tu_cs_emit_regs(cs, A7XX_GRAS_FSR_BUFFER_BASE());
4701 /* We need to invalidate cache when changing to NULL FSR attachment, but
4702 * only once.
4703 */
4704 if (!cmd->prev_fsr_is_null) {
4705 tu_emit_raw_event_write<A7XX>(cmd, cs, LRZ_Q_CACHE_INVALIDATE,
4706 false);
4707 cmd->prev_fsr_is_null = true;
4708 }
4709 return;
4710 }
4711
4712 const struct tu_image_view *iview =
4713 cmd->state.attachments[subpass->fsr_attachment];
4714 assert(iview->vk.format == VK_FORMAT_R8_UINT);
4715
4716 tu_cs_emit_regs(
4717 cs,
4718 A7XX_GRAS_FSR_BUFFER_DESC(.layered = true,
4719 .tile_mode =
4720 (a6xx_tile_mode) iview->image->layout[0]
4721 .tile_mode, ),
4722 A7XX_GRAS_FSR_BUFFER_SIZE(.width = iview->view.width,
4723 .height = iview->view.height));
4724 tu_cs_emit_regs(
4725 cs, A7XX_GRAS_FSR_BUFFER_PITCH(.pitch = iview->view.pitch,
4726 .array_pitch = iview->view.layer_size));
4727 tu_cs_emit_regs(cs,
4728 A7XX_GRAS_FSR_BUFFER_BASE(.qword = iview->view.base_addr));
4729
4730 tu_emit_raw_event_write<A7XX>(cmd, cs, LRZ_Q_CACHE_INVALIDATE, false);
4731 cmd->prev_fsr_is_null = false;
4732 }
4733
4734 /* emit loads, clears, and mrt/zs/msaa/ubwc state for the subpass that is
4735 * starting (either at vkCmdBeginRenderPass2() or vkCmdNextSubpass2())
4736 *
4737 * Clears and loads have to happen at this point, because with
4738 * VK_ATTACHMENT_DESCRIPTION_MAY_ALIAS_BIT the loads may depend on the output of
4739 * a previous aliased attachment's store.
4740 */
4741 template <chip CHIP>
4742 static void
tu_emit_subpass_begin(struct tu_cmd_buffer * cmd)4743 tu_emit_subpass_begin(struct tu_cmd_buffer *cmd)
4744 {
4745 tu_fill_render_pass_state(&cmd->state.vk_rp, cmd->state.pass, cmd->state.subpass);
4746
4747 struct tu_resolve_group resolve_group = {};
4748
4749 tu_emit_subpass_begin_gmem<CHIP>(cmd, &resolve_group);
4750 tu_emit_subpass_begin_sysmem<CHIP>(cmd);
4751 if (cmd->device->physical_device->info->a7xx.has_generic_clear) {
4752 tu7_emit_subpass_clear(cmd, &resolve_group);
4753 }
4754
4755 tu_emit_resolve_group<CHIP>(cmd, &cmd->draw_cs, &resolve_group);
4756
4757 tu6_emit_zs<CHIP>(cmd, cmd->state.subpass, &cmd->draw_cs);
4758 tu6_emit_mrt<CHIP>(cmd, cmd->state.subpass, &cmd->draw_cs);
4759 tu6_emit_render_cntl<CHIP>(cmd, cmd->state.subpass, &cmd->draw_cs, false);
4760
4761 if (CHIP >= A7XX) {
4762 tu7_emit_subpass_shading_rate(cmd, cmd->state.subpass, &cmd->draw_cs);
4763 }
4764
4765 tu_set_input_attachments(cmd, cmd->state.subpass);
4766
4767 vk_cmd_set_cb_attachment_count(&cmd->vk, cmd->state.subpass->color_count);
4768
4769 cmd->state.dirty |= TU_CMD_DIRTY_SUBPASS;
4770 }
4771
4772 template <chip CHIP>
4773 VKAPI_ATTR void VKAPI_CALL
tu_CmdBeginRenderPass2(VkCommandBuffer commandBuffer,const VkRenderPassBeginInfo * pRenderPassBegin,const VkSubpassBeginInfo * pSubpassBeginInfo)4774 tu_CmdBeginRenderPass2(VkCommandBuffer commandBuffer,
4775 const VkRenderPassBeginInfo *pRenderPassBegin,
4776 const VkSubpassBeginInfo *pSubpassBeginInfo)
4777 {
4778 VK_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
4779
4780 if (TU_DEBUG(DYNAMIC)) {
4781 vk_common_CmdBeginRenderPass2(commandBuffer, pRenderPassBegin,
4782 pSubpassBeginInfo);
4783 return;
4784 }
4785
4786 VK_FROM_HANDLE(tu_render_pass, pass, pRenderPassBegin->renderPass);
4787 VK_FROM_HANDLE(tu_framebuffer, fb, pRenderPassBegin->framebuffer);
4788
4789 const struct VkRenderPassAttachmentBeginInfo *pAttachmentInfo =
4790 vk_find_struct_const(pRenderPassBegin->pNext,
4791 RENDER_PASS_ATTACHMENT_BEGIN_INFO);
4792
4793 cmd->state.pass = pass;
4794 cmd->state.subpass = pass->subpasses;
4795 cmd->state.framebuffer = fb;
4796 cmd->state.render_area = pRenderPassBegin->renderArea;
4797
4798 if (pass->attachment_count > 0) {
4799 VK_MULTIALLOC(ma);
4800 vk_multialloc_add(&ma, &cmd->state.attachments,
4801 const struct tu_image_view *, pass->attachment_count);
4802 vk_multialloc_add(&ma, &cmd->state.clear_values, VkClearValue,
4803 pRenderPassBegin->clearValueCount);
4804 if (!vk_multialloc_alloc(&ma, &cmd->vk.pool->alloc,
4805 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT)) {
4806 vk_command_buffer_set_error(&cmd->vk, VK_ERROR_OUT_OF_HOST_MEMORY);
4807 return;
4808 }
4809 }
4810
4811 if (cmd->device->dbg_renderpass_stomp_cs) {
4812 tu_cs_emit_call(&cmd->cs, cmd->device->dbg_renderpass_stomp_cs);
4813 }
4814
4815 for (unsigned i = 0; i < pass->attachment_count; i++) {
4816 cmd->state.attachments[i] = pAttachmentInfo ?
4817 tu_image_view_from_handle(pAttachmentInfo->pAttachments[i]) :
4818 cmd->state.framebuffer->attachments[i].attachment;
4819 }
4820 if (pass->attachment_count) {
4821 for (unsigned i = 0; i < pRenderPassBegin->clearValueCount; i++)
4822 cmd->state.clear_values[i] = pRenderPassBegin->pClearValues[i];
4823 }
4824
4825 tu_choose_gmem_layout(cmd);
4826
4827 tu_trace_start_render_pass(cmd);
4828
4829 /* Note: because this is external, any flushes will happen before draw_cs
4830 * gets called. However deferred flushes could have to happen later as part
4831 * of the subpass.
4832 */
4833 tu_subpass_barrier(cmd, &pass->subpasses[0].start_barrier, true);
4834 cmd->state.renderpass_cache.pending_flush_bits =
4835 cmd->state.cache.pending_flush_bits;
4836 cmd->state.renderpass_cache.flush_bits = 0;
4837
4838 if (pass->subpasses[0].feedback_invalidate) {
4839 cmd->state.renderpass_cache.flush_bits |=
4840 TU_CMD_FLAG_CACHE_INVALIDATE | TU_CMD_FLAG_BLIT_CACHE_CLEAN |
4841 TU_CMD_FLAG_WAIT_FOR_IDLE;
4842 }
4843
4844 tu_lrz_begin_renderpass<CHIP>(cmd);
4845
4846 cmd->trace_renderpass_start = u_trace_end_iterator(&cmd->trace);
4847
4848 tu_emit_renderpass_begin(cmd);
4849 tu_emit_subpass_begin<CHIP>(cmd);
4850
4851 cmd->patchpoints_ctx = ralloc_context(NULL);
4852 }
4853 TU_GENX(tu_CmdBeginRenderPass2);
4854
4855 template <chip CHIP>
4856 VKAPI_ATTR void VKAPI_CALL
tu_CmdBeginRendering(VkCommandBuffer commandBuffer,const VkRenderingInfo * pRenderingInfo)4857 tu_CmdBeginRendering(VkCommandBuffer commandBuffer,
4858 const VkRenderingInfo *pRenderingInfo)
4859 {
4860 VK_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
4861
4862 tu_setup_dynamic_render_pass(cmd, pRenderingInfo);
4863 tu_setup_dynamic_framebuffer(cmd, pRenderingInfo);
4864
4865 cmd->state.pass = &cmd->dynamic_pass;
4866 cmd->state.subpass = &cmd->dynamic_subpass;
4867 cmd->state.framebuffer = &cmd->dynamic_framebuffer;
4868 cmd->state.render_area = pRenderingInfo->renderArea;
4869 cmd->state.blit_cache_cleaned = false;
4870
4871 cmd->state.attachments = cmd->dynamic_attachments;
4872 cmd->state.clear_values = cmd->dynamic_clear_values;
4873
4874 for (unsigned i = 0; i < pRenderingInfo->colorAttachmentCount; i++) {
4875 uint32_t a = cmd->dynamic_subpass.color_attachments[i].attachment;
4876 if (!pRenderingInfo->pColorAttachments[i].imageView)
4877 continue;
4878
4879 cmd->state.clear_values[a] =
4880 pRenderingInfo->pColorAttachments[i].clearValue;
4881
4882 VK_FROM_HANDLE(tu_image_view, view,
4883 pRenderingInfo->pColorAttachments[i].imageView);
4884 cmd->state.attachments[a] = view;
4885
4886 a = cmd->dynamic_subpass.resolve_attachments[i].attachment;
4887 if (a != VK_ATTACHMENT_UNUSED) {
4888 VK_FROM_HANDLE(tu_image_view, resolve_view,
4889 pRenderingInfo->pColorAttachments[i].resolveImageView);
4890 cmd->state.attachments[a] = resolve_view;
4891 }
4892 }
4893
4894 uint32_t a = cmd->dynamic_subpass.depth_stencil_attachment.attachment;
4895 if (pRenderingInfo->pDepthAttachment || pRenderingInfo->pStencilAttachment) {
4896 const struct VkRenderingAttachmentInfo *common_info =
4897 (pRenderingInfo->pDepthAttachment &&
4898 pRenderingInfo->pDepthAttachment->imageView != VK_NULL_HANDLE) ?
4899 pRenderingInfo->pDepthAttachment :
4900 pRenderingInfo->pStencilAttachment;
4901 if (common_info && common_info->imageView != VK_NULL_HANDLE) {
4902 VK_FROM_HANDLE(tu_image_view, view, common_info->imageView);
4903 cmd->state.attachments[a] = view;
4904 if (pRenderingInfo->pDepthAttachment) {
4905 cmd->state.clear_values[a].depthStencil.depth =
4906 pRenderingInfo->pDepthAttachment->clearValue.depthStencil.depth;
4907 }
4908
4909 if (pRenderingInfo->pStencilAttachment) {
4910 cmd->state.clear_values[a].depthStencil.stencil =
4911 pRenderingInfo->pStencilAttachment->clearValue.depthStencil.stencil;
4912 }
4913
4914 if (cmd->dynamic_subpass.resolve_count >
4915 cmd->dynamic_subpass.color_count) {
4916 VK_FROM_HANDLE(tu_image_view, resolve_view,
4917 common_info->resolveImageView);
4918 a = cmd->dynamic_subpass.resolve_attachments[cmd->dynamic_subpass.color_count].attachment;
4919 cmd->state.attachments[a] = resolve_view;
4920 }
4921 }
4922 }
4923
4924 a = cmd->dynamic_pass.fragment_density_map.attachment;
4925 if (a != VK_ATTACHMENT_UNUSED) {
4926 const VkRenderingFragmentDensityMapAttachmentInfoEXT *fdm_info =
4927 vk_find_struct_const(pRenderingInfo->pNext,
4928 RENDERING_FRAGMENT_DENSITY_MAP_ATTACHMENT_INFO_EXT);
4929 VK_FROM_HANDLE(tu_image_view, view, fdm_info->imageView);
4930 cmd->state.attachments[a] = view;
4931 }
4932
4933 const VkRenderingAttachmentLocationInfoKHR ral_info = {
4934 .sType = VK_STRUCTURE_TYPE_RENDERING_ATTACHMENT_LOCATION_INFO_KHR,
4935 .colorAttachmentCount = pRenderingInfo->colorAttachmentCount,
4936 };
4937 vk_cmd_set_rendering_attachment_locations(&cmd->vk, &ral_info);
4938
4939 cmd->patchpoints_ctx = ralloc_context(NULL);
4940
4941 a = cmd->dynamic_subpass.fsr_attachment;
4942 if (a != VK_ATTACHMENT_UNUSED) {
4943 const VkRenderingFragmentShadingRateAttachmentInfoKHR *fsr_info =
4944 vk_find_struct_const(pRenderingInfo->pNext,
4945 RENDERING_FRAGMENT_SHADING_RATE_ATTACHMENT_INFO_KHR);
4946 VK_FROM_HANDLE(tu_image_view, view, fsr_info->imageView);
4947 cmd->state.attachments[a] = view;
4948 }
4949
4950 tu_choose_gmem_layout(cmd);
4951
4952 cmd->state.renderpass_cache.pending_flush_bits =
4953 cmd->state.cache.pending_flush_bits;
4954 cmd->state.renderpass_cache.flush_bits = 0;
4955
4956 bool resuming = pRenderingInfo->flags & VK_RENDERING_RESUMING_BIT;
4957 bool suspending = pRenderingInfo->flags & VK_RENDERING_SUSPENDING_BIT;
4958 cmd->state.suspending = suspending;
4959 cmd->state.resuming = resuming;
4960
4961 if (!resuming && cmd->device->dbg_renderpass_stomp_cs) {
4962 tu_cs_emit_call(&cmd->cs, cmd->device->dbg_renderpass_stomp_cs);
4963 }
4964
4965 /* We can't track LRZ across command buffer boundaries, so we have to
4966 * disable LRZ when resuming/suspending unless we can track on the GPU.
4967 */
4968 if ((resuming || suspending) &&
4969 !cmd->device->physical_device->info->a6xx.has_lrz_dir_tracking) {
4970 cmd->state.lrz.valid = false;
4971 } else {
4972 if (resuming)
4973 tu_lrz_begin_resumed_renderpass<CHIP>(cmd);
4974 else
4975 tu_lrz_begin_renderpass<CHIP>(cmd);
4976 }
4977
4978
4979 if (suspending) {
4980 cmd->state.suspended_pass.pass = cmd->state.pass;
4981 cmd->state.suspended_pass.subpass = cmd->state.subpass;
4982 cmd->state.suspended_pass.framebuffer = cmd->state.framebuffer;
4983 cmd->state.suspended_pass.render_area = cmd->state.render_area;
4984 cmd->state.suspended_pass.attachments = cmd->state.attachments;
4985 cmd->state.suspended_pass.clear_values = cmd->state.clear_values;
4986 cmd->state.suspended_pass.gmem_layout = cmd->state.gmem_layout;
4987 }
4988
4989 if (!resuming)
4990 tu_trace_start_render_pass(cmd);
4991
4992 if (!resuming || cmd->state.suspend_resume == SR_NONE) {
4993 cmd->trace_renderpass_start = u_trace_end_iterator(&cmd->trace);
4994 }
4995
4996 if (!resuming) {
4997 tu_emit_renderpass_begin(cmd);
4998 tu_emit_subpass_begin<CHIP>(cmd);
4999 }
5000
5001 if (suspending && !resuming) {
5002 /* entering a chain */
5003 switch (cmd->state.suspend_resume) {
5004 case SR_NONE:
5005 cmd->state.suspend_resume = SR_IN_CHAIN;
5006 break;
5007 case SR_AFTER_PRE_CHAIN:
5008 cmd->state.suspend_resume = SR_IN_CHAIN_AFTER_PRE_CHAIN;
5009 break;
5010 case SR_IN_PRE_CHAIN:
5011 case SR_IN_CHAIN:
5012 case SR_IN_CHAIN_AFTER_PRE_CHAIN:
5013 unreachable("suspending render pass not followed by resuming pass");
5014 break;
5015 }
5016 }
5017
5018 if (resuming && cmd->state.suspend_resume == SR_NONE)
5019 cmd->state.suspend_resume = SR_IN_PRE_CHAIN;
5020 }
5021 TU_GENX(tu_CmdBeginRendering);
5022
5023 template <chip CHIP>
5024 VKAPI_ATTR void VKAPI_CALL
tu_CmdSetRenderingAttachmentLocationsKHR(VkCommandBuffer commandBuffer,const VkRenderingAttachmentLocationInfoKHR * pLocationInfo)5025 tu_CmdSetRenderingAttachmentLocationsKHR(
5026 VkCommandBuffer commandBuffer,
5027 const VkRenderingAttachmentLocationInfoKHR *pLocationInfo)
5028 {
5029 VK_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
5030
5031 vk_common_CmdSetRenderingAttachmentLocationsKHR(commandBuffer, pLocationInfo);
5032
5033 tu6_emit_mrt<CHIP>(cmd, cmd->state.subpass, &cmd->draw_cs);
5034 tu6_emit_render_cntl<CHIP>(cmd, cmd->state.subpass, &cmd->draw_cs, false);
5035
5036 /* Because this is just a remapping and not a different "reference", there
5037 * doesn't need to be a barrier between accesses to the same attachment
5038 * with a different index. This is different from "classic" renderpasses.
5039 * Before a7xx the CCU includes the render target ID in the cache location
5040 * calculation, so we need to manually flush/invalidate color CCU here
5041 * since the same render target/attachment may be in a different location.
5042 */
5043 if (cmd->device->physical_device->info->chip == 6) {
5044 struct tu_cache_state *cache = &cmd->state.renderpass_cache;
5045 tu_flush_for_access(cache, TU_ACCESS_CCU_COLOR_INCOHERENT_WRITE,
5046 TU_ACCESS_CCU_COLOR_INCOHERENT_WRITE);
5047 cache->flush_bits |= TU_CMD_FLAG_WAIT_FOR_IDLE;
5048 }
5049 }
5050 TU_GENX(tu_CmdSetRenderingAttachmentLocationsKHR);
5051
5052 VKAPI_ATTR void VKAPI_CALL
tu_CmdSetRenderingInputAttachmentIndicesKHR(VkCommandBuffer commandBuffer,const VkRenderingInputAttachmentIndexInfoKHR * pLocationInfo)5053 tu_CmdSetRenderingInputAttachmentIndicesKHR(
5054 VkCommandBuffer commandBuffer,
5055 const VkRenderingInputAttachmentIndexInfoKHR *pLocationInfo)
5056 {
5057 VK_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
5058
5059 vk_common_CmdSetRenderingInputAttachmentIndicesKHR(commandBuffer, pLocationInfo);
5060
5061 const struct vk_input_attachment_location_state *ial =
5062 &cmd->vk.dynamic_graphics_state.ial;
5063
5064 struct tu_subpass *subpass = &cmd->dynamic_subpass;
5065
5066 for (unsigned i = 0; i < ARRAY_SIZE(cmd->dynamic_input_attachments); i++) {
5067 subpass->input_attachments[i].attachment = VK_ATTACHMENT_UNUSED;
5068 }
5069
5070 unsigned input_count = 0;
5071 for (unsigned i = 0; i < subpass->color_count; i++) {
5072 if (ial->color_map[i] == MESA_VK_ATTACHMENT_UNUSED)
5073 continue;
5074 subpass->input_attachments[ial->color_map[i] + TU_DYN_INPUT_ATT_OFFSET].attachment =
5075 subpass->color_attachments[i].attachment;
5076 input_count = MAX2(input_count, ial->color_map[i] + TU_DYN_INPUT_ATT_OFFSET + 1);
5077 }
5078
5079 if (ial->depth_att != MESA_VK_ATTACHMENT_UNUSED) {
5080 if (ial->depth_att == MESA_VK_ATTACHMENT_NO_INDEX) {
5081 subpass->input_attachments[0].attachment =
5082 subpass->depth_stencil_attachment.attachment;
5083 input_count = MAX2(input_count, 1);
5084 } else {
5085 subpass->input_attachments[ial->depth_att + TU_DYN_INPUT_ATT_OFFSET].attachment =
5086 subpass->depth_stencil_attachment.attachment;
5087 input_count = MAX2(input_count, ial->depth_att + TU_DYN_INPUT_ATT_OFFSET + 1);
5088 }
5089 }
5090
5091 if (ial->stencil_att != MESA_VK_ATTACHMENT_UNUSED) {
5092 if (ial->stencil_att == MESA_VK_ATTACHMENT_NO_INDEX) {
5093 subpass->input_attachments[0].attachment =
5094 subpass->depth_stencil_attachment.attachment;
5095 input_count = MAX2(input_count, 1);
5096 } else {
5097 subpass->input_attachments[ial->stencil_att + TU_DYN_INPUT_ATT_OFFSET].attachment =
5098 subpass->depth_stencil_attachment.attachment;
5099 input_count = MAX2(input_count, ial->stencil_att + TU_DYN_INPUT_ATT_OFFSET + 1);
5100 }
5101 }
5102
5103 subpass->input_count = input_count;
5104
5105 tu_set_input_attachments(cmd, cmd->state.subpass);
5106 }
5107
5108 template <chip CHIP>
5109 VKAPI_ATTR void VKAPI_CALL
tu_CmdNextSubpass2(VkCommandBuffer commandBuffer,const VkSubpassBeginInfo * pSubpassBeginInfo,const VkSubpassEndInfo * pSubpassEndInfo)5110 tu_CmdNextSubpass2(VkCommandBuffer commandBuffer,
5111 const VkSubpassBeginInfo *pSubpassBeginInfo,
5112 const VkSubpassEndInfo *pSubpassEndInfo)
5113 {
5114 VK_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
5115
5116 if (TU_DEBUG(DYNAMIC)) {
5117 vk_common_CmdNextSubpass2(commandBuffer, pSubpassBeginInfo,
5118 pSubpassEndInfo);
5119 return;
5120 }
5121
5122 const struct tu_render_pass *pass = cmd->state.pass;
5123 const struct tu_framebuffer *fb = cmd->state.framebuffer;
5124 struct tu_cs *cs = &cmd->draw_cs;
5125 const struct tu_subpass *last_subpass = cmd->state.subpass;
5126
5127 const struct tu_subpass *subpass = cmd->state.subpass++;
5128
5129 /* Track LRZ valid state
5130 *
5131 * TODO: Improve this tracking for keeping the state of the past depth/stencil images,
5132 * so if they become active again, we reuse its old state.
5133 */
5134 if (last_subpass->depth_stencil_attachment.attachment != subpass->depth_stencil_attachment.attachment) {
5135 cmd->state.lrz.valid = false;
5136 cmd->state.dirty |= TU_CMD_DIRTY_LRZ;
5137 }
5138
5139 if (cmd->state.tiling->possible) {
5140 if (cmd->state.pass->has_fdm)
5141 tu_cs_set_writeable(cs, true);
5142
5143 tu_cond_exec_start(cs, CP_COND_EXEC_0_RENDER_MODE_GMEM);
5144
5145 if (subpass->resolve_attachments) {
5146 tu6_emit_blit_scissor(cmd, cs, true);
5147
5148 struct tu_resolve_group resolve_group = {};
5149
5150 for (unsigned i = 0; i < subpass->resolve_count; i++) {
5151 uint32_t a = subpass->resolve_attachments[i].attachment;
5152 if (a == VK_ATTACHMENT_UNUSED)
5153 continue;
5154
5155 uint32_t gmem_a = tu_subpass_get_attachment_to_resolve(subpass, i);
5156
5157 tu_store_gmem_attachment<CHIP>(cmd, cs, &resolve_group, a, gmem_a,
5158 fb->layers, subpass->multiview_mask, false);
5159
5160 if (!pass->attachments[a].gmem)
5161 continue;
5162
5163 /* check if the resolved attachment is needed by later subpasses,
5164 * if it is, should be doing a GMEM->GMEM resolve instead of GMEM->MEM->GMEM..
5165 */
5166 perf_debug(cmd->device, "TODO: missing GMEM->GMEM resolve path\n");
5167 tu_load_gmem_attachment<CHIP>(cmd, cs, &resolve_group, a, false, true);
5168 }
5169
5170 tu_emit_resolve_group<CHIP>(cmd, cs, &resolve_group);
5171 }
5172
5173 tu_cond_exec_end(cs);
5174
5175 if (cmd->state.pass->has_fdm)
5176 tu_cs_set_writeable(cs, false);
5177
5178 tu_cond_exec_start(cs, CP_COND_EXEC_0_RENDER_MODE_SYSMEM);
5179 }
5180
5181 tu6_emit_sysmem_resolves<CHIP>(cmd, cs, subpass);
5182
5183 if (cmd->state.tiling->possible)
5184 tu_cond_exec_end(cs);
5185
5186 /* Handle dependencies for the next subpass */
5187 tu_subpass_barrier(cmd, &cmd->state.subpass->start_barrier, false);
5188
5189 if (cmd->state.subpass->feedback_invalidate) {
5190 cmd->state.renderpass_cache.flush_bits |=
5191 TU_CMD_FLAG_CACHE_INVALIDATE | TU_CMD_FLAG_BLIT_CACHE_CLEAN |
5192 TU_CMD_FLAG_WAIT_FOR_IDLE;
5193 }
5194
5195 tu_emit_subpass_begin<CHIP>(cmd);
5196 }
5197 TU_GENX(tu_CmdNextSubpass2);
5198
5199 static uint32_t
tu6_user_consts_size(const struct tu_const_state * const_state,bool ldgk,gl_shader_stage type)5200 tu6_user_consts_size(const struct tu_const_state *const_state,
5201 bool ldgk,
5202 gl_shader_stage type)
5203 {
5204 uint32_t dwords = 0;
5205
5206 if (const_state->push_consts.type == IR3_PUSH_CONSTS_PER_STAGE) {
5207 unsigned num_units = const_state->push_consts.dwords;
5208 dwords += 4 + num_units;
5209 assert(num_units > 0);
5210 }
5211
5212 if (ldgk) {
5213 dwords += 6 + (2 * const_state->num_inline_ubos + 4);
5214 } else {
5215 dwords += 8 * const_state->num_inline_ubos;
5216 }
5217
5218 return dwords;
5219 }
5220
5221 static void
tu6_emit_per_stage_push_consts(struct tu_cs * cs,const struct tu_const_state * const_state,const struct ir3_const_state * ir_const_state,gl_shader_stage type,uint32_t * push_constants)5222 tu6_emit_per_stage_push_consts(struct tu_cs *cs,
5223 const struct tu_const_state *const_state,
5224 const struct ir3_const_state *ir_const_state,
5225 gl_shader_stage type,
5226 uint32_t *push_constants)
5227 {
5228 if (const_state->push_consts.type == IR3_PUSH_CONSTS_PER_STAGE) {
5229 unsigned num_units = const_state->push_consts.dwords;
5230 unsigned offset_vec4 =
5231 ir_const_state->allocs.consts[IR3_CONST_ALLOC_PUSH_CONSTS]
5232 .offset_vec4;
5233 assert(num_units > 0);
5234
5235 /* DST_OFF and NUM_UNIT requires vec4 units */
5236 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + num_units);
5237 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(offset_vec4) |
5238 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
5239 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
5240 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
5241 CP_LOAD_STATE6_0_NUM_UNIT(num_units / 4));
5242 tu_cs_emit(cs, 0);
5243 tu_cs_emit(cs, 0);
5244
5245 unsigned lo = const_state->push_consts.lo_dwords;
5246 for (unsigned i = 0; i < num_units; i++)
5247 tu_cs_emit(cs, push_constants[i + lo]);
5248 }
5249 }
5250
5251 static void
tu6_emit_inline_ubo(struct tu_cs * cs,const struct tu_const_state * const_state,unsigned constlen,gl_shader_stage type,struct tu_descriptor_state * descriptors)5252 tu6_emit_inline_ubo(struct tu_cs *cs,
5253 const struct tu_const_state *const_state,
5254 unsigned constlen,
5255 gl_shader_stage type,
5256 struct tu_descriptor_state *descriptors)
5257 {
5258 assert(const_state->num_inline_ubos == 0 || !cs->device->physical_device->info->a7xx.load_shader_consts_via_preamble);
5259
5260 /* Emit loads of inline uniforms. These load directly from the uniform's
5261 * storage space inside the descriptor set.
5262 */
5263 for (unsigned i = 0; i < const_state->num_inline_ubos; i++) {
5264 const struct tu_inline_ubo *ubo = &const_state->ubos[i];
5265
5266 if (constlen <= ubo->const_offset_vec4)
5267 continue;
5268
5269 uint64_t va = descriptors->set_iova[ubo->base] & ~0x3f;
5270
5271 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), ubo->push_address ? 7 : 3);
5272 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(ubo->const_offset_vec4) |
5273 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
5274 CP_LOAD_STATE6_0_STATE_SRC(ubo->push_address ? SS6_DIRECT : SS6_INDIRECT) |
5275 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
5276 CP_LOAD_STATE6_0_NUM_UNIT(MIN2(ubo->size_vec4, constlen - ubo->const_offset_vec4)));
5277 if (ubo->push_address) {
5278 tu_cs_emit(cs, 0);
5279 tu_cs_emit(cs, 0);
5280 tu_cs_emit_qw(cs, va + ubo->offset);
5281 tu_cs_emit(cs, 0);
5282 tu_cs_emit(cs, 0);
5283 } else {
5284 tu_cs_emit_qw(cs, va + ubo->offset);
5285 }
5286 }
5287 }
5288
5289 static void
tu7_emit_inline_ubo(struct tu_cs * cs,const struct tu_const_state * const_state,const struct ir3_const_state * ir_const_state,unsigned constlen,gl_shader_stage type,struct tu_descriptor_state * descriptors)5290 tu7_emit_inline_ubo(struct tu_cs *cs,
5291 const struct tu_const_state *const_state,
5292 const struct ir3_const_state *ir_const_state,
5293 unsigned constlen,
5294 gl_shader_stage type,
5295 struct tu_descriptor_state *descriptors)
5296 {
5297 uint64_t addresses[7] = {0};
5298 unsigned offset = const_state->inline_uniforms_ubo.idx;
5299
5300 if (offset == -1)
5301 return;
5302
5303 for (unsigned i = 0; i < const_state->num_inline_ubos; i++) {
5304 const struct tu_inline_ubo *ubo = &const_state->ubos[i];
5305
5306 uint64_t va = descriptors->set_iova[ubo->base] & ~0x3f;
5307 addresses[i] = va + ubo->offset;
5308 }
5309
5310 /* A7XX TODO: Emit data via sub_cs instead of NOP */
5311 uint64_t iova = tu_cs_emit_data_nop(cs, (uint32_t *)addresses, const_state->num_inline_ubos * 2, 4);
5312
5313 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 5);
5314 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(offset) |
5315 CP_LOAD_STATE6_0_STATE_TYPE(ST6_UBO) |
5316 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
5317 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
5318 CP_LOAD_STATE6_0_NUM_UNIT(1));
5319 tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
5320 tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
5321 int size_vec4s = DIV_ROUND_UP(const_state->num_inline_ubos * 2, 4);
5322 tu_cs_emit_qw(cs, iova | ((uint64_t)A6XX_UBO_1_SIZE(size_vec4s) << 32));
5323 }
5324
5325 static void
tu_emit_inline_ubo(struct tu_cs * cs,const struct tu_const_state * const_state,const struct ir3_const_state * ir_const_state,unsigned constlen,gl_shader_stage type,struct tu_descriptor_state * descriptors)5326 tu_emit_inline_ubo(struct tu_cs *cs,
5327 const struct tu_const_state *const_state,
5328 const struct ir3_const_state *ir_const_state,
5329 unsigned constlen,
5330 gl_shader_stage type,
5331 struct tu_descriptor_state *descriptors)
5332 {
5333 if (!const_state->num_inline_ubos)
5334 return;
5335
5336 if (cs->device->physical_device->info->a7xx.load_inline_uniforms_via_preamble_ldgk) {
5337 tu7_emit_inline_ubo(cs, const_state, ir_const_state, constlen, type, descriptors);
5338 } else {
5339 tu6_emit_inline_ubo(cs, const_state, constlen, type, descriptors);
5340 }
5341 }
5342
5343 static void
tu6_emit_shared_consts(struct tu_cs * cs,const struct tu_push_constant_range * shared_consts,uint32_t * push_constants,bool compute)5344 tu6_emit_shared_consts(struct tu_cs *cs,
5345 const struct tu_push_constant_range *shared_consts,
5346 uint32_t *push_constants,
5347 bool compute)
5348 {
5349 if (shared_consts->dwords > 0) {
5350 /* Offset and num_units for shared consts are in units of dwords. */
5351 unsigned num_units = shared_consts->dwords;
5352 unsigned offset = shared_consts->lo_dwords;
5353
5354 enum a6xx_state_type st = compute ? ST6_UBO : ST6_CONSTANTS;
5355 uint32_t cp_load_state = compute ? CP_LOAD_STATE6_FRAG : CP_LOAD_STATE6;
5356
5357 tu_cs_emit_pkt7(cs, cp_load_state, 3 + num_units);
5358 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(offset) |
5359 CP_LOAD_STATE6_0_STATE_TYPE(st) |
5360 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
5361 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_IBO) |
5362 CP_LOAD_STATE6_0_NUM_UNIT(num_units));
5363 tu_cs_emit(cs, 0);
5364 tu_cs_emit(cs, 0);
5365
5366 for (unsigned i = 0; i < num_units; i++)
5367 tu_cs_emit(cs, push_constants[i + offset]);
5368 }
5369 }
5370
5371 static void
tu7_emit_shared_preamble_consts(struct tu_cs * cs,const struct tu_push_constant_range * shared_consts,uint32_t * push_constants)5372 tu7_emit_shared_preamble_consts(
5373 struct tu_cs *cs,
5374 const struct tu_push_constant_range *shared_consts,
5375 uint32_t *push_constants)
5376 {
5377 tu_cs_emit_pkt4(cs, REG_A7XX_HLSQ_SHARED_CONSTS_IMM(shared_consts->lo_dwords),
5378 shared_consts->dwords);
5379 tu_cs_emit_array(cs, push_constants + shared_consts->lo_dwords,
5380 shared_consts->dwords);
5381 }
5382
5383 static uint32_t
tu6_const_size(struct tu_cmd_buffer * cmd,const struct tu_push_constant_range * shared_consts,bool compute)5384 tu6_const_size(struct tu_cmd_buffer *cmd,
5385 const struct tu_push_constant_range *shared_consts,
5386 bool compute)
5387 {
5388 uint32_t dwords = 0;
5389
5390 if (shared_consts->type == IR3_PUSH_CONSTS_SHARED) {
5391 dwords += shared_consts->dwords + 4;
5392 } else if (shared_consts->type == IR3_PUSH_CONSTS_SHARED_PREAMBLE) {
5393 dwords += shared_consts->dwords + 1;
5394 }
5395
5396 bool ldgk = cmd->device->physical_device->info->a7xx.load_inline_uniforms_via_preamble_ldgk;
5397 if (compute) {
5398 dwords +=
5399 tu6_user_consts_size(&cmd->state.shaders[MESA_SHADER_COMPUTE]->const_state, ldgk, MESA_SHADER_COMPUTE);
5400 } else {
5401 for (uint32_t type = MESA_SHADER_VERTEX; type <= MESA_SHADER_FRAGMENT; type++)
5402 dwords += tu6_user_consts_size(&cmd->state.shaders[type]->const_state, ldgk, (gl_shader_stage) type);
5403 }
5404
5405 return dwords;
5406 }
5407
5408 static struct tu_draw_state
tu_emit_consts(struct tu_cmd_buffer * cmd,bool compute)5409 tu_emit_consts(struct tu_cmd_buffer *cmd, bool compute)
5410 {
5411 uint32_t dwords = 0;
5412 const struct tu_push_constant_range *shared_consts =
5413 compute ? &cmd->state.shaders[MESA_SHADER_COMPUTE]->const_state.push_consts :
5414 &cmd->state.program.shared_consts;
5415
5416 dwords = tu6_const_size(cmd, shared_consts, compute);
5417
5418 if (dwords == 0)
5419 return (struct tu_draw_state) {};
5420
5421 struct tu_cs cs;
5422 tu_cs_begin_sub_stream(&cmd->sub_cs, dwords, &cs);
5423
5424 if (shared_consts->type == IR3_PUSH_CONSTS_SHARED) {
5425 tu6_emit_shared_consts(&cs, shared_consts, cmd->push_constants, compute);
5426 } else if (shared_consts->type == IR3_PUSH_CONSTS_SHARED_PREAMBLE) {
5427 tu7_emit_shared_preamble_consts(&cs, shared_consts, cmd->push_constants);
5428 }
5429
5430 if (compute) {
5431 tu6_emit_per_stage_push_consts(
5432 &cs, &cmd->state.shaders[MESA_SHADER_COMPUTE]->const_state,
5433 cmd->state.shaders[MESA_SHADER_COMPUTE]->variant->const_state,
5434 MESA_SHADER_COMPUTE, cmd->push_constants);
5435 tu_emit_inline_ubo(
5436 &cs, &cmd->state.shaders[MESA_SHADER_COMPUTE]->const_state,
5437 cmd->state.shaders[MESA_SHADER_COMPUTE]->variant->const_state,
5438 cmd->state.shaders[MESA_SHADER_COMPUTE]->variant->constlen,
5439 MESA_SHADER_COMPUTE,
5440 tu_get_descriptors_state(cmd, VK_PIPELINE_BIND_POINT_COMPUTE));
5441 } else {
5442 struct tu_descriptor_state *descriptors =
5443 tu_get_descriptors_state(cmd, VK_PIPELINE_BIND_POINT_GRAPHICS);
5444 for (uint32_t type = MESA_SHADER_VERTEX; type <= MESA_SHADER_FRAGMENT; type++) {
5445 const struct tu_program_descriptor_linkage *link =
5446 &cmd->state.program.link[type];
5447 tu6_emit_per_stage_push_consts(&cs, &link->tu_const_state,
5448 &link->const_state,
5449 (gl_shader_stage) type,
5450 cmd->push_constants);
5451 tu_emit_inline_ubo(&cs, &link->tu_const_state,
5452 &link->const_state, link->constlen,
5453 (gl_shader_stage) type, descriptors);
5454 }
5455 }
5456
5457 return tu_cs_end_draw_state(&cmd->sub_cs, &cs);
5458 }
5459
5460 /* Various frontends (ANGLE, zink at least) will enable stencil testing with
5461 * what works out to be no-op writes. Simplify what they give us into flags
5462 * that LRZ can use.
5463 */
5464 static void
tu6_update_simplified_stencil_state(struct tu_cmd_buffer * cmd)5465 tu6_update_simplified_stencil_state(struct tu_cmd_buffer *cmd)
5466 {
5467 const struct vk_depth_stencil_state *ds =
5468 &cmd->vk.dynamic_graphics_state.ds;
5469 bool stencil_test_enable = ds->stencil.test_enable;
5470
5471 if (!stencil_test_enable) {
5472 cmd->state.stencil_front_write = false;
5473 cmd->state.stencil_back_write = false;
5474 return;
5475 }
5476
5477 bool stencil_front_writemask = ds->stencil.front.write_mask;
5478 bool stencil_back_writemask = ds->stencil.back.write_mask;
5479
5480 VkStencilOp front_fail_op = (VkStencilOp)ds->stencil.front.op.fail;
5481 VkStencilOp front_pass_op = (VkStencilOp)ds->stencil.front.op.pass;
5482 VkStencilOp front_depth_fail_op = (VkStencilOp)ds->stencil.front.op.depth_fail;
5483 VkStencilOp back_fail_op = (VkStencilOp)ds->stencil.back.op.fail;
5484 VkStencilOp back_pass_op = (VkStencilOp)ds->stencil.back.op.pass;
5485 VkStencilOp back_depth_fail_op = (VkStencilOp)ds->stencil.back.op.depth_fail;
5486
5487 bool stencil_front_op_writes =
5488 front_pass_op != VK_STENCIL_OP_KEEP ||
5489 front_fail_op != VK_STENCIL_OP_KEEP ||
5490 front_depth_fail_op != VK_STENCIL_OP_KEEP;
5491
5492 bool stencil_back_op_writes =
5493 back_pass_op != VK_STENCIL_OP_KEEP ||
5494 back_fail_op != VK_STENCIL_OP_KEEP ||
5495 back_depth_fail_op != VK_STENCIL_OP_KEEP;
5496
5497 cmd->state.stencil_front_write =
5498 stencil_front_op_writes && stencil_front_writemask;
5499 cmd->state.stencil_back_write =
5500 stencil_back_op_writes && stencil_back_writemask;
5501 }
5502
5503 static bool
tu6_writes_depth(struct tu_cmd_buffer * cmd,bool depth_test_enable)5504 tu6_writes_depth(struct tu_cmd_buffer *cmd, bool depth_test_enable)
5505 {
5506 bool depth_write_enable =
5507 cmd->vk.dynamic_graphics_state.ds.depth.write_enable;
5508
5509 VkCompareOp depth_compare_op = (VkCompareOp)
5510 cmd->vk.dynamic_graphics_state.ds.depth.compare_op;
5511
5512 bool depth_compare_op_writes = depth_compare_op != VK_COMPARE_OP_NEVER;
5513
5514 return depth_test_enable && depth_write_enable && depth_compare_op_writes;
5515 }
5516
5517 static bool
tu6_writes_stencil(struct tu_cmd_buffer * cmd)5518 tu6_writes_stencil(struct tu_cmd_buffer *cmd)
5519 {
5520 return cmd->state.stencil_front_write || cmd->state.stencil_back_write;
5521 }
5522
5523 static bool
tu_fs_reads_dynamic_ds_input_attachment(struct tu_cmd_buffer * cmd,const struct tu_shader * fs)5524 tu_fs_reads_dynamic_ds_input_attachment(struct tu_cmd_buffer *cmd,
5525 const struct tu_shader *fs)
5526 {
5527 uint8_t depth_att = cmd->vk.dynamic_graphics_state.ial.depth_att;
5528 if (depth_att == MESA_VK_ATTACHMENT_UNUSED)
5529 return false;
5530 unsigned depth_idx =
5531 (depth_att == MESA_VK_ATTACHMENT_NO_INDEX) ? 0 : depth_att + 1;
5532 return fs->fs.dynamic_input_attachments_used & (1u << depth_idx);
5533 }
5534
5535 static void
tu6_build_depth_plane_z_mode(struct tu_cmd_buffer * cmd,struct tu_cs * cs)5536 tu6_build_depth_plane_z_mode(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
5537 {
5538 enum a6xx_ztest_mode zmode = A6XX_EARLY_Z;
5539 bool depth_test_enable = cmd->vk.dynamic_graphics_state.ds.depth.test_enable;
5540 bool depth_write = tu6_writes_depth(cmd, depth_test_enable);
5541 bool stencil_write = tu6_writes_stencil(cmd);
5542 const struct tu_shader *fs = cmd->state.shaders[MESA_SHADER_FRAGMENT];
5543 const struct tu_render_pass *pass = cmd->state.pass;
5544 const struct tu_subpass *subpass = cmd->state.subpass;
5545
5546 if ((fs->variant->has_kill ||
5547 (cmd->state.pipeline_feedback_loops & VK_IMAGE_ASPECT_DEPTH_BIT) ||
5548 (cmd->vk.dynamic_graphics_state.feedback_loops &
5549 VK_IMAGE_ASPECT_DEPTH_BIT) ||
5550 tu_fs_reads_dynamic_ds_input_attachment(cmd, fs)) &&
5551 (depth_write || stencil_write)) {
5552 zmode = (cmd->state.lrz.valid && cmd->state.lrz.enabled)
5553 ? A6XX_EARLY_LRZ_LATE_Z
5554 : A6XX_LATE_Z;
5555 }
5556
5557 bool force_late_z =
5558 (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED &&
5559 pass->attachments[subpass->depth_stencil_attachment.attachment].format
5560 == VK_FORMAT_S8_UINT) ||
5561 fs->fs.lrz.force_late_z ||
5562 /* alpha-to-coverage can behave like a discard. */
5563 cmd->vk.dynamic_graphics_state.ms.alpha_to_coverage_enable;
5564 if ((force_late_z && !fs->variant->fs.early_fragment_tests) ||
5565 !depth_test_enable)
5566 zmode = A6XX_LATE_Z;
5567
5568 /* User defined early tests take precedence above all else */
5569 if (fs->variant->fs.early_fragment_tests)
5570 zmode = A6XX_EARLY_Z;
5571
5572 tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL, 1);
5573 tu_cs_emit(cs, A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE(zmode));
5574
5575 tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_PLANE_CNTL, 1);
5576 tu_cs_emit(cs, A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE(zmode));
5577 }
5578
5579 static uint32_t
fs_params_offset(struct tu_cmd_buffer * cmd)5580 fs_params_offset(struct tu_cmd_buffer *cmd)
5581 {
5582 const struct tu_program_descriptor_linkage *link =
5583 &cmd->state.program.link[MESA_SHADER_FRAGMENT];
5584 const struct ir3_const_state *const_state = &link->const_state;
5585
5586 if (const_state->num_driver_params <= IR3_DP_FS_DYNAMIC)
5587 return 0;
5588
5589 uint32_t param_offset =
5590 const_state->allocs.consts[IR3_CONST_ALLOC_DRIVER_PARAMS].offset_vec4;
5591
5592 if (param_offset + IR3_DP_FS_DYNAMIC / 4 >= link->constlen)
5593 return 0;
5594
5595 return param_offset + IR3_DP_FS_DYNAMIC / 4;
5596 }
5597
5598 static uint32_t
fs_params_size(struct tu_cmd_buffer * cmd)5599 fs_params_size(struct tu_cmd_buffer *cmd)
5600 {
5601 const struct tu_program_descriptor_linkage *link =
5602 &cmd->state.program.link[MESA_SHADER_FRAGMENT];
5603 const struct ir3_const_state *const_state = &link->const_state;
5604
5605 return DIV_ROUND_UP(const_state->num_driver_params - IR3_DP_FS_DYNAMIC, 4);
5606 }
5607
5608 struct apply_fs_params_state {
5609 unsigned num_consts;
5610 };
5611
5612 static void
fdm_apply_fs_params(struct tu_cmd_buffer * cmd,struct tu_cs * cs,void * data,VkRect2D bin,unsigned views,VkExtent2D * frag_areas)5613 fdm_apply_fs_params(struct tu_cmd_buffer *cmd,
5614 struct tu_cs *cs,
5615 void *data,
5616 VkRect2D bin,
5617 unsigned views,
5618 VkExtent2D *frag_areas)
5619 {
5620 const struct apply_fs_params_state *state =
5621 (const struct apply_fs_params_state *)data;
5622 unsigned num_consts = state->num_consts;
5623
5624 for (unsigned i = 0; i < num_consts; i++) {
5625 assert(i < views);
5626 VkExtent2D area = frag_areas[i];
5627 VkOffset2D offset = tu_fdm_per_bin_offset(area, bin);
5628
5629 tu_cs_emit(cs, area.width);
5630 tu_cs_emit(cs, area.height);
5631 tu_cs_emit(cs, fui(offset.x));
5632 tu_cs_emit(cs, fui(offset.y));
5633 }
5634 }
5635
5636 static void
tu_emit_fdm_params(struct tu_cmd_buffer * cmd,struct tu_cs * cs,struct tu_shader * fs,unsigned num_units)5637 tu_emit_fdm_params(struct tu_cmd_buffer *cmd,
5638 struct tu_cs *cs, struct tu_shader *fs,
5639 unsigned num_units)
5640 {
5641 STATIC_ASSERT(IR3_DP_FS(frag_invocation_count) == IR3_DP_FS_DYNAMIC);
5642 tu_cs_emit(cs, fs->fs.per_samp ?
5643 cmd->vk.dynamic_graphics_state.ms.rasterization_samples : 1);
5644 tu_cs_emit(cs, 0);
5645 tu_cs_emit(cs, 0);
5646 tu_cs_emit(cs, 0);
5647
5648 STATIC_ASSERT(IR3_DP_FS(frag_size) == IR3_DP_FS_DYNAMIC + 4);
5649 STATIC_ASSERT(IR3_DP_FS(frag_offset) == IR3_DP_FS_DYNAMIC + 6);
5650 if (num_units > 1) {
5651 if (fs->fs.has_fdm) {
5652 struct apply_fs_params_state state = {
5653 .num_consts = num_units - 1,
5654 };
5655 tu_create_fdm_bin_patchpoint(cmd, cs, 4 * (num_units - 1),
5656 fdm_apply_fs_params, state);
5657 } else {
5658 for (unsigned i = 1; i < num_units; i++) {
5659 tu_cs_emit(cs, 1);
5660 tu_cs_emit(cs, 1);
5661 tu_cs_emit(cs, fui(0.0f));
5662 tu_cs_emit(cs, fui(0.0f));
5663 }
5664 }
5665 }
5666 }
5667
5668 static void
tu6_emit_fs_params(struct tu_cmd_buffer * cmd)5669 tu6_emit_fs_params(struct tu_cmd_buffer *cmd)
5670 {
5671 uint32_t offset = fs_params_offset(cmd);
5672
5673 if (offset == 0) {
5674 cmd->state.fs_params = (struct tu_draw_state) {};
5675 return;
5676 }
5677
5678 struct tu_shader *fs = cmd->state.shaders[MESA_SHADER_FRAGMENT];
5679
5680 unsigned num_units = fs_params_size(cmd);
5681
5682 if (fs->fs.has_fdm)
5683 tu_cs_set_writeable(&cmd->sub_cs, true);
5684
5685 struct tu_cs cs;
5686 VkResult result = tu_cs_begin_sub_stream(&cmd->sub_cs, 4 + 4 * num_units, &cs);
5687 if (result != VK_SUCCESS) {
5688 tu_cs_set_writeable(&cmd->sub_cs, false);
5689 vk_command_buffer_set_error(&cmd->vk, result);
5690 return;
5691 }
5692
5693 tu_cs_emit_pkt7(&cs, CP_LOAD_STATE6_FRAG, 3 + 4 * num_units);
5694 tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(offset) |
5695 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
5696 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
5697 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_FS_SHADER) |
5698 CP_LOAD_STATE6_0_NUM_UNIT(num_units));
5699 tu_cs_emit(&cs, 0);
5700 tu_cs_emit(&cs, 0);
5701
5702 tu_emit_fdm_params(cmd, &cs, fs, num_units);
5703
5704 cmd->state.fs_params = tu_cs_end_draw_state(&cmd->sub_cs, &cs);
5705
5706 if (fs->fs.has_fdm)
5707 tu_cs_set_writeable(&cmd->sub_cs, false);
5708 }
5709
5710 static void
tu7_emit_fs_params(struct tu_cmd_buffer * cmd)5711 tu7_emit_fs_params(struct tu_cmd_buffer *cmd)
5712 {
5713 struct tu_shader *fs = cmd->state.shaders[MESA_SHADER_FRAGMENT];
5714
5715 int ubo_offset = fs->const_state.fdm_ubo.idx;
5716 if (ubo_offset < 0) {
5717 cmd->state.fs_params = (struct tu_draw_state) {};
5718 return;
5719 }
5720
5721 unsigned num_units = DIV_ROUND_UP(fs->const_state.fdm_ubo.size, 4);
5722
5723 if (fs->fs.has_fdm)
5724 tu_cs_set_writeable(&cmd->sub_cs, true);
5725
5726 struct tu_cs cs;
5727 VkResult result =
5728 tu_cs_begin_sub_stream_aligned(&cmd->sub_cs, num_units, 4, &cs);
5729 if (result != VK_SUCCESS) {
5730 tu_cs_set_writeable(&cmd->sub_cs, false);
5731 vk_command_buffer_set_error(&cmd->vk, result);
5732 return;
5733 }
5734
5735 tu_emit_fdm_params(cmd, &cs, fs, num_units);
5736
5737 struct tu_draw_state fdm_ubo = tu_cs_end_draw_state(&cmd->sub_cs, &cs);
5738
5739 if (fs->fs.has_fdm)
5740 tu_cs_set_writeable(&cmd->sub_cs, false);
5741
5742 result = tu_cs_begin_sub_stream(&cmd->sub_cs, 6, &cs);
5743 if (result != VK_SUCCESS) {
5744 vk_command_buffer_set_error(&cmd->vk, result);
5745 return;
5746 }
5747
5748 tu_cs_emit_pkt7(&cs, CP_LOAD_STATE6_FRAG, 5);
5749 tu_cs_emit(&cs,
5750 CP_LOAD_STATE6_0_DST_OFF(ubo_offset) |
5751 CP_LOAD_STATE6_0_STATE_TYPE(ST6_UBO)|
5752 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
5753 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_FS_SHADER) |
5754 CP_LOAD_STATE6_0_NUM_UNIT(1));
5755 tu_cs_emit(&cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
5756 tu_cs_emit(&cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
5757 tu_cs_emit_qw(&cs,
5758 fdm_ubo.iova |
5759 (uint64_t)A6XX_UBO_1_SIZE(num_units) << 32);
5760
5761 cmd->state.fs_params = tu_cs_end_draw_state(&cmd->sub_cs, &cs);
5762 }
5763
5764 static void
tu_emit_fs_params(struct tu_cmd_buffer * cmd)5765 tu_emit_fs_params(struct tu_cmd_buffer *cmd)
5766 {
5767 if (cmd->device->compiler->load_shader_consts_via_preamble)
5768 tu7_emit_fs_params(cmd);
5769 else
5770 tu6_emit_fs_params(cmd);
5771 }
5772
5773 static void
tu_flush_dynamic_input_attachments(struct tu_cmd_buffer * cmd)5774 tu_flush_dynamic_input_attachments(struct tu_cmd_buffer *cmd)
5775 {
5776 struct tu_shader *fs = cmd->state.shaders[MESA_SHADER_FRAGMENT];
5777
5778 if (!fs->fs.dynamic_input_attachments_used)
5779 return;
5780
5781 /* Input attachments may read data from a load op, so we have to invalidate
5782 * UCHE and force pending blits to complete unless we know it's already
5783 * been invalidated. This is the same as tu_subpass::feedback_invalidate
5784 * but for dynamic renderpasses.
5785 */
5786 if (!cmd->state.blit_cache_cleaned) {
5787 cmd->state.renderpass_cache.flush_bits |=
5788 TU_CMD_FLAG_CACHE_INVALIDATE | TU_CMD_FLAG_BLIT_CACHE_CLEAN |
5789 TU_CMD_FLAG_WAIT_FOR_IDLE;
5790 }
5791 }
5792
5793 template <chip CHIP>
5794 static VkResult
tu6_draw_common(struct tu_cmd_buffer * cmd,struct tu_cs * cs,bool indexed,uint32_t draw_count)5795 tu6_draw_common(struct tu_cmd_buffer *cmd,
5796 struct tu_cs *cs,
5797 bool indexed,
5798 /* note: draw_count is 0 for indirect */
5799 uint32_t draw_count)
5800 {
5801 const struct tu_program_state *program = &cmd->state.program;
5802 struct tu_render_pass_state *rp = &cmd->state.rp;
5803
5804 /* Emit state first, because it's needed for bandwidth calculations */
5805 uint32_t dynamic_draw_state_dirty = 0;
5806 if (!BITSET_IS_EMPTY(cmd->vk.dynamic_graphics_state.dirty) ||
5807 (cmd->state.dirty & ~TU_CMD_DIRTY_COMPUTE_DESC_SETS)) {
5808 dynamic_draw_state_dirty = tu_emit_draw_state<CHIP>(cmd);
5809 }
5810
5811 /* Primitive restart value works in non-indexed draws, we have to disable
5812 * prim restart for such draws since we may read stale restart index.
5813 */
5814 if (cmd->state.last_draw_indexed != indexed) {
5815 cmd->state.last_draw_indexed = indexed;
5816 BITSET_SET(cmd->vk.dynamic_graphics_state.dirty,
5817 MESA_VK_DYNAMIC_IA_PRIMITIVE_RESTART_ENABLE);
5818 }
5819
5820 /* Fill draw stats for autotuner */
5821 rp->drawcall_count++;
5822
5823 rp->drawcall_bandwidth_per_sample_sum +=
5824 cmd->state.bandwidth.color_bandwidth_per_sample;
5825
5826 /* add depth memory bandwidth cost */
5827 const uint32_t depth_bandwidth = cmd->state.bandwidth.depth_cpp_per_sample;
5828 if (cmd->vk.dynamic_graphics_state.ds.depth.write_enable)
5829 rp->drawcall_bandwidth_per_sample_sum += depth_bandwidth;
5830 if (cmd->vk.dynamic_graphics_state.ds.depth.test_enable)
5831 rp->drawcall_bandwidth_per_sample_sum += depth_bandwidth;
5832
5833 /* add stencil memory bandwidth cost */
5834 const uint32_t stencil_bandwidth =
5835 cmd->state.bandwidth.stencil_cpp_per_sample;
5836 if (cmd->vk.dynamic_graphics_state.ds.stencil.test_enable)
5837 rp->drawcall_bandwidth_per_sample_sum += stencil_bandwidth * 2;
5838
5839 if (cmd->state.dirty & TU_CMD_DIRTY_FS)
5840 tu_flush_dynamic_input_attachments(cmd);
5841
5842 tu_emit_cache_flush_renderpass<CHIP>(cmd);
5843
5844 if (BITSET_TEST(cmd->vk.dynamic_graphics_state.dirty,
5845 MESA_VK_DYNAMIC_IA_PRIMITIVE_RESTART_ENABLE) ||
5846 BITSET_TEST(cmd->vk.dynamic_graphics_state.dirty,
5847 MESA_VK_DYNAMIC_RS_PROVOKING_VERTEX) ||
5848 (cmd->state.dirty & TU_CMD_DIRTY_DRAW_STATE)) {
5849 bool primitive_restart_enabled =
5850 cmd->vk.dynamic_graphics_state.ia.primitive_restart_enable;
5851
5852 bool primitive_restart = primitive_restart_enabled && indexed;
5853 bool provoking_vtx_last =
5854 cmd->vk.dynamic_graphics_state.rs.provoking_vertex ==
5855 VK_PROVOKING_VERTEX_MODE_LAST_VERTEX_EXT;
5856
5857 uint32_t primitive_cntl_0 =
5858 A6XX_PC_PRIMITIVE_CNTL_0(.primitive_restart = primitive_restart,
5859 .provoking_vtx_last = provoking_vtx_last).value;
5860 tu_cs_emit_regs(cs, A6XX_PC_PRIMITIVE_CNTL_0(.dword = primitive_cntl_0));
5861 if (CHIP == A7XX) {
5862 tu_cs_emit_regs(cs, A7XX_VPC_PRIMITIVE_CNTL_0(.dword = primitive_cntl_0));
5863 }
5864 }
5865
5866 struct tu_tess_params *tess_params = &cmd->state.tess_params;
5867 if ((cmd->state.dirty & TU_CMD_DIRTY_TESS_PARAMS) ||
5868 BITSET_TEST(cmd->vk.dynamic_graphics_state.dirty,
5869 MESA_VK_DYNAMIC_TS_DOMAIN_ORIGIN) ||
5870 (cmd->state.dirty & TU_CMD_DIRTY_DRAW_STATE)) {
5871 bool tess_upper_left_domain_origin =
5872 (VkTessellationDomainOrigin)cmd->vk.dynamic_graphics_state.ts.domain_origin ==
5873 VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT;
5874 tu_cs_emit_regs(cs, A6XX_PC_TESS_CNTL(
5875 .spacing = tess_params->spacing,
5876 .output = tess_upper_left_domain_origin ?
5877 tess_params->output_upper_left :
5878 tess_params->output_lower_left));
5879 }
5880
5881 if (cmd->device->physical_device->info->a7xx.has_rt_workaround &&
5882 cmd->state.program.uses_ray_intersection) {
5883 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
5884 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_SHADER_USES_RT);
5885 }
5886
5887 /* Early exit if there is nothing to emit, saves CPU cycles */
5888 uint32_t dirty = cmd->state.dirty;
5889 if (!dynamic_draw_state_dirty && !(dirty & ~TU_CMD_DIRTY_COMPUTE_DESC_SETS))
5890 return VK_SUCCESS;
5891
5892 bool dirty_lrz =
5893 (dirty & TU_CMD_DIRTY_LRZ) ||
5894 BITSET_TEST(cmd->vk.dynamic_graphics_state.dirty,
5895 MESA_VK_DYNAMIC_DS_DEPTH_TEST_ENABLE) ||
5896 BITSET_TEST(cmd->vk.dynamic_graphics_state.dirty,
5897 MESA_VK_DYNAMIC_DS_DEPTH_WRITE_ENABLE) ||
5898 BITSET_TEST(cmd->vk.dynamic_graphics_state.dirty,
5899 MESA_VK_DYNAMIC_DS_DEPTH_BOUNDS_TEST_ENABLE) ||
5900 BITSET_TEST(cmd->vk.dynamic_graphics_state.dirty,
5901 MESA_VK_DYNAMIC_DS_DEPTH_COMPARE_OP) ||
5902 BITSET_TEST(cmd->vk.dynamic_graphics_state.dirty,
5903 MESA_VK_DYNAMIC_DS_STENCIL_TEST_ENABLE) ||
5904 BITSET_TEST(cmd->vk.dynamic_graphics_state.dirty,
5905 MESA_VK_DYNAMIC_DS_STENCIL_OP) ||
5906 BITSET_TEST(cmd->vk.dynamic_graphics_state.dirty,
5907 MESA_VK_DYNAMIC_DS_STENCIL_WRITE_MASK) ||
5908 BITSET_TEST(cmd->vk.dynamic_graphics_state.dirty,
5909 MESA_VK_DYNAMIC_MS_ALPHA_TO_COVERAGE_ENABLE) ||
5910 BITSET_TEST(cmd->vk.dynamic_graphics_state.dirty,
5911 MESA_VK_DYNAMIC_ATTACHMENT_FEEDBACK_LOOP_ENABLE);
5912
5913 if (dirty_lrz) {
5914 struct tu_cs cs;
5915 uint32_t size = 8 +
5916 (cmd->device->physical_device->info->a6xx.lrz_track_quirk ? 2 : 0) +
5917 (CHIP >= A7XX ? 2 : 0); // A7XX has extra packets from LRZ_CNTL2.
5918
5919 cmd->state.lrz_and_depth_plane_state =
5920 tu_cs_draw_state(&cmd->sub_cs, &cs, size);
5921 tu6_update_simplified_stencil_state(cmd);
5922 tu6_emit_lrz<CHIP>(cmd, &cs);
5923 tu6_build_depth_plane_z_mode(cmd, &cs);
5924 }
5925
5926 if (BITSET_TEST(cmd->vk.dynamic_graphics_state.dirty,
5927 MESA_VK_DYNAMIC_ATTACHMENT_FEEDBACK_LOOP_ENABLE)) {
5928 if (cmd->vk.dynamic_graphics_state.feedback_loops &&
5929 !cmd->state.rp.disable_gmem) {
5930 perf_debug(
5931 cmd->device,
5932 "Disabling gmem due to VK_EXT_attachment_feedback_loop_layout");
5933 cmd->state.rp.disable_gmem = true;
5934 }
5935 }
5936
5937 if (BITSET_TEST(cmd->vk.dynamic_graphics_state.dirty,
5938 MESA_VK_DYNAMIC_VI_BINDINGS_VALID)) {
5939 cmd->state.vertex_buffers.size =
5940 util_last_bit(cmd->vk.dynamic_graphics_state.vi_bindings_valid) * 4;
5941 dirty |= TU_CMD_DIRTY_VERTEX_BUFFERS;
5942 }
5943
5944 if (dirty & TU_CMD_DIRTY_SHADER_CONSTS)
5945 cmd->state.shader_const = tu_emit_consts(cmd, false);
5946
5947 if (dirty & TU_CMD_DIRTY_DESC_SETS)
5948 tu6_emit_descriptor_sets<CHIP>(cmd, VK_PIPELINE_BIND_POINT_GRAPHICS);
5949
5950 if (BITSET_TEST(cmd->vk.dynamic_graphics_state.dirty,
5951 MESA_VK_DYNAMIC_MS_RASTERIZATION_SAMPLES) ||
5952 BITSET_TEST(cmd->vk.dynamic_graphics_state.dirty,
5953 MESA_VK_DYNAMIC_IA_PRIMITIVE_TOPOLOGY) ||
5954 BITSET_TEST(cmd->vk.dynamic_graphics_state.dirty,
5955 MESA_VK_DYNAMIC_RS_LINE_MODE) ||
5956 (cmd->state.dirty & TU_CMD_DIRTY_TES) ||
5957 (cmd->state.dirty & TU_CMD_DIRTY_DRAW_STATE)) {
5958 tu6_update_msaa_disable(cmd);
5959 }
5960
5961 if (BITSET_TEST(cmd->vk.dynamic_graphics_state.dirty,
5962 MESA_VK_DYNAMIC_MS_RASTERIZATION_SAMPLES) ||
5963 (cmd->state.dirty & TU_CMD_DIRTY_DRAW_STATE)) {
5964 tu6_update_msaa(cmd);
5965 }
5966
5967 bool dirty_fs_params = false;
5968 if (BITSET_TEST(cmd->vk.dynamic_graphics_state.dirty,
5969 MESA_VK_DYNAMIC_MS_RASTERIZATION_SAMPLES) ||
5970 (cmd->state.dirty & (TU_CMD_DIRTY_PROGRAM | TU_CMD_DIRTY_FDM))) {
5971 tu_emit_fs_params(cmd);
5972 dirty_fs_params = true;
5973 }
5974
5975 /* for the first draw in a renderpass, re-emit all the draw states
5976 *
5977 * and if a draw-state disabling path (CmdClearAttachments 3D fallback) was
5978 * used, then draw states must be re-emitted. note however this only happens
5979 * in the sysmem path, so this can be skipped this for the gmem path (TODO)
5980 *
5981 * the two input attachment states are excluded because secondary command
5982 * buffer doesn't have a state ib to restore it, and not re-emitting them
5983 * is OK since CmdClearAttachments won't disable/overwrite them
5984 */
5985 if (dirty & TU_CMD_DIRTY_DRAW_STATE) {
5986 tu_pipeline_update_rp_state(&cmd->state);
5987
5988 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3 * (TU_DRAW_STATE_COUNT - 2));
5989
5990 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_PROGRAM_CONFIG, program->config_state);
5991 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VS, program->vs_state);
5992 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VS_BINNING, program->vs_binning_state);
5993 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_HS, program->hs_state);
5994 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_DS, program->ds_state);
5995 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_GS, program->gs_state);
5996 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_GS_BINNING, program->gs_binning_state);
5997 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_FS, program->fs_state);
5998 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VPC, program->vpc_state);
5999 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_PRIM_MODE_GMEM, cmd->state.prim_order_gmem);
6000 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_CONST, cmd->state.shader_const);
6001 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_DESC_SETS, cmd->state.desc_sets);
6002 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_DESC_SETS_LOAD, cmd->state.load_state);
6003 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VB, cmd->state.vertex_buffers);
6004 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VS_PARAMS, cmd->state.vs_params);
6005 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_FS_PARAMS, cmd->state.fs_params);
6006 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_LRZ_AND_DEPTH_PLANE, cmd->state.lrz_and_depth_plane_state);
6007
6008 for (uint32_t i = 0; i < ARRAY_SIZE(cmd->state.dynamic_state); i++) {
6009 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_DYNAMIC + i,
6010 cmd->state.dynamic_state[i]);
6011 }
6012 } else {
6013 /* emit draw states that were just updated */
6014 uint32_t draw_state_count =
6015 util_bitcount(dynamic_draw_state_dirty) +
6016 ((dirty & TU_CMD_DIRTY_SHADER_CONSTS) ? 1 : 0) +
6017 ((dirty & TU_CMD_DIRTY_DESC_SETS) ? 1 : 0) +
6018 ((dirty & TU_CMD_DIRTY_VERTEX_BUFFERS) ? 1 : 0) +
6019 ((dirty & TU_CMD_DIRTY_VS_PARAMS) ? 1 : 0) +
6020 (dirty_fs_params ? 1 : 0) +
6021 (dirty_lrz ? 1 : 0);
6022
6023 if (draw_state_count > 0)
6024 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3 * draw_state_count);
6025
6026 if (dirty & TU_CMD_DIRTY_SHADER_CONSTS)
6027 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_CONST, cmd->state.shader_const);
6028 if (dirty & TU_CMD_DIRTY_DESC_SETS) {
6029 /* tu6_emit_descriptor_sets emitted the cmd->state.desc_sets draw state. */
6030 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_DESC_SETS_LOAD, cmd->state.load_state);
6031 }
6032 if (dirty & TU_CMD_DIRTY_VERTEX_BUFFERS)
6033 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VB, cmd->state.vertex_buffers);
6034 u_foreach_bit (i, dynamic_draw_state_dirty) {
6035 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_DYNAMIC + i,
6036 cmd->state.dynamic_state[i]);
6037 }
6038 if (dirty & TU_CMD_DIRTY_VS_PARAMS)
6039 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VS_PARAMS, cmd->state.vs_params);
6040 if (dirty_fs_params)
6041 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_FS_PARAMS, cmd->state.fs_params);
6042 if (dirty_lrz) {
6043 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_LRZ_AND_DEPTH_PLANE, cmd->state.lrz_and_depth_plane_state);
6044 }
6045 }
6046
6047 tu_cs_sanity_check(cs);
6048
6049 /* There are too many graphics dirty bits to list here, so just list the
6050 * bits to preserve instead. The only things not emitted here are
6051 * compute-related state.
6052 */
6053 cmd->state.dirty &= TU_CMD_DIRTY_COMPUTE_DESC_SETS;
6054 BITSET_ZERO(cmd->vk.dynamic_graphics_state.dirty);
6055 return VK_SUCCESS;
6056 }
6057
6058 static uint32_t
tu_draw_initiator(struct tu_cmd_buffer * cmd,enum pc_di_src_sel src_sel)6059 tu_draw_initiator(struct tu_cmd_buffer *cmd, enum pc_di_src_sel src_sel)
6060 {
6061 enum pc_di_primtype primtype =
6062 tu6_primtype((VkPrimitiveTopology)cmd->vk.dynamic_graphics_state.ia.primitive_topology);
6063
6064 if (primtype == DI_PT_PATCHES0)
6065 primtype = (enum pc_di_primtype) (primtype +
6066 cmd->vk.dynamic_graphics_state.ts.patch_control_points);
6067
6068 uint32_t initiator =
6069 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
6070 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(src_sel) |
6071 CP_DRAW_INDX_OFFSET_0_INDEX_SIZE((enum a4xx_index_size) cmd->state.index_size) |
6072 CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY);
6073
6074 if (cmd->state.shaders[MESA_SHADER_GEOMETRY]->variant)
6075 initiator |= CP_DRAW_INDX_OFFSET_0_GS_ENABLE;
6076
6077 const struct tu_shader *tes = cmd->state.shaders[MESA_SHADER_TESS_EVAL];
6078 if (tes->variant) {
6079 switch (tes->variant->key.tessellation) {
6080 case IR3_TESS_TRIANGLES:
6081 initiator |= CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(TESS_TRIANGLES) |
6082 CP_DRAW_INDX_OFFSET_0_TESS_ENABLE;
6083 break;
6084 case IR3_TESS_ISOLINES:
6085 initiator |= CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(TESS_ISOLINES) |
6086 CP_DRAW_INDX_OFFSET_0_TESS_ENABLE;
6087 break;
6088 case IR3_TESS_QUADS:
6089 initiator |= CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(TESS_QUADS) |
6090 CP_DRAW_INDX_OFFSET_0_TESS_ENABLE;
6091 break;
6092 }
6093 }
6094 return initiator;
6095 }
6096
6097
6098 static uint32_t
vs_params_offset(struct tu_cmd_buffer * cmd)6099 vs_params_offset(struct tu_cmd_buffer *cmd)
6100 {
6101 const struct tu_program_descriptor_linkage *link =
6102 &cmd->state.program.link[MESA_SHADER_VERTEX];
6103 const struct ir3_const_state *const_state = &link->const_state;
6104
6105 uint32_t param_offset =
6106 const_state->allocs.consts[IR3_CONST_ALLOC_DRIVER_PARAMS].offset_vec4;
6107
6108 if (!ir3_const_can_upload(&const_state->allocs,
6109 IR3_CONST_ALLOC_DRIVER_PARAMS, link->constlen))
6110 return 0;
6111
6112 /* this layout is required by CP_DRAW_INDIRECT_MULTI */
6113 STATIC_ASSERT(IR3_DP_VS(draw_id) == 0);
6114 STATIC_ASSERT(IR3_DP_VS(vtxid_base) == 1);
6115 STATIC_ASSERT(IR3_DP_VS(instid_base) == 2);
6116
6117 /* 0 means disabled for CP_DRAW_INDIRECT_MULTI */
6118 assert(param_offset != 0);
6119
6120 return param_offset;
6121 }
6122
6123 static void
tu6_emit_empty_vs_params(struct tu_cmd_buffer * cmd)6124 tu6_emit_empty_vs_params(struct tu_cmd_buffer *cmd)
6125 {
6126 if (cmd->state.vs_params.iova) {
6127 cmd->state.vs_params = (struct tu_draw_state) {};
6128 cmd->state.dirty |= TU_CMD_DIRTY_VS_PARAMS;
6129 }
6130 }
6131
6132 static void
tu6_emit_vs_params(struct tu_cmd_buffer * cmd,uint32_t draw_id,uint32_t vertex_offset,uint32_t first_instance)6133 tu6_emit_vs_params(struct tu_cmd_buffer *cmd,
6134 uint32_t draw_id,
6135 uint32_t vertex_offset,
6136 uint32_t first_instance)
6137 {
6138 uint32_t offset = vs_params_offset(cmd);
6139
6140 /* Beside re-emitting params when they are changed, we should re-emit
6141 * them after constants are invalidated via HLSQ_INVALIDATE_CMD or after we
6142 * emit an empty vs params.
6143 */
6144 if (!(cmd->state.dirty & (TU_CMD_DIRTY_DRAW_STATE | TU_CMD_DIRTY_VS_PARAMS |
6145 TU_CMD_DIRTY_PROGRAM)) &&
6146 cmd->state.vs_params.iova &&
6147 (offset == 0 || draw_id == cmd->state.last_vs_params.draw_id) &&
6148 vertex_offset == cmd->state.last_vs_params.vertex_offset &&
6149 first_instance == cmd->state.last_vs_params.first_instance) {
6150 return;
6151 }
6152
6153 uint64_t consts_iova = 0;
6154 if (offset) {
6155 struct tu_cs_memory consts;
6156 VkResult result = tu_cs_alloc(&cmd->sub_cs, 1, 4, &consts);
6157 if (result != VK_SUCCESS) {
6158 vk_command_buffer_set_error(&cmd->vk, result);
6159 return;
6160 }
6161 consts.map[0] = draw_id;
6162 consts.map[1] = vertex_offset;
6163 consts.map[2] = first_instance;
6164 consts.map[3] = 0;
6165
6166 consts_iova = consts.iova;
6167 }
6168
6169 struct tu_cs cs;
6170 VkResult result = tu_cs_begin_sub_stream(&cmd->sub_cs, 3 + (offset ? 4 : 0), &cs);
6171 if (result != VK_SUCCESS) {
6172 vk_command_buffer_set_error(&cmd->vk, result);
6173 return;
6174 }
6175
6176 tu_cs_emit_regs(&cs,
6177 A6XX_VFD_INDEX_OFFSET(vertex_offset),
6178 A6XX_VFD_INSTANCE_START_OFFSET(first_instance));
6179
6180 /* It is implemented as INDIRECT load even on a750+ because with UBO
6181 * lowering it would be tricky to get const offset for to use in multidraw,
6182 * also we would need to ensure the offset is not 0.
6183 * TODO/A7XX: Rework vs params to use UBO lowering.
6184 */
6185 if (offset) {
6186 tu_cs_emit_pkt7(&cs, CP_LOAD_STATE6_GEOM, 3);
6187 tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(offset) |
6188 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
6189 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
6190 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_VS_SHADER) |
6191 CP_LOAD_STATE6_0_NUM_UNIT(1));
6192 tu_cs_emit_qw(&cs, consts_iova);
6193 }
6194
6195 cmd->state.last_vs_params.vertex_offset = vertex_offset;
6196 cmd->state.last_vs_params.first_instance = first_instance;
6197 cmd->state.last_vs_params.draw_id = draw_id;
6198
6199 struct tu_cs_entry entry = tu_cs_end_sub_stream(&cmd->sub_cs, &cs);
6200 cmd->state.vs_params = (struct tu_draw_state) {entry.bo->iova + entry.offset, entry.size / 4};
6201
6202 cmd->state.dirty |= TU_CMD_DIRTY_VS_PARAMS;
6203 }
6204
6205 template <chip CHIP>
6206 VKAPI_ATTR void VKAPI_CALL
tu_CmdDraw(VkCommandBuffer commandBuffer,uint32_t vertexCount,uint32_t instanceCount,uint32_t firstVertex,uint32_t firstInstance)6207 tu_CmdDraw(VkCommandBuffer commandBuffer,
6208 uint32_t vertexCount,
6209 uint32_t instanceCount,
6210 uint32_t firstVertex,
6211 uint32_t firstInstance)
6212 {
6213 VK_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
6214 struct tu_cs *cs = &cmd->draw_cs;
6215
6216 tu6_emit_vs_params(cmd, 0, firstVertex, firstInstance);
6217
6218 tu6_draw_common<CHIP>(cmd, cs, false, vertexCount);
6219
6220 tu_cs_emit_pkt7(cs, CP_DRAW_INDX_OFFSET, 3);
6221 tu_cs_emit(cs, tu_draw_initiator(cmd, DI_SRC_SEL_AUTO_INDEX));
6222 tu_cs_emit(cs, instanceCount);
6223 tu_cs_emit(cs, vertexCount);
6224 }
6225 TU_GENX(tu_CmdDraw);
6226
6227 template <chip CHIP>
6228 VKAPI_ATTR void VKAPI_CALL
tu_CmdDrawMultiEXT(VkCommandBuffer commandBuffer,uint32_t drawCount,const VkMultiDrawInfoEXT * pVertexInfo,uint32_t instanceCount,uint32_t firstInstance,uint32_t stride)6229 tu_CmdDrawMultiEXT(VkCommandBuffer commandBuffer,
6230 uint32_t drawCount,
6231 const VkMultiDrawInfoEXT *pVertexInfo,
6232 uint32_t instanceCount,
6233 uint32_t firstInstance,
6234 uint32_t stride)
6235 {
6236 VK_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
6237 struct tu_cs *cs = &cmd->draw_cs;
6238
6239 if (!drawCount)
6240 return;
6241
6242 bool has_tess = cmd->state.shaders[MESA_SHADER_TESS_CTRL]->variant;
6243
6244 uint32_t max_vertex_count = 0;
6245 if (has_tess) {
6246 uint32_t i = 0;
6247 vk_foreach_multi_draw(draw, i, pVertexInfo, drawCount, stride) {
6248 max_vertex_count = MAX2(max_vertex_count, draw->vertexCount);
6249 }
6250 }
6251
6252 uint32_t i = 0;
6253 vk_foreach_multi_draw(draw, i, pVertexInfo, drawCount, stride) {
6254 tu6_emit_vs_params(cmd, i, draw->firstVertex, firstInstance);
6255
6256 if (i == 0)
6257 tu6_draw_common<CHIP>(cmd, cs, false, max_vertex_count);
6258
6259 if (cmd->state.dirty & TU_CMD_DIRTY_VS_PARAMS) {
6260 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
6261 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VS_PARAMS, cmd->state.vs_params);
6262 cmd->state.dirty &= ~TU_CMD_DIRTY_VS_PARAMS;
6263 }
6264
6265 tu_cs_emit_pkt7(cs, CP_DRAW_INDX_OFFSET, 3);
6266 tu_cs_emit(cs, tu_draw_initiator(cmd, DI_SRC_SEL_AUTO_INDEX));
6267 tu_cs_emit(cs, instanceCount);
6268 tu_cs_emit(cs, draw->vertexCount);
6269 }
6270 }
6271 TU_GENX(tu_CmdDrawMultiEXT);
6272
6273 template <chip CHIP>
6274 VKAPI_ATTR void VKAPI_CALL
tu_CmdDrawIndexed(VkCommandBuffer commandBuffer,uint32_t indexCount,uint32_t instanceCount,uint32_t firstIndex,int32_t vertexOffset,uint32_t firstInstance)6275 tu_CmdDrawIndexed(VkCommandBuffer commandBuffer,
6276 uint32_t indexCount,
6277 uint32_t instanceCount,
6278 uint32_t firstIndex,
6279 int32_t vertexOffset,
6280 uint32_t firstInstance)
6281 {
6282 VK_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
6283 struct tu_cs *cs = &cmd->draw_cs;
6284
6285 tu6_emit_vs_params(cmd, 0, vertexOffset, firstInstance);
6286
6287 tu6_draw_common<CHIP>(cmd, cs, true, indexCount);
6288
6289 tu_cs_emit_pkt7(cs, CP_DRAW_INDX_OFFSET, 7);
6290 tu_cs_emit(cs, tu_draw_initiator(cmd, DI_SRC_SEL_DMA));
6291 tu_cs_emit(cs, instanceCount);
6292 tu_cs_emit(cs, indexCount);
6293 tu_cs_emit(cs, firstIndex);
6294 tu_cs_emit_qw(cs, cmd->state.index_va);
6295 tu_cs_emit(cs, cmd->state.max_index_count);
6296 }
6297 TU_GENX(tu_CmdDrawIndexed);
6298
6299 template <chip CHIP>
6300 VKAPI_ATTR void VKAPI_CALL
tu_CmdDrawMultiIndexedEXT(VkCommandBuffer commandBuffer,uint32_t drawCount,const VkMultiDrawIndexedInfoEXT * pIndexInfo,uint32_t instanceCount,uint32_t firstInstance,uint32_t stride,const int32_t * pVertexOffset)6301 tu_CmdDrawMultiIndexedEXT(VkCommandBuffer commandBuffer,
6302 uint32_t drawCount,
6303 const VkMultiDrawIndexedInfoEXT *pIndexInfo,
6304 uint32_t instanceCount,
6305 uint32_t firstInstance,
6306 uint32_t stride,
6307 const int32_t *pVertexOffset)
6308 {
6309 VK_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
6310 struct tu_cs *cs = &cmd->draw_cs;
6311
6312 if (!drawCount)
6313 return;
6314
6315 bool has_tess = cmd->state.shaders[MESA_SHADER_TESS_CTRL]->variant;
6316
6317 uint32_t max_index_count = 0;
6318 if (has_tess) {
6319 uint32_t i = 0;
6320 vk_foreach_multi_draw_indexed(draw, i, pIndexInfo, drawCount, stride) {
6321 max_index_count = MAX2(max_index_count, draw->indexCount);
6322 }
6323 }
6324
6325 uint32_t i = 0;
6326 vk_foreach_multi_draw_indexed(draw, i, pIndexInfo, drawCount, stride) {
6327 int32_t vertexOffset = pVertexOffset ? *pVertexOffset : draw->vertexOffset;
6328 tu6_emit_vs_params(cmd, i, vertexOffset, firstInstance);
6329
6330 if (i == 0)
6331 tu6_draw_common<CHIP>(cmd, cs, true, max_index_count);
6332
6333 if (cmd->state.dirty & TU_CMD_DIRTY_VS_PARAMS) {
6334 tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3);
6335 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VS_PARAMS, cmd->state.vs_params);
6336 cmd->state.dirty &= ~TU_CMD_DIRTY_VS_PARAMS;
6337 }
6338
6339 tu_cs_emit_pkt7(cs, CP_DRAW_INDX_OFFSET, 7);
6340 tu_cs_emit(cs, tu_draw_initiator(cmd, DI_SRC_SEL_DMA));
6341 tu_cs_emit(cs, instanceCount);
6342 tu_cs_emit(cs, draw->indexCount);
6343 tu_cs_emit(cs, draw->firstIndex);
6344 tu_cs_emit_qw(cs, cmd->state.index_va);
6345 tu_cs_emit(cs, cmd->state.max_index_count);
6346 }
6347 }
6348 TU_GENX(tu_CmdDrawMultiIndexedEXT);
6349
6350 /* Various firmware bugs/inconsistencies mean that some indirect draw opcodes
6351 * do not wait for WFI's to complete before executing. Add a WAIT_FOR_ME if
6352 * pending for these opcodes. This may result in a few extra WAIT_FOR_ME's
6353 * with these opcodes, but the alternative would add unnecessary WAIT_FOR_ME's
6354 * before draw opcodes that don't need it.
6355 */
6356 static void
draw_wfm(struct tu_cmd_buffer * cmd)6357 draw_wfm(struct tu_cmd_buffer *cmd)
6358 {
6359 cmd->state.renderpass_cache.flush_bits |=
6360 cmd->state.renderpass_cache.pending_flush_bits & TU_CMD_FLAG_WAIT_FOR_ME;
6361 cmd->state.renderpass_cache.pending_flush_bits &= ~TU_CMD_FLAG_WAIT_FOR_ME;
6362 }
6363
6364 template <chip CHIP>
6365 VKAPI_ATTR void VKAPI_CALL
tu_CmdDrawIndirect(VkCommandBuffer commandBuffer,VkBuffer _buffer,VkDeviceSize offset,uint32_t drawCount,uint32_t stride)6366 tu_CmdDrawIndirect(VkCommandBuffer commandBuffer,
6367 VkBuffer _buffer,
6368 VkDeviceSize offset,
6369 uint32_t drawCount,
6370 uint32_t stride)
6371 {
6372 VK_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
6373 VK_FROM_HANDLE(tu_buffer, buf, _buffer);
6374 struct tu_cs *cs = &cmd->draw_cs;
6375
6376 tu6_emit_empty_vs_params(cmd);
6377
6378 if (cmd->device->physical_device->info->a6xx.indirect_draw_wfm_quirk)
6379 draw_wfm(cmd);
6380
6381 tu6_draw_common<CHIP>(cmd, cs, false, 0);
6382
6383 tu_cs_emit_pkt7(cs, CP_DRAW_INDIRECT_MULTI, 6);
6384 tu_cs_emit(cs, tu_draw_initiator(cmd, DI_SRC_SEL_AUTO_INDEX));
6385 tu_cs_emit(cs, A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(INDIRECT_OP_NORMAL) |
6386 A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF(vs_params_offset(cmd)));
6387 tu_cs_emit(cs, drawCount);
6388 tu_cs_emit_qw(cs, buf->iova + offset);
6389 tu_cs_emit(cs, stride);
6390 }
6391 TU_GENX(tu_CmdDrawIndirect);
6392
6393 template <chip CHIP>
6394 VKAPI_ATTR void VKAPI_CALL
tu_CmdDrawIndexedIndirect(VkCommandBuffer commandBuffer,VkBuffer _buffer,VkDeviceSize offset,uint32_t drawCount,uint32_t stride)6395 tu_CmdDrawIndexedIndirect(VkCommandBuffer commandBuffer,
6396 VkBuffer _buffer,
6397 VkDeviceSize offset,
6398 uint32_t drawCount,
6399 uint32_t stride)
6400 {
6401 VK_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
6402 VK_FROM_HANDLE(tu_buffer, buf, _buffer);
6403 struct tu_cs *cs = &cmd->draw_cs;
6404
6405 tu6_emit_empty_vs_params(cmd);
6406
6407 if (cmd->device->physical_device->info->a6xx.indirect_draw_wfm_quirk)
6408 draw_wfm(cmd);
6409
6410 tu6_draw_common<CHIP>(cmd, cs, true, 0);
6411
6412 tu_cs_emit_pkt7(cs, CP_DRAW_INDIRECT_MULTI, 9);
6413 tu_cs_emit(cs, tu_draw_initiator(cmd, DI_SRC_SEL_DMA));
6414 tu_cs_emit(cs, A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(INDIRECT_OP_INDEXED) |
6415 A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF(vs_params_offset(cmd)));
6416 tu_cs_emit(cs, drawCount);
6417 tu_cs_emit_qw(cs, cmd->state.index_va);
6418 tu_cs_emit(cs, cmd->state.max_index_count);
6419 tu_cs_emit_qw(cs, buf->iova + offset);
6420 tu_cs_emit(cs, stride);
6421 }
6422 TU_GENX(tu_CmdDrawIndexedIndirect);
6423
6424 template <chip CHIP>
6425 VKAPI_ATTR void VKAPI_CALL
tu_CmdDrawIndirectCount(VkCommandBuffer commandBuffer,VkBuffer _buffer,VkDeviceSize offset,VkBuffer countBuffer,VkDeviceSize countBufferOffset,uint32_t drawCount,uint32_t stride)6426 tu_CmdDrawIndirectCount(VkCommandBuffer commandBuffer,
6427 VkBuffer _buffer,
6428 VkDeviceSize offset,
6429 VkBuffer countBuffer,
6430 VkDeviceSize countBufferOffset,
6431 uint32_t drawCount,
6432 uint32_t stride)
6433 {
6434 VK_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
6435 VK_FROM_HANDLE(tu_buffer, buf, _buffer);
6436 VK_FROM_HANDLE(tu_buffer, count_buf, countBuffer);
6437 struct tu_cs *cs = &cmd->draw_cs;
6438
6439 tu6_emit_empty_vs_params(cmd);
6440
6441 /* It turns out that the firmware we have for a650 only partially fixed the
6442 * problem with CP_DRAW_INDIRECT_MULTI not waiting for WFI's to complete
6443 * before reading indirect parameters. It waits for WFI's before reading
6444 * the draw parameters, but after reading the indirect count :(.
6445 */
6446 draw_wfm(cmd);
6447
6448 tu6_draw_common<CHIP>(cmd, cs, false, 0);
6449
6450 tu_cs_emit_pkt7(cs, CP_DRAW_INDIRECT_MULTI, 8);
6451 tu_cs_emit(cs, tu_draw_initiator(cmd, DI_SRC_SEL_AUTO_INDEX));
6452 tu_cs_emit(cs, A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(INDIRECT_OP_INDIRECT_COUNT) |
6453 A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF(vs_params_offset(cmd)));
6454 tu_cs_emit(cs, drawCount);
6455 tu_cs_emit_qw(cs, buf->iova + offset);
6456 tu_cs_emit_qw(cs, count_buf->iova + countBufferOffset);
6457 tu_cs_emit(cs, stride);
6458 }
6459 TU_GENX(tu_CmdDrawIndirectCount);
6460
6461 template <chip CHIP>
6462 VKAPI_ATTR void VKAPI_CALL
tu_CmdDrawIndexedIndirectCount(VkCommandBuffer commandBuffer,VkBuffer _buffer,VkDeviceSize offset,VkBuffer countBuffer,VkDeviceSize countBufferOffset,uint32_t drawCount,uint32_t stride)6463 tu_CmdDrawIndexedIndirectCount(VkCommandBuffer commandBuffer,
6464 VkBuffer _buffer,
6465 VkDeviceSize offset,
6466 VkBuffer countBuffer,
6467 VkDeviceSize countBufferOffset,
6468 uint32_t drawCount,
6469 uint32_t stride)
6470 {
6471 VK_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
6472 VK_FROM_HANDLE(tu_buffer, buf, _buffer);
6473 VK_FROM_HANDLE(tu_buffer, count_buf, countBuffer);
6474 struct tu_cs *cs = &cmd->draw_cs;
6475
6476 tu6_emit_empty_vs_params(cmd);
6477
6478 draw_wfm(cmd);
6479
6480 tu6_draw_common<CHIP>(cmd, cs, true, 0);
6481
6482 tu_cs_emit_pkt7(cs, CP_DRAW_INDIRECT_MULTI, 11);
6483 tu_cs_emit(cs, tu_draw_initiator(cmd, DI_SRC_SEL_DMA));
6484 tu_cs_emit(cs, A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(INDIRECT_OP_INDIRECT_COUNT_INDEXED) |
6485 A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF(vs_params_offset(cmd)));
6486 tu_cs_emit(cs, drawCount);
6487 tu_cs_emit_qw(cs, cmd->state.index_va);
6488 tu_cs_emit(cs, cmd->state.max_index_count);
6489 tu_cs_emit_qw(cs, buf->iova + offset);
6490 tu_cs_emit_qw(cs, count_buf->iova + countBufferOffset);
6491 tu_cs_emit(cs, stride);
6492 }
6493 TU_GENX(tu_CmdDrawIndexedIndirectCount);
6494
6495 template <chip CHIP>
6496 VKAPI_ATTR void VKAPI_CALL
tu_CmdDrawIndirectByteCountEXT(VkCommandBuffer commandBuffer,uint32_t instanceCount,uint32_t firstInstance,VkBuffer _counterBuffer,VkDeviceSize counterBufferOffset,uint32_t counterOffset,uint32_t vertexStride)6497 tu_CmdDrawIndirectByteCountEXT(VkCommandBuffer commandBuffer,
6498 uint32_t instanceCount,
6499 uint32_t firstInstance,
6500 VkBuffer _counterBuffer,
6501 VkDeviceSize counterBufferOffset,
6502 uint32_t counterOffset,
6503 uint32_t vertexStride)
6504 {
6505 VK_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
6506 VK_FROM_HANDLE(tu_buffer, buf, _counterBuffer);
6507 struct tu_cs *cs = &cmd->draw_cs;
6508
6509 /* All known firmware versions do not wait for WFI's with CP_DRAW_AUTO.
6510 * Plus, for the common case where the counter buffer is written by
6511 * vkCmdEndTransformFeedback, we need to wait for the CP_WAIT_MEM_WRITES to
6512 * complete which means we need a WAIT_FOR_ME anyway.
6513 */
6514 draw_wfm(cmd);
6515
6516 tu6_emit_vs_params(cmd, 0, 0, firstInstance);
6517
6518 tu6_draw_common<CHIP>(cmd, cs, false, 0);
6519
6520 tu_cs_emit_pkt7(cs, CP_DRAW_AUTO, 6);
6521 if (CHIP == A6XX) {
6522 tu_cs_emit(cs, tu_draw_initiator(cmd, DI_SRC_SEL_AUTO_XFB));
6523 } else {
6524 tu_cs_emit(cs, tu_draw_initiator(cmd, DI_SRC_SEL_AUTO_INDEX));
6525 /* On a7xx the counter value and offset are shifted right by 2, so
6526 * the vertexStride should also be in units of dwords.
6527 */
6528 vertexStride = vertexStride >> 2;
6529 }
6530 tu_cs_emit(cs, instanceCount);
6531 tu_cs_emit_qw(cs, buf->iova + counterBufferOffset);
6532 tu_cs_emit(cs, counterOffset);
6533 tu_cs_emit(cs, vertexStride);
6534 }
6535 TU_GENX(tu_CmdDrawIndirectByteCountEXT);
6536
6537 struct tu_dispatch_info
6538 {
6539 /**
6540 * Determine the layout of the grid (in block units) to be used.
6541 */
6542 uint32_t blocks[3];
6543
6544 /**
6545 * A starting offset for the grid. If unaligned is set, the offset
6546 * must still be aligned.
6547 */
6548 uint32_t offsets[3];
6549 /**
6550 * Whether it's an unaligned compute dispatch.
6551 */
6552 bool unaligned;
6553
6554 /**
6555 * Indirect compute parameters resource.
6556 */
6557 VkDeviceAddress indirect;
6558 };
6559
6560 static inline struct ir3_driver_params_cs
build_driver_params_cs(const struct ir3_shader_variant * variant,const struct tu_dispatch_info * info)6561 build_driver_params_cs(const struct ir3_shader_variant *variant,
6562 const struct tu_dispatch_info *info)
6563 {
6564 unsigned subgroup_size = variant->info.subgroup_size;
6565 unsigned subgroup_shift = util_logbase2(subgroup_size);
6566
6567 return (struct ir3_driver_params_cs) {
6568 .num_work_groups_x = info->blocks[0],
6569 .num_work_groups_y = info->blocks[1],
6570 .num_work_groups_z = info->blocks[2],
6571 .work_dim = 0,
6572 .base_group_x = info->offsets[0],
6573 .base_group_y = info->offsets[1],
6574 .base_group_z = info->offsets[2],
6575 .subgroup_size = subgroup_size,
6576 .local_group_size_x = 0,
6577 .local_group_size_y = 0,
6578 .local_group_size_z = 0,
6579 .subgroup_id_shift = subgroup_shift,
6580 };
6581 }
6582
6583 template <chip CHIP>
6584 static void
tu_emit_compute_driver_params(struct tu_cmd_buffer * cmd,struct tu_cs * cs,const struct tu_dispatch_info * info)6585 tu_emit_compute_driver_params(struct tu_cmd_buffer *cmd,
6586 struct tu_cs *cs,
6587 const struct tu_dispatch_info *info)
6588 {
6589 gl_shader_stage type = MESA_SHADER_COMPUTE;
6590 const struct tu_shader *shader = cmd->state.shaders[MESA_SHADER_COMPUTE];
6591 const struct ir3_shader_variant *variant = shader->variant;
6592 const struct ir3_const_state *const_state = variant->const_state;
6593 unsigned subgroup_size = variant->info.subgroup_size;
6594 unsigned subgroup_shift = util_logbase2(subgroup_size);
6595
6596 if (cmd->device->physical_device->info->a7xx.load_shader_consts_via_preamble) {
6597 uint32_t num_consts = const_state->driver_params_ubo.size;
6598 if (num_consts == 0)
6599 return;
6600
6601 bool direct_indirect_load =
6602 !(info->indirect & 0xf) &&
6603 !(info->indirect && num_consts > IR3_DP_CS(base_group_x));
6604
6605 uint64_t iova = 0;
6606
6607 if (!info->indirect) {
6608 struct ir3_driver_params_cs driver_params =
6609 build_driver_params_cs(variant, info);
6610
6611 assert(num_consts <= dword_sizeof(driver_params));
6612
6613 struct tu_cs_memory consts;
6614 uint32_t consts_vec4 = DIV_ROUND_UP(num_consts, 4);
6615 VkResult result = tu_cs_alloc(&cmd->sub_cs, consts_vec4, 4, &consts);
6616 if (result != VK_SUCCESS) {
6617 vk_command_buffer_set_error(&cmd->vk, result);
6618 return;
6619 }
6620 memcpy(consts.map, &driver_params, num_consts * sizeof(uint32_t));
6621 iova = consts.iova;
6622 } else if (direct_indirect_load) {
6623 iova = info->indirect;
6624 } else {
6625 /* Vulkan guarantees only 4 byte alignment for indirect_offset.
6626 * However, CP_LOAD_STATE.EXT_SRC_ADDR needs 16 byte alignment.
6627 */
6628
6629 uint64_t indirect_iova = info->indirect;
6630
6631 /* Wait for any previous uses to finish. */
6632 tu_cs_emit_wfi(cs);
6633
6634 for (uint32_t i = 0; i < 3; i++) {
6635 tu_cs_emit_pkt7(cs, CP_MEM_TO_MEM, 5);
6636 tu_cs_emit(cs, 0);
6637 tu_cs_emit_qw(cs, global_iova_arr(cmd, cs_indirect_xyz, i));
6638 tu_cs_emit_qw(cs, indirect_iova + i * sizeof(uint32_t));
6639 }
6640
6641 /* Fill out IR3_DP_CS_SUBGROUP_SIZE and IR3_DP_SUBGROUP_ID_SHIFT for
6642 * indirect dispatch.
6643 */
6644 if (info->indirect && num_consts > IR3_DP_CS(base_group_x)) {
6645 uint32_t indirect_driver_params[8] = {
6646 0, 0, 0, subgroup_size,
6647 0, 0, 0, subgroup_shift,
6648 };
6649 bool emit_local = num_consts > IR3_DP_CS(local_group_size_x);
6650 uint32_t emit_size = emit_local ? 8 : 4;
6651
6652 tu_cs_emit_pkt7(cs, CP_MEM_WRITE, 2 + emit_size);
6653 tu_cs_emit_qw(cs, global_iova_arr(cmd, cs_indirect_xyz, 0) + 4 * sizeof(uint32_t));
6654 for (uint32_t i = 0; i < emit_size; i++) {
6655 tu_cs_emit(cs, indirect_driver_params[i]);
6656 }
6657 }
6658
6659 tu_cs_emit_pkt7(cs, CP_WAIT_MEM_WRITES, 0);
6660 tu_emit_event_write<CHIP>(cmd, cs, FD_CACHE_INVALIDATE);
6661 tu_cs_emit_wfi(cs);
6662
6663 iova = global_iova(cmd, cs_indirect_xyz[0]);
6664 }
6665
6666 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 5);
6667 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(const_state->driver_params_ubo.idx) |
6668 CP_LOAD_STATE6_0_STATE_TYPE(ST6_UBO) |
6669 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
6670 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
6671 CP_LOAD_STATE6_0_NUM_UNIT(1));
6672 tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
6673 tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
6674 int size_vec4s = DIV_ROUND_UP(num_consts, 4);
6675 tu_cs_emit_qw(cs, iova | ((uint64_t)A6XX_UBO_1_SIZE(size_vec4s) << 32));
6676
6677 } else {
6678 uint32_t offset =
6679 const_state->allocs.consts[IR3_CONST_ALLOC_DRIVER_PARAMS].offset_vec4;
6680 if (!ir3_const_can_upload(&const_state->allocs,
6681 IR3_CONST_ALLOC_DRIVER_PARAMS,
6682 variant->constlen))
6683 return;
6684
6685 uint32_t num_consts = MIN2(const_state->num_driver_params,
6686 (variant->constlen - offset) * 4);
6687
6688 if (!info->indirect) {
6689 struct ir3_driver_params_cs driver_params =
6690 build_driver_params_cs(variant, info);
6691
6692 assert(num_consts <= dword_sizeof(driver_params));
6693
6694 /* push constants */
6695 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + num_consts);
6696 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(offset) |
6697 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
6698 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
6699 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
6700 CP_LOAD_STATE6_0_NUM_UNIT(num_consts / 4));
6701 tu_cs_emit(cs, 0);
6702 tu_cs_emit(cs, 0);
6703 tu_cs_emit_array(cs, (uint32_t *)&driver_params, num_consts);
6704 } else if (!(info->indirect & 0xf)) {
6705 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3);
6706 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(offset) |
6707 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
6708 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
6709 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
6710 CP_LOAD_STATE6_0_NUM_UNIT(1));
6711 tu_cs_emit_qw(cs, info->indirect);
6712 } else {
6713 /* Vulkan guarantees only 4 byte alignment for indirect_offset.
6714 * However, CP_LOAD_STATE.EXT_SRC_ADDR needs 16 byte alignment.
6715 */
6716
6717 /* Wait for any previous uses to finish. */
6718 tu_cs_emit_wfi(cs);
6719
6720 for (uint32_t i = 0; i < 3; i++) {
6721 tu_cs_emit_pkt7(cs, CP_MEM_TO_MEM, 5);
6722 tu_cs_emit(cs, 0);
6723 tu_cs_emit_qw(cs, global_iova_arr(cmd, cs_indirect_xyz, i));
6724 tu_cs_emit_qw(cs, info->indirect + i * 4);
6725 }
6726
6727 tu_cs_emit_pkt7(cs, CP_WAIT_MEM_WRITES, 0);
6728 tu_emit_event_write<CHIP>(cmd, cs, FD_CACHE_INVALIDATE);
6729 tu_cs_emit_wfi(cs);
6730
6731 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3);
6732 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(offset) |
6733 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
6734 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
6735 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
6736 CP_LOAD_STATE6_0_NUM_UNIT(1));
6737 tu_cs_emit_qw(cs, global_iova(cmd, cs_indirect_xyz[0]));
6738 }
6739
6740 /* Fill out IR3_DP_CS_SUBGROUP_SIZE and IR3_DP_SUBGROUP_ID_SHIFT for
6741 * indirect dispatch.
6742 */
6743 if (info->indirect && num_consts > IR3_DP_CS(base_group_x)) {
6744 bool emit_local = num_consts > IR3_DP_CS(local_group_size_x);
6745 tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 7 + (emit_local ? 4 : 0));
6746 tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(offset + (IR3_DP_CS(base_group_x) / 4)) |
6747 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
6748 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
6749 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) |
6750 CP_LOAD_STATE6_0_NUM_UNIT((num_consts - IR3_DP_CS(base_group_x)) / 4));
6751 tu_cs_emit_qw(cs, 0);
6752 tu_cs_emit(cs, 0); /* BASE_GROUP_X */
6753 tu_cs_emit(cs, 0); /* BASE_GROUP_Y */
6754 tu_cs_emit(cs, 0); /* BASE_GROUP_Z */
6755 tu_cs_emit(cs, subgroup_size);
6756 if (emit_local) {
6757 assert(num_consts == align(IR3_DP_CS(subgroup_id_shift), 4));
6758 tu_cs_emit(cs, 0); /* LOCAL_GROUP_SIZE_X */
6759 tu_cs_emit(cs, 0); /* LOCAL_GROUP_SIZE_Y */
6760 tu_cs_emit(cs, 0); /* LOCAL_GROUP_SIZE_Z */
6761 tu_cs_emit(cs, subgroup_shift);
6762 }
6763 }
6764 }
6765 }
6766
6767 template <chip CHIP>
6768 static void
tu_dispatch(struct tu_cmd_buffer * cmd,const struct tu_dispatch_info * info)6769 tu_dispatch(struct tu_cmd_buffer *cmd,
6770 const struct tu_dispatch_info *info)
6771 {
6772 if (!info->indirect &&
6773 (info->blocks[0] == 0 || info->blocks[1] == 0 || info->blocks[2] == 0))
6774 return;
6775
6776 struct tu_cs *cs = &cmd->cs;
6777 struct tu_shader *shader = cmd->state.shaders[MESA_SHADER_COMPUTE];
6778
6779 bool emit_instrlen_workaround =
6780 shader->variant->instrlen >
6781 cmd->device->physical_device->info->a6xx.instr_cache_size;
6782
6783 /* We don't use draw states for dispatches, so the bound pipeline
6784 * could be overwritten by reg stomping in a renderpass or blit.
6785 */
6786 if (cmd->device->dbg_renderpass_stomp_cs) {
6787 tu_cs_emit_state_ib(&cmd->cs, shader->state);
6788 }
6789
6790 /* There appears to be a HW bug where in some rare circumstances it appears
6791 * to accidentally use the FS instrlen instead of the CS instrlen, which
6792 * affects all known gens. Based on various experiments it appears that the
6793 * issue is that when prefetching a branch destination and there is a cache
6794 * miss, when fetching from memory the HW bounds-checks the fetch against
6795 * SP_CS_INSTRLEN, except when one of the two register contexts is active
6796 * it accidentally fetches SP_FS_INSTRLEN from the other (inactive)
6797 * context. To workaround it we set the FS instrlen here and do a dummy
6798 * event to roll the context (because it fetches SP_FS_INSTRLEN from the
6799 * "wrong" context). Because the bug seems to involve cache misses, we
6800 * don't emit this if the entire CS program fits in cache, which will
6801 * hopefully be the majority of cases.
6802 *
6803 * See https://gitlab.freedesktop.org/mesa/mesa/-/issues/5892
6804 */
6805 if (emit_instrlen_workaround) {
6806 tu_cs_emit_regs(cs, A6XX_SP_FS_INSTRLEN(shader->variant->instrlen));
6807 tu_emit_event_write<CHIP>(cmd, cs, FD_LABEL);
6808 }
6809
6810 /* TODO: We could probably flush less if we add a compute_flush_bits
6811 * bitfield.
6812 */
6813 tu_emit_cache_flush<CHIP>(cmd);
6814
6815 /* note: no reason to have this in a separate IB */
6816 tu_cs_emit_state_ib(cs, tu_emit_consts(cmd, true));
6817
6818 tu_emit_compute_driver_params<CHIP>(cmd, cs, info);
6819
6820 if (cmd->state.dirty & TU_CMD_DIRTY_COMPUTE_DESC_SETS) {
6821 tu6_emit_descriptor_sets<CHIP>(cmd, VK_PIPELINE_BIND_POINT_COMPUTE);
6822 tu_cs_emit_state_ib(cs, cmd->state.compute_load_state);
6823 }
6824
6825 cmd->state.dirty &= ~TU_CMD_DIRTY_COMPUTE_DESC_SETS;
6826
6827 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
6828 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_COMPUTE));
6829
6830 const uint16_t *local_size = shader->variant->local_size;
6831 const uint32_t *num_groups = info->blocks;
6832
6833 if (info->unaligned) {
6834 assert(CHIP >= A7XX);
6835
6836 if (info->indirect) {
6837 /* This path is tailored for BVH building and currently only supports
6838 * 1-dimensional dispatches with a power-of-two local size. We use
6839 * CP_RUN_OPENCL instead of CP_EXEC_CS in order to dynamically set
6840 * HLSQ_CS_KERNEL_GROUP_X, which is usually set implicitly by the
6841 * packet, to the number of workgroups. The registers for Y and Z
6842 * dimensions should be unused because we set the kernel dimension to
6843 * 1.
6844 */
6845 assert(local_size[1] == 1 && local_size[2] == 1);
6846 assert(util_is_power_of_two_nonzero(local_size[0]));
6847
6848 tu_cs_emit_regs(cs,
6849 HLSQ_CS_NDRANGE_0(CHIP, .kerneldim = 1,
6850 .localsizex = local_size[0] - 1));
6851
6852 tu_cs_emit_regs(cs, HLSQ_CS_NDRANGE_2(CHIP, .globaloff_x = 0));
6853
6854 /* This does:
6855 * - waits for pending cache flushes to finish
6856 * - CP_WAIT_FOR_ME
6857 *
6858 * In a sequence of indirect dispatches this shouldn't wait for the
6859 * previous dispatches to finish.
6860 */
6861 tu_cs_emit_pkt7(cs, CP_MEM_TO_REG, 3);
6862 tu_cs_emit(cs, CP_MEM_TO_REG_0_REG(REG_A7XX_HLSQ_CS_NDRANGE_1));
6863 tu_cs_emit_qw(cs, info->indirect);
6864
6865 tu_cs_emit_pkt7(cs, CP_SCRATCH_WRITE, 2);
6866 tu_cs_emit(cs, CP_SCRATCH_WRITE_0_SCRATCH(0));
6867 tu_cs_emit(cs, ~0u);
6868
6869 /* CP_REG_RMW and CP_REG_TO_SCRATCH implicitly do a CP_WAIT_FOR_IDLE
6870 * *and* CP_WAIT_FOR_ME, which is a full pipeline stall that we don't
6871 * want, so manually wait for the CP_MEM_TO_REG write to land and
6872 * then skip waiting below with SKIP_WAIT_FOR_ME.
6873 */
6874 tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
6875
6876 /* scratch0 = ((scratch0 & CS_NDRANGE_1) + -1
6877 * = ((~0 & CS_NDRANGE_1) + -1
6878 * = CS_NDRANGE_1 - 1
6879 */
6880 tu_cs_emit_pkt7(cs, CP_REG_RMW, 3);
6881 tu_cs_emit(cs,
6882 CP_REG_RMW_0_DST_REG(0) |
6883 CP_REG_RMW_0_DST_SCRATCH |
6884 CP_REG_RMW_0_SKIP_WAIT_FOR_ME |
6885 CP_REG_RMW_0_SRC0_IS_REG |
6886 CP_REG_RMW_0_SRC1_ADD);
6887 tu_cs_emit(cs, REG_A7XX_HLSQ_CS_NDRANGE_1); /* SRC0 */
6888 tu_cs_emit(cs, -1); /* SRC1 */
6889
6890 /* scratch0 = ((scratch0 & (local_size - 1)) rot 2
6891 * = ((scratch0 & (local_size - 1)) << 2
6892 */
6893 tu_cs_emit_pkt7(cs, CP_REG_RMW, 3);
6894 tu_cs_emit(cs,
6895 CP_REG_RMW_0_DST_REG(0) |
6896 CP_REG_RMW_0_DST_SCRATCH |
6897 CP_REG_RMW_0_SKIP_WAIT_FOR_ME |
6898 CP_REG_RMW_0_ROTATE(A7XX_HLSQ_CS_LAST_LOCAL_SIZE_LOCALSIZEX__SHIFT));
6899 tu_cs_emit(cs, local_size[0] - 1); /* SRC0 */
6900 tu_cs_emit(cs, 0); /* SRC1 */
6901
6902 /* write scratch0 to HLSQ_CS_LAST_LOCAL_SIZE */
6903 tu_cs_emit_pkt7(cs, CP_SCRATCH_TO_REG, 1);
6904 tu_cs_emit(cs,
6905 CP_SCRATCH_TO_REG_0_REG(REG_A7XX_HLSQ_CS_LAST_LOCAL_SIZE) |
6906 CP_SCRATCH_TO_REG_0_SCRATCH(0));
6907
6908 tu_cs_emit_pkt7(cs, CP_SCRATCH_WRITE, 2);
6909 tu_cs_emit(cs, CP_SCRATCH_WRITE_0_SCRATCH(0));
6910 tu_cs_emit(cs, ~0u);
6911
6912 /* scratch0 = (scratch0 & CS_NDRANGE_1) + local_size - 1
6913 * = (~0u & CS_NDRANGE_1) + local_size - 1
6914 * = CS_NDRANGE_1 + local_size - 1
6915 */
6916 tu_cs_emit_pkt7(cs, CP_REG_RMW, 3);
6917 tu_cs_emit(cs,
6918 CP_REG_RMW_0_DST_REG(0) |
6919 CP_REG_RMW_0_DST_SCRATCH |
6920 CP_REG_RMW_0_SKIP_WAIT_FOR_ME |
6921 CP_REG_RMW_0_SRC0_IS_REG |
6922 CP_REG_RMW_0_SRC1_ADD);
6923 tu_cs_emit(cs, REG_A7XX_HLSQ_CS_NDRANGE_1); /* SRC0 */
6924 tu_cs_emit(cs, local_size[0] - 1); /* SRC1 */
6925
6926 unsigned local_size_log2 = util_logbase2(local_size[0]);
6927
6928 /* scratch0 = (scratch0 & (~(local_size - 1)) rot (32 - log2(local_size))
6929 * = scratch0 >> log2(local_size)
6930 * = scratch0 / local_size
6931 * = (CS_NDRANGE_1 + local_size - 1) / local_size
6932 */
6933 tu_cs_emit_pkt7(cs, CP_REG_RMW, 3);
6934 tu_cs_emit(cs,
6935 CP_REG_RMW_0_DST_REG(0) |
6936 CP_REG_RMW_0_DST_SCRATCH |
6937 CP_REG_RMW_0_SKIP_WAIT_FOR_ME |
6938 CP_REG_RMW_0_ROTATE(32 - local_size_log2));
6939 tu_cs_emit(cs, ~(local_size[0] - 1)); /* SRC0 */
6940 tu_cs_emit(cs, 0); /* SRC1 */
6941
6942 /* write scratch0 to HLSQ_CS_KERNEL_GROUP_X */
6943 tu_cs_emit_pkt7(cs, CP_SCRATCH_TO_REG, 1);
6944 tu_cs_emit(cs,
6945 CP_SCRATCH_TO_REG_0_REG(REG_A7XX_HLSQ_CS_KERNEL_GROUP_X) |
6946 CP_SCRATCH_TO_REG_0_SCRATCH(0));
6947 } else {
6948 tu_cs_emit_regs(cs,
6949 HLSQ_CS_NDRANGE_0(CHIP, .kerneldim = 3,
6950 .localsizex = local_size[0] - 1,
6951 .localsizey = local_size[1] - 1,
6952 .localsizez = local_size[2] - 1),
6953 HLSQ_CS_NDRANGE_1(CHIP, .globalsize_x = num_groups[0]),
6954 HLSQ_CS_NDRANGE_2(CHIP, .globaloff_x = 0),
6955 HLSQ_CS_NDRANGE_3(CHIP, .globalsize_y = num_groups[1]),
6956 HLSQ_CS_NDRANGE_4(CHIP, .globaloff_y = 0),
6957 HLSQ_CS_NDRANGE_5(CHIP, .globalsize_z = num_groups[2]),
6958 HLSQ_CS_NDRANGE_6(CHIP, .globaloff_z = 0));
6959 uint32_t last_local_size[3];
6960 for (unsigned i = 0; i < 3; i++)
6961 last_local_size[i] = ((num_groups[i] - 1) % local_size[i]) + 1;
6962 tu_cs_emit_regs(cs,
6963 A7XX_HLSQ_CS_LAST_LOCAL_SIZE(.localsizex = last_local_size[0] - 1,
6964 .localsizey = last_local_size[1] - 1,
6965 .localsizez = last_local_size[2] - 1));
6966 }
6967 } else {
6968 tu_cs_emit_regs(cs,
6969 HLSQ_CS_NDRANGE_0(CHIP, .kerneldim = 3,
6970 .localsizex = local_size[0] - 1,
6971 .localsizey = local_size[1] - 1,
6972 .localsizez = local_size[2] - 1),
6973 HLSQ_CS_NDRANGE_1(CHIP, .globalsize_x = local_size[0] * num_groups[0]),
6974 HLSQ_CS_NDRANGE_2(CHIP, .globaloff_x = 0),
6975 HLSQ_CS_NDRANGE_3(CHIP, .globalsize_y = local_size[1] * num_groups[1]),
6976 HLSQ_CS_NDRANGE_4(CHIP, .globaloff_y = 0),
6977 HLSQ_CS_NDRANGE_5(CHIP, .globalsize_z = local_size[2] * num_groups[2]),
6978 HLSQ_CS_NDRANGE_6(CHIP, .globaloff_z = 0));
6979 if (CHIP >= A7XX) {
6980 tu_cs_emit_regs(cs,
6981 A7XX_HLSQ_CS_LAST_LOCAL_SIZE(.localsizex = local_size[0] - 1,
6982 .localsizey = local_size[1] - 1,
6983 .localsizez = local_size[2] - 1));
6984 }
6985 }
6986
6987 if (cmd->device->physical_device->info->a7xx.has_rt_workaround &&
6988 shader->variant->info.uses_ray_intersection) {
6989 tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
6990 tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_SHADER_USES_RT);
6991 }
6992
6993 if (info->indirect) {
6994 trace_start_compute_indirect(&cmd->trace, cs, info->unaligned);
6995
6996 if (info->unaligned) {
6997 tu_cs_emit_pkt7(cs, CP_RUN_OPENCL, 1);
6998 tu_cs_emit(cs, 0x00000000);
6999 } else {
7000 tu_cs_emit_pkt7(cs, CP_EXEC_CS_INDIRECT, 4);
7001 tu_cs_emit(cs, 0x00000000);
7002 tu_cs_emit_qw(cs, info->indirect);
7003 tu_cs_emit(cs,
7004 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(local_size[0] - 1) |
7005 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(local_size[1] - 1) |
7006 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(local_size[2] - 1));
7007
7008 }
7009
7010 trace_end_compute_indirect(&cmd->trace, cs,
7011 (struct u_trace_address) {
7012 .bo = NULL,
7013 .offset = info->indirect,
7014 });
7015 } else {
7016 trace_start_compute(&cmd->trace, cs, info->indirect != 0,
7017 info->unaligned, local_size[0], local_size[1],
7018 local_size[2], info->blocks[0], info->blocks[1],
7019 info->blocks[2]);
7020
7021 if (info->unaligned) {
7022 tu_cs_emit_pkt7(cs, CP_EXEC_CS, 4);
7023 tu_cs_emit(cs, 0x00000000);
7024 tu_cs_emit(cs, CP_EXEC_CS_1_NGROUPS_X(DIV_ROUND_UP(info->blocks[0],
7025 local_size[0])));
7026 tu_cs_emit(cs, CP_EXEC_CS_2_NGROUPS_Y(DIV_ROUND_UP(info->blocks[1],
7027 local_size[1])));
7028 tu_cs_emit(cs, CP_EXEC_CS_3_NGROUPS_Z(DIV_ROUND_UP(info->blocks[2],
7029 local_size[2])));
7030 } else {
7031 tu_cs_emit_pkt7(cs, CP_EXEC_CS, 4);
7032 tu_cs_emit(cs, 0x00000000);
7033 tu_cs_emit(cs, CP_EXEC_CS_1_NGROUPS_X(info->blocks[0]));
7034 tu_cs_emit(cs, CP_EXEC_CS_2_NGROUPS_Y(info->blocks[1]));
7035 tu_cs_emit(cs, CP_EXEC_CS_3_NGROUPS_Z(info->blocks[2]));
7036 }
7037
7038 trace_end_compute(&cmd->trace, cs);
7039 }
7040
7041 /* For the workaround above, because it's using the "wrong" context for
7042 * SP_FS_INSTRLEN we should emit another dummy event write to avoid a
7043 * potential race between writing the register and the CP_EXEC_CS we just
7044 * did. We don't need to reset the register because it will be re-emitted
7045 * anyway when the next renderpass starts.
7046 */
7047 if (emit_instrlen_workaround) {
7048 tu_emit_event_write<CHIP>(cmd, cs, FD_LABEL);
7049 }
7050 }
7051
7052 template <chip CHIP>
7053 VKAPI_ATTR void VKAPI_CALL
tu_CmdDispatchBase(VkCommandBuffer commandBuffer,uint32_t base_x,uint32_t base_y,uint32_t base_z,uint32_t x,uint32_t y,uint32_t z)7054 tu_CmdDispatchBase(VkCommandBuffer commandBuffer,
7055 uint32_t base_x,
7056 uint32_t base_y,
7057 uint32_t base_z,
7058 uint32_t x,
7059 uint32_t y,
7060 uint32_t z)
7061 {
7062 VK_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
7063 struct tu_dispatch_info info = {};
7064
7065 info.blocks[0] = x;
7066 info.blocks[1] = y;
7067 info.blocks[2] = z;
7068
7069 info.offsets[0] = base_x;
7070 info.offsets[1] = base_y;
7071 info.offsets[2] = base_z;
7072 tu_dispatch<CHIP>(cmd_buffer, &info);
7073 }
7074 TU_GENX(tu_CmdDispatchBase);
7075
7076 template <chip CHIP>
7077 VKAPI_ATTR void VKAPI_CALL
tu_CmdDispatchIndirect(VkCommandBuffer commandBuffer,VkBuffer _buffer,VkDeviceSize offset)7078 tu_CmdDispatchIndirect(VkCommandBuffer commandBuffer,
7079 VkBuffer _buffer,
7080 VkDeviceSize offset)
7081 {
7082 VK_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
7083 VK_FROM_HANDLE(tu_buffer, buffer, _buffer);
7084 struct tu_dispatch_info info = {};
7085
7086 info.indirect = buffer->iova + offset;
7087
7088 tu_dispatch<CHIP>(cmd_buffer, &info);
7089 }
7090 TU_GENX(tu_CmdDispatchIndirect);
7091
7092 void
tu_dispatch_unaligned(VkCommandBuffer commandBuffer,uint32_t x,uint32_t y,uint32_t z)7093 tu_dispatch_unaligned(VkCommandBuffer commandBuffer,
7094 uint32_t x, uint32_t y, uint32_t z)
7095 {
7096 VK_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
7097 struct tu_dispatch_info info = {};
7098
7099 info.unaligned = true;
7100 info.blocks[0] = x;
7101 info.blocks[1] = y;
7102 info.blocks[2] = z;
7103 TU_CALLX(cmd_buffer->device, tu_dispatch)(cmd_buffer, &info);
7104 }
7105
7106 void
tu_dispatch_unaligned_indirect(VkCommandBuffer commandBuffer,VkDeviceAddress size_addr)7107 tu_dispatch_unaligned_indirect(VkCommandBuffer commandBuffer,
7108 VkDeviceAddress size_addr)
7109 {
7110 VK_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
7111 struct tu_dispatch_info info = {};
7112
7113 info.unaligned = true;
7114 info.indirect = size_addr;
7115
7116 TU_CALLX(cmd_buffer->device, tu_dispatch)(cmd_buffer, &info);
7117 }
7118
7119 VKAPI_ATTR void VKAPI_CALL
tu_CmdEndRenderPass2(VkCommandBuffer commandBuffer,const VkSubpassEndInfo * pSubpassEndInfo)7120 tu_CmdEndRenderPass2(VkCommandBuffer commandBuffer,
7121 const VkSubpassEndInfo *pSubpassEndInfo)
7122 {
7123 VK_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
7124
7125 if (TU_DEBUG(DYNAMIC)) {
7126 vk_common_CmdEndRenderPass2(commandBuffer, pSubpassEndInfo);
7127 return;
7128 }
7129
7130 tu_cs_end(&cmd_buffer->draw_cs);
7131 tu_cs_end(&cmd_buffer->draw_epilogue_cs);
7132 TU_CALLX(cmd_buffer->device, tu_cmd_render)(cmd_buffer);
7133
7134 cmd_buffer->state.cache.pending_flush_bits |=
7135 cmd_buffer->state.renderpass_cache.pending_flush_bits;
7136 tu_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier, true);
7137
7138 vk_free(&cmd_buffer->vk.pool->alloc, cmd_buffer->state.attachments);
7139
7140 tu_reset_render_pass(cmd_buffer);
7141 }
7142
7143 VKAPI_ATTR void VKAPI_CALL
tu_CmdEndRendering(VkCommandBuffer commandBuffer)7144 tu_CmdEndRendering(VkCommandBuffer commandBuffer)
7145 {
7146 VK_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
7147
7148 if (cmd_buffer->state.suspending) {
7149 cmd_buffer->state.suspended_pass.lrz = cmd_buffer->state.lrz;
7150 /* We cannot pass LRZ state to next resuming renderpass, so we have to
7151 * force disable it here.
7152 */
7153 TU_CALLX(cmd_buffer->device, tu_lrz_flush_valid_during_renderpass)
7154 (cmd_buffer, &cmd_buffer->draw_cs);
7155 }
7156
7157 if (!cmd_buffer->state.suspending) {
7158 tu_cs_end(&cmd_buffer->draw_cs);
7159 tu_cs_end(&cmd_buffer->draw_epilogue_cs);
7160
7161 if (cmd_buffer->state.suspend_resume == SR_IN_PRE_CHAIN) {
7162 cmd_buffer->trace_renderpass_end = u_trace_end_iterator(&cmd_buffer->trace);
7163 tu_save_pre_chain(cmd_buffer);
7164
7165 /* Even we don't call tu_cmd_render here, renderpass is finished
7166 * and draw states should be disabled.
7167 */
7168 tu_disable_draw_states(cmd_buffer, &cmd_buffer->cs);
7169 } else {
7170 TU_CALLX(cmd_buffer->device, tu_cmd_render)(cmd_buffer);
7171 }
7172
7173 tu_reset_render_pass(cmd_buffer);
7174 }
7175
7176 if (cmd_buffer->state.resuming && !cmd_buffer->state.suspending) {
7177 /* exiting suspend/resume chain */
7178 switch (cmd_buffer->state.suspend_resume) {
7179 case SR_IN_CHAIN:
7180 cmd_buffer->state.suspend_resume = SR_NONE;
7181 break;
7182 case SR_IN_PRE_CHAIN:
7183 case SR_IN_CHAIN_AFTER_PRE_CHAIN:
7184 cmd_buffer->state.suspend_resume = SR_AFTER_PRE_CHAIN;
7185 break;
7186 default:
7187 unreachable("suspending render pass not followed by resuming pass");
7188 }
7189 }
7190 }
7191
7192 void
tu_barrier(struct tu_cmd_buffer * cmd,uint32_t dep_count,const VkDependencyInfo * dep_infos)7193 tu_barrier(struct tu_cmd_buffer *cmd,
7194 uint32_t dep_count,
7195 const VkDependencyInfo *dep_infos)
7196 {
7197 VkPipelineStageFlags2 srcStage = 0;
7198 VkPipelineStageFlags2 dstStage = 0;
7199 BITMASK_ENUM(tu_cmd_access_mask) src_flags = 0;
7200 BITMASK_ENUM(tu_cmd_access_mask) dst_flags = 0;
7201
7202 /* Inside a renderpass, we don't know yet whether we'll be using sysmem
7203 * so we have to use the sysmem flushes.
7204 */
7205 bool gmem = cmd->state.ccu_state == TU_CMD_CCU_GMEM &&
7206 !cmd->state.pass;
7207
7208 for (uint32_t dep_idx = 0; dep_idx < dep_count; dep_idx++) {
7209 const VkDependencyInfo *dep_info = &dep_infos[dep_idx];
7210
7211 for (uint32_t i = 0; i < dep_info->memoryBarrierCount; i++) {
7212 VkPipelineStageFlags2 sanitized_src_stage =
7213 sanitize_src_stage(dep_info->pMemoryBarriers[i].srcStageMask);
7214 VkPipelineStageFlags2 sanitized_dst_stage =
7215 sanitize_dst_stage(dep_info->pMemoryBarriers[i].dstStageMask);
7216 src_flags |= vk2tu_access(dep_info->pMemoryBarriers[i].srcAccessMask,
7217 sanitized_src_stage, false, gmem);
7218 dst_flags |= vk2tu_access(dep_info->pMemoryBarriers[i].dstAccessMask,
7219 sanitized_dst_stage, false, gmem);
7220 srcStage |= sanitized_src_stage;
7221 dstStage |= sanitized_dst_stage;
7222 }
7223
7224 for (uint32_t i = 0; i < dep_info->bufferMemoryBarrierCount; i++) {
7225 VkPipelineStageFlags2 sanitized_src_stage =
7226 sanitize_src_stage(dep_info->pBufferMemoryBarriers[i].srcStageMask);
7227 VkPipelineStageFlags2 sanitized_dst_stage =
7228 sanitize_dst_stage(dep_info->pBufferMemoryBarriers[i].dstStageMask);
7229 src_flags |= vk2tu_access(dep_info->pBufferMemoryBarriers[i].srcAccessMask,
7230 sanitized_src_stage, false, gmem);
7231 dst_flags |= vk2tu_access(dep_info->pBufferMemoryBarriers[i].dstAccessMask,
7232 sanitized_dst_stage, false, gmem);
7233 srcStage |= sanitized_src_stage;
7234 dstStage |= sanitized_dst_stage;
7235 }
7236
7237 for (uint32_t i = 0; i < dep_info->imageMemoryBarrierCount; i++) {
7238 VkImageLayout old_layout = dep_info->pImageMemoryBarriers[i].oldLayout;
7239 if (old_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
7240 /* The underlying memory for this image may have been used earlier
7241 * within the same queue submission for a different image, which
7242 * means that there may be old, stale cache entries which are in the
7243 * "wrong" location, which could cause problems later after writing
7244 * to the image. We don't want these entries being flushed later and
7245 * overwriting the actual image, so we need to flush the CCU.
7246 */
7247 VK_FROM_HANDLE(tu_image, image, dep_info->pImageMemoryBarriers[i].image);
7248
7249 if (vk_format_is_depth_or_stencil(image->vk.format)) {
7250 src_flags |= TU_ACCESS_CCU_DEPTH_INCOHERENT_WRITE;
7251 } else {
7252 src_flags |= TU_ACCESS_CCU_COLOR_INCOHERENT_WRITE;
7253 }
7254 }
7255 VkPipelineStageFlags2 sanitized_src_stage =
7256 sanitize_src_stage(dep_info->pImageMemoryBarriers[i].srcStageMask);
7257 VkPipelineStageFlags2 sanitized_dst_stage =
7258 sanitize_dst_stage(dep_info->pImageMemoryBarriers[i].dstStageMask);
7259 src_flags |= vk2tu_access(dep_info->pImageMemoryBarriers[i].srcAccessMask,
7260 sanitized_src_stage, true, gmem);
7261 dst_flags |= vk2tu_access(dep_info->pImageMemoryBarriers[i].dstAccessMask,
7262 sanitized_dst_stage, true, gmem);
7263 srcStage |= sanitized_src_stage;
7264 dstStage |= sanitized_dst_stage;
7265 }
7266 }
7267
7268 if (cmd->state.pass) {
7269 const VkPipelineStageFlags framebuffer_space_stages =
7270 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
7271 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
7272 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
7273 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT;
7274
7275 /* We cannot have non-by-region "fb-space to fb-space" barriers.
7276 *
7277 * From the Vulkan 1.2.185 spec, section 7.6.1 "Subpass Self-dependency":
7278 *
7279 * If the source and destination stage masks both include
7280 * framebuffer-space stages, then dependencyFlags must include
7281 * VK_DEPENDENCY_BY_REGION_BIT.
7282 * [...]
7283 * Each of the synchronization scopes and access scopes of a
7284 * vkCmdPipelineBarrier2 or vkCmdPipelineBarrier command inside
7285 * a render pass instance must be a subset of the scopes of one of
7286 * the self-dependencies for the current subpass.
7287 *
7288 * If the self-dependency has VK_DEPENDENCY_BY_REGION_BIT or
7289 * VK_DEPENDENCY_VIEW_LOCAL_BIT set, then so must the pipeline barrier.
7290 *
7291 * By-region barriers are ok for gmem. All other barriers would involve
7292 * vtx stages which are NOT ok for gmem rendering.
7293 * See dep_invalid_for_gmem().
7294 */
7295 if ((srcStage & ~framebuffer_space_stages) ||
7296 (dstStage & ~framebuffer_space_stages)) {
7297 cmd->state.rp.disable_gmem = true;
7298 }
7299 }
7300
7301 struct tu_cache_state *cache =
7302 cmd->state.pass ? &cmd->state.renderpass_cache : &cmd->state.cache;
7303
7304 /* a750 has a HW bug where writing a UBWC compressed image with a compute
7305 * shader followed by reading it as a texture (or readonly image) requires
7306 * a CACHE_CLEAN event. Some notes about this bug:
7307 * - It only happens after a blit happens.
7308 * - It's fast-clear related, it happens when the image is fast cleared
7309 * before the write and the value read is (incorrectly) the fast clear
7310 * color.
7311 * - CACHE_FLUSH is supposed to be the same as CACHE_CLEAN +
7312 * CACHE_INVALIDATE, but it doesn't work whereas CACHE_CLEAN +
7313 * CACHE_INVALIDATE does.
7314 *
7315 * The srcAccess can be replaced by a OpMemoryBarrier(MakeAvailable), so
7316 * we can't use that to insert the flush. Instead we use the shader source
7317 * stage.
7318 */
7319 if (cmd->device->physical_device->info->a7xx.ubwc_coherency_quirk &&
7320 (srcStage &
7321 (VK_PIPELINE_STAGE_2_VERTEX_SHADER_BIT |
7322 VK_PIPELINE_STAGE_2_TESSELLATION_CONTROL_SHADER_BIT |
7323 VK_PIPELINE_STAGE_2_TESSELLATION_EVALUATION_SHADER_BIT |
7324 VK_PIPELINE_STAGE_2_GEOMETRY_SHADER_BIT |
7325 VK_PIPELINE_STAGE_2_FRAGMENT_SHADER_BIT |
7326 VK_PIPELINE_STAGE_2_COMPUTE_SHADER_BIT |
7327 VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT |
7328 VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT))) {
7329 cache->flush_bits |= TU_CMD_FLAG_CACHE_CLEAN;
7330 cache->pending_flush_bits &= ~TU_CMD_FLAG_CACHE_CLEAN;
7331 }
7332
7333 tu_flush_for_access(cache, src_flags, dst_flags);
7334
7335 enum tu_stage src_stage = vk2tu_src_stage(srcStage);
7336 enum tu_stage dst_stage = vk2tu_dst_stage(dstStage);
7337 tu_flush_for_stage(cache, src_stage, dst_stage);
7338 }
7339
7340 VKAPI_ATTR void VKAPI_CALL
tu_CmdPipelineBarrier2(VkCommandBuffer commandBuffer,const VkDependencyInfo * pDependencyInfo)7341 tu_CmdPipelineBarrier2(VkCommandBuffer commandBuffer,
7342 const VkDependencyInfo *pDependencyInfo)
7343 {
7344 VK_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
7345
7346 tu_barrier(cmd_buffer, 1, pDependencyInfo);
7347 }
7348
7349 template <chip CHIP>
7350 void
tu_write_event(struct tu_cmd_buffer * cmd,struct tu_event * event,VkPipelineStageFlags2 stageMask,unsigned value)7351 tu_write_event(struct tu_cmd_buffer *cmd, struct tu_event *event,
7352 VkPipelineStageFlags2 stageMask, unsigned value)
7353 {
7354 struct tu_cs *cs = &cmd->cs;
7355
7356 /* vkCmdSetEvent/vkCmdResetEvent cannot be called inside a render pass */
7357 assert(!cmd->state.pass);
7358
7359 tu_emit_cache_flush<CHIP>(cmd);
7360
7361 /* Flags that only require a top-of-pipe event. DrawIndirect parameters are
7362 * read by the CP, so the draw indirect stage counts as top-of-pipe too.
7363 */
7364 VkPipelineStageFlags2 top_of_pipe_flags =
7365 VK_PIPELINE_STAGE_2_TOP_OF_PIPE_BIT |
7366 VK_PIPELINE_STAGE_2_DRAW_INDIRECT_BIT;
7367
7368 if (!(stageMask & ~top_of_pipe_flags)) {
7369 tu_cs_emit_pkt7(cs, CP_MEM_WRITE, 3);
7370 tu_cs_emit_qw(cs, event->bo->iova); /* ADDR_LO/HI */
7371 tu_cs_emit(cs, value);
7372 } else {
7373 /* Use a RB_DONE_TS event to wait for everything to complete. */
7374 if (CHIP == A6XX) {
7375 tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, 4);
7376 tu_cs_emit(cs, CP_EVENT_WRITE_0_EVENT(RB_DONE_TS));
7377 } else {
7378 tu_cs_emit_pkt7(cs, CP_EVENT_WRITE7, 4);
7379 tu_cs_emit(cs, CP_EVENT_WRITE7_0(.event = RB_DONE_TS,
7380 .write_src = EV_WRITE_USER_32B,
7381 .write_dst = EV_DST_RAM,
7382 .write_enabled = true).value);
7383 }
7384
7385 tu_cs_emit_qw(cs, event->bo->iova);
7386 tu_cs_emit(cs, value);
7387 }
7388 }
7389 TU_GENX(tu_write_event);
7390
7391 template <chip CHIP>
7392 VKAPI_ATTR void VKAPI_CALL
tu_CmdBeginConditionalRenderingEXT(VkCommandBuffer commandBuffer,const VkConditionalRenderingBeginInfoEXT * pConditionalRenderingBegin)7393 tu_CmdBeginConditionalRenderingEXT(VkCommandBuffer commandBuffer,
7394 const VkConditionalRenderingBeginInfoEXT *pConditionalRenderingBegin)
7395 {
7396 VK_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
7397
7398 cmd->state.predication_active = true;
7399
7400 struct tu_cs *cs = cmd->state.pass ? &cmd->draw_cs : &cmd->cs;
7401
7402 tu_cs_emit_pkt7(cs, CP_DRAW_PRED_ENABLE_GLOBAL, 1);
7403 tu_cs_emit(cs, 1);
7404
7405 /* Wait for any writes to the predicate to land */
7406 if (cmd->state.pass)
7407 tu_emit_cache_flush_renderpass<CHIP>(cmd);
7408 else
7409 tu_emit_cache_flush<CHIP>(cmd);
7410
7411 VK_FROM_HANDLE(tu_buffer, buf, pConditionalRenderingBegin->buffer);
7412 uint64_t iova = buf->iova + pConditionalRenderingBegin->offset;
7413
7414 /* qcom doesn't support 32-bit reference values, only 64-bit, but Vulkan
7415 * mandates 32-bit comparisons. Our workaround is to copy the the reference
7416 * value to the low 32-bits of a location where the high 32 bits are known
7417 * to be 0 and then compare that.
7418 */
7419 tu_cs_emit_pkt7(cs, CP_MEM_TO_MEM, 5);
7420 tu_cs_emit(cs, 0);
7421 tu_cs_emit_qw(cs, global_iova(cmd, predicate));
7422 tu_cs_emit_qw(cs, iova);
7423
7424 tu_cs_emit_pkt7(cs, CP_WAIT_MEM_WRITES, 0);
7425 tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
7426
7427 bool inv = pConditionalRenderingBegin->flags & VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT;
7428 tu_cs_emit_pkt7(cs, CP_DRAW_PRED_SET, 3);
7429 tu_cs_emit(cs, CP_DRAW_PRED_SET_0_SRC(PRED_SRC_MEM) |
7430 CP_DRAW_PRED_SET_0_TEST(inv ? EQ_0_PASS : NE_0_PASS));
7431 tu_cs_emit_qw(cs, global_iova(cmd, predicate));
7432 }
7433 TU_GENX(tu_CmdBeginConditionalRenderingEXT);
7434
7435 VKAPI_ATTR void VKAPI_CALL
tu_CmdEndConditionalRenderingEXT(VkCommandBuffer commandBuffer)7436 tu_CmdEndConditionalRenderingEXT(VkCommandBuffer commandBuffer)
7437 {
7438 VK_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
7439
7440 cmd->state.predication_active = false;
7441
7442 struct tu_cs *cs = cmd->state.pass ? &cmd->draw_cs : &cmd->cs;
7443
7444 tu_cs_emit_pkt7(cs, CP_DRAW_PRED_ENABLE_GLOBAL, 1);
7445 tu_cs_emit(cs, 0);
7446 }
7447
7448 template <chip CHIP>
7449 void
tu_CmdWriteBufferMarker2AMD(VkCommandBuffer commandBuffer,VkPipelineStageFlagBits2 pipelineStage,VkBuffer dstBuffer,VkDeviceSize dstOffset,uint32_t marker)7450 tu_CmdWriteBufferMarker2AMD(VkCommandBuffer commandBuffer,
7451 VkPipelineStageFlagBits2 pipelineStage,
7452 VkBuffer dstBuffer,
7453 VkDeviceSize dstOffset,
7454 uint32_t marker)
7455 {
7456 /* Almost the same as tu_write_event, but also allowed in renderpass */
7457 VK_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
7458 VK_FROM_HANDLE(tu_buffer, buffer, dstBuffer);
7459
7460 uint64_t va = buffer->iova + dstOffset;
7461
7462 struct tu_cs *cs = cmd->state.pass ? &cmd->draw_cs : &cmd->cs;
7463 struct tu_cache_state *cache =
7464 cmd->state.pass ? &cmd->state.renderpass_cache : &cmd->state.cache;
7465
7466 /* From the Vulkan 1.2.203 spec:
7467 *
7468 * The access scope for buffer marker writes falls under
7469 * the VK_ACCESS_TRANSFER_WRITE_BIT, and the pipeline stages for
7470 * identifying the synchronization scope must include both pipelineStage
7471 * and VK_PIPELINE_STAGE_TRANSFER_BIT.
7472 *
7473 * Transfer operations use CCU however here we write via CP.
7474 * Flush CCU in order to make the results of previous transfer
7475 * operation visible to CP.
7476 */
7477 tu_flush_for_access(cache, TU_ACCESS_NONE, TU_ACCESS_SYSMEM_WRITE);
7478
7479 /* Flags that only require a top-of-pipe event. DrawIndirect parameters are
7480 * read by the CP, so the draw indirect stage counts as top-of-pipe too.
7481 */
7482 VkPipelineStageFlags2 top_of_pipe_flags =
7483 VK_PIPELINE_STAGE_2_TOP_OF_PIPE_BIT |
7484 VK_PIPELINE_STAGE_2_DRAW_INDIRECT_BIT;
7485
7486 bool is_top_of_pipe = !(pipelineStage & ~top_of_pipe_flags);
7487
7488 /* We have to WFI only if we flushed CCU here and are using CP_MEM_WRITE.
7489 * Otherwise:
7490 * - We do CP_EVENT_WRITE(RB_DONE_TS) which should wait for flushes;
7491 * - There was a barrier to synchronize other writes with WriteBufferMarkerAMD
7492 * and they had to include our pipelineStage which forces the WFI.
7493 */
7494 if (cache->flush_bits && is_top_of_pipe) {
7495 cache->flush_bits |= TU_CMD_FLAG_WAIT_FOR_IDLE;
7496 }
7497
7498 if (cmd->state.pass) {
7499 tu_emit_cache_flush_renderpass<CHIP>(cmd);
7500 } else {
7501 tu_emit_cache_flush<CHIP>(cmd);
7502 }
7503
7504 if (is_top_of_pipe) {
7505 tu_cs_emit_pkt7(cs, CP_MEM_WRITE, 3);
7506 tu_cs_emit_qw(cs, va); /* ADDR_LO/HI */
7507 tu_cs_emit(cs, marker);
7508 } else {
7509 /* Use a RB_DONE_TS event to wait for everything to complete. */
7510 if (CHIP == A6XX) {
7511 tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, 4);
7512 tu_cs_emit(cs, CP_EVENT_WRITE_0_EVENT(RB_DONE_TS));
7513 } else {
7514 tu_cs_emit_pkt7(cs, CP_EVENT_WRITE7, 4);
7515 tu_cs_emit(cs, CP_EVENT_WRITE7_0(.event = RB_DONE_TS,
7516 .write_src = EV_WRITE_USER_32B,
7517 .write_dst = EV_DST_RAM,
7518 .write_enabled = true).value);
7519 }
7520 tu_cs_emit_qw(cs, va);
7521 tu_cs_emit(cs, marker);
7522 }
7523
7524 /* Make sure the result of this write is visible to others. */
7525 tu_flush_for_access(cache, TU_ACCESS_CP_WRITE, TU_ACCESS_NONE);
7526 }
7527 TU_GENX(tu_CmdWriteBufferMarker2AMD);
7528
7529 void
tu_write_buffer_cp(VkCommandBuffer commandBuffer,VkDeviceAddress addr,void * data,uint32_t size)7530 tu_write_buffer_cp(VkCommandBuffer commandBuffer,
7531 VkDeviceAddress addr,
7532 void *data, uint32_t size)
7533 {
7534 VK_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
7535
7536 TU_CALLX(cmd->device, tu_emit_cache_flush)(cmd);
7537
7538 struct tu_cs *cs = &cmd->cs;
7539
7540 tu_cs_emit_pkt7(cs, CP_MEM_WRITE, 2 + size / 4);
7541 tu_cs_emit_qw(cs, addr);
7542 tu_cs_emit_array(cs, (uint32_t *)data, size / 4);
7543 }
7544
7545 void
tu_flush_buffer_write_cp(VkCommandBuffer commandBuffer)7546 tu_flush_buffer_write_cp(VkCommandBuffer commandBuffer)
7547 {
7548 VK_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
7549
7550 struct tu_cache_state *cache = &cmd->state.cache;
7551 tu_flush_for_access(cache, TU_ACCESS_CP_WRITE, (enum tu_cmd_access_mask)0);
7552 }
7553
7554