1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 * SPDX-License-Identifier: MIT
5 *
6 * based in part on anv driver which is:
7 * Copyright © 2015 Intel Corporation
8 */
9
10 #ifndef TU_PIPELINE_H
11 #define TU_PIPELINE_H
12
13 #include "tu_common.h"
14
15 #include "tu_cs.h"
16 #include "tu_descriptor_set.h"
17 #include "tu_shader.h"
18 #include "tu_suballoc.h"
19
20 enum tu_dynamic_state
21 {
22 TU_DYNAMIC_STATE_VIEWPORT,
23 TU_DYNAMIC_STATE_SCISSOR,
24 TU_DYNAMIC_STATE_RAST,
25 TU_DYNAMIC_STATE_DEPTH_BIAS,
26 TU_DYNAMIC_STATE_BLEND_CONSTANTS,
27 TU_DYNAMIC_STATE_DS,
28 TU_DYNAMIC_STATE_RB_DEPTH_CNTL,
29 TU_DYNAMIC_STATE_SAMPLE_LOCATIONS,
30 TU_DYNAMIC_STATE_VB_STRIDE,
31 TU_DYNAMIC_STATE_BLEND,
32 TU_DYNAMIC_STATE_VERTEX_INPUT,
33 TU_DYNAMIC_STATE_PATCH_CONTROL_POINTS,
34 TU_DYNAMIC_STATE_PRIM_MODE_SYSMEM,
35 TU_DYNAMIC_STATE_A7XX_FRAGMENT_SHADING_RATE = TU_DYNAMIC_STATE_PRIM_MODE_SYSMEM,
36 TU_DYNAMIC_STATE_COUNT,
37 };
38
39 struct cache_entry;
40
41 struct tu_lrz_blend
42 {
43 bool valid;
44 bool reads_dest;
45 };
46
47 struct tu_bandwidth
48 {
49 uint32_t color_bandwidth_per_sample;
50 uint32_t depth_cpp_per_sample;
51 uint32_t stencil_cpp_per_sample;
52 bool valid;
53 };
54
55 struct tu_nir_shaders
56 {
57 struct vk_pipeline_cache_object base;
58
59 /* This is optional, and is only filled out when a library pipeline is
60 * compiled with RETAIN_LINK_TIME_OPTIMIZATION_INFO.
61 */
62 nir_shader *nir[MESA_SHADER_STAGES];
63 };
64
65 extern const struct vk_pipeline_cache_object_ops tu_nir_shaders_ops;
66
67 static bool inline
tu6_shared_constants_enable(const struct tu_pipeline_layout * layout,const struct ir3_compiler * compiler)68 tu6_shared_constants_enable(const struct tu_pipeline_layout *layout,
69 const struct ir3_compiler *compiler)
70 {
71 return layout->push_constant_size > 0 &&
72 layout->push_constant_size <= (compiler->shared_consts_size * 16);
73 }
74
75 enum ir3_push_consts_type
76 tu_push_consts_type(const struct tu_pipeline_layout *layout,
77 const struct ir3_compiler *compiler);
78
79 struct tu_program_descriptor_linkage
80 {
81 struct ir3_const_state const_state;
82
83 uint32_t constlen;
84
85 struct tu_const_state tu_const_state;
86 };
87
88 struct tu_program_state
89 {
90 struct tu_draw_state config_state;
91 struct tu_draw_state vs_state, vs_binning_state;
92 struct tu_draw_state hs_state;
93 struct tu_draw_state ds_state;
94 struct tu_draw_state gs_state, gs_binning_state;
95 struct tu_draw_state vpc_state;
96 struct tu_draw_state fs_state;
97
98 struct tu_push_constant_range shared_consts;
99
100 struct tu_program_descriptor_linkage link[MESA_SHADER_STAGES];
101
102 unsigned dynamic_descriptor_offsets[MAX_SETS];
103
104 bool per_view_viewport;
105 bool writes_shading_rate;
106 bool reads_shading_rate;
107 bool accesses_smask;
108 bool uses_ray_intersection;
109 };
110
111 struct tu_pipeline_executable {
112 gl_shader_stage stage;
113
114 struct ir3_info stats;
115 bool is_binning;
116
117 char *nir_from_spirv;
118 char *nir_final;
119 char *disasm;
120 };
121
122 enum tu_pipeline_type {
123 TU_PIPELINE_GRAPHICS,
124 TU_PIPELINE_GRAPHICS_LIB,
125 TU_PIPELINE_COMPUTE,
126 };
127
128 struct tu_pipeline
129 {
130 struct vk_object_base base;
131 enum tu_pipeline_type type;
132
133 struct tu_cs cs;
134 struct tu_suballoc_bo bo;
135
136 VkShaderStageFlags active_stages;
137 uint32_t active_desc_sets;
138
139 /* mask of enabled dynamic states
140 * if BIT(i) is set, pipeline->dynamic_state[i] is used
141 */
142 uint32_t set_state_mask;
143 struct tu_draw_state dynamic_state[TU_DYNAMIC_STATE_COUNT];
144
145 BITSET_DECLARE(static_state_mask, MESA_VK_DYNAMIC_GRAPHICS_STATE_ENUM_MAX);
146
147 struct {
148 bool raster_order_attachment_access;
149 } ds;
150
151 /* Misc. info from the fragment output interface state that is used
152 * elsewhere.
153 */
154 struct {
155 bool raster_order_attachment_access;
156 } output;
157
158 /* In other words - framebuffer fetch support */
159 struct {
160 /* If the pipeline sets SINGLE_PRIM_MODE for sysmem. */
161 bool sysmem_single_prim_mode;
162 struct tu_draw_state state_gmem;
163 } prim_order;
164
165 /* draw states for the pipeline */
166 struct tu_draw_state load_state;
167
168 struct tu_shader *shaders[MESA_SHADER_STAGES];
169
170 struct tu_program_state program;
171
172 struct tu_lrz_blend lrz_blend;
173 struct tu_bandwidth bandwidth;
174
175 void *executables_mem_ctx;
176 /* tu_pipeline_executable */
177 struct util_dynarray executables;
178 };
179
180 struct tu_graphics_lib_pipeline {
181 struct tu_pipeline base;
182
183 VkGraphicsPipelineLibraryFlagsEXT state;
184
185 struct vk_graphics_pipeline_state graphics_state;
186
187 /* For vk_graphics_pipeline_state */
188 void *state_data;
189
190 struct tu_nir_shaders *nir_shaders;
191 struct {
192 nir_shader *nir;
193 struct tu_shader_key key;
194 } shaders[MESA_SHADER_FRAGMENT + 1];
195
196 /* Used to stitch together an overall layout for the final pipeline. */
197 struct tu_descriptor_set_layout *layouts[MAX_SETS];
198 unsigned num_sets;
199 unsigned push_constant_size;
200 bool independent_sets;
201 };
202
203 struct tu_graphics_pipeline {
204 struct tu_pipeline base;
205
206 struct vk_dynamic_graphics_state dynamic_state;
207
208 /* Only used if the sample locations are static but the enable is dynamic.
209 * Otherwise we should be able to precompile the draw state.
210 */
211 struct vk_sample_locations_state sample_locations;
212
213 VkImageAspectFlags feedback_loops;
214 bool feedback_loop_may_involve_textures;
215 };
216
217 struct tu_compute_pipeline {
218 struct tu_pipeline base;
219
220 uint32_t local_size[3];
221 uint32_t instrlen;
222 };
223
224 VK_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline, base, VkPipeline,
225 VK_OBJECT_TYPE_PIPELINE)
226
227 #define TU_DECL_PIPELINE_DOWNCAST(pipe_type, pipe_enum) \
228 static inline struct tu_##pipe_type##_pipeline * \
229 tu_pipeline_to_##pipe_type(struct tu_pipeline *pipeline) \
230 { \
231 assert(pipeline->type == pipe_enum); \
232 return (struct tu_##pipe_type##_pipeline *) pipeline; \
233 }
234
235 TU_DECL_PIPELINE_DOWNCAST(graphics, TU_PIPELINE_GRAPHICS)
236 TU_DECL_PIPELINE_DOWNCAST(graphics_lib, TU_PIPELINE_GRAPHICS_LIB)
237 TU_DECL_PIPELINE_DOWNCAST(compute, TU_PIPELINE_COMPUTE)
238
239 VkOffset2D tu_fdm_per_bin_offset(VkExtent2D frag_area, VkRect2D bin);
240
241 template <chip CHIP>
242 uint32_t tu_emit_draw_state(struct tu_cmd_buffer *cmd);
243
244 struct tu_pvtmem_config {
245 uint64_t iova;
246 uint32_t per_fiber_size;
247 uint32_t per_sp_size;
248 bool per_wave;
249 };
250
251 template <chip CHIP>
252 void
253 tu6_emit_xs_config(struct tu_cs *cs,
254 gl_shader_stage stage,
255 const struct ir3_shader_variant *xs);
256
257 template <chip CHIP>
258 void
259 tu6_emit_shared_consts_enable(struct tu_cs *cs, bool shared_consts_enable);
260
261 template <chip CHIP>
262 void
263 tu6_emit_vpc(struct tu_cs *cs,
264 const struct ir3_shader_variant *vs,
265 const struct ir3_shader_variant *hs,
266 const struct ir3_shader_variant *ds,
267 const struct ir3_shader_variant *gs,
268 const struct ir3_shader_variant *fs);
269
270 void
271 tu_fill_render_pass_state(struct vk_render_pass_state *rp,
272 const struct tu_render_pass *pass,
273 const struct tu_subpass *subpass);
274
275 #endif /* TU_PIPELINE_H */
276