1 /*
2 * Copyright (c) 2014-2015 Etnaviv Project
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Wladimir J. van der Laan <laanwj@gmail.com>
25 */
26
27 #include "etnaviv_emit.h"
28
29 #include "etnaviv_blend.h"
30 #include "etnaviv_compiler.h"
31 #include "etnaviv_context.h"
32 #include "etnaviv_rasterizer.h"
33 #include "etnaviv_resource.h"
34 #include "etnaviv_rs.h"
35 #include "etnaviv_screen.h"
36 #include "etnaviv_shader.h"
37 #include "etnaviv_texture.h"
38 #include "etnaviv_translate.h"
39 #include "etnaviv_uniforms.h"
40 #include "etnaviv_util.h"
41 #include "etnaviv_zsa.h"
42 #include "hw/state.xml.h"
43 #include "hw/state_blt.xml.h"
44 #include "util/u_math.h"
45
46 /* Queue a STALL command (queues 2 words) */
47 static inline void
CMD_STALL(struct etna_cmd_stream * stream,uint32_t from,uint32_t to)48 CMD_STALL(struct etna_cmd_stream *stream, uint32_t from, uint32_t to)
49 {
50 etna_cmd_stream_emit(stream, VIV_FE_STALL_HEADER_OP_STALL);
51 etna_cmd_stream_emit(stream, VIV_FE_STALL_TOKEN_FROM(from) | VIV_FE_STALL_TOKEN_TO(to));
52 }
53
54 void
etna_stall(struct etna_cmd_stream * stream,uint32_t from,uint32_t to)55 etna_stall(struct etna_cmd_stream *stream, uint32_t from, uint32_t to)
56 {
57 bool blt = (from == SYNC_RECIPIENT_BLT) || (to == SYNC_RECIPIENT_BLT);
58 etna_cmd_stream_reserve(stream, blt ? 8 : 4);
59
60 if (blt) {
61 etna_emit_load_state(stream, VIVS_BLT_ENABLE >> 2, 1, 0);
62 etna_cmd_stream_emit(stream, 1);
63 }
64
65 /* TODO: set bit 28/29 of token after BLT COPY_BUFFER */
66 etna_emit_load_state(stream, VIVS_GL_SEMAPHORE_TOKEN >> 2, 1, 0);
67 etna_cmd_stream_emit(stream, VIVS_GL_SEMAPHORE_TOKEN_FROM(from) | VIVS_GL_SEMAPHORE_TOKEN_TO(to));
68
69 if (from == SYNC_RECIPIENT_FE) {
70 /* if the frontend is to be stalled, queue a STALL frontend command */
71 CMD_STALL(stream, from, to);
72 } else {
73 /* otherwise, load the STALL token state */
74 etna_emit_load_state(stream, VIVS_GL_STALL_TOKEN >> 2, 1, 0);
75 etna_cmd_stream_emit(stream, VIVS_GL_STALL_TOKEN_FROM(from) | VIVS_GL_STALL_TOKEN_TO(to));
76 }
77
78 if (blt) {
79 etna_emit_load_state(stream, VIVS_BLT_ENABLE >> 2, 1, 0);
80 etna_cmd_stream_emit(stream, 0);
81 }
82 }
83
84 #define EMIT_STATE(state_name, src_value) \
85 etna_coalsence_emit(stream, &coalesce, VIVS_##state_name, src_value)
86
87 #define EMIT_STATE_FIXP(state_name, src_value) \
88 etna_coalsence_emit_fixp(stream, &coalesce, VIVS_##state_name, src_value)
89
90 #define EMIT_STATE_RELOC(state_name, src_value) \
91 etna_coalsence_emit_reloc(stream, &coalesce, VIVS_##state_name, src_value)
92
93 #define ETNA_3D_CONTEXT_SIZE (400) /* keep this number above "Total state updates (fixed)" from gen_weave_state tool */
94
95 static unsigned
required_stream_size(struct etna_context * ctx)96 required_stream_size(struct etna_context *ctx)
97 {
98 unsigned size = ETNA_3D_CONTEXT_SIZE;
99
100 /* stall + flush */
101 size += 2 + 4;
102
103 /* vertex elements */
104 size += ctx->vertex_elements->num_elements + 1;
105
106 /* uniforms - worst case (2 words per uniform load) */
107 size += ctx->shader.vs->uniforms.count * 2;
108 size += ctx->shader.fs->uniforms.count * 2;
109
110 /* shader */
111 size += ctx->shader_state.vs_inst_mem_size + 1;
112 size += ctx->shader_state.ps_inst_mem_size + 1;
113
114 /* DRAW_INDEXED_PRIMITIVES command */
115 size += 6;
116
117 /* reserve for alignment etc. */
118 size += 64;
119
120 return size;
121 }
122
123 /* Emit state that only exists on HALTI5+ */
124 static void
emit_halti5_only_state(struct etna_context * ctx,int vs_output_count)125 emit_halti5_only_state(struct etna_context *ctx, int vs_output_count)
126 {
127 struct etna_cmd_stream *stream = ctx->stream;
128 uint32_t dirty = ctx->dirty;
129 struct etna_coalesce coalesce;
130
131 etna_coalesce_start(stream, &coalesce);
132 if (unlikely(dirty & (ETNA_DIRTY_SHADER))) {
133 /* Magic states (load balancing, inter-unit sync, buffers) */
134 /*007C4*/ EMIT_STATE(FE_HALTI5_ID_CONFIG, ctx->shader_state.FE_HALTI5_ID_CONFIG);
135 /*00870*/ EMIT_STATE(VS_HALTI5_OUTPUT_COUNT, vs_output_count | ((vs_output_count * 0x10) << 8));
136 /*008A0*/ EMIT_STATE(VS_HALTI5_UNK008A0, 0x0001000e | ((0x110/vs_output_count) << 20));
137 for (int x = 0; x < VIVS_VS_HALTI5_OUTPUT__LEN; ++x) {
138 /*008E0*/ EMIT_STATE(VS_HALTI5_OUTPUT(x), ctx->shader_state.VS_OUTPUT[x]);
139 }
140 }
141 if (unlikely(dirty & (ETNA_DIRTY_VERTEX_ELEMENTS | ETNA_DIRTY_SHADER))) {
142 for (int x = 0; x < 4; ++x) {
143 /*008C0*/ EMIT_STATE(VS_HALTI5_INPUT(x), ctx->shader_state.VS_INPUT[x]);
144 }
145 }
146 if (unlikely(dirty & (ETNA_DIRTY_SHADER))) {
147 /*00A90*/ EMIT_STATE(PA_VARYING_NUM_COMPONENTS(0), ctx->shader_state.GL_VARYING_NUM_COMPONENTS[0]);
148 /*00A94*/ EMIT_STATE(PA_VARYING_NUM_COMPONENTS(1), ctx->shader_state.GL_VARYING_NUM_COMPONENTS[1]);
149 /*00AA8*/ EMIT_STATE(PA_VS_OUTPUT_COUNT, vs_output_count);
150 /*01080*/ EMIT_STATE(PS_VARYING_NUM_COMPONENTS(0), ctx->shader_state.GL_VARYING_NUM_COMPONENTS[0]);
151 /*01084*/ EMIT_STATE(PS_VARYING_NUM_COMPONENTS(1), ctx->shader_state.GL_VARYING_NUM_COMPONENTS[1]);
152 /*03888*/ EMIT_STATE(GL_HALTI5_SH_SPECIALS, ctx->shader_state.GL_HALTI5_SH_SPECIALS);
153 for (int x = 0; x < ctx->shader_state.halti5_shader_attributes_states; ++x) {
154 /*038C0*/ EMIT_STATE(GL_HALTI5_SHADER_ATTRIBUTES(x), ctx->shader_state.GL_HALTI5_SHADER_ATTRIBUTES[x]);
155 }
156 }
157 if (unlikely(dirty & (ETNA_DIRTY_BLEND))) {
158 for (int i = 1; i < ctx->framebuffer.num_rt; i++) {
159 const uint8_t rt = i - 1;
160 /*14920*/ EMIT_STATE(PE_HALTI5_RT_COLORMASK(rt), etna_blend_state(ctx->blend)->rt[i].PE_HALTI5_COLORMASK);
161 }
162 for (int i = 1; i < ctx->framebuffer.num_rt; i++) {
163 const uint8_t rt = i - 1;
164 /*14960*/ EMIT_STATE(PE_HALTI5_RT_ALPHA_CONFIG(rt), etna_blend_state(ctx->blend)->rt[i].PE_ALPHA_CONFIG);
165 }
166 }
167 if (unlikely(dirty & (ETNA_DIRTY_BLEND_COLOR))) {
168 for (int i = 1; i < ctx->framebuffer.num_rt; i++) {
169 const uint8_t rt = i - 1;
170 /*14980*/ EMIT_STATE(PE_HALTI5_RT_ALPHA_COLOR_EXT0(rt), ctx->blend_color.rt[i].PE_ALPHA_COLOR_EXT0);
171 }
172 for (int i = 1; i < ctx->framebuffer.num_rt; i++) {
173 const uint8_t rt = i - 1;
174 /*149A0*/ EMIT_STATE(PE_HALTI5_RT_ALPHA_COLOR_EXT1(rt), ctx->blend_color.rt[i].PE_ALPHA_COLOR_EXT1);
175 }
176 }
177
178 etna_coalesce_end(stream, &coalesce);
179 }
180
181 /* Emit state that no longer exists on HALTI5 */
182 static void
emit_pre_halti5_state(struct etna_context * ctx)183 emit_pre_halti5_state(struct etna_context *ctx)
184 {
185 struct etna_cmd_stream *stream = ctx->stream;
186 uint32_t dirty = ctx->dirty;
187 struct etna_coalesce coalesce;
188
189 etna_coalesce_start(stream, &coalesce);
190 if (unlikely(dirty & (ETNA_DIRTY_SHADER))) {
191 /*00800*/ EMIT_STATE(VS_END_PC, ctx->shader_state.VS_END_PC);
192 }
193 if (unlikely(dirty & (ETNA_DIRTY_SHADER))) {
194 for (int x = 0; x < VIVS_VS_OUTPUT__LEN; ++x) {
195 /*00810*/ EMIT_STATE(VS_OUTPUT(x), ctx->shader_state.VS_OUTPUT[x]);
196 }
197 }
198 if (unlikely(dirty & (ETNA_DIRTY_VERTEX_ELEMENTS | ETNA_DIRTY_SHADER))) {
199 for (int x = 0; x < 4; ++x) {
200 /*00820*/ EMIT_STATE(VS_INPUT(x), ctx->shader_state.VS_INPUT[x]);
201 }
202 }
203 if (unlikely(dirty & (ETNA_DIRTY_SHADER))) {
204 /*00838*/ EMIT_STATE(VS_START_PC, ctx->shader_state.VS_START_PC);
205 }
206 if (unlikely(dirty & (ETNA_DIRTY_SHADER))) {
207 for (int x = 0; x < ctx->shader_state.pa_shader_attributes_states; ++x) {
208 /*00A40*/ EMIT_STATE(PA_SHADER_ATTRIBUTES(x), ctx->shader_state.PA_SHADER_ATTRIBUTES[x]);
209 }
210 }
211 if (unlikely(dirty & (ETNA_DIRTY_FRAMEBUFFER))) {
212 /*00E04*/ EMIT_STATE(RA_MULTISAMPLE_UNK00E04, ctx->framebuffer.RA_MULTISAMPLE_UNK00E04);
213 for (int x = 0; x < 4; ++x) {
214 /*00E10*/ EMIT_STATE(RA_MULTISAMPLE_UNK00E10(x), ctx->framebuffer.RA_MULTISAMPLE_UNK00E10[x]);
215 }
216 for (int x = 0; x < 16; ++x) {
217 /*00E40*/ EMIT_STATE(RA_CENTROID_TABLE(x), ctx->framebuffer.RA_CENTROID_TABLE[x]);
218 }
219 }
220 if (unlikely(dirty & (ETNA_DIRTY_SHADER | ETNA_DIRTY_FRAMEBUFFER))) {
221 /*01000*/ EMIT_STATE(PS_END_PC, ctx->shader_state.PS_END_PC);
222 }
223 if (unlikely(dirty & (ETNA_DIRTY_SHADER | ETNA_DIRTY_FRAMEBUFFER))) {
224 /*01018*/ EMIT_STATE(PS_START_PC, ctx->shader_state.PS_START_PC);
225 }
226 if (unlikely(dirty & (ETNA_DIRTY_SHADER))) {
227 /*03820*/ EMIT_STATE(GL_VARYING_NUM_COMPONENTS, ctx->shader_state.GL_VARYING_NUM_COMPONENTS[0]);
228 for (int x = 0; x < 2; ++x) {
229 /*03828*/ EMIT_STATE(GL_VARYING_COMPONENT_USE(x), ctx->shader_state.GL_VARYING_COMPONENT_USE[x]);
230 }
231 /*03834*/ EMIT_STATE(GL_VARYING_NUM_COMPONENTS2, ctx->shader_state.GL_VARYING_NUM_COMPONENTS[1]);
232 /*03838*/ EMIT_STATE(GL_VARYING_COMPONENT_USE2, ctx->shader_state.GL_VARYING_COMPONENT_USE[2]);
233 /*03854*/ EMIT_STATE(GL_VARYING_COMPONENT_USE3, ctx->shader_state.GL_VARYING_COMPONENT_USE[3]);
234 }
235 etna_coalesce_end(stream, &coalesce);
236 }
237
238 /* Weave state before draw operation. This function merges all the compiled
239 * state blocks under the context into one device register state. Parts of
240 * this state that are changed since last call (dirty) will be uploaded as
241 * state changes in the command buffer. */
242 void
etna_emit_state(struct etna_context * ctx)243 etna_emit_state(struct etna_context *ctx)
244 {
245 struct etna_cmd_stream *stream = ctx->stream;
246 struct etna_screen *screen = ctx->screen;
247 unsigned ccw = ctx->rasterizer->front_ccw;
248
249
250 /* Pre-reserve the command buffer space which we are likely to need.
251 * This must cover all the state emitted below, and the following
252 * draw command. */
253 etna_cmd_stream_reserve(stream, required_stream_size(ctx));
254
255 uint32_t dirty = ctx->dirty;
256
257 /* Pre-processing: see what caches we need to flush before making state changes. */
258 uint32_t to_flush = 0, to_flush_separate = 0;
259 if (unlikely(dirty & (ETNA_DIRTY_BLEND)))
260 to_flush |= VIVS_GL_FLUSH_CACHE_COLOR;
261 if (unlikely(dirty & ETNA_DIRTY_ZSA))
262 to_flush |= VIVS_GL_FLUSH_CACHE_DEPTH;
263 if (unlikely(dirty & (ETNA_DIRTY_TEXTURE_CACHES))) {
264 to_flush |= VIVS_GL_FLUSH_CACHE_TEXTURE;
265 to_flush_separate |= VIVS_GL_FLUSH_CACHE_TEXTUREVS;
266 }
267 if (unlikely(dirty & ETNA_DIRTY_SHADER_CACHES))
268 to_flush |= VIVS_GL_FLUSH_CACHE_SHADER_L1;
269 if (unlikely(dirty & (ETNA_DIRTY_FRAMEBUFFER))) /* Framebuffer config changed? */
270 to_flush |= VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH;
271 if (DBG_ENABLED(ETNA_DBG_CFLUSH_ALL)) {
272 to_flush |= VIVS_GL_FLUSH_CACHE_TEXTURE | VIVS_GL_FLUSH_CACHE_COLOR |
273 VIVS_GL_FLUSH_CACHE_DEPTH;
274 to_flush_separate |= VIVS_GL_FLUSH_CACHE_TEXTUREVS;
275 }
276
277 if (to_flush) {
278 etna_set_state(stream, VIVS_GL_FLUSH_CACHE, to_flush);
279 if (to_flush_separate)
280 etna_set_state(stream, VIVS_GL_FLUSH_CACHE, to_flush_separate);
281 etna_stall(stream, SYNC_RECIPIENT_RA, SYNC_RECIPIENT_PE);
282 }
283
284 /* Flush TS cache before changing TS configuration. */
285 if (unlikely(dirty & ETNA_DIRTY_TS)) {
286 etna_set_state(stream, VIVS_TS_FLUSH_CACHE, VIVS_TS_FLUSH_CACHE_FLUSH);
287 }
288
289 /* Update vertex elements. This is different from any of the other states, in that
290 * a) the number of vertex elements written matters: so write only active ones
291 * b) the vertex element states must all be written: do not skip entries that stay the same */
292 if (dirty & (ETNA_DIRTY_VERTEX_ELEMENTS)) {
293 if (screen->info->halti >= 5) {
294 /*17800*/ etna_set_state_multi(stream, VIVS_NFE_GENERIC_ATTRIB_CONFIG0(0),
295 ctx->vertex_elements->num_elements,
296 ctx->vertex_elements->NFE_GENERIC_ATTRIB_CONFIG0);
297 /*17A00*/ etna_set_state_multi(stream, VIVS_NFE_GENERIC_ATTRIB_SCALE(0),
298 ctx->vertex_elements->num_elements,
299 ctx->vertex_elements->NFE_GENERIC_ATTRIB_SCALE);
300 /*17A80*/ etna_set_state_multi(stream, VIVS_NFE_GENERIC_ATTRIB_CONFIG1(0),
301 ctx->vertex_elements->num_elements,
302 ctx->vertex_elements->NFE_GENERIC_ATTRIB_CONFIG1);
303 } else {
304 /* Special case: vertex elements must always be sent in full if changed */
305 /*00600*/ etna_set_state_multi(stream, VIVS_FE_VERTEX_ELEMENT_CONFIG(0),
306 ctx->vertex_elements->num_elements,
307 ctx->vertex_elements->FE_VERTEX_ELEMENT_CONFIG);
308 if (screen->info->halti >= 2) {
309 /*00780*/ etna_set_state_multi(stream, VIVS_FE_GENERIC_ATTRIB_SCALE(0),
310 ctx->vertex_elements->num_elements,
311 ctx->vertex_elements->NFE_GENERIC_ATTRIB_SCALE);
312 }
313 }
314 }
315 unsigned vs_output_count = etna_rasterizer_state(ctx->rasterizer)->point_size_per_vertex
316 ? ctx->shader_state.VS_OUTPUT_COUNT_PSIZE
317 : ctx->shader_state.VS_OUTPUT_COUNT;
318
319 /* The following code is originally generated by gen_merge_state.py, to
320 * emit state in increasing order of address (this makes it possible to merge
321 * consecutive register updates into one SET_STATE command)
322 *
323 * There have been some manual changes, where the weaving operation is not
324 * simply bitwise or:
325 * - scissor fixp
326 * - num vertex elements
327 * - scissor handling
328 * - num samplers
329 * - texture lod
330 * - ETNA_DIRTY_TS
331 * - removed ETNA_DIRTY_BASE_SETUP statements -- these are guaranteed to not
332 * change anyway
333 * - PS / framebuffer interaction for MSAA
334 * - move update of GL_MULTI_SAMPLE_CONFIG first
335 * - add unlikely()/likely()
336 */
337 struct etna_coalesce coalesce;
338
339 etna_coalesce_start(stream, &coalesce);
340
341 /* begin only EMIT_STATE -- make sure no new etna_reserve calls are done here
342 * directly
343 * or indirectly */
344 /* multi sample config is set first, and outside of the normal sorting
345 * order, as changing the multisample state clobbers PS.INPUT_COUNT (and
346 * possibly PS.TEMP_REGISTER_CONTROL).
347 */
348 if (unlikely(dirty & (ETNA_DIRTY_FRAMEBUFFER | ETNA_DIRTY_SAMPLE_MASK))) {
349 uint32_t val = VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES(ctx->sample_mask);
350 val |= ctx->framebuffer.GL_MULTI_SAMPLE_CONFIG;
351
352 /*03818*/ EMIT_STATE(GL_MULTI_SAMPLE_CONFIG, val);
353 }
354 if (likely(dirty & (ETNA_DIRTY_INDEX_BUFFER))) {
355 /*00644*/ EMIT_STATE_RELOC(FE_INDEX_STREAM_BASE_ADDR, &ctx->index_buffer.FE_INDEX_STREAM_BASE_ADDR);
356 /*00648*/ EMIT_STATE(FE_INDEX_STREAM_CONTROL, ctx->index_buffer.FE_INDEX_STREAM_CONTROL);
357 }
358 if (likely(dirty & (ETNA_DIRTY_INDEX_BUFFER))) {
359 /*00674*/ EMIT_STATE(FE_PRIMITIVE_RESTART_INDEX, ctx->index_buffer.FE_PRIMITIVE_RESTART_INDEX);
360 }
361 if (likely(dirty & (ETNA_DIRTY_VERTEX_BUFFERS))) {
362 if (screen->info->halti >= 2) { /* HALTI2+: NFE_VERTEX_STREAMS */
363 for (int x = 0; x < ctx->vertex_buffer.count; ++x) {
364 /*14600*/ EMIT_STATE_RELOC(NFE_VERTEX_STREAMS_BASE_ADDR(x), &ctx->vertex_buffer.cvb[x].FE_VERTEX_STREAM_BASE_ADDR);
365 }
366 } else if(screen->info->gpu.stream_count > 1) { /* hw w/ multiple vertex streams */
367 for (int x = 0; x < ctx->vertex_buffer.count; ++x) {
368 /*00680*/ EMIT_STATE_RELOC(FE_VERTEX_STREAMS_BASE_ADDR(x), &ctx->vertex_buffer.cvb[x].FE_VERTEX_STREAM_BASE_ADDR);
369 }
370 } else { /* hw w/ single vertex stream */
371 /*0064C*/ EMIT_STATE_RELOC(FE_VERTEX_STREAM_BASE_ADDR, &ctx->vertex_buffer.cvb[0].FE_VERTEX_STREAM_BASE_ADDR);
372 }
373 }
374 /* gallium has instance divisor as part of elements state */
375 if (dirty & (ETNA_DIRTY_VERTEX_ELEMENTS)) {
376 for (int x = 0; x < ctx->vertex_elements->num_buffers; ++x) {
377 if (ctx->vertex_buffer.cvb[x].FE_VERTEX_STREAM_BASE_ADDR.bo) {
378 if (screen->info->halti >= 2)
379 /*14640*/ EMIT_STATE(NFE_VERTEX_STREAMS_CONTROL(x), ctx->vertex_elements->FE_VERTEX_STREAM_CONTROL[x]);
380 else if (screen->info->gpu.stream_count > 1)
381 /*006A0*/ EMIT_STATE(FE_VERTEX_STREAMS_CONTROL(x), ctx->vertex_elements->FE_VERTEX_STREAM_CONTROL[x]);
382 else
383 /*00650*/ EMIT_STATE(FE_VERTEX_STREAM_CONTROL, ctx->vertex_elements->FE_VERTEX_STREAM_CONTROL[0]);
384 }
385 }
386 if (screen->info->halti >= 2) {
387 for (int x = 0; x < ctx->vertex_elements->num_buffers; ++x) {
388 /*14680*/ EMIT_STATE(NFE_VERTEX_STREAMS_VERTEX_DIVISOR(x), ctx->vertex_elements->NFE_VERTEX_STREAMS_VERTEX_DIVISOR[x]);
389 }
390 }
391 }
392
393 if (unlikely(dirty & (ETNA_DIRTY_SHADER | ETNA_DIRTY_RASTERIZER))) {
394
395 /*00804*/ EMIT_STATE(VS_OUTPUT_COUNT, vs_output_count);
396 }
397 if (unlikely(dirty & (ETNA_DIRTY_VERTEX_ELEMENTS | ETNA_DIRTY_SHADER))) {
398 /*00808*/ EMIT_STATE(VS_INPUT_COUNT, ctx->shader_state.VS_INPUT_COUNT);
399 /*0080C*/ EMIT_STATE(VS_TEMP_REGISTER_CONTROL, ctx->shader_state.VS_TEMP_REGISTER_CONTROL);
400 }
401 if (unlikely(dirty & (ETNA_DIRTY_SHADER))) {
402 /*00830*/ EMIT_STATE(VS_LOAD_BALANCING, ctx->shader_state.VS_LOAD_BALANCING);
403 }
404 if (unlikely(dirty & (ETNA_DIRTY_VIEWPORT))) {
405 /*00A00*/ EMIT_STATE_FIXP(PA_VIEWPORT_SCALE_X, ctx->viewport.PA_VIEWPORT_SCALE_X);
406 /*00A04*/ EMIT_STATE_FIXP(PA_VIEWPORT_SCALE_Y, ctx->viewport.PA_VIEWPORT_SCALE_Y);
407 /*00A08*/ EMIT_STATE(PA_VIEWPORT_SCALE_Z, ctx->viewport.PA_VIEWPORT_SCALE_Z);
408 /*00A0C*/ EMIT_STATE_FIXP(PA_VIEWPORT_OFFSET_X, ctx->viewport.PA_VIEWPORT_OFFSET_X);
409 /*00A10*/ EMIT_STATE_FIXP(PA_VIEWPORT_OFFSET_Y, ctx->viewport.PA_VIEWPORT_OFFSET_Y);
410 /*00A14*/ EMIT_STATE(PA_VIEWPORT_OFFSET_Z, ctx->viewport.PA_VIEWPORT_OFFSET_Z);
411 }
412 if (unlikely(dirty & (ETNA_DIRTY_RASTERIZER))) {
413 struct etna_rasterizer_state *rasterizer = etna_rasterizer_state(ctx->rasterizer);
414
415 /*00A18*/ EMIT_STATE(PA_LINE_WIDTH, rasterizer->PA_LINE_WIDTH);
416 /*00A1C*/ EMIT_STATE(PA_POINT_SIZE, rasterizer->PA_POINT_SIZE);
417 /*00A28*/ EMIT_STATE(PA_SYSTEM_MODE, rasterizer->PA_SYSTEM_MODE);
418 }
419 if (unlikely(dirty & (ETNA_DIRTY_SHADER))) {
420 /*00A30*/ EMIT_STATE(PA_ATTRIBUTE_ELEMENT_COUNT, ctx->shader_state.PA_ATTRIBUTE_ELEMENT_COUNT);
421 }
422 if (unlikely(dirty & (ETNA_DIRTY_RASTERIZER | ETNA_DIRTY_SHADER))) {
423 uint32_t val = etna_rasterizer_state(ctx->rasterizer)->PA_CONFIG;
424 /*00A34*/ EMIT_STATE(PA_CONFIG, val & ctx->shader_state.PA_CONFIG);
425 }
426 if (unlikely(dirty & (ETNA_DIRTY_RASTERIZER))) {
427 struct etna_rasterizer_state *rasterizer = etna_rasterizer_state(ctx->rasterizer);
428 /*00A38*/ EMIT_STATE(PA_WIDE_LINE_WIDTH0, rasterizer->PA_LINE_WIDTH);
429 /*00A3C*/ EMIT_STATE(PA_WIDE_LINE_WIDTH1, rasterizer->PA_LINE_WIDTH);
430 }
431 if (unlikely(dirty & (ETNA_DIRTY_SCISSOR_CLIP))) {
432 /*00C00*/ EMIT_STATE_FIXP(SE_SCISSOR_LEFT, ctx->clipping.minx << 16);
433 /*00C04*/ EMIT_STATE_FIXP(SE_SCISSOR_TOP, ctx->clipping.miny << 16);
434 /*00C08*/ EMIT_STATE_FIXP(SE_SCISSOR_RIGHT, (ctx->clipping.maxx << 16) + ETNA_SE_SCISSOR_MARGIN_RIGHT);
435 /*00C0C*/ EMIT_STATE_FIXP(SE_SCISSOR_BOTTOM, (ctx->clipping.maxy << 16) + ETNA_SE_SCISSOR_MARGIN_BOTTOM);
436 }
437 if (unlikely(dirty & (ETNA_DIRTY_RASTERIZER))) {
438 /*00C10*/ EMIT_STATE(SE_DEPTH_SCALE, etna_rasterizer_state(ctx->rasterizer)->SE_DEPTH_SCALE);
439
440 }
441 if (unlikely(dirty & (ETNA_DIRTY_RASTERIZER | ETNA_DIRTY_FRAMEBUFFER))) {
442 /*00C14*/ EMIT_STATE(SE_DEPTH_BIAS, fui(etna_rasterizer_state(ctx->rasterizer)->offset_units * ctx->framebuffer.depth_mrd));
443 }
444 if (unlikely(dirty & (ETNA_DIRTY_RASTERIZER))) {
445 /*00C18*/ EMIT_STATE(SE_CONFIG, etna_rasterizer_state(ctx->rasterizer)->SE_CONFIG);
446 }
447 if (unlikely(dirty & (ETNA_DIRTY_SCISSOR_CLIP))) {
448 /*00C20*/ EMIT_STATE_FIXP(SE_CLIP_RIGHT, (ctx->clipping.maxx << 16) + ETNA_SE_CLIP_MARGIN_RIGHT);
449 /*00C24*/ EMIT_STATE_FIXP(SE_CLIP_BOTTOM, (ctx->clipping.maxy << 16) + ETNA_SE_CLIP_MARGIN_BOTTOM);
450 }
451 if (unlikely(dirty & (ETNA_DIRTY_SHADER))) {
452 /*00E00*/ EMIT_STATE(RA_CONTROL, ctx->shader_state.RA_CONTROL);
453 }
454 if (unlikely(dirty & (ETNA_DIRTY_ZSA))) {
455 /*00E08*/ EMIT_STATE(RA_EARLY_DEPTH, etna_zsa_state(ctx->zsa)->RA_DEPTH_CONFIG);
456 }
457 if (unlikely(dirty & (ETNA_DIRTY_SHADER | ETNA_DIRTY_FRAMEBUFFER))) {
458 /*01004*/ EMIT_STATE(PS_OUTPUT_REG, ctx->shader_state.PS_OUTPUT_REG[0]);
459 /*01008*/ EMIT_STATE(PS_INPUT_COUNT,
460 ctx->framebuffer.msaa_mode
461 ? ctx->shader_state.PS_INPUT_COUNT_MSAA
462 : ctx->shader_state.PS_INPUT_COUNT);
463 /*0100C*/ EMIT_STATE(PS_TEMP_REGISTER_CONTROL,
464 ctx->framebuffer.msaa_mode
465 ? ctx->shader_state.PS_TEMP_REGISTER_CONTROL_MSAA
466 : ctx->shader_state.PS_TEMP_REGISTER_CONTROL);
467 /*01010*/ EMIT_STATE(PS_CONTROL, ctx->framebuffer.PS_CONTROL);
468
469 if (screen->specs.num_rts == 8)
470 /*0102C*/ EMIT_STATE(PS_OUTPUT_REG2, ctx->shader_state.PS_OUTPUT_REG[1]);
471
472 /*01030*/ EMIT_STATE(PS_CONTROL_EXT, ctx->framebuffer.PS_CONTROL_EXT);
473 }
474 if (unlikely(dirty & (ETNA_DIRTY_ZSA | ETNA_DIRTY_FRAMEBUFFER))) {
475 /*01400*/ EMIT_STATE(PE_DEPTH_CONFIG, (etna_zsa_state(ctx->zsa)->PE_DEPTH_CONFIG |
476 ctx->framebuffer.PE_DEPTH_CONFIG));
477 }
478 if (unlikely(dirty & (ETNA_DIRTY_VIEWPORT))) {
479 /*01404*/ EMIT_STATE(PE_DEPTH_NEAR, ctx->viewport.PE_DEPTH_NEAR);
480 /*01408*/ EMIT_STATE(PE_DEPTH_FAR, ctx->viewport.PE_DEPTH_FAR);
481 }
482 if (unlikely(dirty & (ETNA_DIRTY_FRAMEBUFFER))) {
483 /*0140C*/ EMIT_STATE(PE_DEPTH_NORMALIZE, ctx->framebuffer.PE_DEPTH_NORMALIZE);
484
485 if (screen->info->halti < 0 || screen->info->model == 0x880) {
486 /*01410*/ EMIT_STATE_RELOC(PE_DEPTH_ADDR, &ctx->framebuffer.PE_DEPTH_ADDR);
487 }
488
489 /*01414*/ EMIT_STATE(PE_DEPTH_STRIDE, ctx->framebuffer.PE_DEPTH_STRIDE);
490 }
491
492 if (unlikely(dirty & (ETNA_DIRTY_ZSA | ETNA_DIRTY_RASTERIZER))) {
493 uint32_t val = etna_zsa_state(ctx->zsa)->PE_STENCIL_OP[ccw];
494 /*01418*/ EMIT_STATE(PE_STENCIL_OP, val);
495 }
496 if (unlikely(dirty & (ETNA_DIRTY_ZSA | ETNA_DIRTY_STENCIL_REF | ETNA_DIRTY_RASTERIZER))) {
497 uint32_t val = etna_zsa_state(ctx->zsa)->PE_STENCIL_CONFIG[ccw];
498 /*0141C*/ EMIT_STATE(PE_STENCIL_CONFIG, val | ctx->stencil_ref.PE_STENCIL_CONFIG[ccw]);
499 }
500 if (unlikely(dirty & (ETNA_DIRTY_ZSA))) {
501 uint32_t val = etna_zsa_state(ctx->zsa)->PE_ALPHA_OP;
502 /*01420*/ EMIT_STATE(PE_ALPHA_OP, val);
503 }
504 if (unlikely(dirty & (ETNA_DIRTY_BLEND_COLOR))) {
505 /*01424*/ EMIT_STATE(PE_ALPHA_BLEND_COLOR, ctx->blend_color.PE_ALPHA_BLEND_COLOR);
506 }
507 if (unlikely(dirty & (ETNA_DIRTY_BLEND))) {
508 uint32_t val = etna_blend_state(ctx->blend)->rt[0].PE_ALPHA_CONFIG;
509 /*01428*/ EMIT_STATE(PE_ALPHA_CONFIG, val);
510 }
511 if (unlikely(dirty & (ETNA_DIRTY_BLEND | ETNA_DIRTY_FRAMEBUFFER))) {
512 uint32_t val;
513 /* Use the components and overwrite bits in framebuffer.PE_COLOR_FORMAT
514 * as a mask to enable the bits from blend PE_COLOR_FORMAT */
515 val = ~(VIVS_PE_COLOR_FORMAT_COMPONENTS__MASK |
516 VIVS_PE_COLOR_FORMAT_OVERWRITE);
517 val |= etna_blend_state(ctx->blend)->rt[0].PE_COLOR_FORMAT;
518 val &= ctx->framebuffer.PE_COLOR_FORMAT;
519 /*0142C*/ EMIT_STATE(PE_COLOR_FORMAT, val);
520 }
521 if (unlikely(dirty & (ETNA_DIRTY_FRAMEBUFFER))) {
522 if (screen->info->halti >= 0 && screen->info->model != 0x880) {
523 /*01434*/ EMIT_STATE(PE_COLOR_STRIDE, ctx->framebuffer.PE_COLOR_STRIDE);
524 /*01454*/ EMIT_STATE(PE_HDEPTH_CONTROL, ctx->framebuffer.PE_HDEPTH_CONTROL);
525 /*01460*/ EMIT_STATE_RELOC(PE_PIPE_COLOR_ADDR(0), &ctx->framebuffer.PE_PIPE_COLOR_ADDR[0]);
526 /*01464*/ EMIT_STATE_RELOC(PE_PIPE_COLOR_ADDR(1), &ctx->framebuffer.PE_PIPE_COLOR_ADDR[1]);
527 /*01480*/ EMIT_STATE_RELOC(PE_PIPE_DEPTH_ADDR(0), &ctx->framebuffer.PE_PIPE_DEPTH_ADDR[0]);
528 /*01484*/ EMIT_STATE_RELOC(PE_PIPE_DEPTH_ADDR(1), &ctx->framebuffer.PE_PIPE_DEPTH_ADDR[1]);
529 } else {
530 /*01430*/ EMIT_STATE_RELOC(PE_COLOR_ADDR, &ctx->framebuffer.PE_COLOR_ADDR);
531 /*01434*/ EMIT_STATE(PE_COLOR_STRIDE, ctx->framebuffer.PE_COLOR_STRIDE);
532 /*01454*/ EMIT_STATE(PE_HDEPTH_CONTROL, ctx->framebuffer.PE_HDEPTH_CONTROL);
533 }
534 }
535 if (unlikely(dirty & (ETNA_DIRTY_STENCIL_REF | ETNA_DIRTY_RASTERIZER | ETNA_DIRTY_ZSA))) {
536 uint32_t val = etna_zsa_state(ctx->zsa)->PE_STENCIL_CONFIG_EXT;
537 if (!ctx->zsa->stencil[1].enabled &&
538 ctx->zsa->stencil[0].enabled &&
539 ctx->zsa->stencil[0].valuemask)
540 val |= ctx->stencil_ref.PE_STENCIL_CONFIG_EXT[!ccw];
541 else
542 val |= ctx->stencil_ref.PE_STENCIL_CONFIG_EXT[ccw];
543 /*014A0*/ EMIT_STATE(PE_STENCIL_CONFIG_EXT, val);
544 }
545 if (unlikely(dirty & (ETNA_DIRTY_BLEND | ETNA_DIRTY_FRAMEBUFFER))) {
546 struct etna_blend_state *blend = etna_blend_state(ctx->blend);
547 /*014A4*/ EMIT_STATE(PE_LOGIC_OP, blend->PE_LOGIC_OP | ctx->framebuffer.PE_LOGIC_OP);
548 }
549 if (unlikely(dirty & (ETNA_DIRTY_BLEND))) {
550 struct etna_blend_state *blend = etna_blend_state(ctx->blend);
551 for (int x = 0; x < 2; ++x) {
552 /*014A8*/ EMIT_STATE(PE_DITHER(x), blend->PE_DITHER[x]);
553 }
554 }
555 if (unlikely(dirty & (ETNA_DIRTY_BLEND_COLOR)) &&
556 VIV_FEATURE(screen, ETNA_FEATURE_HALF_FLOAT)) {
557 /*014B0*/ EMIT_STATE(PE_ALPHA_COLOR_EXT0, ctx->blend_color.rt[0].PE_ALPHA_COLOR_EXT0);
558 /*014B4*/ EMIT_STATE(PE_ALPHA_COLOR_EXT1, ctx->blend_color.rt[0].PE_ALPHA_COLOR_EXT1);
559 }
560 if (unlikely(dirty & (ETNA_DIRTY_ZSA | ETNA_DIRTY_RASTERIZER))) {
561 /*014B8*/ EMIT_STATE(PE_STENCIL_CONFIG_EXT2, etna_zsa_state(ctx->zsa)->PE_STENCIL_CONFIG_EXT2[ccw]);
562 }
563 if (unlikely(dirty & (ETNA_DIRTY_FRAMEBUFFER)) && screen->info->halti >= 3)
564 /*014BC*/ EMIT_STATE(PE_MEM_CONFIG, ctx->framebuffer.PE_MEM_CONFIG);
565 if (unlikely(dirty & (ETNA_DIRTY_FRAMEBUFFER | ETNA_DIRTY_TS))) {
566 /*01654*/ EMIT_STATE(TS_MEM_CONFIG, ctx->framebuffer.TS_MEM_CONFIG);
567 /*01658*/ EMIT_STATE_RELOC(TS_COLOR_STATUS_BASE, &ctx->framebuffer.TS_COLOR_STATUS_BASE);
568 /*0165C*/ EMIT_STATE_RELOC(TS_COLOR_SURFACE_BASE, &ctx->framebuffer.TS_COLOR_SURFACE_BASE);
569 /*01660*/ EMIT_STATE(TS_COLOR_CLEAR_VALUE, ctx->framebuffer.TS_COLOR_CLEAR_VALUE);
570 /*01664*/ EMIT_STATE_RELOC(TS_DEPTH_STATUS_BASE, &ctx->framebuffer.TS_DEPTH_STATUS_BASE);
571 /*01668*/ EMIT_STATE_RELOC(TS_DEPTH_SURFACE_BASE, &ctx->framebuffer.TS_DEPTH_SURFACE_BASE);
572 /*0166C*/ EMIT_STATE(TS_DEPTH_CLEAR_VALUE, ctx->framebuffer.TS_DEPTH_CLEAR_VALUE);
573 /*016BC*/ EMIT_STATE(TS_COLOR_CLEAR_VALUE_EXT, ctx->framebuffer.TS_COLOR_CLEAR_VALUE_EXT);
574 }
575 if (unlikely(dirty & (ETNA_DIRTY_SHADER))) {
576 /*0381C*/ EMIT_STATE(GL_VARYING_TOTAL_COMPONENTS, ctx->shader_state.GL_VARYING_TOTAL_COMPONENTS);
577 }
578
579 if (unlikely(dirty & (ETNA_DIRTY_FRAMEBUFFER))) {
580 if (screen->specs.num_rts == 4) {
581 for (int i = 1; i < ctx->framebuffer.num_rt; i++) {
582 const uint8_t rt = i - 1;
583 /*01500*/ EMIT_STATE_RELOC(PE_RT_ADDR_4_PIPE(rt, 0), &ctx->framebuffer.PE_RT_PIPE_COLOR_ADDR[rt][0]);
584 /*01520*/ EMIT_STATE_RELOC(PE_RT_ADDR_4_PIPE(rt, 1), &ctx->framebuffer.PE_RT_PIPE_COLOR_ADDR[rt][1]);
585 /*01580*/ EMIT_STATE(PE_RT_CONFIG_4(rt), ctx->framebuffer.PE_RT_CONFIG[rt]);
586 }
587 } else if (screen->specs.num_rts == 8) {
588 for (int i = 1; i < ctx->framebuffer.num_rt; i++) {
589 const uint8_t rt = i - 1;
590 /*14800*/ EMIT_STATE_RELOC(PE_RT_ADDR_8_PIPE(rt, 0), &ctx->framebuffer.PE_RT_PIPE_COLOR_ADDR[rt][0]);
591 /*14800*/ EMIT_STATE_RELOC(PE_RT_ADDR_8_PIPE(rt, 1), &ctx->framebuffer.PE_RT_PIPE_COLOR_ADDR[rt][1]);
592 /*14900*/ EMIT_STATE(PE_RT_CONFIG_8(rt), ctx->framebuffer.PE_RT_CONFIG[rt]);
593 }
594 }
595 }
596
597 if (unlikely(dirty & (ETNA_DIRTY_FRAMEBUFFER | ETNA_DIRTY_TS))) {
598 for (int i = 1; i < ctx->framebuffer.num_rt; i++) {
599 const uint8_t rt = i - 1;
600 /* Index 0 is not used by the binary blob. */
601 EMIT_STATE(TS_RT_CONFIG(i), ctx->framebuffer.RT_TS_MEM_CONFIG[rt]);
602 EMIT_STATE(TS_RT_CLEAR_VALUE(i), ctx->framebuffer.RT_TS_COLOR_CLEAR_VALUE[rt]);
603 EMIT_STATE(TS_RT_CLEAR_VALUE2(i), ctx->framebuffer.RT_TS_COLOR_CLEAR_VALUE_EXT[rt]);
604 EMIT_STATE_RELOC(TS_RT_STATUS_BASE(i), &ctx->framebuffer.RT_TS_COLOR_STATUS_BASE[rt]);
605 EMIT_STATE_RELOC(TS_RT_SURFACE_BASE(i), &ctx->framebuffer.RT_TS_COLOR_SURFACE_BASE[rt]);
606 }
607 }
608
609 etna_coalesce_end(stream, &coalesce);
610 /* end only EMIT_STATE */
611
612 /* Emit strongly architecture-specific state */
613 if (screen->info->halti >= 5)
614 emit_halti5_only_state(ctx, vs_output_count);
615 else
616 emit_pre_halti5_state(ctx);
617
618 /* Beginning from Halti0 some of the new shader and sampler states are not
619 * self-synchronizing anymore. Thus we need to stall the FE on PE completion
620 * before loading the new states to avoid corrupting the state of the
621 * in-flight draw.
622 */
623 if (screen->info->halti >= 0 &&
624 (ctx->dirty & (ETNA_DIRTY_SHADER | ETNA_DIRTY_CONSTBUF |
625 ETNA_DIRTY_SAMPLERS | ETNA_DIRTY_SAMPLER_VIEWS)))
626 etna_stall(ctx->stream, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
627
628 ctx->emit_texture_state(ctx);
629
630 /* We need to update the uniform cache only if one of the following bits are
631 * set in ctx->dirty:
632 * - ETNA_DIRTY_SHADER
633 * - ETNA_DIRTY_CONSTBUF
634 * - uniforms_dirty_bits
635 *
636 * In case of ETNA_DIRTY_SHADER we need load all uniforms from the cache. In
637 * all
638 * other cases we can load on the changed uniforms.
639 */
640 static const uint32_t uniform_dirty_bits =
641 ETNA_DIRTY_SHADER | ETNA_DIRTY_CONSTBUF;
642
643 /**** Large dynamically-sized state ****/
644 bool do_uniform_flush = screen->info->halti < 5;
645 if (dirty & (ETNA_DIRTY_SHADER)) {
646 /* Special case: a new shader was loaded; simply re-load all uniforms and
647 * shader code at once */
648 /* This sequence is special, do not change ordering unless necessary. According to comment
649 snippets in the Vivante kernel driver a process called "steering" goes on while programming
650 shader state. This (as I understand it) means certain unified states are "steered"
651 toward a specific shader unit (VS/PS/...) based on either explicit flags in register
652 00860, or what other state is written before "auto-steering". So this means some
653 state can legitimately be programmed multiple times.
654 */
655
656 if (screen->info->halti >= 5) { /* ICACHE (HALTI5) */
657 assert(ctx->shader_state.VS_INST_ADDR.bo && ctx->shader_state.PS_INST_ADDR.bo);
658 /* Set icache (VS) */
659 etna_set_state(stream, VIVS_VS_NEWRANGE_LOW, 0);
660 etna_set_state(stream, VIVS_VS_NEWRANGE_HIGH, ctx->shader_state.vs_inst_mem_size / 4);
661 assert(ctx->shader_state.VS_INST_ADDR.bo);
662 etna_set_state_reloc(stream, VIVS_VS_INST_ADDR, &ctx->shader_state.VS_INST_ADDR);
663 etna_set_state(stream, VIVS_SH_CONFIG, 0x00000002);
664 etna_set_state(stream, VIVS_VS_ICACHE_CONTROL, VIVS_VS_ICACHE_CONTROL_ENABLE);
665 etna_set_state(stream, VIVS_VS_ICACHE_COUNT, ctx->shader_state.vs_inst_mem_size / 4 - 1);
666
667 /* Set icache (PS) */
668 etna_set_state(stream, VIVS_PS_NEWRANGE_LOW, 0);
669 etna_set_state(stream, VIVS_PS_NEWRANGE_HIGH, ctx->shader_state.ps_inst_mem_size / 4);
670 assert(ctx->shader_state.PS_INST_ADDR.bo);
671 etna_set_state_reloc(stream, VIVS_PS_INST_ADDR, &ctx->shader_state.PS_INST_ADDR);
672 etna_set_state(stream, VIVS_SH_CONFIG, 0x00000002);
673 etna_set_state(stream, VIVS_VS_ICACHE_CONTROL, VIVS_VS_ICACHE_CONTROL_ENABLE);
674 etna_set_state(stream, VIVS_PS_ICACHE_COUNT, ctx->shader_state.ps_inst_mem_size / 4 - 1);
675
676 } else if (ctx->shader_state.VS_INST_ADDR.bo || ctx->shader_state.PS_INST_ADDR.bo) {
677 /* ICACHE (pre-HALTI5) */
678 assert(screen->specs.has_icache && screen->specs.has_shader_range_registers);
679 /* Set icache (VS) */
680 etna_set_state(stream, VIVS_VS_RANGE, (ctx->shader_state.vs_inst_mem_size / 4 - 1) << 16);
681 etna_set_state(stream, VIVS_VS_ICACHE_CONTROL,
682 VIVS_VS_ICACHE_CONTROL_ENABLE |
683 VIVS_VS_ICACHE_CONTROL_FLUSH_VS);
684 assert(ctx->shader_state.VS_INST_ADDR.bo);
685 etna_set_state_reloc(stream, VIVS_VS_INST_ADDR, &ctx->shader_state.VS_INST_ADDR);
686
687 /* Set icache (PS) */
688 etna_set_state(stream, VIVS_PS_RANGE, (ctx->shader_state.ps_inst_mem_size / 4 - 1) << 16);
689 etna_set_state(stream, VIVS_VS_ICACHE_CONTROL,
690 VIVS_VS_ICACHE_CONTROL_ENABLE |
691 VIVS_VS_ICACHE_CONTROL_FLUSH_PS);
692 assert(ctx->shader_state.PS_INST_ADDR.bo);
693 etna_set_state_reloc(stream, VIVS_PS_INST_ADDR, &ctx->shader_state.PS_INST_ADDR);
694 } else {
695 /* Upload shader directly, first flushing and disabling icache if
696 * supported on this hw */
697 if (screen->specs.has_icache) {
698 etna_set_state(stream, VIVS_VS_ICACHE_CONTROL,
699 VIVS_VS_ICACHE_CONTROL_FLUSH_PS |
700 VIVS_VS_ICACHE_CONTROL_FLUSH_VS);
701 }
702 if (screen->specs.has_shader_range_registers) {
703 etna_set_state(stream, VIVS_VS_RANGE, (ctx->shader_state.vs_inst_mem_size / 4 - 1) << 16);
704 etna_set_state(stream, VIVS_PS_RANGE, ((ctx->shader_state.ps_inst_mem_size / 4 - 1 + 0x100) << 16) |
705 0x100);
706 }
707 etna_set_state_multi(stream, screen->specs.vs_offset,
708 ctx->shader_state.vs_inst_mem_size,
709 ctx->shader_state.VS_INST_MEM);
710 etna_set_state_multi(stream, screen->specs.ps_offset,
711 ctx->shader_state.ps_inst_mem_size,
712 ctx->shader_state.PS_INST_MEM);
713 }
714
715 if (screen->specs.has_unified_uniforms) {
716 etna_set_state(stream, VIVS_VS_UNIFORM_BASE, 0);
717 etna_set_state(stream, VIVS_PS_UNIFORM_BASE, ctx->shader.vs->uniforms.count / 4);
718 }
719
720 if (do_uniform_flush)
721 etna_set_state(stream, VIVS_VS_UNIFORM_CACHE, VIVS_VS_UNIFORM_CACHE_FLUSH);
722
723 etna_uniforms_write(ctx, ctx->shader.vs, ctx->constant_buffer[PIPE_SHADER_VERTEX].cb);
724
725 if (do_uniform_flush)
726 etna_set_state(stream, VIVS_VS_UNIFORM_CACHE, VIVS_VS_UNIFORM_CACHE_FLUSH | VIVS_VS_UNIFORM_CACHE_PS);
727
728 etna_uniforms_write(ctx, ctx->shader.fs, ctx->constant_buffer[PIPE_SHADER_FRAGMENT].cb);
729
730 if (screen->info->halti >= 5) {
731 /* HALTI5 needs to be prompted to pre-fetch shaders */
732 etna_set_state(stream, VIVS_VS_ICACHE_PREFETCH, 0x00000000);
733 etna_set_state(stream, VIVS_PS_ICACHE_PREFETCH, 0x00000000);
734 etna_stall(stream, SYNC_RECIPIENT_RA, SYNC_RECIPIENT_PE);
735 }
736 } else {
737 /* ideally this cache would only be flushed if there are VS uniform changes */
738 if (do_uniform_flush)
739 etna_set_state(stream, VIVS_VS_UNIFORM_CACHE, VIVS_VS_UNIFORM_CACHE_FLUSH);
740
741 if (dirty & (uniform_dirty_bits | ctx->shader.vs->uniforms_dirty_bits))
742 etna_uniforms_write(ctx, ctx->shader.vs, ctx->constant_buffer[PIPE_SHADER_VERTEX].cb);
743
744 /* ideally this cache would only be flushed if there are PS uniform changes */
745 if (do_uniform_flush)
746 etna_set_state(stream, VIVS_VS_UNIFORM_CACHE, VIVS_VS_UNIFORM_CACHE_FLUSH | VIVS_VS_UNIFORM_CACHE_PS);
747
748 if (dirty & (uniform_dirty_bits | ctx->shader.fs->uniforms_dirty_bits))
749 etna_uniforms_write(ctx, ctx->shader.fs, ctx->constant_buffer[PIPE_SHADER_FRAGMENT].cb);
750 }
751 /**** End of state update ****/
752 #undef EMIT_STATE
753 #undef EMIT_STATE_FIXP
754 #undef EMIT_STATE_RELOC
755 ctx->dirty = 0;
756 ctx->dirty_sampler_views = 0;
757 }
758