1 /**************************************************************************
2 *
3 * Copyright 2008 VMware, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 #include "compiler/nir/nir.h"
29 #include "draw/draw_context.h"
30 #include "nir/nir_to_tgsi.h"
31 #include "util/format/u_format.h"
32 #include "util/format/u_format_s3tc.h"
33 #include "util/os_misc.h"
34 #include "util/u_inlines.h"
35 #include "util/u_memory.h"
36 #include "util/u_screen.h"
37 #include "util/u_string.h"
38
39 #include "i915_context.h"
40 #include "i915_debug.h"
41 #include "i915_fpc.h"
42 #include "i915_public.h"
43 #include "i915_reg.h"
44 #include "i915_resource.h"
45 #include "i915_screen.h"
46 #include "i915_winsys.h"
47
48 /*
49 * Probe functions
50 */
51
52 static const char *
i915_get_vendor(struct pipe_screen * screen)53 i915_get_vendor(struct pipe_screen *screen)
54 {
55 return "Mesa Project";
56 }
57
58 static const char *
i915_get_device_vendor(struct pipe_screen * screen)59 i915_get_device_vendor(struct pipe_screen *screen)
60 {
61 return "Intel";
62 }
63
64 static const char *
i915_get_name(struct pipe_screen * screen)65 i915_get_name(struct pipe_screen *screen)
66 {
67 static char buffer[128];
68 const char *chipset;
69
70 switch (i915_screen(screen)->iws->pci_id) {
71 case PCI_CHIP_I915_G:
72 chipset = "915G";
73 break;
74 case PCI_CHIP_I915_GM:
75 chipset = "915GM";
76 break;
77 case PCI_CHIP_I945_G:
78 chipset = "945G";
79 break;
80 case PCI_CHIP_I945_GM:
81 chipset = "945GM";
82 break;
83 case PCI_CHIP_I945_GME:
84 chipset = "945GME";
85 break;
86 case PCI_CHIP_G33_G:
87 chipset = "G33";
88 break;
89 case PCI_CHIP_Q35_G:
90 chipset = "Q35";
91 break;
92 case PCI_CHIP_Q33_G:
93 chipset = "Q33";
94 break;
95 case PCI_CHIP_PINEVIEW_G:
96 chipset = "Pineview G";
97 break;
98 case PCI_CHIP_PINEVIEW_M:
99 chipset = "Pineview M";
100 break;
101 default:
102 chipset = "unknown";
103 break;
104 }
105
106 snprintf(buffer, sizeof(buffer), "i915 (chipset: %s)", chipset);
107 return buffer;
108 }
109
110 static const nir_shader_compiler_options i915_compiler_options = {
111 .fdot_replicates = true,
112 .fuse_ffma32 = true,
113 .lower_bitops = true, /* required for !CAP_INTEGERS nir_to_tgsi */
114 .lower_extract_byte = true,
115 .lower_extract_word = true,
116 .lower_fdiv = true,
117 .lower_fdph = true,
118 .lower_flrp32 = true,
119 .lower_fmod = true,
120 .lower_sincos = true,
121 .lower_uniforms_to_ubo = true,
122 .lower_vector_cmp = true,
123 .force_indirect_unrolling = nir_var_all,
124 .force_indirect_unrolling_sampler = true,
125 .max_unroll_iterations = 32,
126 .no_integers = true,
127 .has_fused_comp_and_csel = true,
128 };
129
130 static const struct nir_shader_compiler_options gallivm_nir_options = {
131 .fdot_replicates = true,
132 .lower_bitops = true, /* required for !CAP_INTEGERS nir_to_tgsi */
133 .lower_scmp = true,
134 .lower_flrp32 = true,
135 .lower_flrp64 = true,
136 .lower_fsat = true,
137 .lower_bitfield_insert = true,
138 .lower_bitfield_extract = true,
139 .lower_fdph = true,
140 .lower_ffma16 = true,
141 .lower_ffma32 = true,
142 .lower_ffma64 = true,
143 .lower_fmod = true,
144 .lower_hadd = true,
145 .lower_uadd_sat = true,
146 .lower_usub_sat = true,
147 .lower_iadd_sat = true,
148 .lower_ldexp = true,
149 .lower_pack_snorm_2x16 = true,
150 .lower_pack_snorm_4x8 = true,
151 .lower_pack_unorm_2x16 = true,
152 .lower_pack_unorm_4x8 = true,
153 .lower_pack_half_2x16 = true,
154 .lower_pack_split = true,
155 .lower_unpack_snorm_2x16 = true,
156 .lower_unpack_snorm_4x8 = true,
157 .lower_unpack_unorm_2x16 = true,
158 .lower_unpack_unorm_4x8 = true,
159 .lower_unpack_half_2x16 = true,
160 .lower_extract_byte = true,
161 .lower_extract_word = true,
162 .lower_uadd_carry = true,
163 .lower_usub_borrow = true,
164 .lower_mul_2x32_64 = true,
165 .lower_ifind_msb = true,
166 .max_unroll_iterations = 32,
167 .lower_cs_local_index_to_id = true,
168 .lower_uniforms_to_ubo = true,
169 .lower_vector_cmp = true,
170 .lower_device_index_to_zero = true,
171 /* .support_16bit_alu = true, */
172 .support_indirect_inputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES),
173 .support_indirect_outputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES),
174 .has_ddx_intrinsics = true,
175 .no_integers = true,
176 };
177
178 static const void *
i915_get_compiler_options(struct pipe_screen * pscreen,enum pipe_shader_ir ir,enum pipe_shader_type shader)179 i915_get_compiler_options(struct pipe_screen *pscreen, enum pipe_shader_ir ir,
180 enum pipe_shader_type shader)
181 {
182 assert(ir == PIPE_SHADER_IR_NIR);
183 if (shader == PIPE_SHADER_FRAGMENT)
184 return &i915_compiler_options;
185 else
186 return &gallivm_nir_options;
187 }
188
189 static void
i915_optimize_nir(struct nir_shader * s)190 i915_optimize_nir(struct nir_shader *s)
191 {
192 bool progress;
193
194 do {
195 progress = false;
196
197 NIR_PASS_V(s, nir_lower_vars_to_ssa);
198
199 NIR_PASS(progress, s, nir_copy_prop);
200 NIR_PASS(progress, s, nir_opt_algebraic);
201 NIR_PASS(progress, s, nir_opt_constant_folding);
202 NIR_PASS(progress, s, nir_opt_remove_phis);
203 NIR_PASS(progress, s, nir_opt_conditional_discard);
204 NIR_PASS(progress, s, nir_opt_dce);
205 NIR_PASS(progress, s, nir_opt_dead_cf);
206 NIR_PASS(progress, s, nir_opt_cse);
207 NIR_PASS(progress, s, nir_opt_find_array_copies);
208 NIR_PASS(progress, s, nir_opt_if, nir_opt_if_optimize_phi_true_false);
209 NIR_PASS(progress, s, nir_opt_peephole_select, ~0 /* flatten all IFs. */,
210 true, true);
211 NIR_PASS(progress, s, nir_opt_algebraic);
212 NIR_PASS(progress, s, nir_opt_constant_folding);
213 NIR_PASS(progress, s, nir_opt_shrink_stores, true);
214 NIR_PASS(progress, s, nir_opt_shrink_vectors, false);
215 NIR_PASS(progress, s, nir_opt_loop);
216 NIR_PASS(progress, s, nir_opt_undef);
217 NIR_PASS(progress, s, nir_opt_loop_unroll);
218
219 } while (progress);
220
221 NIR_PASS(progress, s, nir_remove_dead_variables, nir_var_function_temp,
222 NULL);
223
224 /* Group texture loads together to try to avoid hitting the
225 * texture indirection phase limit.
226 */
227 NIR_PASS_V(s, nir_group_loads, nir_group_all, ~0);
228 }
229
230 static char *
i915_finalize_nir(struct pipe_screen * pscreen,struct nir_shader * s)231 i915_finalize_nir(struct pipe_screen *pscreen, struct nir_shader *s)
232 {
233 if (s->info.stage == MESA_SHADER_FRAGMENT)
234 i915_optimize_nir(s);
235
236 /* st_program.c's parameter list optimization requires that future nir
237 * variants don't reallocate the uniform storage, so we have to remove
238 * uniforms that occupy storage. But we don't want to remove samplers,
239 * because they're needed for YUV variant lowering.
240 */
241 nir_remove_dead_derefs(s);
242 nir_foreach_uniform_variable_safe (var, s) {
243 if (var->data.mode == nir_var_uniform &&
244 (glsl_type_get_image_count(var->type) ||
245 glsl_type_get_sampler_count(var->type)))
246 continue;
247
248 exec_node_remove(&var->node);
249 }
250 nir_validate_shader(s, "after uniform var removal");
251
252 nir_sweep(s);
253 return NULL;
254 }
255
256 static int
i915_get_shader_param(struct pipe_screen * screen,enum pipe_shader_type shader,enum pipe_shader_cap cap)257 i915_get_shader_param(struct pipe_screen *screen, enum pipe_shader_type shader,
258 enum pipe_shader_cap cap)
259 {
260 switch (cap) {
261 case PIPE_SHADER_CAP_SUPPORTED_IRS:
262 return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_TGSI);
263
264 case PIPE_SHADER_CAP_INTEGERS:
265 /* mesa/st requires that this cap is the same across stages, and the FS
266 * can't do ints.
267 */
268 return 0;
269
270 /* i915 can't do these, and even if gallivm NIR can we call nir_to_tgsi
271 * manually and TGSI can't.
272 */
273 case PIPE_SHADER_CAP_INT16:
274 case PIPE_SHADER_CAP_FP16:
275 case PIPE_SHADER_CAP_FP16_DERIVATIVES:
276 case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:
277 return 0;
278
279 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
280 /* While draw could normally handle this for the VS, the NIR lowering
281 * to regs can't handle our non-native-integers, so we have to lower to
282 * if ladders.
283 */
284 return 0;
285
286 default:
287 break;
288 }
289
290 switch (shader) {
291 case PIPE_SHADER_VERTEX:
292 switch (cap) {
293 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
294 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
295 return 0;
296 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
297 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
298 return 0;
299 default:
300 return draw_get_shader_param(shader, cap);
301 }
302 case PIPE_SHADER_FRAGMENT:
303 /* XXX: some of these are just shader model 2.0 values, fix this! */
304 switch (cap) {
305 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
306 return I915_MAX_ALU_INSN + I915_MAX_TEX_INSN;
307 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
308 return I915_MAX_ALU_INSN;
309 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
310 return I915_MAX_TEX_INSN;
311 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
312 return 4;
313 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
314 return 0;
315 case PIPE_SHADER_CAP_MAX_INPUTS:
316 return 10;
317 case PIPE_SHADER_CAP_MAX_OUTPUTS:
318 return 1;
319 case PIPE_SHADER_CAP_MAX_CONST_BUFFER0_SIZE:
320 return 32 * sizeof(float[4]);
321 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
322 return 1;
323 case PIPE_SHADER_CAP_MAX_TEMPS:
324 /* 16 inter-phase temps, 3 intra-phase temps. i915c reported 16. too. */
325 return 16;
326 case PIPE_SHADER_CAP_CONT_SUPPORTED:
327 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
328 return 0;
329 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
330 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
331 case PIPE_SHADER_CAP_SUBROUTINES:
332 return 0;
333 case PIPE_SHADER_CAP_INT64_ATOMICS:
334 case PIPE_SHADER_CAP_INT16:
335 case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
336 return 0;
337 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
338 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
339 return I915_TEX_UNITS;
340 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
341 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
342 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
343 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
344 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
345 return 0;
346
347 default:
348 debug_printf("%s: Unknown cap %u.\n", __func__, cap);
349 return 0;
350 }
351 break;
352 default:
353 return 0;
354 }
355 }
356
357 static void
i915_init_screen_caps(struct i915_screen * is)358 i915_init_screen_caps(struct i915_screen *is)
359 {
360 struct pipe_caps *caps = (struct pipe_caps *)&is->base.caps;
361
362 u_init_pipe_screen_caps(&is->base, 1);
363
364 /* Supported features (boolean caps). */
365 caps->anisotropic_filter = true;
366 caps->npot_textures = true;
367 caps->mixed_framebuffer_sizes = true;
368 caps->primitive_restart = true; /* draw module */
369 caps->primitive_restart_fixed_index = true;
370 caps->vertex_element_instance_divisor = true;
371 caps->blend_equation_separate = true;
372 caps->vs_instanceid = true;
373 caps->vertex_color_clamped = true;
374 caps->user_vertex_buffers = true;
375 caps->mixed_color_depth_bits = true;
376 caps->tgsi_texcoord = true;
377
378 caps->texture_transfer_modes =
379 caps->pci_group =
380 caps->pci_bus =
381 caps->pci_device =
382 caps->pci_function = 0;
383
384 caps->allow_mapped_buffers_during_execution = false;
385
386 /* Can't expose shareable shaders because the draw shaders reference the
387 * draw module's state, which is per-context.
388 */
389 caps->shareable_shaders = false;
390
391 caps->max_gs_invocations = 32;
392
393 caps->max_shader_buffer_size = 1 << 27;
394
395 caps->max_viewports = 1;
396
397 caps->min_map_buffer_alignment = 64;
398
399 caps->glsl_feature_level =
400 caps->glsl_feature_level_compatibility = 120;
401
402 caps->constant_buffer_offset_alignment = 16;
403
404 /* Texturing. */
405 caps->max_texture_2d_size = 1 << (I915_MAX_TEXTURE_2D_LEVELS - 1);
406 caps->max_texture_3d_levels = I915_MAX_TEXTURE_3D_LEVELS;
407 caps->max_texture_cube_levels = I915_MAX_TEXTURE_2D_LEVELS;
408
409 /* Render targets. */
410 caps->max_render_targets = 1;
411
412 caps->max_vertex_attrib_stride = 2048;
413
414 /* Fragment coordinate conventions. */
415 caps->fs_coord_origin_upper_left =
416 caps->fs_coord_pixel_center_half_integer = true;
417 caps->endianness = PIPE_ENDIAN_LITTLE;
418 caps->max_varyings = 10;
419
420 caps->nir_images_as_deref = false;
421
422 caps->vendor_id = 0x8086;
423 caps->device_id = is->iws->pci_id;
424
425 /* Once a batch uses more than 75% of the maximum mappable size, we
426 * assume that there's some fragmentation, and we start doing extra
427 * flushing, etc. That's the big cliff apps will care about.
428 */
429 const int gpu_mappable_megabytes = is->iws->aperture_size(is->iws) * 3 / 4;
430 uint64_t system_memory;
431 caps->video_memory =
432 os_get_total_physical_memory(&system_memory) ?
433 MIN2(gpu_mappable_megabytes, (int)(system_memory >> 20)) : 0;
434 caps->uma = true;
435
436 caps->min_line_width =
437 caps->min_line_width_aa =
438 caps->min_point_size =
439 caps->min_point_size_aa = 1;
440
441 caps->point_size_granularity =
442 caps->line_width_granularity = 0.1;
443
444 caps->max_line_width =
445 caps->max_line_width_aa = 7.5;
446
447 caps->max_point_size =
448 caps->max_point_size_aa = 255.0;
449
450 caps->max_texture_anisotropy = 4.0;
451
452 caps->max_texture_lod_bias = 16.0;
453 }
454
455 bool
i915_is_format_supported(struct pipe_screen * screen,enum pipe_format format,enum pipe_texture_target target,unsigned sample_count,unsigned storage_sample_count,unsigned tex_usage)456 i915_is_format_supported(struct pipe_screen *screen, enum pipe_format format,
457 enum pipe_texture_target target, unsigned sample_count,
458 unsigned storage_sample_count, unsigned tex_usage)
459 {
460 static const enum pipe_format tex_supported[] = {
461 PIPE_FORMAT_B8G8R8A8_UNORM, PIPE_FORMAT_B8G8R8A8_SRGB,
462 PIPE_FORMAT_B8G8R8X8_UNORM, PIPE_FORMAT_R8G8B8A8_UNORM,
463 PIPE_FORMAT_R8G8B8X8_UNORM, PIPE_FORMAT_B4G4R4A4_UNORM,
464 PIPE_FORMAT_B5G6R5_UNORM, PIPE_FORMAT_B5G5R5A1_UNORM,
465 PIPE_FORMAT_B10G10R10A2_UNORM, PIPE_FORMAT_L8_UNORM, PIPE_FORMAT_A8_UNORM,
466 PIPE_FORMAT_I8_UNORM, PIPE_FORMAT_L8A8_UNORM, PIPE_FORMAT_UYVY,
467 PIPE_FORMAT_YUYV,
468 /* XXX why not?
469 PIPE_FORMAT_Z16_UNORM, */
470 PIPE_FORMAT_DXT1_RGB, PIPE_FORMAT_DXT1_SRGB, PIPE_FORMAT_DXT1_RGBA,
471 PIPE_FORMAT_DXT1_SRGBA, PIPE_FORMAT_DXT3_RGBA, PIPE_FORMAT_DXT3_SRGBA,
472 PIPE_FORMAT_DXT5_RGBA, PIPE_FORMAT_DXT5_SRGBA, PIPE_FORMAT_Z24X8_UNORM,
473 PIPE_FORMAT_FXT1_RGB, PIPE_FORMAT_FXT1_RGBA,
474 PIPE_FORMAT_Z24_UNORM_S8_UINT, PIPE_FORMAT_NONE /* list terminator */
475 };
476 static const enum pipe_format render_supported[] = {
477 PIPE_FORMAT_B8G8R8A8_UNORM, PIPE_FORMAT_B8G8R8X8_UNORM,
478 PIPE_FORMAT_R8G8B8A8_UNORM, PIPE_FORMAT_R8G8B8X8_UNORM,
479 PIPE_FORMAT_B5G6R5_UNORM, PIPE_FORMAT_B5G5R5A1_UNORM,
480 PIPE_FORMAT_B4G4R4A4_UNORM, PIPE_FORMAT_B10G10R10A2_UNORM,
481 PIPE_FORMAT_L8_UNORM, PIPE_FORMAT_A8_UNORM,
482 PIPE_FORMAT_I8_UNORM, PIPE_FORMAT_NONE /* list terminator */
483 };
484 static const enum pipe_format depth_supported[] = {
485 /* XXX why not?
486 PIPE_FORMAT_Z16_UNORM, */
487 PIPE_FORMAT_Z24X8_UNORM, PIPE_FORMAT_Z24_UNORM_S8_UINT,
488 PIPE_FORMAT_NONE /* list terminator */
489 };
490 const enum pipe_format *list;
491 uint32_t i;
492
493 if (sample_count > 1)
494 return false;
495
496 if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
497 return false;
498
499 if (tex_usage & PIPE_BIND_DEPTH_STENCIL)
500 list = depth_supported;
501 else if (tex_usage & PIPE_BIND_RENDER_TARGET)
502 list = render_supported;
503 else if (tex_usage & PIPE_BIND_SAMPLER_VIEW)
504 list = tex_supported;
505 else
506 return true; /* PIPE_BIND_{VERTEX,INDEX}_BUFFER */
507
508 for (i = 0; list[i] != PIPE_FORMAT_NONE; i++) {
509 if (list[i] == format)
510 return true;
511 }
512
513 return false;
514 }
515
516 /*
517 * Fence functions
518 */
519
520 static void
i915_fence_reference(struct pipe_screen * screen,struct pipe_fence_handle ** ptr,struct pipe_fence_handle * fence)521 i915_fence_reference(struct pipe_screen *screen, struct pipe_fence_handle **ptr,
522 struct pipe_fence_handle *fence)
523 {
524 struct i915_screen *is = i915_screen(screen);
525
526 is->iws->fence_reference(is->iws, ptr, fence);
527 }
528
529 static bool
i915_fence_finish(struct pipe_screen * screen,struct pipe_context * ctx,struct pipe_fence_handle * fence,uint64_t timeout)530 i915_fence_finish(struct pipe_screen *screen, struct pipe_context *ctx,
531 struct pipe_fence_handle *fence, uint64_t timeout)
532 {
533 struct i915_screen *is = i915_screen(screen);
534
535 if (!timeout)
536 return is->iws->fence_signalled(is->iws, fence) == 1;
537
538 return is->iws->fence_finish(is->iws, fence) == 1;
539 }
540
541 /*
542 * Generic functions
543 */
544
545 static void
i915_destroy_screen(struct pipe_screen * screen)546 i915_destroy_screen(struct pipe_screen *screen)
547 {
548 struct i915_screen *is = i915_screen(screen);
549
550 if (is->iws)
551 is->iws->destroy(is->iws);
552
553 FREE(is);
554 }
555
556 static int
i915_screen_get_fd(struct pipe_screen * screen)557 i915_screen_get_fd(struct pipe_screen *screen)
558 {
559 struct i915_screen *is = i915_screen(screen);
560
561 return is->iws->get_fd(is->iws);
562 }
563
564 /**
565 * Create a new i915_screen object
566 */
567 struct pipe_screen *
i915_screen_create(struct i915_winsys * iws)568 i915_screen_create(struct i915_winsys *iws)
569 {
570 struct i915_screen *is = CALLOC_STRUCT(i915_screen);
571
572 if (!is)
573 return NULL;
574
575 switch (iws->pci_id) {
576 case PCI_CHIP_I915_G:
577 case PCI_CHIP_I915_GM:
578 is->is_i945 = false;
579 break;
580
581 case PCI_CHIP_I945_G:
582 case PCI_CHIP_I945_GM:
583 case PCI_CHIP_I945_GME:
584 case PCI_CHIP_G33_G:
585 case PCI_CHIP_Q33_G:
586 case PCI_CHIP_Q35_G:
587 case PCI_CHIP_PINEVIEW_G:
588 case PCI_CHIP_PINEVIEW_M:
589 is->is_i945 = true;
590 break;
591
592 default:
593 debug_printf("%s: unknown pci id 0x%x, cannot create screen\n", __func__,
594 iws->pci_id);
595 FREE(is);
596 return NULL;
597 }
598
599 is->iws = iws;
600
601 is->base.destroy = i915_destroy_screen;
602
603 is->base.get_name = i915_get_name;
604 is->base.get_vendor = i915_get_vendor;
605 is->base.get_device_vendor = i915_get_device_vendor;
606 is->base.get_screen_fd = i915_screen_get_fd;
607 is->base.get_shader_param = i915_get_shader_param;
608 is->base.get_compiler_options = i915_get_compiler_options;
609 is->base.finalize_nir = i915_finalize_nir;
610 is->base.is_format_supported = i915_is_format_supported;
611
612 is->base.context_create = i915_create_context;
613
614 is->base.fence_reference = i915_fence_reference;
615 is->base.fence_finish = i915_fence_finish;
616
617 i915_init_screen_resource_functions(is);
618
619 i915_init_screen_caps(is);
620
621 i915_debug_init(is);
622
623 return &is->base;
624 }
625