1 /*
2 * Copyright © 2017 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23 /**
24 * @file iris_batch.c
25 *
26 * Batchbuffer and command submission module.
27 *
28 * Every API draw call results in a number of GPU commands, which we
29 * collect into a "batch buffer". Typically, many draw calls are grouped
30 * into a single batch to amortize command submission overhead.
31 *
32 * We submit batches to the kernel using the I915_GEM_EXECBUFFER2 ioctl.
33 * One critical piece of data is the "validation list", which contains a
34 * list of the buffer objects (BOs) which the commands in the GPU need.
35 * The kernel will make sure these are resident and pinned at the correct
36 * virtual memory address before executing our batch. If a BO is not in
37 * the validation list, it effectively does not exist, so take care.
38 */
39
40 #include "iris_batch.h"
41 #include "iris_bufmgr.h"
42 #include "iris_context.h"
43 #include "iris_fence.h"
44 #include "iris_kmd_backend.h"
45 #include "iris_utrace.h"
46 #include "i915/iris_batch.h"
47 #include "xe/iris_batch.h"
48
49 #include "common/intel_aux_map.h"
50 #include "intel/common/intel_gem.h"
51 #include "intel/compiler/brw_compiler.h"
52 #ifdef INTEL_USE_ELK
53 #include "intel/compiler/elk/elk_compiler.h"
54 #endif
55 #include "intel/ds/intel_tracepoints.h"
56 #include "util/hash_table.h"
57 #include "util/u_debug.h"
58 #include "util/set.h"
59 #include "util/u_upload_mgr.h"
60
61 #include <errno.h>
62 #include <xf86drm.h>
63
64 #ifdef HAVE_VALGRIND
65 #include <valgrind.h>
66 #include <memcheck.h>
67 #define VG(x) x
68 #else
69 #define VG(x)
70 #endif
71
72 #define FILE_DEBUG_FLAG DEBUG_BUFMGR
73
74 static void
75 iris_batch_reset(struct iris_batch *batch);
76
77 unsigned
iris_batch_num_fences(struct iris_batch * batch)78 iris_batch_num_fences(struct iris_batch *batch)
79 {
80 return util_dynarray_num_elements(&batch->exec_fences,
81 struct iris_batch_fence);
82 }
83
84 /**
85 * Debugging code to dump the fence list, used by INTEL_DEBUG=submit.
86 */
87 void
iris_dump_fence_list(struct iris_batch * batch)88 iris_dump_fence_list(struct iris_batch *batch)
89 {
90 fprintf(stderr, "Fence list (length %u): ", iris_batch_num_fences(batch));
91
92 util_dynarray_foreach(&batch->exec_fences, struct iris_batch_fence, f) {
93 fprintf(stderr, "%s%u%s ",
94 (f->flags & IRIS_BATCH_FENCE_WAIT) ? "..." : "",
95 f->handle,
96 (f->flags & IRIS_BATCH_FENCE_SIGNAL) ? "!" : "");
97 }
98
99 fprintf(stderr, "\n");
100 }
101
102 /**
103 * Debugging code to dump the validation list, used by INTEL_DEBUG=submit.
104 */
105 void
iris_dump_bo_list(struct iris_batch * batch)106 iris_dump_bo_list(struct iris_batch *batch)
107 {
108 fprintf(stderr, "BO list (length %d):\n", batch->exec_count);
109
110 for (int i = 0; i < batch->exec_count; i++) {
111 struct iris_bo *bo = batch->exec_bos[i];
112 struct iris_bo *backing = iris_get_backing_bo(bo);
113 bool written = BITSET_TEST(batch->bos_written, i);
114 bool exported = iris_bo_is_exported(bo);
115 bool imported = iris_bo_is_imported(bo);
116
117 fprintf(stderr, "[%2d]: %3d (%3d) %-14s @ 0x%016"PRIx64" (%-15s %8"PRIu64"B) %2d refs %s%s%s\n",
118 i,
119 bo->gem_handle,
120 backing->gem_handle,
121 bo->name,
122 bo->address,
123 iris_heap_to_string[backing->real.heap],
124 bo->size,
125 bo->refcount,
126 written ? " write" : "",
127 exported ? " exported" : "",
128 imported ? " imported" : "");
129 }
130 }
131
132 /**
133 * Return BO information to the batch decoder (for debugging).
134 */
135 static struct intel_batch_decode_bo
decode_get_bo(void * v_batch,bool ppgtt,uint64_t address)136 decode_get_bo(void *v_batch, bool ppgtt, uint64_t address)
137 {
138 struct iris_batch *batch = v_batch;
139
140 assert(ppgtt);
141
142 for (int i = 0; i < batch->exec_count; i++) {
143 struct iris_bo *bo = batch->exec_bos[i];
144 /* The decoder zeroes out the top 16 bits, so we need to as well */
145 uint64_t bo_address = bo->address & (~0ull >> 16);
146
147 if (address >= bo_address && address < bo_address + bo->size) {
148 if (bo->real.mmap_mode == IRIS_MMAP_NONE)
149 return (struct intel_batch_decode_bo) { };
150
151 return (struct intel_batch_decode_bo) {
152 .addr = bo_address,
153 .size = bo->size,
154 .map = iris_bo_map(batch->dbg, bo, MAP_READ | MAP_ASYNC),
155 };
156 }
157 }
158
159 return (struct intel_batch_decode_bo) { };
160 }
161
162 static unsigned
decode_get_state_size(void * v_batch,uint64_t address,UNUSED uint64_t base_address)163 decode_get_state_size(void *v_batch,
164 uint64_t address,
165 UNUSED uint64_t base_address)
166 {
167 struct iris_batch *batch = v_batch;
168 unsigned size = (uintptr_t)
169 _mesa_hash_table_u64_search(batch->state_sizes, address);
170
171 return size;
172 }
173
174 /**
175 * Decode the current batch.
176 */
177 void
iris_batch_decode_batch(struct iris_batch * batch)178 iris_batch_decode_batch(struct iris_batch *batch)
179 {
180 void *map = iris_bo_map(batch->dbg, batch->exec_bos[0], MAP_READ);
181 intel_print_batch(&batch->decoder, map, batch->primary_batch_size,
182 batch->exec_bos[0]->address, false);
183 }
184
185 static void
iris_init_batch(struct iris_context * ice,enum iris_batch_name name)186 iris_init_batch(struct iris_context *ice,
187 enum iris_batch_name name)
188 {
189 struct iris_batch *batch = &ice->batches[name];
190 struct iris_screen *screen = (void *) ice->ctx.screen;
191
192 /* Note: screen, ctx_id, exec_flags and has_engines_context fields are
193 * initialized at an earlier phase when contexts are created.
194 *
195 * See iris_init_batches(), which calls either iris_init_engines_context()
196 * or iris_init_non_engine_contexts().
197 */
198
199 batch->dbg = &ice->dbg;
200 batch->reset = &ice->reset;
201 batch->state_sizes = ice->state.sizes;
202 batch->name = name;
203 batch->ice = ice;
204 batch->screen = screen;
205 batch->contains_fence_signal = false;
206
207 batch->fine_fences.uploader =
208 u_upload_create(&ice->ctx, 4096, PIPE_BIND_CUSTOM,
209 PIPE_USAGE_STAGING, 0);
210 iris_fine_fence_init(batch);
211
212 util_dynarray_init(&batch->exec_fences, ralloc_context(NULL));
213 util_dynarray_init(&batch->syncobjs, ralloc_context(NULL));
214
215 batch->exec_count = 0;
216 batch->max_gem_handle = 0;
217 batch->exec_array_size = 128;
218 batch->exec_bos =
219 malloc(batch->exec_array_size * sizeof(batch->exec_bos[0]));
220 batch->bos_written =
221 rzalloc_array(NULL, BITSET_WORD, BITSET_WORDS(batch->exec_array_size));
222
223 batch->bo_aux_modes = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
224 _mesa_key_pointer_equal);
225
226 batch->num_other_batches = 0;
227 memset(batch->other_batches, 0, sizeof(batch->other_batches));
228
229 iris_foreach_batch(ice, other_batch) {
230 if (batch != other_batch)
231 batch->other_batches[batch->num_other_batches++] = other_batch;
232 }
233
234 if (INTEL_DEBUG(DEBUG_BATCH | DEBUG_BATCH_STATS)) {
235 const unsigned decode_flags = INTEL_BATCH_DECODE_DEFAULT_FLAGS |
236 (INTEL_DEBUG(DEBUG_COLOR) ? INTEL_BATCH_DECODE_IN_COLOR : 0);
237
238 if (screen->brw) {
239 intel_batch_decode_ctx_init_brw(&batch->decoder, &screen->brw->isa,
240 screen->devinfo,
241 stderr, decode_flags, NULL,
242 decode_get_bo, decode_get_state_size, batch);
243 } else {
244 #ifdef INTEL_USE_ELK
245 assert(screen->elk);
246 intel_batch_decode_ctx_init_elk(&batch->decoder, &screen->elk->isa,
247 screen->devinfo,
248 stderr, decode_flags, NULL,
249 decode_get_bo, decode_get_state_size, batch);
250 #else
251 unreachable("no elk support");
252 #endif
253 }
254 batch->decoder.dynamic_base = IRIS_MEMZONE_DYNAMIC_START;
255 batch->decoder.instruction_base = IRIS_MEMZONE_SHADER_START;
256 batch->decoder.surface_base = IRIS_MEMZONE_BINDER_START;
257 batch->decoder.max_vbo_decoded_lines = 32;
258 if (batch->name == IRIS_BATCH_BLITTER)
259 batch->decoder.engine = INTEL_ENGINE_CLASS_COPY;
260 }
261
262 iris_init_batch_measure(ice, batch);
263
264 u_trace_init(&batch->trace, &ice->ds.trace_context);
265
266 iris_batch_reset(batch);
267 }
268
269 void
iris_init_batches(struct iris_context * ice)270 iris_init_batches(struct iris_context *ice)
271 {
272 struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen;
273 struct iris_bufmgr *bufmgr = screen->bufmgr;
274 const struct intel_device_info *devinfo = iris_bufmgr_get_device_info(bufmgr);
275
276 switch (devinfo->kmd_type) {
277 case INTEL_KMD_TYPE_I915:
278 iris_i915_init_batches(ice);
279 break;
280 case INTEL_KMD_TYPE_XE:
281 iris_xe_init_batches(ice);
282 break;
283 default:
284 unreachable("missing");
285 }
286
287 iris_foreach_batch(ice, batch)
288 iris_init_batch(ice, batch - &ice->batches[0]);
289 }
290
291 static int
find_exec_index(struct iris_batch * batch,struct iris_bo * bo)292 find_exec_index(struct iris_batch *batch, struct iris_bo *bo)
293 {
294 unsigned index = READ_ONCE(bo->index);
295
296 if (index == -1)
297 return -1;
298
299 if (index < batch->exec_count && batch->exec_bos[index] == bo)
300 return index;
301
302 /* May have been shared between multiple active batches */
303 for (index = 0; index < batch->exec_count; index++) {
304 if (batch->exec_bos[index] == bo)
305 return index;
306 }
307
308 return -1;
309 }
310
311 static void
ensure_exec_obj_space(struct iris_batch * batch,uint32_t count)312 ensure_exec_obj_space(struct iris_batch *batch, uint32_t count)
313 {
314 while (batch->exec_count + count > batch->exec_array_size) {
315 unsigned old_size = batch->exec_array_size;
316
317 batch->exec_array_size *= 2;
318 batch->exec_bos =
319 realloc(batch->exec_bos,
320 batch->exec_array_size * sizeof(batch->exec_bos[0]));
321 batch->bos_written =
322 rerzalloc(NULL, batch->bos_written, BITSET_WORD,
323 BITSET_WORDS(old_size),
324 BITSET_WORDS(batch->exec_array_size));
325 }
326 }
327
328 static void
add_bo_to_batch(struct iris_batch * batch,struct iris_bo * bo,bool writable)329 add_bo_to_batch(struct iris_batch *batch, struct iris_bo *bo, bool writable)
330 {
331 assert(batch->exec_array_size > batch->exec_count);
332
333 iris_bo_reference(bo);
334
335 batch->exec_bos[batch->exec_count] = bo;
336
337 if (writable)
338 BITSET_SET(batch->bos_written, batch->exec_count);
339
340 bo->index = batch->exec_count;
341 batch->exec_count++;
342 batch->aperture_space += bo->size;
343
344 batch->max_gem_handle =
345 MAX2(batch->max_gem_handle, iris_get_backing_bo(bo)->gem_handle);
346 }
347
348 static void
flush_for_cross_batch_dependencies(struct iris_batch * batch,struct iris_bo * bo,bool writable)349 flush_for_cross_batch_dependencies(struct iris_batch *batch,
350 struct iris_bo *bo,
351 bool writable)
352 {
353 if (batch->measure && bo == batch->measure->bo)
354 return;
355
356 /* When a batch uses a buffer for the first time, or newly writes a buffer
357 * it had already referenced, we may need to flush other batches in order
358 * to correctly synchronize them.
359 */
360 for (int b = 0; b < batch->num_other_batches; b++) {
361 struct iris_batch *other_batch = batch->other_batches[b];
362 int other_index = find_exec_index(other_batch, bo);
363
364 /* If the buffer is referenced by another batch, and either batch
365 * intends to write it, then flush the other batch and synchronize.
366 *
367 * Consider these cases:
368 *
369 * 1. They read, we read => No synchronization required.
370 * 2. They read, we write => Synchronize (they need the old value)
371 * 3. They write, we read => Synchronize (we need their new value)
372 * 4. They write, we write => Synchronize (order writes)
373 *
374 * The read/read case is very common, as multiple batches usually
375 * share a streaming state buffer or shader assembly buffer, and
376 * we want to avoid synchronizing in this case.
377 */
378 if (other_index != -1 &&
379 (writable || BITSET_TEST(other_batch->bos_written, other_index)))
380 iris_batch_flush(other_batch);
381 }
382 }
383
384 /**
385 * Add a buffer to the current batch's validation list.
386 *
387 * You must call this on any BO you wish to use in this batch, to ensure
388 * that it's resident when the GPU commands execute.
389 */
390 void
iris_use_pinned_bo(struct iris_batch * batch,struct iris_bo * bo,bool writable,enum iris_domain access)391 iris_use_pinned_bo(struct iris_batch *batch,
392 struct iris_bo *bo,
393 bool writable, enum iris_domain access)
394 {
395 assert(bo != batch->bo);
396
397 /* Never mark the workaround BO with EXEC_OBJECT_WRITE. We don't care
398 * about the order of any writes to that buffer, and marking it writable
399 * would introduce data dependencies between multiple batches which share
400 * the buffer. It is added directly to the batch using add_bo_to_batch()
401 * during batch reset time.
402 */
403 if (bo == batch->screen->workaround_bo)
404 return;
405
406 if (access < NUM_IRIS_DOMAINS) {
407 assert(batch->sync_region_depth);
408 iris_bo_bump_seqno(bo, batch->next_seqno, access);
409 }
410
411 int existing_index = find_exec_index(batch, bo);
412
413 if (existing_index == -1) {
414 flush_for_cross_batch_dependencies(batch, bo, writable);
415
416 ensure_exec_obj_space(batch, 1);
417 add_bo_to_batch(batch, bo, writable);
418 } else if (writable && !BITSET_TEST(batch->bos_written, existing_index)) {
419 flush_for_cross_batch_dependencies(batch, bo, writable);
420
421 /* The BO is already in the list; mark it writable */
422 BITSET_SET(batch->bos_written, existing_index);
423 }
424 }
425
426 static void
create_batch(struct iris_batch * batch)427 create_batch(struct iris_batch *batch)
428 {
429 struct iris_screen *screen = batch->screen;
430 struct iris_bufmgr *bufmgr = screen->bufmgr;
431
432 /* TODO: We probably could suballocate batches... */
433 batch->bo = iris_bo_alloc(bufmgr, "command buffer",
434 BATCH_SZ + BATCH_RESERVED, 8,
435 IRIS_MEMZONE_OTHER,
436 BO_ALLOC_NO_SUBALLOC | BO_ALLOC_CAPTURE);
437 batch->map = iris_bo_map(NULL, batch->bo, MAP_READ | MAP_WRITE);
438 batch->map_next = batch->map;
439
440 ensure_exec_obj_space(batch, 1);
441 add_bo_to_batch(batch, batch->bo, false);
442 }
443
444 static void
iris_batch_maybe_noop(struct iris_batch * batch)445 iris_batch_maybe_noop(struct iris_batch *batch)
446 {
447 /* We only insert the NOOP at the beginning of the batch. */
448 assert(iris_batch_bytes_used(batch) == 0);
449
450 if (batch->noop_enabled) {
451 /* Emit MI_BATCH_BUFFER_END to prevent any further command to be
452 * executed.
453 */
454 uint32_t *map = batch->map_next;
455
456 map[0] = (0xA << 23);
457
458 batch->map_next += 4;
459 }
460 }
461
462 static void
iris_batch_reset(struct iris_batch * batch)463 iris_batch_reset(struct iris_batch *batch)
464 {
465 struct iris_screen *screen = batch->screen;
466 struct iris_bufmgr *bufmgr = screen->bufmgr;
467 const struct intel_device_info *devinfo = screen->devinfo;
468
469 u_trace_fini(&batch->trace);
470
471 iris_bo_unreference(batch->bo);
472 batch->primary_batch_size = 0;
473 batch->total_chained_batch_size = 0;
474 batch->contains_draw = false;
475 batch->contains_fence_signal = false;
476 if (devinfo->ver < 11)
477 batch->decoder.surface_base = batch->last_binder_address;
478 else
479 batch->decoder.bt_pool_base = batch->last_binder_address;
480
481 create_batch(batch);
482 assert(batch->bo->index == 0);
483
484 memset(batch->bos_written, 0,
485 sizeof(BITSET_WORD) * BITSET_WORDS(batch->exec_array_size));
486
487 struct iris_syncobj *syncobj = iris_create_syncobj(bufmgr);
488 iris_batch_add_syncobj(batch, syncobj, IRIS_BATCH_FENCE_SIGNAL);
489 iris_syncobj_reference(bufmgr, &syncobj, NULL);
490
491 assert(!batch->sync_region_depth);
492 iris_batch_sync_boundary(batch);
493 iris_batch_mark_reset_sync(batch);
494
495 /* Always add the workaround BO, it contains a driver identifier at the
496 * beginning quite helpful to debug error states.
497 */
498 add_bo_to_batch(batch, screen->workaround_bo, false);
499
500 iris_batch_maybe_noop(batch);
501
502 u_trace_init(&batch->trace, &batch->ice->ds.trace_context);
503 batch->begin_trace_recorded = false;
504 }
505
506 static void
iris_batch_free(const struct iris_context * ice,struct iris_batch * batch)507 iris_batch_free(const struct iris_context *ice, struct iris_batch *batch)
508 {
509 struct iris_screen *screen = batch->screen;
510 struct iris_bufmgr *bufmgr = screen->bufmgr;
511 const struct intel_device_info *devinfo = iris_bufmgr_get_device_info(bufmgr);
512
513 for (int i = 0; i < batch->exec_count; i++) {
514 iris_bo_unreference(batch->exec_bos[i]);
515 }
516 free(batch->exec_bos);
517 ralloc_free(batch->bos_written);
518
519 ralloc_free(batch->exec_fences.mem_ctx);
520
521 pipe_resource_reference(&batch->fine_fences.ref.res, NULL);
522
523 util_dynarray_foreach(&batch->syncobjs, struct iris_syncobj *, s)
524 iris_syncobj_reference(bufmgr, s, NULL);
525 ralloc_free(batch->syncobjs.mem_ctx);
526
527 iris_fine_fence_reference(batch->screen, &batch->last_fence, NULL);
528 u_upload_destroy(batch->fine_fences.uploader);
529
530 iris_bo_unreference(batch->bo);
531 batch->bo = NULL;
532 batch->map = NULL;
533 batch->map_next = NULL;
534
535 switch (devinfo->kmd_type) {
536 case INTEL_KMD_TYPE_I915:
537 iris_i915_destroy_batch(batch);
538 break;
539 case INTEL_KMD_TYPE_XE:
540 iris_xe_destroy_batch(batch);
541 break;
542 default:
543 unreachable("missing");
544 }
545
546 iris_destroy_batch_measure(batch->measure);
547 batch->measure = NULL;
548
549 u_trace_fini(&batch->trace);
550
551 _mesa_hash_table_destroy(batch->bo_aux_modes, NULL);
552
553 if (INTEL_DEBUG(DEBUG_BATCH | DEBUG_BATCH_STATS))
554 intel_batch_decode_ctx_finish(&batch->decoder);
555 }
556
557 void
iris_destroy_batches(struct iris_context * ice)558 iris_destroy_batches(struct iris_context *ice)
559 {
560 iris_foreach_batch(ice, batch)
561 iris_batch_free(ice, batch);
562 }
563
iris_batch_maybe_begin_frame(struct iris_batch * batch)564 void iris_batch_maybe_begin_frame(struct iris_batch *batch)
565 {
566 struct iris_context *ice = batch->ice;
567
568 if (ice->utrace.begin_frame != ice->frame) {
569 trace_intel_begin_frame(&batch->trace, batch);
570 ice->utrace.begin_frame = ice->utrace.end_frame = ice->frame;
571 }
572 }
573
574 /**
575 * If we've chained to a secondary batch, or are getting near to the end,
576 * then flush. This should only be called between draws.
577 */
578 void
iris_batch_maybe_flush(struct iris_batch * batch,unsigned estimate)579 iris_batch_maybe_flush(struct iris_batch *batch, unsigned estimate)
580 {
581 if (batch->bo != batch->exec_bos[0] ||
582 iris_batch_bytes_used(batch) + estimate >= BATCH_SZ) {
583 iris_batch_flush(batch);
584 }
585 }
586
587 static void
record_batch_sizes(struct iris_batch * batch)588 record_batch_sizes(struct iris_batch *batch)
589 {
590 unsigned batch_size = iris_batch_bytes_used(batch);
591
592 VG(VALGRIND_CHECK_MEM_IS_DEFINED(batch->map, batch_size));
593
594 if (batch->bo == batch->exec_bos[0])
595 batch->primary_batch_size = batch_size;
596
597 batch->total_chained_batch_size += batch_size;
598 }
599
600 void
iris_chain_to_new_batch(struct iris_batch * batch)601 iris_chain_to_new_batch(struct iris_batch *batch)
602 {
603 uint32_t *cmd = batch->map_next;
604 uint64_t *addr = batch->map_next + 4;
605 batch->map_next += 12;
606
607 record_batch_sizes(batch);
608
609 /* No longer held by batch->bo, still held by validation list */
610 iris_bo_unreference(batch->bo);
611 create_batch(batch);
612
613 /* Emit MI_BATCH_BUFFER_START to chain to another batch. */
614 *cmd = (0x31 << 23) | (1 << 8) | (3 - 2);
615 *addr = batch->bo->address;
616 }
617
618 static void
add_aux_map_bos_to_batch(struct iris_batch * batch)619 add_aux_map_bos_to_batch(struct iris_batch *batch)
620 {
621 void *aux_map_ctx = iris_bufmgr_get_aux_map_context(batch->screen->bufmgr);
622 if (!aux_map_ctx)
623 return;
624
625 uint32_t count = intel_aux_map_get_num_buffers(aux_map_ctx);
626 ensure_exec_obj_space(batch, count);
627 intel_aux_map_fill_bos(aux_map_ctx,
628 (void**)&batch->exec_bos[batch->exec_count], count);
629 for (uint32_t i = 0; i < count; i++) {
630 struct iris_bo *bo = batch->exec_bos[batch->exec_count];
631 add_bo_to_batch(batch, bo, false);
632 }
633 }
634
635 static void
add_pixel_hash_table_bo_to_batch(struct iris_batch * batch)636 add_pixel_hash_table_bo_to_batch(struct iris_batch *batch)
637 {
638
639 if (batch->ice->state.pixel_hashing_tables &&
640 batch->name == IRIS_BATCH_RENDER) {
641 struct iris_bo *bo = iris_resource_bo(
642 batch->ice->state.pixel_hashing_tables);
643 ensure_exec_obj_space(batch, 1);
644 add_bo_to_batch(batch, bo, false);
645 }
646 }
647
648 static void
finish_seqno(struct iris_batch * batch)649 finish_seqno(struct iris_batch *batch)
650 {
651 struct iris_fine_fence *sq = iris_fine_fence_new(batch);
652 if (!sq)
653 return;
654
655 iris_fine_fence_reference(batch->screen, &batch->last_fence, sq);
656 iris_fine_fence_reference(batch->screen, &sq, NULL);
657 }
658
659 /**
660 * Terminate a batch with MI_BATCH_BUFFER_END.
661 */
662 static void
iris_finish_batch(struct iris_batch * batch)663 iris_finish_batch(struct iris_batch *batch)
664 {
665 const struct intel_device_info *devinfo = batch->screen->devinfo;
666
667 if (devinfo->ver == 12 && batch->name == IRIS_BATCH_RENDER) {
668 /* We re-emit constants at the beginning of every batch as a hardware
669 * bug workaround, so invalidate indirect state pointers in order to
670 * save ourselves the overhead of restoring constants redundantly when
671 * the next render batch is executed.
672 */
673 iris_emit_pipe_control_flush(batch, "ISP invalidate at batch end",
674 PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE |
675 PIPE_CONTROL_STALL_AT_SCOREBOARD |
676 PIPE_CONTROL_CS_STALL);
677 }
678
679 add_aux_map_bos_to_batch(batch);
680 add_pixel_hash_table_bo_to_batch(batch);
681
682 finish_seqno(batch);
683
684 trace_intel_end_batch(&batch->trace, batch->name);
685
686 struct iris_context *ice = batch->ice;
687 if (ice->utrace.end_frame != ice->frame) {
688 trace_intel_end_frame(&batch->trace, batch, ice->utrace.end_frame);
689 ice->utrace.end_frame = ice->frame;
690 }
691
692 /* Emit MI_BATCH_BUFFER_END to finish our batch. */
693 uint32_t *map = batch->map_next;
694
695 map[0] = (0xA << 23);
696
697 batch->map_next += 4;
698
699 record_batch_sizes(batch);
700 }
701
702 /**
703 * Replace our current GEM context with a new one (in case it got banned).
704 */
705 static bool
replace_kernel_ctx(struct iris_batch * batch)706 replace_kernel_ctx(struct iris_batch *batch)
707 {
708 struct iris_screen *screen = batch->screen;
709 struct iris_bufmgr *bufmgr = screen->bufmgr;
710 const struct intel_device_info *devinfo = iris_bufmgr_get_device_info(bufmgr);
711
712 threaded_context_unwrap_sync(&batch->ice->ctx);
713
714 switch (devinfo->kmd_type) {
715 case INTEL_KMD_TYPE_I915:
716 return iris_i915_replace_batch(batch);
717 case INTEL_KMD_TYPE_XE:
718 return iris_xe_replace_batch(batch);
719 default:
720 unreachable("missing");
721 return false;
722 }
723 }
724
725 enum pipe_reset_status
iris_batch_check_for_reset(struct iris_batch * batch)726 iris_batch_check_for_reset(struct iris_batch *batch)
727 {
728 struct iris_screen *screen = batch->screen;
729 struct iris_bufmgr *bufmgr = screen->bufmgr;
730 struct iris_context *ice = batch->ice;
731 const struct iris_kmd_backend *backend;
732 enum pipe_reset_status status = PIPE_NO_RESET;
733
734 /* Banned context was already signalled to application */
735 if (ice->context_reset_signaled)
736 return status;
737
738 backend = iris_bufmgr_get_kernel_driver_backend(bufmgr);
739 status = backend->batch_check_for_reset(batch);
740
741 if (status != PIPE_NO_RESET)
742 ice->context_reset_signaled = true;
743
744 return status;
745 }
746
747 static void
move_syncobj_to_batch(struct iris_batch * batch,struct iris_syncobj ** p_syncobj,uint32_t flags)748 move_syncobj_to_batch(struct iris_batch *batch,
749 struct iris_syncobj **p_syncobj,
750 uint32_t flags)
751 {
752 struct iris_bufmgr *bufmgr = batch->screen->bufmgr;
753
754 if (!*p_syncobj)
755 return;
756
757 bool found = false;
758 util_dynarray_foreach(&batch->syncobjs, struct iris_syncobj *, s) {
759 if (*p_syncobj == *s) {
760 found = true;
761 break;
762 }
763 }
764
765 if (!found)
766 iris_batch_add_syncobj(batch, *p_syncobj, flags);
767
768 iris_syncobj_reference(bufmgr, p_syncobj, NULL);
769 }
770
771 static void
update_bo_syncobjs(struct iris_batch * batch,struct iris_bo * bo,bool write)772 update_bo_syncobjs(struct iris_batch *batch, struct iris_bo *bo, bool write)
773 {
774 struct iris_screen *screen = batch->screen;
775 struct iris_bufmgr *bufmgr = screen->bufmgr;
776 struct iris_context *ice = batch->ice;
777
778 simple_mtx_assert_locked(iris_bufmgr_get_bo_deps_lock(bufmgr));
779
780 /* Make sure bo->deps is big enough */
781 if (screen->id >= bo->deps_size) {
782 int new_size = screen->id + 1;
783 bo->deps = realloc(bo->deps, new_size * sizeof(bo->deps[0]));
784 assert(bo->deps);
785 memset(&bo->deps[bo->deps_size], 0,
786 sizeof(bo->deps[0]) * (new_size - bo->deps_size));
787
788 bo->deps_size = new_size;
789 }
790
791 /* When it comes to execbuf submission of non-shared buffers, we only need
792 * to care about the reads and writes done by the other batches of our own
793 * screen, and we also don't care about the reads and writes done by our
794 * own batch, although we need to track them. Just note that other places of
795 * our code may need to care about all the operations done by every batch
796 * on every screen.
797 */
798 struct iris_bo_screen_deps *bo_deps = &bo->deps[screen->id];
799 int batch_idx = batch->name;
800
801 /* Make our batch depend on additional syncobjs depending on what other
802 * batches have been doing to this bo.
803 *
804 * We also look at the dependencies set by our own batch since those could
805 * have come from a different context, and apps don't like it when we don't
806 * do inter-context tracking.
807 */
808 iris_foreach_batch(ice, batch_i) {
809 unsigned i = batch_i->name;
810
811 /* If the bo is being written to by others, wait for them. */
812 if (bo_deps->write_syncobjs[i])
813 move_syncobj_to_batch(batch, &bo_deps->write_syncobjs[i],
814 IRIS_BATCH_FENCE_WAIT);
815
816 /* If we're writing to the bo, wait on the reads from other batches. */
817 if (write)
818 move_syncobj_to_batch(batch, &bo_deps->read_syncobjs[i],
819 IRIS_BATCH_FENCE_WAIT);
820 }
821
822 struct iris_syncobj *batch_syncobj =
823 iris_batch_get_signal_syncobj(batch);
824
825 /* Update bo_deps depending on what we're doing with the bo in this batch
826 * by putting the batch's syncobj in the bo_deps lists accordingly. Only
827 * keep track of the last time we wrote to or read the BO.
828 */
829 if (write) {
830 iris_syncobj_reference(bufmgr, &bo_deps->write_syncobjs[batch_idx],
831 batch_syncobj);
832 } else {
833 iris_syncobj_reference(bufmgr, &bo_deps->read_syncobjs[batch_idx],
834 batch_syncobj);
835 }
836 }
837
838 void
iris_batch_update_syncobjs(struct iris_batch * batch)839 iris_batch_update_syncobjs(struct iris_batch *batch)
840 {
841 for (int i = 0; i < batch->exec_count; i++) {
842 struct iris_bo *bo = batch->exec_bos[i];
843 bool write = BITSET_TEST(batch->bos_written, i);
844
845 if (bo == batch->screen->workaround_bo)
846 continue;
847
848 update_bo_syncobjs(batch, bo, write);
849 }
850 }
851
852 /**
853 * Convert the syncobj which will be signaled when this batch completes
854 * to a SYNC_FILE object, for use with import/export sync ioctls.
855 */
856 bool
iris_batch_syncobj_to_sync_file_fd(struct iris_batch * batch,int * out_fd)857 iris_batch_syncobj_to_sync_file_fd(struct iris_batch *batch, int *out_fd)
858 {
859 int drm_fd = batch->screen->fd;
860
861 struct iris_syncobj *batch_syncobj =
862 iris_batch_get_signal_syncobj(batch);
863
864 struct drm_syncobj_handle syncobj_to_fd_ioctl = {
865 .handle = batch_syncobj->handle,
866 .flags = DRM_SYNCOBJ_HANDLE_TO_FD_FLAGS_EXPORT_SYNC_FILE,
867 .fd = -1,
868 };
869 if (intel_ioctl(drm_fd, DRM_IOCTL_SYNCOBJ_HANDLE_TO_FD,
870 &syncobj_to_fd_ioctl)) {
871 fprintf(stderr, "DRM_IOCTL_SYNCOBJ_HANDLE_TO_FD ioctl failed (%d)\n",
872 errno);
873 return false;
874 }
875
876 assert(syncobj_to_fd_ioctl.fd >= 0);
877 *out_fd = syncobj_to_fd_ioctl.fd;
878
879 return true;
880 }
881
882 const char *
iris_batch_name_to_string(enum iris_batch_name name)883 iris_batch_name_to_string(enum iris_batch_name name)
884 {
885 const char *names[IRIS_BATCH_COUNT] = {
886 [IRIS_BATCH_RENDER] = "render",
887 [IRIS_BATCH_COMPUTE] = "compute",
888 [IRIS_BATCH_BLITTER] = "blitter",
889 };
890 return names[name];
891 }
892
893 bool
iris_batch_is_banned(struct iris_bufmgr * bufmgr,int ret)894 iris_batch_is_banned(struct iris_bufmgr *bufmgr, int ret)
895 {
896 enum intel_kmd_type kmd_type = iris_bufmgr_get_device_info(bufmgr)->kmd_type;
897
898 assert(ret < 0);
899 /* In i915 EIO means our context is banned, while on Xe ECANCELED means
900 * our exec queue was banned
901 */
902 if ((kmd_type == INTEL_KMD_TYPE_I915 && ret == -EIO) ||
903 (kmd_type == INTEL_KMD_TYPE_XE && ret == -ECANCELED))
904 return true;
905
906 return false;
907 }
908
909 /**
910 * Flush the batch buffer, submitting it to the GPU and resetting it so
911 * we're ready to emit the next batch.
912 */
913 void
_iris_batch_flush(struct iris_batch * batch,const char * file,int line)914 _iris_batch_flush(struct iris_batch *batch, const char *file, int line)
915 {
916 struct iris_screen *screen = batch->screen;
917 struct iris_context *ice = batch->ice;
918 struct iris_bufmgr *bufmgr = screen->bufmgr;
919
920 /* If a fence signals we need to flush it. */
921 if (iris_batch_bytes_used(batch) == 0 && !batch->contains_fence_signal)
922 return;
923
924 iris_measure_batch_end(ice, batch);
925
926 iris_finish_batch(batch);
927
928 if (INTEL_DEBUG(DEBUG_BATCH | DEBUG_SUBMIT | DEBUG_PIPE_CONTROL)) {
929 const char *basefile = strstr(file, "iris/");
930 if (basefile)
931 file = basefile + 5;
932
933 enum intel_kmd_type kmd_type = iris_bufmgr_get_device_info(bufmgr)->kmd_type;
934 uint32_t batch_ctx_id = kmd_type == INTEL_KMD_TYPE_I915 ?
935 batch->i915.ctx_id : batch->xe.exec_queue_id;
936 fprintf(stderr, "%19s:%-3d: %s batch [%u] flush with %5db (%0.1f%%) "
937 "(cmds), %4d BOs (%0.1fMb aperture)\n",
938 file, line, iris_batch_name_to_string(batch->name),
939 batch_ctx_id, batch->total_chained_batch_size,
940 100.0f * batch->total_chained_batch_size / BATCH_SZ,
941 batch->exec_count,
942 (float) batch->aperture_space / (1024 * 1024));
943
944 }
945
946 uint64_t start_ts = intel_ds_begin_submit(&batch->ds);
947 uint64_t submission_id = batch->ds.submission_id;
948 int ret = iris_bufmgr_get_kernel_driver_backend(bufmgr)->batch_submit(batch);
949 intel_ds_end_submit(&batch->ds, start_ts);
950
951 /* When batch submission fails, our end-of-batch syncobj remains
952 * unsignalled, and in fact is not even considered submitted.
953 *
954 * In the hang recovery case (-EIO) or -ENOMEM, we recreate our context and
955 * attempt to carry on. In that case, we need to signal our syncobj,
956 * dubiously claiming that this batch completed, because future batches may
957 * depend on it. If we don't, then execbuf would fail with -EINVAL for
958 * those batches, because they depend on a syncobj that's considered to be
959 * "never submitted". This would lead to an abort(). So here, we signal
960 * the failing batch's syncobj to try and allow further progress to be
961 * made, knowing we may have broken our dependency tracking.
962 */
963 if (ret < 0)
964 iris_syncobj_signal(screen->bufmgr, iris_batch_get_signal_syncobj(batch));
965
966 batch->exec_count = 0;
967 batch->max_gem_handle = 0;
968 batch->aperture_space = 0;
969
970 util_dynarray_foreach(&batch->syncobjs, struct iris_syncobj *, s)
971 iris_syncobj_reference(screen->bufmgr, s, NULL);
972 util_dynarray_clear(&batch->syncobjs);
973
974 util_dynarray_clear(&batch->exec_fences);
975
976 if (INTEL_DEBUG(DEBUG_SYNC)) {
977 dbg_printf("waiting for idle\n");
978 iris_bo_wait_rendering(batch->bo); /* if execbuf failed; this is a nop */
979 }
980
981 if (u_trace_should_process(&ice->ds.trace_context))
982 iris_utrace_flush(batch, submission_id);
983
984 /* Start a new batch buffer. */
985 iris_batch_reset(batch);
986
987 /* Check if context or engine was banned, if yes try to replace it
988 * with a new logical context, and inform iris_context that all state
989 * has been lost and needs to be re-initialized. If this succeeds,
990 * dubiously claim success...
991 */
992 if (ret && iris_batch_is_banned(bufmgr, ret)) {
993 enum pipe_reset_status status = iris_batch_check_for_reset(batch);
994
995 if (status != PIPE_NO_RESET || ice->context_reset_signaled)
996 replace_kernel_ctx(batch);
997
998 if (batch->reset->reset) {
999 /* Tell gallium frontends the device is lost and it was our fault. */
1000 batch->reset->reset(batch->reset->data, status);
1001 }
1002
1003 ret = 0;
1004 }
1005
1006 if (ret < 0) {
1007 #if MESA_DEBUG
1008 const bool color = INTEL_DEBUG(DEBUG_COLOR);
1009 fprintf(stderr, "%siris: Failed to submit batchbuffer: %-80s%s\n",
1010 color ? "\e[1;41m" : "", strerror(-ret), color ? "\e[0m" : "");
1011 #endif
1012 abort();
1013 }
1014 }
1015
1016 /**
1017 * Does the current batch refer to the given BO?
1018 *
1019 * (In other words, is the BO in the current batch's validation list?)
1020 */
1021 bool
iris_batch_references(struct iris_batch * batch,struct iris_bo * bo)1022 iris_batch_references(struct iris_batch *batch, struct iris_bo *bo)
1023 {
1024 return find_exec_index(batch, bo) != -1;
1025 }
1026
1027 /**
1028 * Updates the state of the noop feature. Returns true if there was a noop
1029 * transition that led to state invalidation.
1030 */
1031 bool
iris_batch_prepare_noop(struct iris_batch * batch,bool noop_enable)1032 iris_batch_prepare_noop(struct iris_batch *batch, bool noop_enable)
1033 {
1034 if (batch->noop_enabled == noop_enable)
1035 return 0;
1036
1037 batch->noop_enabled = noop_enable;
1038
1039 iris_batch_flush(batch);
1040
1041 /* If the batch was empty, flush had no effect, so insert our noop. */
1042 if (iris_batch_bytes_used(batch) == 0)
1043 iris_batch_maybe_noop(batch);
1044
1045 /* We only need to update the entire state if we transition from noop ->
1046 * not-noop.
1047 */
1048 return !batch->noop_enabled;
1049 }
1050