1 /*
2 * Copyright 2009 Nicolai Hähnle <nhaehnle@gmail.com>
3 * SPDX-License-Identifier: MIT
4 */
5
6 #include "r300_reg.h"
7 #include "radeon_code.h"
8 #include "radeon_compiler.h"
9
10 #include <stdio.h>
11
12 static const char *r300_vs_ve_ops[] = {
13 /* R300 vector ops */
14 " VE_NO_OP",
15 " VE_DOT_PRODUCT",
16 " VE_MULTIPLY",
17 " VE_ADD",
18 " VE_MULTIPLY_ADD",
19 " VE_DISTANCE_FACTOR",
20 " VE_FRACTION",
21 " VE_MAXIMUM",
22 " VE_MINIMUM",
23 "VE_SET_GREATER_THAN_EQUAL",
24 " VE_SET_LESS_THAN",
25 " VE_MULTIPLYX2_ADD",
26 " VE_MULTIPLY_CLAMP",
27 " VE_FLT2FIX_DX",
28 " VE_FLT2FIX_DX_RND",
29 /* R500 vector ops */
30 " VE_PRED_SET_EQ_PUSH",
31 " VE_PRED_SET_GT_PUSH",
32 " VE_PRED_SET_GTE_PUSH",
33 " VE_PRED_SET_NEQ_PUSH",
34 " VE_COND_WRITE_EQ",
35 " VE_COND_WRITE_GT",
36 " VE_COND_WRITE_GTE",
37 " VE_COND_WRITE_NEQ",
38 " VE_COND_MUX_EQ",
39 " VE_COND_MUX_GT",
40 " VE_COND_MUX_GTE",
41 " VE_SET_GREATER_THAN",
42 " VE_SET_EQUAL",
43 " VE_SET_NOT_EQUAL",
44 " (reserved)",
45 " (reserved)",
46 " (reserved)",
47 };
48
49 static const char *r300_vs_me_ops[] = {
50 /* R300 math ops */
51 " ME_NO_OP",
52 " ME_EXP_BASE2_DX",
53 " ME_LOG_BASE2_DX",
54 " ME_EXP_BASEE_FF",
55 " ME_LIGHT_COEFF_DX",
56 " ME_POWER_FUNC_FF",
57 " ME_RECIP_DX",
58 " ME_RECIP_FF",
59 " ME_RECIP_SQRT_DX",
60 " ME_RECIP_SQRT_FF",
61 " ME_MULTIPLY",
62 " ME_EXP_BASE2_FULL_DX",
63 " ME_LOG_BASE2_FULL_DX",
64 " ME_POWER_FUNC_FF_CLAMP_B",
65 "ME_POWER_FUNC_FF_CLAMP_B1",
66 "ME_POWER_FUNC_FF_CLAMP_01",
67 " ME_SIN",
68 " ME_COS",
69 /* R500 math ops */
70 " ME_LOG_BASE2_IEEE",
71 " ME_RECIP_IEEE",
72 " ME_RECIP_SQRT_IEEE",
73 " ME_PRED_SET_EQ",
74 " ME_PRED_SET_GT",
75 " ME_PRED_SET_GTE",
76 " ME_PRED_SET_NEQ",
77 " ME_PRED_SET_CLR",
78 " ME_PRED_SET_INV",
79 " ME_PRED_SET_POP",
80 " ME_PRED_SET_RESTORE",
81 " (reserved)",
82 " (reserved)",
83 " (reserved)",
84 };
85
86 /* XXX refactor to avoid clashing symbols */
87 static const char *r300_vs_src_debug[] = {
88 "t",
89 "i",
90 "c",
91 "a",
92 };
93
94 static const char *r300_vs_dst_debug[] = {
95 "t",
96 "a0",
97 "o",
98 "ox",
99 "a",
100 "i",
101 "u",
102 "u",
103 };
104
105 static const char *r300_vs_swiz_debug[] = {
106 "X",
107 "Y",
108 "Z",
109 "W",
110 "0",
111 "1",
112 "U",
113 "U",
114 };
115
116 static void
r300_vs_op_dump(uint32_t op)117 r300_vs_op_dump(uint32_t op)
118 {
119 fprintf(stderr, " dst: %d%s op: ", (op >> 13) & 0x7f, r300_vs_dst_debug[(op >> 8) & 0x7]);
120 if ((op >> PVS_DST_PRED_ENABLE_SHIFT) & 0x1) {
121 fprintf(stderr, "PRED %u", (op >> PVS_DST_PRED_SENSE_SHIFT) & 0x1);
122 }
123 if (op & 0x80) {
124 if (op & 0x1) {
125 fprintf(stderr, "PVS_MACRO_OP_2CLK_M2X_ADD\n");
126 } else {
127 fprintf(stderr, " PVS_MACRO_OP_2CLK_MADD\n");
128 }
129 } else if (op & 0x40) {
130 fprintf(stderr, "%s\n", r300_vs_me_ops[op & 0x1f]);
131 } else {
132 fprintf(stderr, "%s\n", r300_vs_ve_ops[op & 0x1f]);
133 }
134 }
135
136 static void
r300_vs_src_dump(uint32_t src)137 r300_vs_src_dump(uint32_t src)
138 {
139 fprintf(stderr, " reg: %d%s swiz: %s%s/%s%s/%s%s/%s%s\n", (src >> 5) & 0xff,
140 r300_vs_src_debug[src & 0x3], src & (1 << 25) ? "-" : " ",
141 r300_vs_swiz_debug[(src >> 13) & 0x7], src & (1 << 26) ? "-" : " ",
142 r300_vs_swiz_debug[(src >> 16) & 0x7], src & (1 << 27) ? "-" : " ",
143 r300_vs_swiz_debug[(src >> 19) & 0x7], src & (1 << 28) ? "-" : " ",
144 r300_vs_swiz_debug[(src >> 22) & 0x7]);
145 }
146
147 void
r300_vertex_program_dump(struct radeon_compiler * compiler,void * user)148 r300_vertex_program_dump(struct radeon_compiler *compiler, void *user)
149 {
150 struct r300_vertex_program_compiler *c = (struct r300_vertex_program_compiler *)compiler;
151 struct r300_vertex_program_code *vs = c->code;
152 unsigned instrcount = vs->length / 4;
153 unsigned i;
154
155 fprintf(stderr, "Final vertex program code:\n");
156
157 for (i = 0; i < instrcount; i++) {
158 unsigned offset = i * 4;
159 unsigned src;
160
161 fprintf(stderr, "%d: op: 0x%08x", i, vs->body.d[offset]);
162 r300_vs_op_dump(vs->body.d[offset]);
163
164 for (src = 0; src < 3; ++src) {
165 fprintf(stderr, " src%i: 0x%08x", src, vs->body.d[offset + 1 + src]);
166 r300_vs_src_dump(vs->body.d[offset + 1 + src]);
167 }
168 }
169
170 fprintf(stderr, "Flow Control Ops: 0x%08x\n", vs->fc_ops);
171 for (i = 0; i < vs->num_fc_ops; i++) {
172 unsigned is_loop = 0;
173 switch ((vs->fc_ops >> (i * 2)) & 0x3) {
174 case 0:
175 fprintf(stderr, "NOP");
176 break;
177 case 1:
178 fprintf(stderr, "JUMP");
179 break;
180 case 2:
181 fprintf(stderr, "LOOP");
182 is_loop = 1;
183 break;
184 case 3:
185 fprintf(stderr, "JSR");
186 break;
187 }
188 if (c->Base.is_r500) {
189 fprintf(stderr,
190 ": uw-> 0x%08x lw-> 0x%08x "
191 "loop data->0x%08x\n",
192 vs->fc_op_addrs.r500[i].uw, vs->fc_op_addrs.r500[i].lw, vs->fc_loop_index[i]);
193 if (is_loop) {
194 fprintf(
195 stderr, "Before = %u First = %u Last = %u\n", vs->fc_op_addrs.r500[i].lw & 0xffff,
196 (vs->fc_op_addrs.r500[i].uw >> 16) & 0xffff, vs->fc_op_addrs.r500[i].uw & 0xffff);
197 }
198 } else {
199 fprintf(stderr, ": 0x%08x\n", vs->fc_op_addrs.r300[i]);
200 }
201 }
202 }
203