1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * SPDX-License-Identifier: MIT
4 */
5
6 #include "r600_pipe.h"
7 #include "r600_public.h"
8 #include "r600_isa.h"
9 #include "r600_sfn.h"
10 #include "evergreen_compute.h"
11 #include "r600d.h"
12
13 #include <errno.h>
14 #include "pipe/p_shader_tokens.h"
15 #include "util/u_debug.h"
16 #include "util/u_endian.h"
17 #include "util/u_memory.h"
18 #include "util/u_screen.h"
19 #include "util/u_simple_shaders.h"
20 #include "util/u_upload_mgr.h"
21 #include "util/u_math.h"
22 #include "vl/vl_decoder.h"
23 #include "vl/vl_video_buffer.h"
24 #include "radeon_video.h"
25 #include "radeon_uvd.h"
26 #include "util/os_time.h"
27
28 static const struct debug_named_value r600_debug_options[] = {
29 /* features */
30 { "nocpdma", DBG_NO_CP_DMA, "Disable CP DMA" },
31
32 DEBUG_NAMED_VALUE_END /* must be last */
33 };
34
35 /*
36 * pipe_context
37 */
38
r600_destroy_context(struct pipe_context * context)39 static void r600_destroy_context(struct pipe_context *context)
40 {
41 struct r600_context *rctx = (struct r600_context *)context;
42 unsigned sh, i;
43
44 r600_isa_destroy(rctx->isa);
45
46 for (sh = 0; sh < (rctx->b.gfx_level < EVERGREEN ? R600_NUM_HW_STAGES : EG_NUM_HW_STAGES); sh++) {
47 r600_resource_reference(&rctx->scratch_buffers[sh].buffer, NULL);
48 }
49 r600_resource_reference(&rctx->dummy_cmask, NULL);
50 r600_resource_reference(&rctx->dummy_fmask, NULL);
51
52 if (rctx->append_fence)
53 pipe_resource_reference((struct pipe_resource**)&rctx->append_fence, NULL);
54 for (sh = 0; sh < PIPE_SHADER_TYPES; sh++) {
55 rctx->b.b.set_constant_buffer(&rctx->b.b, sh, R600_BUFFER_INFO_CONST_BUFFER, false, NULL);
56 free(rctx->driver_consts[sh].constants);
57 }
58
59 if (rctx->fixed_func_tcs_shader)
60 rctx->b.b.delete_tcs_state(&rctx->b.b, rctx->fixed_func_tcs_shader);
61
62 if (rctx->dummy_pixel_shader) {
63 rctx->b.b.delete_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
64 }
65 if (rctx->custom_dsa_flush) {
66 rctx->b.b.delete_depth_stencil_alpha_state(&rctx->b.b, rctx->custom_dsa_flush);
67 }
68 if (rctx->custom_blend_resolve) {
69 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_resolve);
70 }
71 if (rctx->custom_blend_decompress) {
72 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_decompress);
73 }
74 if (rctx->custom_blend_fastclear) {
75 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_fastclear);
76 }
77 util_unreference_framebuffer_state(&rctx->framebuffer.state);
78
79 if (rctx->gs_rings.gsvs_ring.buffer)
80 pipe_resource_reference(&rctx->gs_rings.gsvs_ring.buffer, NULL);
81
82 if (rctx->gs_rings.esgs_ring.buffer)
83 pipe_resource_reference(&rctx->gs_rings.esgs_ring.buffer, NULL);
84
85 for (sh = 0; sh < PIPE_SHADER_TYPES; ++sh)
86 for (i = 0; i < PIPE_MAX_CONSTANT_BUFFERS; ++i)
87 rctx->b.b.set_constant_buffer(context, sh, i, false, NULL);
88
89 if (rctx->blitter) {
90 util_blitter_destroy(rctx->blitter);
91 }
92 u_suballocator_destroy(&rctx->allocator_fetch_shader);
93
94 r600_release_command_buffer(&rctx->start_cs_cmd);
95
96 FREE(rctx->start_compute_cs_cmd.buf);
97
98 r600_common_context_cleanup(&rctx->b);
99
100 r600_resource_reference(&rctx->trace_buf, NULL);
101 r600_resource_reference(&rctx->last_trace_buf, NULL);
102 radeon_clear_saved_cs(&rctx->last_gfx);
103
104 switch (rctx->b.gfx_level) {
105 case EVERGREEN:
106 case CAYMAN:
107 for (i = 0; i < EG_MAX_ATOMIC_BUFFERS; ++i)
108 pipe_resource_reference(&rctx->atomic_buffer_state.buffer[i].buffer, NULL);
109 break;
110 default:
111 break;
112 }
113
114 FREE(rctx);
115 }
116
r600_create_context(struct pipe_screen * screen,void * priv,unsigned flags)117 static struct pipe_context *r600_create_context(struct pipe_screen *screen,
118 void *priv, unsigned flags)
119 {
120 struct r600_context *rctx = CALLOC_STRUCT(r600_context);
121 struct r600_screen* rscreen = (struct r600_screen *)screen;
122 struct radeon_winsys *ws = rscreen->b.ws;
123
124 if (!rctx)
125 return NULL;
126
127 rctx->b.b.screen = screen;
128 assert(!priv);
129 rctx->b.b.priv = NULL; /* for threaded_context_unwrap_sync */
130 rctx->b.b.destroy = r600_destroy_context;
131 rctx->b.set_atom_dirty = (void *)r600_set_atom_dirty;
132
133 if (!r600_common_context_init(&rctx->b, &rscreen->b, flags))
134 goto fail;
135
136 rctx->screen = rscreen;
137 list_inithead(&rctx->texture_buffers);
138
139 r600_init_blit_functions(rctx);
140
141 if (rscreen->b.info.ip[AMD_IP_UVD].num_queues) {
142 rctx->b.b.create_video_codec = r600_uvd_create_decoder;
143 rctx->b.b.create_video_buffer = r600_video_buffer_create;
144 } else {
145 rctx->b.b.create_video_codec = vl_create_decoder;
146 rctx->b.b.create_video_buffer = vl_video_buffer_create;
147 }
148
149 if (getenv("R600_TRACE"))
150 rctx->is_debug = true;
151 r600_init_common_state_functions(rctx);
152
153 switch (rctx->b.gfx_level) {
154 case R600:
155 case R700:
156 r600_init_state_functions(rctx);
157 r600_init_atom_start_cs(rctx);
158 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
159 rctx->custom_blend_resolve = rctx->b.gfx_level == R700 ? r700_create_resolve_blend(rctx)
160 : r600_create_resolve_blend(rctx);
161 rctx->custom_blend_decompress = r600_create_decompress_blend(rctx);
162 rctx->has_vertex_cache = !(rctx->b.family == CHIP_RV610 ||
163 rctx->b.family == CHIP_RV620 ||
164 rctx->b.family == CHIP_RS780 ||
165 rctx->b.family == CHIP_RS880 ||
166 rctx->b.family == CHIP_RV710);
167 break;
168 case EVERGREEN:
169 case CAYMAN:
170 evergreen_init_state_functions(rctx);
171 evergreen_init_atom_start_cs(rctx);
172 evergreen_init_atom_start_compute_cs(rctx);
173 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
174 rctx->custom_blend_resolve = evergreen_create_resolve_blend(rctx);
175 rctx->custom_blend_decompress = evergreen_create_decompress_blend(rctx);
176 rctx->custom_blend_fastclear = evergreen_create_fastclear_blend(rctx);
177 rctx->has_vertex_cache = !(rctx->b.family == CHIP_CEDAR ||
178 rctx->b.family == CHIP_PALM ||
179 rctx->b.family == CHIP_SUMO ||
180 rctx->b.family == CHIP_SUMO2 ||
181 rctx->b.family == CHIP_CAICOS ||
182 rctx->b.family == CHIP_CAYMAN ||
183 rctx->b.family == CHIP_ARUBA);
184
185 rctx->append_fence = pipe_buffer_create(rctx->b.b.screen, PIPE_BIND_CUSTOM,
186 PIPE_USAGE_DEFAULT, 32);
187 break;
188 default:
189 R600_ERR("Unsupported gfx level %d.\n", rctx->b.gfx_level);
190 goto fail;
191 }
192
193 ws->cs_create(&rctx->b.gfx.cs, rctx->b.ctx, AMD_IP_GFX,
194 r600_context_gfx_flush, rctx);
195 rctx->b.gfx.flush = r600_context_gfx_flush;
196
197 u_suballocator_init(&rctx->allocator_fetch_shader, &rctx->b.b, 64 * 1024,
198 0, PIPE_USAGE_DEFAULT, 0, false);
199
200 rctx->isa = calloc(1, sizeof(struct r600_isa));
201 if (!rctx->isa || r600_isa_init(rctx->b.gfx_level, rctx->isa))
202 goto fail;
203
204 if (rscreen->b.debug_flags & DBG_FORCE_DMA)
205 rctx->b.b.resource_copy_region = rctx->b.dma_copy;
206
207 rctx->blitter = util_blitter_create(&rctx->b.b);
208 if (rctx->blitter == NULL)
209 goto fail;
210 util_blitter_set_texture_multisample(rctx->blitter, rscreen->has_msaa);
211 rctx->blitter->draw_rectangle = r600_draw_rectangle;
212
213 r600_begin_new_cs(rctx);
214
215 rctx->dummy_pixel_shader =
216 util_make_fragment_cloneinput_shader(&rctx->b.b, 0,
217 TGSI_SEMANTIC_GENERIC,
218 TGSI_INTERPOLATE_CONSTANT);
219 rctx->b.b.bind_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
220
221 return &rctx->b.b;
222
223 fail:
224 r600_destroy_context(&rctx->b.b);
225 return NULL;
226 }
227
228 /*
229 * pipe_screen
230 */
231
r600_get_shader_param(struct pipe_screen * pscreen,enum pipe_shader_type shader,enum pipe_shader_cap param)232 static int r600_get_shader_param(struct pipe_screen* pscreen,
233 enum pipe_shader_type shader,
234 enum pipe_shader_cap param)
235 {
236 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
237
238 switch(shader)
239 {
240 case PIPE_SHADER_FRAGMENT:
241 case PIPE_SHADER_VERTEX:
242 break;
243 case PIPE_SHADER_GEOMETRY:
244 break;
245 case PIPE_SHADER_TESS_CTRL:
246 case PIPE_SHADER_TESS_EVAL:
247 case PIPE_SHADER_COMPUTE:
248 if (rscreen->b.family >= CHIP_CEDAR)
249 break;
250 FALLTHROUGH;
251 default:
252 return 0;
253 }
254
255 switch (param) {
256 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
257 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
258 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
259 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
260 return 16384;
261 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
262 return 32;
263 case PIPE_SHADER_CAP_MAX_INPUTS:
264 return shader == PIPE_SHADER_VERTEX ? 16 : 32;
265 case PIPE_SHADER_CAP_MAX_OUTPUTS:
266 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
267 case PIPE_SHADER_CAP_MAX_TEMPS:
268 return 256; /* Max native temporaries. */
269 case PIPE_SHADER_CAP_MAX_CONST_BUFFER0_SIZE:
270 if (shader == PIPE_SHADER_COMPUTE) {
271 uint64_t max_const_buffer_size;
272 pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_NIR,
273 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
274 &max_const_buffer_size);
275 return MIN2(max_const_buffer_size, INT_MAX);
276
277 } else {
278 return R600_MAX_CONST_BUFFER_SIZE;
279 }
280 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
281 return R600_MAX_USER_CONST_BUFFERS;
282 case PIPE_SHADER_CAP_CONT_SUPPORTED:
283 return 1;
284 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
285 return 1;
286 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
287 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
288 return 1;
289 case PIPE_SHADER_CAP_SUBROUTINES:
290 case PIPE_SHADER_CAP_INT64_ATOMICS:
291 case PIPE_SHADER_CAP_FP16:
292 case PIPE_SHADER_CAP_FP16_DERIVATIVES:
293 case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:
294 case PIPE_SHADER_CAP_INT16:
295 case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
296 return 0;
297 case PIPE_SHADER_CAP_INTEGERS:
298 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
299 return 1;
300 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
301 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
302 return 16;
303 case PIPE_SHADER_CAP_SUPPORTED_IRS: {
304 int ir = 0;
305 if (shader == PIPE_SHADER_COMPUTE)
306 ir = 1 << PIPE_SHADER_IR_NATIVE;
307 ir |= 1 << PIPE_SHADER_IR_NIR;
308 return ir;
309 }
310 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
311 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
312 if (rscreen->b.family >= CHIP_CEDAR &&
313 (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE))
314 return 8;
315 return 0;
316 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
317 if (rscreen->b.family >= CHIP_CEDAR && rscreen->has_atomics)
318 return 8;
319 return 0;
320 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
321 /* having to allocate the atomics out amongst shaders stages is messy,
322 so give compute 8 buffers and all the others one */
323 if (rscreen->b.family >= CHIP_CEDAR && rscreen->has_atomics) {
324 return EG_MAX_ATOMIC_BUFFERS;
325 }
326 return 0;
327 }
328 return 0;
329 }
330
r600_init_screen_caps(struct r600_screen * rscreen)331 static void r600_init_screen_caps(struct r600_screen *rscreen)
332 {
333 struct pipe_caps *caps = (struct pipe_caps *)&rscreen->b.b.caps;
334
335 u_init_pipe_screen_caps(&rscreen->b.b, 1);
336
337 enum radeon_family family = rscreen->b.family;
338
339 /* Supported features (boolean caps). */
340 caps->npot_textures = true;
341 caps->mixed_framebuffer_sizes = true;
342 caps->mixed_color_depth_bits = true;
343 caps->anisotropic_filter = true;
344 caps->occlusion_query = true;
345 caps->texture_mirror_clamp = true;
346 caps->texture_mirror_clamp_to_edge = true;
347 caps->blend_equation_separate = true;
348 caps->texture_swizzle = true;
349 caps->depth_clip_disable = true;
350 caps->depth_clip_disable_separate = true;
351 caps->shader_stencil_export = true;
352 caps->vertex_element_instance_divisor = true;
353 caps->fs_coord_origin_upper_left = true;
354 caps->fs_coord_pixel_center_half_integer = true;
355 caps->fragment_shader_texture_lod = true;
356 caps->fragment_shader_derivatives = true;
357 caps->seamless_cube_map = true;
358 caps->primitive_restart = true;
359 caps->primitive_restart_fixed_index = true;
360 caps->conditional_render = true;
361 caps->texture_barrier = true;
362 caps->vertex_color_unclamped = true;
363 caps->quads_follow_provoking_vertex_convention = true;
364 caps->vs_instanceid = true;
365 caps->start_instance = true;
366 caps->max_dual_source_render_targets = true;
367 caps->texture_buffer_objects = true;
368 caps->query_pipeline_statistics = true;
369 caps->texture_multisample = true;
370 caps->vs_window_space_position = true;
371 caps->vs_layer_viewport = true;
372 caps->sample_shading = true;
373 caps->memobj = true;
374 caps->clip_halfz = true;
375 caps->polygon_offset_clamp = true;
376 caps->conditional_render_inverted = true;
377 caps->texture_float_linear = true;
378 caps->texture_half_float_linear = true;
379 caps->texture_query_samples = true;
380 caps->copy_between_compressed_and_plain_formats = true;
381 caps->invalidate_buffer = true;
382 caps->surface_reinterpret_blocks = true;
383 caps->query_memory_info = true;
384 caps->framebuffer_no_attachment = true;
385 caps->polygon_offset_units_unscaled = true;
386 caps->legacy_math_rules = true;
387 caps->can_bind_const_buffer_as_vertex = true;
388 caps->allow_mapped_buffers_during_execution = true;
389 caps->robust_buffer_access_behavior = true;
390
391 caps->vertex_input_alignment = PIPE_VERTEX_INPUT_ALIGNMENT_4BYTE;
392
393 caps->nir_atomics_as_deref = true;
394 caps->gl_spirv = true;
395
396 caps->texture_transfer_modes = PIPE_TEXTURE_TRANSFER_BLIT;
397
398 caps->shareable_shaders = false;
399
400 /* Optimal number for good TexSubImage performance on Polaris10. */
401 caps->max_texture_upload_memory_budget = 64 * 1024 * 1024;
402
403 caps->device_reset_status_query = true;
404
405 caps->resource_from_user_memory =
406 !UTIL_ARCH_BIG_ENDIAN && rscreen->b.info.has_userptr;
407
408 caps->compute = rscreen->b.gfx_level > R700;
409
410 caps->tgsi_texcoord = true;
411
412 caps->nir_images_as_deref = false;
413 caps->fake_sw_msaa = false;
414
415 caps->max_texel_buffer_elements =
416 MIN2(rscreen->b.info.max_heap_size_kb * 1024ull / 4, INT_MAX);
417
418 caps->min_map_buffer_alignment = R600_MAP_BUFFER_ALIGNMENT;
419
420 caps->constant_buffer_offset_alignment = 256;
421
422 caps->texture_buffer_offset_alignment = 4;
423 caps->glsl_feature_level_compatibility =
424 caps->glsl_feature_level = family >= CHIP_CEDAR ? 450 : 330;
425
426 /* Supported except the original R600. */
427 caps->indep_blend_enable =
428 caps->indep_blend_func = family != CHIP_R600; /* R600 doesn't support per-MRT blends */
429
430 /* Supported on Evergreen. */
431 caps->seamless_cube_map_per_texture =
432 caps->cube_map_array =
433 caps->texture_gather_sm5 =
434 caps->texture_query_lod =
435 caps->fs_fine_derivative =
436 caps->sampler_view_target =
437 caps->shader_pack_half_float =
438 caps->shader_clock =
439 caps->shader_array_components =
440 caps->query_buffer_object =
441 caps->image_store_formatted =
442 caps->alpha_to_coverage_dither_control = family >= CHIP_CEDAR;
443 caps->max_texture_gather_components = family >= CHIP_CEDAR ? 4 : 0;
444 /* kernel command checker support is also required */
445 caps->draw_indirect = family >= CHIP_CEDAR;
446
447 caps->buffer_sampler_view_rgba_only = family < CHIP_CEDAR;
448
449 caps->max_combined_shader_output_resources = 8;
450
451 caps->max_gs_invocations = 32;
452
453 /* shader buffer objects */
454 caps->max_shader_buffer_size = 1 << 27;
455 caps->max_combined_shader_buffers = 8;
456
457 caps->int64 =
458 caps->doubles =
459 rscreen->b.family == CHIP_ARUBA ||
460 rscreen->b.family == CHIP_CAYMAN ||
461 rscreen->b.family == CHIP_CYPRESS ||
462 rscreen->b.family == CHIP_HEMLOCK ||
463 rscreen->b.family >= CHIP_CEDAR;
464
465 caps->two_sided_color = false;
466 caps->cull_distance = true;
467
468 caps->shader_buffer_offset_alignment = family >= CHIP_CEDAR ? 256 : 0;
469
470 caps->max_shader_patch_varyings = family >= CHIP_CEDAR ? 30 : 0;
471
472 /* Stream output. */
473 caps->max_stream_output_buffers = rscreen->b.has_streamout ? 4 : 0;
474 caps->stream_output_pause_resume =
475 caps->stream_output_interleave_buffers = rscreen->b.has_streamout;
476 caps->max_stream_output_separate_components =
477 caps->max_stream_output_interleaved_components = 32*4;
478
479 /* Geometry shader output. */
480 caps->max_geometry_output_vertices = 1024;
481 caps->max_geometry_total_output_components = 16384;
482 caps->max_vertex_streams = family >= CHIP_CEDAR ? 4 : 1;
483
484 /* Should be 2047, but 2048 is a requirement for GL 4.4 */
485 caps->max_vertex_attrib_stride = 2048;
486
487 /* Texturing. */
488 caps->max_texture_2d_size = family >= CHIP_CEDAR ? 16384 : 8192;
489 caps->max_texture_cube_levels = family >= CHIP_CEDAR ? 15 : 14;
490 /* textures support 8192, but layered rendering supports 2048 */
491 caps->max_texture_3d_levels = 12;
492 /* textures support 8192, but layered rendering supports 2048 */
493 caps->max_texture_array_layers = 2048;
494
495 /* Render targets. */
496 caps->max_render_targets = 8; /* XXX some r6xx are buggy and can only do 4 */
497
498 caps->max_viewports = R600_MAX_VIEWPORTS;
499 caps->viewport_subpixel_bits =
500 caps->rasterizer_subpixel_bits = 8;
501
502 /* Timer queries, present when the clock frequency is non zero. */
503 caps->query_time_elapsed =
504 caps->query_timestamp = rscreen->b.info.clock_crystal_freq != 0;
505
506 /* Conversion to nanos from cycles per millisecond */
507 caps->timer_resolution = DIV_ROUND_UP(1000000, rscreen->b.info.clock_crystal_freq);
508
509 caps->min_texture_gather_offset =
510 caps->min_texel_offset = -8;
511
512 caps->max_texture_gather_offset =
513 caps->max_texel_offset = 7;
514
515 caps->max_varyings = 32;
516
517 caps->texture_border_color_quirk = PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
518 caps->endianness = PIPE_ENDIAN_LITTLE;
519
520 caps->vendor_id = ATI_VENDOR_ID;
521 caps->device_id = rscreen->b.info.pci_id;
522 caps->video_memory = rscreen->b.info.vram_size_kb >> 10;
523 caps->uma = false;
524 caps->multisample_z_resolve = rscreen->b.gfx_level >= R700;
525 caps->pci_group = rscreen->b.info.pci.domain;
526 caps->pci_bus = rscreen->b.info.pci.bus;
527 caps->pci_device = rscreen->b.info.pci.dev;
528 caps->pci_function = rscreen->b.info.pci.func;
529
530 caps->max_combined_hw_atomic_counters =
531 rscreen->b.family >= CHIP_CEDAR && rscreen->has_atomics ? 8 : 0;
532
533 caps->max_combined_hw_atomic_counter_buffers =
534 rscreen->b.family >= CHIP_CEDAR && rscreen->has_atomics ?
535 EG_MAX_ATOMIC_BUFFERS : 0;
536
537 caps->validate_all_dirty_states = true;
538
539 caps->min_line_width =
540 caps->min_line_width_aa =
541 caps->min_point_size =
542 caps->min_point_size_aa = 1;
543
544 caps->point_size_granularity =
545 caps->line_width_granularity = 0.1;
546
547 caps->max_line_width =
548 caps->max_line_width_aa =
549 caps->max_point_size =
550 caps->max_point_size_aa = 8191.0f;
551 caps->max_texture_anisotropy = 16.0f;
552 caps->max_texture_lod_bias = 16.0f;
553 }
554
r600_destroy_screen(struct pipe_screen * pscreen)555 static void r600_destroy_screen(struct pipe_screen* pscreen)
556 {
557 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
558
559 if (!rscreen)
560 return;
561
562 if (!rscreen->b.ws->unref(rscreen->b.ws))
563 return;
564
565 if (rscreen->global_pool) {
566 compute_memory_pool_delete(rscreen->global_pool);
567 }
568
569 r600_destroy_common_screen(&rscreen->b);
570 }
571
r600_resource_create(struct pipe_screen * screen,const struct pipe_resource * templ)572 static struct pipe_resource *r600_resource_create(struct pipe_screen *screen,
573 const struct pipe_resource *templ)
574 {
575 if (templ->target == PIPE_BUFFER &&
576 (templ->bind & PIPE_BIND_GLOBAL))
577 return r600_compute_global_buffer_create(screen, templ);
578
579 return r600_resource_create_common(screen, templ);
580 }
581
r600_screen_create(struct radeon_winsys * ws,const struct pipe_screen_config * config)582 struct pipe_screen *r600_screen_create(struct radeon_winsys *ws,
583 const struct pipe_screen_config *config)
584 {
585 struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen);
586
587 if (!rscreen) {
588 return NULL;
589 }
590
591 /* Set functions first. */
592 rscreen->b.b.context_create = r600_create_context;
593 rscreen->b.b.destroy = r600_destroy_screen;
594 rscreen->b.b.get_shader_param = r600_get_shader_param;
595 rscreen->b.b.resource_create = r600_resource_create;
596
597 if (!r600_common_screen_init(&rscreen->b, ws)) {
598 FREE(rscreen);
599 return NULL;
600 }
601
602 if (rscreen->b.info.gfx_level >= EVERGREEN) {
603 rscreen->b.b.is_format_supported = evergreen_is_format_supported;
604 } else {
605 rscreen->b.b.is_format_supported = r600_is_format_supported;
606 }
607
608 rscreen->b.debug_flags |= debug_get_flags_option("R600_DEBUG", r600_debug_options, 0);
609 if (debug_get_bool_option("R600_DEBUG_COMPUTE", false))
610 rscreen->b.debug_flags |= DBG_COMPUTE;
611 if (debug_get_bool_option("R600_DUMP_SHADERS", false))
612 rscreen->b.debug_flags |= DBG_ALL_SHADERS | DBG_FS;
613 if (!debug_get_bool_option("R600_HYPERZ", true))
614 rscreen->b.debug_flags |= DBG_NO_HYPERZ;
615
616 if (rscreen->b.family == CHIP_UNKNOWN) {
617 fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->b.info.pci_id);
618 FREE(rscreen);
619 return NULL;
620 }
621
622 rscreen->b.b.finalize_nir = r600_finalize_nir;
623
624 rscreen->b.has_streamout = true;
625
626 rscreen->has_msaa = true;
627
628 /* MSAA support. */
629 switch (rscreen->b.gfx_level) {
630 case R600:
631 case R700:
632 rscreen->has_compressed_msaa_texturing = false;
633 break;
634 case EVERGREEN:
635 rscreen->has_compressed_msaa_texturing = true;
636 break;
637 case CAYMAN:
638 rscreen->has_compressed_msaa_texturing = true;
639 break;
640 default:
641 rscreen->has_compressed_msaa_texturing = false;
642 }
643
644 rscreen->b.has_cp_dma = !(rscreen->b.debug_flags & DBG_NO_CP_DMA);
645
646 rscreen->b.barrier_flags.cp_to_L2 =
647 R600_CONTEXT_INV_VERTEX_CACHE |
648 R600_CONTEXT_INV_TEX_CACHE |
649 R600_CONTEXT_INV_CONST_CACHE;
650 rscreen->b.barrier_flags.compute_to_L2 = R600_CONTEXT_CS_PARTIAL_FLUSH | R600_CONTEXT_FLUSH_AND_INV;
651
652 rscreen->global_pool = compute_memory_pool_new(rscreen);
653
654 rscreen->has_atomics = true;
655
656 r600_init_screen_caps(rscreen);
657
658 /* Create the auxiliary context. This must be done last. */
659 rscreen->b.aux_context = rscreen->b.b.context_create(&rscreen->b.b, NULL, 0);
660
661 #if 0 /* This is for testing whether aux_context and buffer clearing work correctly. */
662 struct pipe_resource templ = {};
663
664 templ.width0 = 4;
665 templ.height0 = 2048;
666 templ.depth0 = 1;
667 templ.array_size = 1;
668 templ.target = PIPE_TEXTURE_2D;
669 templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
670 templ.usage = PIPE_USAGE_DEFAULT;
671
672 struct r600_resource *res = r600_resource(rscreen->screen.resource_create(&rscreen->screen, &templ));
673 unsigned char *map = ws->buffer_map(res->buf, NULL, PIPE_MAP_WRITE);
674
675 memset(map, 0, 256);
676
677 r600_screen_clear_buffer(rscreen, &res->b.b, 4, 4, 0xCC);
678 r600_screen_clear_buffer(rscreen, &res->b.b, 8, 4, 0xDD);
679 r600_screen_clear_buffer(rscreen, &res->b.b, 12, 4, 0xEE);
680 r600_screen_clear_buffer(rscreen, &res->b.b, 20, 4, 0xFF);
681 r600_screen_clear_buffer(rscreen, &res->b.b, 32, 20, 0x87);
682
683 ws->buffer_wait(res->buf, RADEON_USAGE_WRITE);
684
685 int i;
686 for (i = 0; i < 256; i++) {
687 printf("%02X", map[i]);
688 if (i % 16 == 15)
689 printf("\n");
690 }
691 #endif
692
693 if (rscreen->b.debug_flags & DBG_TEST_DMA)
694 r600_test_dma(&rscreen->b);
695
696 r600_query_fix_enabled_rb_mask(&rscreen->b);
697 return &rscreen->b.b;
698 }
699