1 /**************************************************************************
2 *
3 * Copyright 2011 Advanced Micro Devices, Inc.
4 *
5 * SPDX-License-Identifier: MIT
6 *
7 **************************************************************************/
8
9 #include "radeon_uvd.h"
10
11 #include "pipe/p_video_codec.h"
12 #include "radeon_video.h"
13 #include "radeonsi/si_pipe.h"
14 #include "util/u_memory.h"
15 #include "util/u_video.h"
16 #include "vl/vl_defines.h"
17 #include "vl/vl_mpeg12_decoder.h"
18 #include <sys/types.h>
19
20 #include <assert.h>
21 #include <errno.h>
22 #include <stdio.h>
23 #include <unistd.h>
24
25 #define NUM_BUFFERS 4
26
27 #define NUM_MPEG2_REFS 6
28 #define NUM_H264_REFS 17
29 #define NUM_VC1_REFS 5
30
31 #define FB_BUFFER_OFFSET 0x1000
32 #define FB_BUFFER_SIZE 2048
33 #define FB_BUFFER_SIZE_TONGA (2048 * 64)
34 #define IT_SCALING_TABLE_SIZE 992
35 #define UVD_SESSION_CONTEXT_SIZE (128 * 1024)
36
37 /* UVD decoder representation */
38 struct ruvd_decoder {
39 struct pipe_video_codec base;
40
41 ruvd_set_dtb set_dtb;
42
43 unsigned stream_handle;
44 unsigned stream_type;
45 unsigned frame_number;
46
47 struct pipe_screen *screen;
48 struct radeon_winsys *ws;
49 struct radeon_cmdbuf cs;
50
51 unsigned cur_buffer;
52
53 struct rvid_buffer msg_fb_it_buffers[NUM_BUFFERS];
54 struct ruvd_msg *msg;
55 uint32_t *fb;
56 unsigned fb_size;
57 uint8_t *it;
58
59 struct rvid_buffer bs_buffers[NUM_BUFFERS];
60 void *bs_ptr;
61 unsigned bs_size;
62
63 struct rvid_buffer dpb;
64 bool use_legacy;
65 struct rvid_buffer ctx;
66 struct rvid_buffer sessionctx;
67 struct {
68 unsigned data0;
69 unsigned data1;
70 unsigned cmd;
71 unsigned cntl;
72 } reg;
73
74 void *render_pic_list[16];
75 };
76
77 /* flush IB to the hardware */
flush(struct ruvd_decoder * dec,unsigned flags,struct pipe_fence_handle ** fence)78 static int flush(struct ruvd_decoder *dec, unsigned flags, struct pipe_fence_handle **fence)
79 {
80 return dec->ws->cs_flush(&dec->cs, flags, fence);
81 }
82
ruvd_dec_fence_wait(struct pipe_video_codec * decoder,struct pipe_fence_handle * fence,uint64_t timeout)83 static int ruvd_dec_fence_wait(struct pipe_video_codec *decoder,
84 struct pipe_fence_handle *fence,
85 uint64_t timeout)
86 {
87 struct ruvd_decoder *dec = (struct ruvd_decoder *)decoder;
88 return dec->ws->fence_wait(dec->ws, fence, timeout);
89 }
90
ruvd_dec_destroy_fence(struct pipe_video_codec * decoder,struct pipe_fence_handle * fence)91 static void ruvd_dec_destroy_fence(struct pipe_video_codec *decoder,
92 struct pipe_fence_handle *fence)
93 {
94 struct ruvd_decoder *dec = (struct ruvd_decoder *)decoder;
95
96 dec->ws->fence_reference(dec->ws, &fence, NULL);
97 }
98
99 /* add a new set register command to the IB */
set_reg(struct ruvd_decoder * dec,unsigned reg,uint32_t val)100 static void set_reg(struct ruvd_decoder *dec, unsigned reg, uint32_t val)
101 {
102 radeon_emit(&dec->cs, RUVD_PKT0(reg >> 2, 0));
103 radeon_emit(&dec->cs, val);
104 }
105
106 /* send a command to the VCPU through the GPCOM registers */
send_cmd(struct ruvd_decoder * dec,unsigned cmd,struct pb_buffer_lean * buf,uint32_t off,unsigned usage,enum radeon_bo_domain domain)107 static void send_cmd(struct ruvd_decoder *dec, unsigned cmd, struct pb_buffer_lean *buf, uint32_t off,
108 unsigned usage, enum radeon_bo_domain domain)
109 {
110 int reloc_idx;
111
112 reloc_idx = dec->ws->cs_add_buffer(&dec->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED, domain);
113 if (!dec->use_legacy) {
114 uint64_t addr;
115 addr = dec->ws->buffer_get_virtual_address(buf);
116 addr = addr + off;
117 set_reg(dec, dec->reg.data0, addr);
118 set_reg(dec, dec->reg.data1, addr >> 32);
119 } else {
120 off += dec->ws->buffer_get_reloc_offset(buf);
121 set_reg(dec, RUVD_GPCOM_VCPU_DATA0, off);
122 set_reg(dec, RUVD_GPCOM_VCPU_DATA1, reloc_idx * 4);
123 }
124 set_reg(dec, dec->reg.cmd, cmd << 1);
125 }
126
127 /* do the codec needs an IT buffer ?*/
have_it(struct ruvd_decoder * dec)128 static bool have_it(struct ruvd_decoder *dec)
129 {
130 return dec->stream_type == RUVD_CODEC_H264_PERF || dec->stream_type == RUVD_CODEC_H265;
131 }
132
133 /* map the next available message/feedback/itscaling buffer */
map_msg_fb_it_buf(struct ruvd_decoder * dec)134 static void map_msg_fb_it_buf(struct ruvd_decoder *dec)
135 {
136 struct rvid_buffer *buf;
137 uint8_t *ptr;
138
139 /* grab the current message/feedback buffer */
140 buf = &dec->msg_fb_it_buffers[dec->cur_buffer];
141
142 /* and map it for CPU access */
143 ptr =
144 dec->ws->buffer_map(dec->ws, buf->res->buf, &dec->cs, PIPE_MAP_WRITE | RADEON_MAP_TEMPORARY);
145
146 /* calc buffer offsets */
147 dec->msg = (struct ruvd_msg *)ptr;
148 memset(dec->msg, 0, sizeof(*dec->msg));
149
150 dec->fb = (uint32_t *)(ptr + FB_BUFFER_OFFSET);
151 if (have_it(dec))
152 dec->it = (uint8_t *)(ptr + FB_BUFFER_OFFSET + dec->fb_size);
153 }
154
155 /* unmap and send a message command to the VCPU */
send_msg_buf(struct ruvd_decoder * dec)156 static void send_msg_buf(struct ruvd_decoder *dec)
157 {
158 struct rvid_buffer *buf;
159
160 /* ignore the request if message/feedback buffer isn't mapped */
161 if (!dec->msg || !dec->fb)
162 return;
163
164 /* grab the current message buffer */
165 buf = &dec->msg_fb_it_buffers[dec->cur_buffer];
166
167 /* unmap the buffer */
168 dec->ws->buffer_unmap(dec->ws, buf->res->buf);
169 dec->msg = NULL;
170 dec->fb = NULL;
171 dec->it = NULL;
172
173 if (dec->sessionctx.res)
174 send_cmd(dec, RUVD_CMD_SESSION_CONTEXT_BUFFER, dec->sessionctx.res->buf, 0,
175 RADEON_USAGE_READWRITE, RADEON_DOMAIN_VRAM);
176
177 /* and send it to the hardware */
178 send_cmd(dec, RUVD_CMD_MSG_BUFFER, buf->res->buf, 0, RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
179 }
180
181 /* cycle to the next set of buffers */
next_buffer(struct ruvd_decoder * dec)182 static void next_buffer(struct ruvd_decoder *dec)
183 {
184 ++dec->cur_buffer;
185 dec->cur_buffer %= NUM_BUFFERS;
186 }
187
188 /* convert the profile into something UVD understands */
profile2stream_type(struct ruvd_decoder * dec,unsigned family)189 static uint32_t profile2stream_type(struct ruvd_decoder *dec, unsigned family)
190 {
191 switch (u_reduce_video_profile(dec->base.profile)) {
192 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
193 return (family >= CHIP_TONGA) ? RUVD_CODEC_H264_PERF : RUVD_CODEC_H264;
194
195 case PIPE_VIDEO_FORMAT_VC1:
196 return RUVD_CODEC_VC1;
197
198 case PIPE_VIDEO_FORMAT_MPEG12:
199 return RUVD_CODEC_MPEG2;
200
201 case PIPE_VIDEO_FORMAT_MPEG4:
202 return RUVD_CODEC_MPEG4;
203
204 case PIPE_VIDEO_FORMAT_HEVC:
205 return RUVD_CODEC_H265;
206
207 case PIPE_VIDEO_FORMAT_JPEG:
208 return RUVD_CODEC_MJPEG;
209
210 default:
211 assert(0);
212 return 0;
213 }
214 }
215
calc_ctx_size_h264_perf(struct ruvd_decoder * dec)216 static unsigned calc_ctx_size_h264_perf(struct ruvd_decoder *dec)
217 {
218 unsigned width_in_mb, height_in_mb, ctx_size;
219 unsigned width = align(dec->base.width, VL_MACROBLOCK_WIDTH);
220 unsigned height = align(dec->base.height, VL_MACROBLOCK_HEIGHT);
221
222 unsigned max_references = dec->base.max_references + 1;
223
224 // picture width & height in 16 pixel units
225 width_in_mb = width / VL_MACROBLOCK_WIDTH;
226 height_in_mb = align(height / VL_MACROBLOCK_HEIGHT, 2);
227
228 if (!dec->use_legacy) {
229 unsigned fs_in_mb = width_in_mb * height_in_mb;
230 unsigned num_dpb_buffer_lean;
231 switch (dec->base.level) {
232 case 30:
233 num_dpb_buffer_lean = 8100 / fs_in_mb;
234 break;
235 case 31:
236 num_dpb_buffer_lean = 18000 / fs_in_mb;
237 break;
238 case 32:
239 num_dpb_buffer_lean = 20480 / fs_in_mb;
240 break;
241 case 41:
242 num_dpb_buffer_lean = 32768 / fs_in_mb;
243 break;
244 case 42:
245 num_dpb_buffer_lean = 34816 / fs_in_mb;
246 break;
247 case 50:
248 num_dpb_buffer_lean = 110400 / fs_in_mb;
249 break;
250 case 51:
251 num_dpb_buffer_lean = 184320 / fs_in_mb;
252 break;
253 default:
254 num_dpb_buffer_lean = 184320 / fs_in_mb;
255 break;
256 }
257 num_dpb_buffer_lean++;
258 max_references = MAX2(MIN2(NUM_H264_REFS, num_dpb_buffer_lean), max_references);
259 ctx_size = max_references * align(width_in_mb * height_in_mb * 192, 256);
260 } else {
261 // the firmware seems to always assume a minimum of ref frames
262 max_references = MAX2(NUM_H264_REFS, max_references);
263 // macroblock context buffer
264 ctx_size = align(width_in_mb * height_in_mb * max_references * 192, 256);
265 }
266
267 return ctx_size;
268 }
269
calc_ctx_size_h265_main(struct ruvd_decoder * dec)270 static unsigned calc_ctx_size_h265_main(struct ruvd_decoder *dec)
271 {
272 unsigned width = align(dec->base.width, VL_MACROBLOCK_WIDTH);
273 unsigned height = align(dec->base.height, VL_MACROBLOCK_HEIGHT);
274
275 unsigned max_references = dec->base.max_references + 1;
276
277 if (dec->base.width * dec->base.height >= 4096 * 2000)
278 max_references = MAX2(max_references, 8);
279 else
280 max_references = MAX2(max_references, 17);
281
282 width = align(width, 16);
283 height = align(height, 16);
284 return ((width + 255) / 16) * ((height + 255) / 16) * 16 * max_references + 52 * 1024;
285 }
286
calc_ctx_size_h265_main10(struct ruvd_decoder * dec,struct pipe_h265_picture_desc * pic)287 static unsigned calc_ctx_size_h265_main10(struct ruvd_decoder *dec,
288 struct pipe_h265_picture_desc *pic)
289 {
290 unsigned log2_ctb_size, width_in_ctb, height_in_ctb, num_16x16_block_per_ctb;
291 unsigned context_buffer_size_per_ctb_row, cm_buffer_size, max_mb_address, db_left_tile_pxl_size;
292 unsigned db_left_tile_ctx_size = 4096 / 16 * (32 + 16 * 4);
293
294 unsigned width = align(dec->base.width, VL_MACROBLOCK_WIDTH);
295 unsigned height = align(dec->base.height, VL_MACROBLOCK_HEIGHT);
296 unsigned coeff_10bit =
297 (pic->pps->sps->bit_depth_luma_minus8 || pic->pps->sps->bit_depth_chroma_minus8) ? 2 : 1;
298
299 unsigned max_references = dec->base.max_references + 1;
300
301 if (dec->base.width * dec->base.height >= 4096 * 2000)
302 max_references = MAX2(max_references, 8);
303 else
304 max_references = MAX2(max_references, 17);
305
306 log2_ctb_size = pic->pps->sps->log2_min_luma_coding_block_size_minus3 + 3 +
307 pic->pps->sps->log2_diff_max_min_luma_coding_block_size;
308
309 width_in_ctb = (width + ((1 << log2_ctb_size) - 1)) >> log2_ctb_size;
310 height_in_ctb = (height + ((1 << log2_ctb_size) - 1)) >> log2_ctb_size;
311
312 num_16x16_block_per_ctb = ((1 << log2_ctb_size) >> 4) * ((1 << log2_ctb_size) >> 4);
313 context_buffer_size_per_ctb_row = align(width_in_ctb * num_16x16_block_per_ctb * 16, 256);
314 max_mb_address = (unsigned)ceil(height * 8 / 2048.0);
315
316 cm_buffer_size = max_references * context_buffer_size_per_ctb_row * height_in_ctb;
317 db_left_tile_pxl_size = coeff_10bit * (max_mb_address * 2 * 2048 + 1024);
318
319 return cm_buffer_size + db_left_tile_ctx_size + db_left_tile_pxl_size;
320 }
321
get_db_pitch_alignment(struct ruvd_decoder * dec)322 static unsigned get_db_pitch_alignment(struct ruvd_decoder *dec)
323 {
324 if (((struct si_screen *)dec->screen)->info.family < CHIP_VEGA10)
325 return 16;
326 else
327 return 32;
328 }
329
330 /* calculate size of reference picture buffer */
calc_dpb_size(struct ruvd_decoder * dec)331 static unsigned calc_dpb_size(struct ruvd_decoder *dec)
332 {
333 unsigned width_in_mb, height_in_mb, image_size, dpb_size;
334
335 // always align them to MB size for dpb calculation
336 unsigned width = align(dec->base.width, VL_MACROBLOCK_WIDTH);
337 unsigned height = align(dec->base.height, VL_MACROBLOCK_HEIGHT);
338
339 // always one more for currently decoded picture
340 unsigned max_references = dec->base.max_references + 1;
341
342 // aligned size of a single frame
343 image_size = align(width, get_db_pitch_alignment(dec)) * height;
344 image_size += image_size / 2;
345 image_size = align(image_size, 1024);
346
347 // picture width & height in 16 pixel units
348 width_in_mb = width / VL_MACROBLOCK_WIDTH;
349 height_in_mb = align(height / VL_MACROBLOCK_HEIGHT, 2);
350
351 switch (u_reduce_video_profile(dec->base.profile)) {
352 case PIPE_VIDEO_FORMAT_MPEG4_AVC: {
353 if (!dec->use_legacy) {
354 unsigned fs_in_mb = width_in_mb * height_in_mb;
355 unsigned alignment = 64, num_dpb_buffer_lean;
356
357 if (dec->stream_type == RUVD_CODEC_H264_PERF)
358 alignment = 256;
359 switch (dec->base.level) {
360 case 30:
361 num_dpb_buffer_lean = 8100 / fs_in_mb;
362 break;
363 case 31:
364 num_dpb_buffer_lean = 18000 / fs_in_mb;
365 break;
366 case 32:
367 num_dpb_buffer_lean = 20480 / fs_in_mb;
368 break;
369 case 41:
370 num_dpb_buffer_lean = 32768 / fs_in_mb;
371 break;
372 case 42:
373 num_dpb_buffer_lean = 34816 / fs_in_mb;
374 break;
375 case 50:
376 num_dpb_buffer_lean = 110400 / fs_in_mb;
377 break;
378 case 51:
379 num_dpb_buffer_lean = 184320 / fs_in_mb;
380 break;
381 default:
382 num_dpb_buffer_lean = 184320 / fs_in_mb;
383 break;
384 }
385 num_dpb_buffer_lean++;
386 max_references = MAX2(MIN2(NUM_H264_REFS, num_dpb_buffer_lean), max_references);
387 dpb_size = image_size * max_references;
388 if ((dec->stream_type != RUVD_CODEC_H264_PERF) ||
389 (((struct si_screen *)dec->screen)->info.family < CHIP_POLARIS10)) {
390 dpb_size += max_references * align(width_in_mb * height_in_mb * 192, alignment);
391 dpb_size += align(width_in_mb * height_in_mb * 32, alignment);
392 }
393 } else {
394 // the firmware seems to always assume a minimum of ref frames
395 max_references = MAX2(NUM_H264_REFS, max_references);
396 // reference picture buffer
397 dpb_size = image_size * max_references;
398 if ((dec->stream_type != RUVD_CODEC_H264_PERF) ||
399 (((struct si_screen *)dec->screen)->info.family < CHIP_POLARIS10)) {
400 // macroblock context buffer
401 dpb_size += width_in_mb * height_in_mb * max_references * 192;
402 // IT surface buffer
403 dpb_size += width_in_mb * height_in_mb * 32;
404 }
405 }
406 break;
407 }
408
409 case PIPE_VIDEO_FORMAT_HEVC:
410 if (dec->base.width * dec->base.height >= 4096 * 2000)
411 max_references = MAX2(max_references, 8);
412 else
413 max_references = MAX2(max_references, 17);
414
415 width = align(width, 16);
416 height = align(height, 16);
417 if (dec->base.profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
418 dpb_size = align((align(width, get_db_pitch_alignment(dec)) * height * 9) / 4, 256) *
419 max_references;
420 else
421 dpb_size = align((align(width, get_db_pitch_alignment(dec)) * height * 3) / 2, 256) *
422 max_references;
423 break;
424
425 case PIPE_VIDEO_FORMAT_VC1:
426 // the firmware seems to always assume a minimum of ref frames
427 max_references = MAX2(NUM_VC1_REFS, max_references);
428
429 // reference picture buffer
430 dpb_size = image_size * max_references;
431
432 // CONTEXT_BUFFER
433 dpb_size += width_in_mb * height_in_mb * 128;
434
435 // IT surface buffer
436 dpb_size += width_in_mb * 64;
437
438 // DB surface buffer
439 dpb_size += width_in_mb * 128;
440
441 // BP
442 dpb_size += align(MAX2(width_in_mb, height_in_mb) * 7 * 16, 64);
443 break;
444
445 case PIPE_VIDEO_FORMAT_MPEG12:
446 // reference picture buffer, must be big enough for all frames
447 dpb_size = image_size * NUM_MPEG2_REFS;
448 break;
449
450 case PIPE_VIDEO_FORMAT_MPEG4:
451 // reference picture buffer
452 dpb_size = image_size * max_references;
453
454 // CM
455 dpb_size += width_in_mb * height_in_mb * 64;
456
457 // IT surface buffer
458 dpb_size += align(width_in_mb * height_in_mb * 32, 64);
459
460 dpb_size = MAX2(dpb_size, 30 * 1024 * 1024);
461 break;
462
463 case PIPE_VIDEO_FORMAT_JPEG:
464 dpb_size = 0;
465 break;
466
467 default:
468 // something is missing here
469 assert(0);
470
471 // at least use a sane default value
472 dpb_size = 32 * 1024 * 1024;
473 break;
474 }
475 return dpb_size;
476 }
477
478 /* free associated data in the video buffer callback */
ruvd_destroy_associated_data(void * data)479 static void ruvd_destroy_associated_data(void *data)
480 {
481 /* NOOP, since we only use an intptr */
482 }
483
484 /* get h264 specific message bits */
get_h264_msg(struct ruvd_decoder * dec,struct pipe_h264_picture_desc * pic)485 static struct ruvd_h264 get_h264_msg(struct ruvd_decoder *dec, struct pipe_h264_picture_desc *pic)
486 {
487 struct ruvd_h264 result;
488
489 memset(&result, 0, sizeof(result));
490 switch (pic->base.profile) {
491 case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
492 case PIPE_VIDEO_PROFILE_MPEG4_AVC_CONSTRAINED_BASELINE:
493 result.profile = RUVD_H264_PROFILE_BASELINE;
494 break;
495
496 case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
497 result.profile = RUVD_H264_PROFILE_MAIN;
498 break;
499
500 case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
501 result.profile = RUVD_H264_PROFILE_HIGH;
502 break;
503
504 default:
505 assert(0);
506 break;
507 }
508
509 result.level = dec->base.level;
510
511 result.sps_info_flags = 0;
512 result.sps_info_flags |= pic->pps->sps->direct_8x8_inference_flag << 0;
513 result.sps_info_flags |= pic->pps->sps->mb_adaptive_frame_field_flag << 1;
514 result.sps_info_flags |= pic->pps->sps->frame_mbs_only_flag << 2;
515 result.sps_info_flags |= pic->pps->sps->delta_pic_order_always_zero_flag << 3;
516
517 result.chroma_format = pic->pps->sps->chroma_format_idc;
518 result.bit_depth_luma_minus8 = pic->pps->sps->bit_depth_luma_minus8;
519 result.bit_depth_chroma_minus8 = pic->pps->sps->bit_depth_chroma_minus8;
520 result.log2_max_frame_num_minus4 = pic->pps->sps->log2_max_frame_num_minus4;
521 result.pic_order_cnt_type = pic->pps->sps->pic_order_cnt_type;
522 result.log2_max_pic_order_cnt_lsb_minus4 = pic->pps->sps->log2_max_pic_order_cnt_lsb_minus4;
523
524 result.pps_info_flags = 0;
525 result.pps_info_flags |= pic->pps->transform_8x8_mode_flag << 0;
526 result.pps_info_flags |= pic->pps->redundant_pic_cnt_present_flag << 1;
527 result.pps_info_flags |= pic->pps->constrained_intra_pred_flag << 2;
528 result.pps_info_flags |= pic->pps->deblocking_filter_control_present_flag << 3;
529 result.pps_info_flags |= pic->pps->weighted_bipred_idc << 4;
530 result.pps_info_flags |= pic->pps->weighted_pred_flag << 6;
531 result.pps_info_flags |= pic->pps->bottom_field_pic_order_in_frame_present_flag << 7;
532 result.pps_info_flags |= pic->pps->entropy_coding_mode_flag << 8;
533
534 result.num_slice_groups_minus1 = pic->pps->num_slice_groups_minus1;
535 result.slice_group_map_type = pic->pps->slice_group_map_type;
536 result.slice_group_change_rate_minus1 = pic->pps->slice_group_change_rate_minus1;
537 result.pic_init_qp_minus26 = pic->pps->pic_init_qp_minus26;
538 result.chroma_qp_index_offset = pic->pps->chroma_qp_index_offset;
539 result.second_chroma_qp_index_offset = pic->pps->second_chroma_qp_index_offset;
540
541 memcpy(result.scaling_list_4x4, pic->pps->ScalingList4x4, 6 * 16);
542 memcpy(result.scaling_list_8x8, pic->pps->ScalingList8x8, 2 * 64);
543
544 if (dec->stream_type == RUVD_CODEC_H264_PERF) {
545 memcpy(dec->it, result.scaling_list_4x4, 6 * 16);
546 memcpy((dec->it + 96), result.scaling_list_8x8, 2 * 64);
547 }
548
549 result.num_ref_frames = pic->num_ref_frames;
550
551 result.num_ref_idx_l0_active_minus1 = pic->num_ref_idx_l0_active_minus1;
552 result.num_ref_idx_l1_active_minus1 = pic->num_ref_idx_l1_active_minus1;
553
554 result.frame_num = pic->frame_num;
555 memcpy(result.frame_num_list, pic->frame_num_list, 4 * 16);
556 result.curr_field_order_cnt_list[0] = pic->field_order_cnt[0];
557 result.curr_field_order_cnt_list[1] = pic->field_order_cnt[1];
558 memcpy(result.field_order_cnt_list, pic->field_order_cnt_list, 4 * 16 * 2);
559
560 result.decoded_pic_idx = pic->frame_num;
561
562 return result;
563 }
564
565 /* get h265 specific message bits */
get_h265_msg(struct ruvd_decoder * dec,struct pipe_video_buffer * target,struct pipe_h265_picture_desc * pic)566 static struct ruvd_h265 get_h265_msg(struct ruvd_decoder *dec, struct pipe_video_buffer *target,
567 struct pipe_h265_picture_desc *pic)
568 {
569 struct ruvd_h265 result;
570 unsigned i, j;
571
572 memset(&result, 0, sizeof(result));
573
574 result.sps_info_flags = 0;
575 result.sps_info_flags |= pic->pps->sps->scaling_list_enabled_flag << 0;
576 result.sps_info_flags |= pic->pps->sps->amp_enabled_flag << 1;
577 result.sps_info_flags |= pic->pps->sps->sample_adaptive_offset_enabled_flag << 2;
578 result.sps_info_flags |= pic->pps->sps->pcm_enabled_flag << 3;
579 result.sps_info_flags |= pic->pps->sps->pcm_loop_filter_disabled_flag << 4;
580 result.sps_info_flags |= pic->pps->sps->long_term_ref_pics_present_flag << 5;
581 result.sps_info_flags |= pic->pps->sps->sps_temporal_mvp_enabled_flag << 6;
582 result.sps_info_flags |= pic->pps->sps->strong_intra_smoothing_enabled_flag << 7;
583 result.sps_info_flags |= pic->pps->sps->separate_colour_plane_flag << 8;
584 if (((struct si_screen *)dec->screen)->info.family == CHIP_CARRIZO)
585 result.sps_info_flags |= 1 << 9;
586 if (pic->UseRefPicList == true)
587 result.sps_info_flags |= 1 << 10;
588
589 result.chroma_format = pic->pps->sps->chroma_format_idc;
590 result.bit_depth_luma_minus8 = pic->pps->sps->bit_depth_luma_minus8;
591 result.bit_depth_chroma_minus8 = pic->pps->sps->bit_depth_chroma_minus8;
592 result.log2_max_pic_order_cnt_lsb_minus4 = pic->pps->sps->log2_max_pic_order_cnt_lsb_minus4;
593 result.sps_max_dec_pic_buffering_minus1 = pic->pps->sps->sps_max_dec_pic_buffering_minus1;
594 result.log2_min_luma_coding_block_size_minus3 =
595 pic->pps->sps->log2_min_luma_coding_block_size_minus3;
596 result.log2_diff_max_min_luma_coding_block_size =
597 pic->pps->sps->log2_diff_max_min_luma_coding_block_size;
598 result.log2_min_transform_block_size_minus2 =
599 pic->pps->sps->log2_min_transform_block_size_minus2;
600 result.log2_diff_max_min_transform_block_size =
601 pic->pps->sps->log2_diff_max_min_transform_block_size;
602 result.max_transform_hierarchy_depth_inter = pic->pps->sps->max_transform_hierarchy_depth_inter;
603 result.max_transform_hierarchy_depth_intra = pic->pps->sps->max_transform_hierarchy_depth_intra;
604 result.pcm_sample_bit_depth_luma_minus1 = pic->pps->sps->pcm_sample_bit_depth_luma_minus1;
605 result.pcm_sample_bit_depth_chroma_minus1 = pic->pps->sps->pcm_sample_bit_depth_chroma_minus1;
606 result.log2_min_pcm_luma_coding_block_size_minus3 =
607 pic->pps->sps->log2_min_pcm_luma_coding_block_size_minus3;
608 result.log2_diff_max_min_pcm_luma_coding_block_size =
609 pic->pps->sps->log2_diff_max_min_pcm_luma_coding_block_size;
610 result.num_short_term_ref_pic_sets = pic->pps->sps->num_short_term_ref_pic_sets;
611
612 result.pps_info_flags = 0;
613 result.pps_info_flags |= pic->pps->dependent_slice_segments_enabled_flag << 0;
614 result.pps_info_flags |= pic->pps->output_flag_present_flag << 1;
615 result.pps_info_flags |= pic->pps->sign_data_hiding_enabled_flag << 2;
616 result.pps_info_flags |= pic->pps->cabac_init_present_flag << 3;
617 result.pps_info_flags |= pic->pps->constrained_intra_pred_flag << 4;
618 result.pps_info_flags |= pic->pps->transform_skip_enabled_flag << 5;
619 result.pps_info_flags |= pic->pps->cu_qp_delta_enabled_flag << 6;
620 result.pps_info_flags |= pic->pps->pps_slice_chroma_qp_offsets_present_flag << 7;
621 result.pps_info_flags |= pic->pps->weighted_pred_flag << 8;
622 result.pps_info_flags |= pic->pps->weighted_bipred_flag << 9;
623 result.pps_info_flags |= pic->pps->transquant_bypass_enabled_flag << 10;
624 result.pps_info_flags |= pic->pps->tiles_enabled_flag << 11;
625 result.pps_info_flags |= pic->pps->entropy_coding_sync_enabled_flag << 12;
626 result.pps_info_flags |= pic->pps->uniform_spacing_flag << 13;
627 result.pps_info_flags |= pic->pps->loop_filter_across_tiles_enabled_flag << 14;
628 result.pps_info_flags |= pic->pps->pps_loop_filter_across_slices_enabled_flag << 15;
629 result.pps_info_flags |= pic->pps->deblocking_filter_override_enabled_flag << 16;
630 result.pps_info_flags |= pic->pps->pps_deblocking_filter_disabled_flag << 17;
631 result.pps_info_flags |= pic->pps->lists_modification_present_flag << 18;
632 result.pps_info_flags |= pic->pps->slice_segment_header_extension_present_flag << 19;
633 // result.pps_info_flags |= pic->pps->deblocking_filter_control_present_flag; ???
634
635 result.num_extra_slice_header_bits = pic->pps->num_extra_slice_header_bits;
636 result.num_long_term_ref_pic_sps = pic->pps->sps->num_long_term_ref_pics_sps;
637 result.num_ref_idx_l0_default_active_minus1 = pic->pps->num_ref_idx_l0_default_active_minus1;
638 result.num_ref_idx_l1_default_active_minus1 = pic->pps->num_ref_idx_l1_default_active_minus1;
639 result.pps_cb_qp_offset = pic->pps->pps_cb_qp_offset;
640 result.pps_cr_qp_offset = pic->pps->pps_cr_qp_offset;
641 result.pps_beta_offset_div2 = pic->pps->pps_beta_offset_div2;
642 result.pps_tc_offset_div2 = pic->pps->pps_tc_offset_div2;
643 result.diff_cu_qp_delta_depth = pic->pps->diff_cu_qp_delta_depth;
644 result.num_tile_columns_minus1 = pic->pps->num_tile_columns_minus1;
645 result.num_tile_rows_minus1 = pic->pps->num_tile_rows_minus1;
646 result.log2_parallel_merge_level_minus2 = pic->pps->log2_parallel_merge_level_minus2;
647 result.init_qp_minus26 = pic->pps->init_qp_minus26;
648
649 for (i = 0; i < 19; ++i)
650 result.column_width_minus1[i] = pic->pps->column_width_minus1[i];
651
652 for (i = 0; i < 21; ++i)
653 result.row_height_minus1[i] = pic->pps->row_height_minus1[i];
654
655 result.num_delta_pocs_ref_rps_idx = pic->NumDeltaPocsOfRefRpsIdx;
656 result.curr_poc = pic->CurrPicOrderCntVal;
657
658 for (i = 0; i < 16; i++) {
659 for (j = 0; (pic->ref[j] != NULL) && (j < 16); j++) {
660 if (dec->render_pic_list[i] == pic->ref[j])
661 break;
662 if (j == 15)
663 dec->render_pic_list[i] = NULL;
664 else if (pic->ref[j + 1] == NULL)
665 dec->render_pic_list[i] = NULL;
666 }
667 }
668 for (i = 0; i < 16; i++) {
669 if (dec->render_pic_list[i] == NULL) {
670 dec->render_pic_list[i] = target;
671 result.curr_idx = i;
672 break;
673 }
674 }
675
676 vl_video_buffer_set_associated_data(target, &dec->base, (void *)(uintptr_t)result.curr_idx,
677 &ruvd_destroy_associated_data);
678
679 for (i = 0; i < 16; ++i) {
680 struct pipe_video_buffer *ref = pic->ref[i];
681 uintptr_t ref_pic = 0;
682
683 result.poc_list[i] = pic->PicOrderCntVal[i];
684
685 if (ref)
686 ref_pic = (uintptr_t)vl_video_buffer_get_associated_data(ref, &dec->base);
687 else
688 ref_pic = 0x7F;
689 result.ref_pic_list[i] = ref_pic;
690 }
691
692 for (i = 0; i < 8; ++i) {
693 result.ref_pic_set_st_curr_before[i] = 0xFF;
694 result.ref_pic_set_st_curr_after[i] = 0xFF;
695 result.ref_pic_set_lt_curr[i] = 0xFF;
696 }
697
698 for (i = 0; i < pic->NumPocStCurrBefore; ++i)
699 result.ref_pic_set_st_curr_before[i] = pic->RefPicSetStCurrBefore[i];
700
701 for (i = 0; i < pic->NumPocStCurrAfter; ++i)
702 result.ref_pic_set_st_curr_after[i] = pic->RefPicSetStCurrAfter[i];
703
704 for (i = 0; i < pic->NumPocLtCurr; ++i)
705 result.ref_pic_set_lt_curr[i] = pic->RefPicSetLtCurr[i];
706
707 for (i = 0; i < 6; ++i)
708 result.ucScalingListDCCoefSizeID2[i] = pic->pps->sps->ScalingListDCCoeff16x16[i];
709
710 for (i = 0; i < 2; ++i)
711 result.ucScalingListDCCoefSizeID3[i] = pic->pps->sps->ScalingListDCCoeff32x32[i];
712
713 memcpy(dec->it, pic->pps->sps->ScalingList4x4, 6 * 16);
714 memcpy(dec->it + 96, pic->pps->sps->ScalingList8x8, 6 * 64);
715 memcpy(dec->it + 480, pic->pps->sps->ScalingList16x16, 6 * 64);
716 memcpy(dec->it + 864, pic->pps->sps->ScalingList32x32, 2 * 64);
717
718 for (i = 0; i < 2; i++) {
719 for (j = 0; j < 15; j++)
720 result.direct_reflist[i][j] = pic->RefPicList[0][i][j];
721 }
722
723 if (pic->base.profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10) {
724 if (target->buffer_format == PIPE_FORMAT_P010 || target->buffer_format == PIPE_FORMAT_P016) {
725 result.p010_mode = 1;
726 result.msb_mode = 1;
727 } else {
728 result.luma_10to8 = 5;
729 result.chroma_10to8 = 5;
730 result.sclr_luma10to8 = 4;
731 result.sclr_chroma10to8 = 4;
732 }
733 }
734
735 /* TODO
736 result.highestTid;
737 result.isNonRef;
738
739 IDRPicFlag;
740 RAPPicFlag;
741 NumPocTotalCurr;
742 NumShortTermPictureSliceHeaderBits;
743 NumLongTermPictureSliceHeaderBits;
744
745 IsLongTerm[16];
746 */
747
748 return result;
749 }
750
751 /* get vc1 specific message bits */
get_vc1_msg(struct pipe_vc1_picture_desc * pic)752 static struct ruvd_vc1 get_vc1_msg(struct pipe_vc1_picture_desc *pic)
753 {
754 struct ruvd_vc1 result;
755
756 memset(&result, 0, sizeof(result));
757
758 switch (pic->base.profile) {
759 case PIPE_VIDEO_PROFILE_VC1_SIMPLE:
760 result.profile = RUVD_VC1_PROFILE_SIMPLE;
761 result.level = 1;
762 break;
763
764 case PIPE_VIDEO_PROFILE_VC1_MAIN:
765 result.profile = RUVD_VC1_PROFILE_MAIN;
766 result.level = 2;
767 break;
768
769 case PIPE_VIDEO_PROFILE_VC1_ADVANCED:
770 result.profile = RUVD_VC1_PROFILE_ADVANCED;
771 result.level = 4;
772 break;
773
774 default:
775 assert(0);
776 }
777
778 /* fields common for all profiles */
779 result.sps_info_flags |= pic->postprocflag << 7;
780 result.sps_info_flags |= pic->pulldown << 6;
781 result.sps_info_flags |= pic->interlace << 5;
782 result.sps_info_flags |= pic->tfcntrflag << 4;
783 result.sps_info_flags |= pic->finterpflag << 3;
784 result.sps_info_flags |= pic->psf << 1;
785
786 result.pps_info_flags |= pic->range_mapy_flag << 31;
787 result.pps_info_flags |= pic->range_mapy << 28;
788 result.pps_info_flags |= pic->range_mapuv_flag << 27;
789 result.pps_info_flags |= pic->range_mapuv << 24;
790 result.pps_info_flags |= pic->multires << 21;
791 result.pps_info_flags |= pic->maxbframes << 16;
792 result.pps_info_flags |= pic->overlap << 11;
793 result.pps_info_flags |= pic->quantizer << 9;
794 result.pps_info_flags |= pic->panscan_flag << 7;
795 result.pps_info_flags |= pic->refdist_flag << 6;
796 result.pps_info_flags |= pic->vstransform << 0;
797
798 /* some fields only apply to main/advanced profile */
799 if (pic->base.profile != PIPE_VIDEO_PROFILE_VC1_SIMPLE) {
800 result.pps_info_flags |= pic->syncmarker << 20;
801 result.pps_info_flags |= pic->rangered << 19;
802 result.pps_info_flags |= pic->loopfilter << 5;
803 result.pps_info_flags |= pic->fastuvmc << 4;
804 result.pps_info_flags |= pic->extended_mv << 3;
805 result.pps_info_flags |= pic->extended_dmv << 8;
806 result.pps_info_flags |= pic->dquant << 1;
807 }
808
809 result.chroma_format = 1;
810
811 #if 0
812 //(((unsigned int)(pPicParams->advance.reserved1)) << SPS_INFO_VC1_RESERVED_SHIFT)
813 uint32_t slice_count
814 uint8_t picture_type
815 uint8_t frame_coding_mode
816 uint8_t deblockEnable
817 uint8_t pquant
818 #endif
819
820 return result;
821 }
822
823 /* extract the frame number from a referenced video buffer */
get_ref_pic_idx(struct ruvd_decoder * dec,struct pipe_video_buffer * ref)824 static uint32_t get_ref_pic_idx(struct ruvd_decoder *dec, struct pipe_video_buffer *ref)
825 {
826 uint32_t min = MAX2(dec->frame_number, NUM_MPEG2_REFS) - NUM_MPEG2_REFS;
827 uint32_t max = MAX2(dec->frame_number, 1) - 1;
828 uintptr_t frame;
829
830 /* seems to be the most sane fallback */
831 if (!ref)
832 return max;
833
834 /* get the frame number from the associated data */
835 frame = (uintptr_t)vl_video_buffer_get_associated_data(ref, &dec->base);
836
837 /* limit the frame number to a valid range */
838 return MAX2(MIN2(frame, max), min);
839 }
840
841 /* get mpeg2 specific msg bits */
get_mpeg2_msg(struct ruvd_decoder * dec,struct pipe_mpeg12_picture_desc * pic)842 static struct ruvd_mpeg2 get_mpeg2_msg(struct ruvd_decoder *dec,
843 struct pipe_mpeg12_picture_desc *pic)
844 {
845 const int *zscan = pic->alternate_scan ? vl_zscan_alternate : vl_zscan_normal;
846 struct ruvd_mpeg2 result;
847 unsigned i;
848
849 memset(&result, 0, sizeof(result));
850 result.decoded_pic_idx = dec->frame_number;
851 for (i = 0; i < 2; ++i)
852 result.ref_pic_idx[i] = get_ref_pic_idx(dec, pic->ref[i]);
853
854 if (pic->intra_matrix) {
855 result.load_intra_quantiser_matrix = 1;
856 for (i = 0; i < 64; ++i) {
857 result.intra_quantiser_matrix[i] = pic->intra_matrix[zscan[i]];
858 }
859 }
860 if (pic->non_intra_matrix) {
861 result.load_nonintra_quantiser_matrix = 1;
862 for (i = 0; i < 64; ++i) {
863 result.nonintra_quantiser_matrix[i] = pic->non_intra_matrix[zscan[i]];
864 }
865 }
866
867 result.profile_and_level_indication = 0;
868 result.chroma_format = 0x1;
869
870 result.picture_coding_type = pic->picture_coding_type;
871 result.f_code[0][0] = pic->f_code[0][0] + 1;
872 result.f_code[0][1] = pic->f_code[0][1] + 1;
873 result.f_code[1][0] = pic->f_code[1][0] + 1;
874 result.f_code[1][1] = pic->f_code[1][1] + 1;
875 result.intra_dc_precision = pic->intra_dc_precision;
876 result.pic_structure = pic->picture_structure;
877 result.top_field_first = pic->top_field_first;
878 result.frame_pred_frame_dct = pic->frame_pred_frame_dct;
879 result.concealment_motion_vectors = pic->concealment_motion_vectors;
880 result.q_scale_type = pic->q_scale_type;
881 result.intra_vlc_format = pic->intra_vlc_format;
882 result.alternate_scan = pic->alternate_scan;
883
884 return result;
885 }
886
887 /* get mpeg4 specific msg bits */
get_mpeg4_msg(struct ruvd_decoder * dec,struct pipe_mpeg4_picture_desc * pic)888 static struct ruvd_mpeg4 get_mpeg4_msg(struct ruvd_decoder *dec,
889 struct pipe_mpeg4_picture_desc *pic)
890 {
891 struct ruvd_mpeg4 result;
892 unsigned i;
893
894 memset(&result, 0, sizeof(result));
895 result.decoded_pic_idx = dec->frame_number;
896 for (i = 0; i < 2; ++i)
897 result.ref_pic_idx[i] = get_ref_pic_idx(dec, pic->ref[i]);
898
899 result.variant_type = 0;
900 result.profile_and_level_indication = 0xF0; // ASP Level0
901
902 result.video_object_layer_verid = 0x5; // advanced simple
903 result.video_object_layer_shape = 0x0; // rectangular
904
905 result.video_object_layer_width = dec->base.width;
906 result.video_object_layer_height = dec->base.height;
907
908 result.vop_time_increment_resolution = pic->vop_time_increment_resolution;
909
910 result.flags |= pic->short_video_header << 0;
911 // result.flags |= obmc_disable << 1;
912 result.flags |= pic->interlaced << 2;
913 result.flags |= 1 << 3; // load_intra_quant_mat
914 result.flags |= 1 << 4; // load_nonintra_quant_mat
915 result.flags |= pic->quarter_sample << 5;
916 result.flags |= 1 << 6; // complexity_estimation_disable
917 result.flags |= pic->resync_marker_disable << 7;
918 // result.flags |= data_partitioned << 8;
919 // result.flags |= reversible_vlc << 9;
920 result.flags |= 0 << 10; // newpred_enable
921 result.flags |= 0 << 11; // reduced_resolution_vop_enable
922 // result.flags |= scalability << 12;
923 // result.flags |= is_object_layer_identifier << 13;
924 // result.flags |= fixed_vop_rate << 14;
925 // result.flags |= newpred_segment_type << 15;
926
927 result.quant_type = pic->quant_type;
928
929 for (i = 0; i < 64; ++i) {
930 result.intra_quant_mat[i] = pic->intra_matrix[vl_zscan_normal[i]];
931 result.nonintra_quant_mat[i] = pic->non_intra_matrix[vl_zscan_normal[i]];
932 }
933
934 /*
935 int32_t trd [2]
936 int32_t trb [2]
937 uint8_t vop_coding_type
938 uint8_t vop_fcode_forward
939 uint8_t vop_fcode_backward
940 uint8_t rounding_control
941 uint8_t alternate_vertical_scan_flag
942 uint8_t top_field_first
943 */
944
945 return result;
946 }
947
948 /**
949 * destroy this video decoder
950 */
ruvd_destroy(struct pipe_video_codec * decoder)951 static void ruvd_destroy(struct pipe_video_codec *decoder)
952 {
953 struct ruvd_decoder *dec = (struct ruvd_decoder *)decoder;
954 unsigned i;
955
956 assert(decoder);
957
958 map_msg_fb_it_buf(dec);
959 dec->msg->size = sizeof(*dec->msg);
960 dec->msg->msg_type = RUVD_MSG_DESTROY;
961 dec->msg->stream_handle = dec->stream_handle;
962 send_msg_buf(dec);
963
964 flush(dec, 0, NULL);
965
966 dec->ws->cs_destroy(&dec->cs);
967
968 for (i = 0; i < NUM_BUFFERS; ++i) {
969 si_vid_destroy_buffer(&dec->msg_fb_it_buffers[i]);
970 si_vid_destroy_buffer(&dec->bs_buffers[i]);
971 }
972
973 si_vid_destroy_buffer(&dec->dpb);
974 si_vid_destroy_buffer(&dec->ctx);
975 si_vid_destroy_buffer(&dec->sessionctx);
976
977 FREE(dec);
978 }
979
980 /**
981 * start decoding of a new frame
982 */
ruvd_begin_frame(struct pipe_video_codec * decoder,struct pipe_video_buffer * target,struct pipe_picture_desc * picture)983 static void ruvd_begin_frame(struct pipe_video_codec *decoder, struct pipe_video_buffer *target,
984 struct pipe_picture_desc *picture)
985 {
986 struct ruvd_decoder *dec = (struct ruvd_decoder *)decoder;
987 uintptr_t frame;
988
989 assert(decoder);
990
991 frame = ++dec->frame_number;
992 vl_video_buffer_set_associated_data(target, decoder, (void *)frame,
993 &ruvd_destroy_associated_data);
994
995 dec->bs_size = 0;
996 dec->bs_ptr = dec->ws->buffer_map(dec->ws, dec->bs_buffers[dec->cur_buffer].res->buf, &dec->cs,
997 PIPE_MAP_WRITE | RADEON_MAP_TEMPORARY);
998 }
999
1000 /**
1001 * decode a macroblock
1002 */
ruvd_decode_macroblock(struct pipe_video_codec * decoder,struct pipe_video_buffer * target,struct pipe_picture_desc * picture,const struct pipe_macroblock * macroblocks,unsigned num_macroblocks)1003 static void ruvd_decode_macroblock(struct pipe_video_codec *decoder,
1004 struct pipe_video_buffer *target,
1005 struct pipe_picture_desc *picture,
1006 const struct pipe_macroblock *macroblocks,
1007 unsigned num_macroblocks)
1008 {
1009 /* not supported (yet) */
1010 assert(0);
1011 }
1012
1013 /**
1014 * decode a bitstream
1015 */
ruvd_decode_bitstream(struct pipe_video_codec * decoder,struct pipe_video_buffer * target,struct pipe_picture_desc * picture,unsigned num_buffers,const void * const * buffers,const unsigned * sizes)1016 static void ruvd_decode_bitstream(struct pipe_video_codec *decoder,
1017 struct pipe_video_buffer *target,
1018 struct pipe_picture_desc *picture, unsigned num_buffers,
1019 const void *const *buffers, const unsigned *sizes)
1020 {
1021 struct ruvd_decoder *dec = (struct ruvd_decoder *)decoder;
1022 unsigned i;
1023
1024 assert(decoder);
1025
1026 if (!dec->bs_ptr)
1027 return;
1028
1029 unsigned long total_bs_size = dec->bs_size;
1030 for (i = 0; i < num_buffers; ++i)
1031 total_bs_size += sizes[i];
1032
1033 struct rvid_buffer *buf = &dec->bs_buffers[dec->cur_buffer];
1034
1035 if (total_bs_size > buf->res->buf->size) {
1036 dec->ws->buffer_unmap(dec->ws, buf->res->buf);
1037 dec->bs_ptr = NULL;
1038
1039 total_bs_size = align(total_bs_size, 128);
1040
1041 if (!dec->bs_size) {
1042 struct rvid_buffer old_buf = *buf;
1043 if (!si_vid_create_buffer(dec->screen, buf, total_bs_size, buf->usage)) {
1044 RVID_ERR("Can't create bitstream buffer!");
1045 return;
1046 }
1047 si_vid_destroy_buffer(&old_buf);
1048 } else if (!si_vid_resize_buffer(dec->base.context, &dec->cs, buf, total_bs_size, NULL)) {
1049 RVID_ERR("Can't resize bitstream buffer!");
1050 return;
1051 }
1052
1053 dec->bs_ptr = dec->ws->buffer_map(dec->ws, buf->res->buf, &dec->cs,
1054 PIPE_MAP_WRITE | RADEON_MAP_TEMPORARY);
1055 if (!dec->bs_ptr)
1056 return;
1057
1058 dec->bs_ptr += dec->bs_size;
1059 }
1060
1061 for (i = 0; i < num_buffers; ++i) {
1062 memcpy(dec->bs_ptr, buffers[i], sizes[i]);
1063 dec->bs_size += sizes[i];
1064 dec->bs_ptr += sizes[i];
1065 }
1066 }
1067
1068 /**
1069 * end decoding of the current frame
1070 */
ruvd_end_frame(struct pipe_video_codec * decoder,struct pipe_video_buffer * target,struct pipe_picture_desc * picture)1071 static int ruvd_end_frame(struct pipe_video_codec *decoder, struct pipe_video_buffer *target,
1072 struct pipe_picture_desc *picture)
1073 {
1074 struct ruvd_decoder *dec = (struct ruvd_decoder *)decoder;
1075 struct pb_buffer_lean *dt;
1076 struct rvid_buffer *msg_fb_it_buf, *bs_buf;
1077 unsigned bs_size;
1078
1079 assert(decoder);
1080
1081 if (!dec->bs_ptr)
1082 return 1;
1083
1084 msg_fb_it_buf = &dec->msg_fb_it_buffers[dec->cur_buffer];
1085 bs_buf = &dec->bs_buffers[dec->cur_buffer];
1086
1087 bs_size = align(dec->bs_size, 128);
1088 memset(dec->bs_ptr, 0, bs_size - dec->bs_size);
1089 dec->ws->buffer_unmap(dec->ws, bs_buf->res->buf);
1090
1091 map_msg_fb_it_buf(dec);
1092 dec->msg->size = sizeof(*dec->msg);
1093 dec->msg->msg_type = RUVD_MSG_DECODE;
1094 dec->msg->stream_handle = dec->stream_handle;
1095 dec->msg->status_report_feedback_number = dec->frame_number;
1096
1097 dec->msg->body.decode.stream_type = dec->stream_type;
1098 dec->msg->body.decode.decode_flags = 0x1;
1099 dec->msg->body.decode.width_in_samples = dec->base.width;
1100 dec->msg->body.decode.height_in_samples = dec->base.height;
1101
1102 if ((picture->profile == PIPE_VIDEO_PROFILE_VC1_SIMPLE) ||
1103 (picture->profile == PIPE_VIDEO_PROFILE_VC1_MAIN)) {
1104 dec->msg->body.decode.width_in_samples =
1105 align(dec->msg->body.decode.width_in_samples, 16) / 16;
1106 dec->msg->body.decode.height_in_samples =
1107 align(dec->msg->body.decode.height_in_samples, 16) / 16;
1108 }
1109
1110 if (dec->dpb.res)
1111 dec->msg->body.decode.dpb_size = dec->dpb.res->buf->size;
1112 dec->msg->body.decode.bsd_size = bs_size;
1113 dec->msg->body.decode.db_pitch = align(dec->base.width, get_db_pitch_alignment(dec));
1114
1115 if (dec->stream_type == RUVD_CODEC_H264_PERF &&
1116 ((struct si_screen *)dec->screen)->info.family >= CHIP_POLARIS10)
1117 dec->msg->body.decode.dpb_reserved = dec->ctx.res->buf->size;
1118
1119 dt = dec->set_dtb(dec->msg, (struct vl_video_buffer *)target);
1120 if (((struct si_screen *)dec->screen)->info.family >= CHIP_STONEY)
1121 dec->msg->body.decode.dt_wa_chroma_top_offset = dec->msg->body.decode.dt_pitch / 2;
1122
1123 switch (u_reduce_video_profile(picture->profile)) {
1124 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
1125 dec->msg->body.decode.codec.h264 =
1126 get_h264_msg(dec, (struct pipe_h264_picture_desc *)picture);
1127 break;
1128
1129 case PIPE_VIDEO_FORMAT_HEVC:
1130 dec->msg->body.decode.codec.h265 =
1131 get_h265_msg(dec, target, (struct pipe_h265_picture_desc *)picture);
1132 if (dec->ctx.res == NULL) {
1133 unsigned ctx_size;
1134 if (dec->base.profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
1135 ctx_size = calc_ctx_size_h265_main10(dec, (struct pipe_h265_picture_desc *)picture);
1136 else
1137 ctx_size = calc_ctx_size_h265_main(dec);
1138 if (!si_vid_create_buffer(dec->screen, &dec->ctx, ctx_size, PIPE_USAGE_DEFAULT)) {
1139 RVID_ERR("Can't allocated context buffer.\n");
1140 }
1141 }
1142
1143 if (dec->ctx.res)
1144 dec->msg->body.decode.dpb_reserved = dec->ctx.res->buf->size;
1145 break;
1146
1147 case PIPE_VIDEO_FORMAT_VC1:
1148 dec->msg->body.decode.codec.vc1 = get_vc1_msg((struct pipe_vc1_picture_desc *)picture);
1149 break;
1150
1151 case PIPE_VIDEO_FORMAT_MPEG12:
1152 dec->msg->body.decode.codec.mpeg2 =
1153 get_mpeg2_msg(dec, (struct pipe_mpeg12_picture_desc *)picture);
1154 break;
1155
1156 case PIPE_VIDEO_FORMAT_MPEG4:
1157 dec->msg->body.decode.codec.mpeg4 =
1158 get_mpeg4_msg(dec, (struct pipe_mpeg4_picture_desc *)picture);
1159 break;
1160
1161 case PIPE_VIDEO_FORMAT_JPEG:
1162 break;
1163
1164 default:
1165 assert(0);
1166 return 1;
1167 }
1168
1169 dec->msg->body.decode.db_surf_tile_config = dec->msg->body.decode.dt_surf_tile_config;
1170 dec->msg->body.decode.extension_support = 0x1;
1171
1172 /* set at least the feedback buffer size */
1173 dec->fb[0] = dec->fb_size;
1174
1175 send_msg_buf(dec);
1176
1177 if (dec->dpb.res)
1178 send_cmd(dec, RUVD_CMD_DPB_BUFFER, dec->dpb.res->buf, 0, RADEON_USAGE_READWRITE,
1179 RADEON_DOMAIN_VRAM);
1180
1181 if (dec->ctx.res)
1182 send_cmd(dec, RUVD_CMD_CONTEXT_BUFFER, dec->ctx.res->buf, 0, RADEON_USAGE_READWRITE,
1183 RADEON_DOMAIN_VRAM);
1184 send_cmd(dec, RUVD_CMD_BITSTREAM_BUFFER, bs_buf->res->buf, 0, RADEON_USAGE_READ,
1185 RADEON_DOMAIN_GTT);
1186 send_cmd(dec, RUVD_CMD_DECODING_TARGET_BUFFER, dt, 0, RADEON_USAGE_WRITE, RADEON_DOMAIN_VRAM);
1187 send_cmd(dec, RUVD_CMD_FEEDBACK_BUFFER, msg_fb_it_buf->res->buf, FB_BUFFER_OFFSET,
1188 RADEON_USAGE_WRITE, RADEON_DOMAIN_GTT);
1189 if (have_it(dec))
1190 send_cmd(dec, RUVD_CMD_ITSCALING_TABLE_BUFFER, msg_fb_it_buf->res->buf,
1191 FB_BUFFER_OFFSET + dec->fb_size, RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
1192 set_reg(dec, dec->reg.cntl, 1);
1193
1194 flush(dec, picture->flush_flags, picture->fence);
1195 next_buffer(dec);
1196 return 0;
1197 }
1198
1199 /**
1200 * flush any outstanding command buffers to the hardware
1201 */
ruvd_flush(struct pipe_video_codec * decoder)1202 static void ruvd_flush(struct pipe_video_codec *decoder)
1203 {
1204 }
1205
1206 /**
1207 * create and UVD decoder
1208 */
si_common_uvd_create_decoder(struct pipe_context * context,const struct pipe_video_codec * templ,ruvd_set_dtb set_dtb)1209 struct pipe_video_codec *si_common_uvd_create_decoder(struct pipe_context *context,
1210 const struct pipe_video_codec *templ,
1211 ruvd_set_dtb set_dtb)
1212 {
1213 struct si_context *sctx = (struct si_context *)context;
1214 struct radeon_winsys *ws = sctx->ws;
1215 unsigned dpb_size;
1216 unsigned width = templ->width, height = templ->height;
1217 unsigned bs_buf_size;
1218 struct ruvd_decoder *dec;
1219 int r, i;
1220
1221 switch (u_reduce_video_profile(templ->profile)) {
1222 case PIPE_VIDEO_FORMAT_MPEG12:
1223 if (templ->entrypoint > PIPE_VIDEO_ENTRYPOINT_BITSTREAM)
1224 return vl_create_mpeg12_decoder(context, templ);
1225
1226 FALLTHROUGH;
1227 case PIPE_VIDEO_FORMAT_MPEG4:
1228 width = align(width, VL_MACROBLOCK_WIDTH);
1229 height = align(height, VL_MACROBLOCK_HEIGHT);
1230 break;
1231 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
1232 width = align(width, VL_MACROBLOCK_WIDTH);
1233 height = align(height, VL_MACROBLOCK_HEIGHT);
1234 break;
1235
1236 default:
1237 break;
1238 }
1239
1240 dec = CALLOC_STRUCT(ruvd_decoder);
1241
1242 if (!dec)
1243 return NULL;
1244
1245 if (!sctx->screen->info.is_amdgpu)
1246 dec->use_legacy = true;
1247
1248 dec->base = *templ;
1249 dec->base.context = context;
1250 dec->base.width = width;
1251 dec->base.height = height;
1252
1253 dec->base.destroy = ruvd_destroy;
1254 dec->base.begin_frame = ruvd_begin_frame;
1255 dec->base.decode_macroblock = ruvd_decode_macroblock;
1256 dec->base.decode_bitstream = ruvd_decode_bitstream;
1257 dec->base.end_frame = ruvd_end_frame;
1258 dec->base.flush = ruvd_flush;
1259 dec->base.fence_wait = ruvd_dec_fence_wait;
1260 dec->base.destroy_fence = ruvd_dec_destroy_fence;
1261
1262 dec->stream_type = profile2stream_type(dec, sctx->family);
1263 dec->set_dtb = set_dtb;
1264 dec->stream_handle = si_vid_alloc_stream_handle();
1265 dec->screen = context->screen;
1266 dec->ws = ws;
1267
1268 if (!ws->cs_create(&dec->cs, sctx->ctx, AMD_IP_UVD, NULL, NULL)) {
1269 RVID_ERR("Can't get command submission context.\n");
1270 goto error;
1271 }
1272
1273 for (i = 0; i < 16; i++)
1274 dec->render_pic_list[i] = NULL;
1275 dec->fb_size = (sctx->family == CHIP_TONGA) ? FB_BUFFER_SIZE_TONGA : FB_BUFFER_SIZE;
1276 bs_buf_size = align(width * height / 32, 128);
1277 for (i = 0; i < NUM_BUFFERS; ++i) {
1278 unsigned msg_fb_it_size = FB_BUFFER_OFFSET + dec->fb_size;
1279 STATIC_ASSERT(sizeof(struct ruvd_msg) <= FB_BUFFER_OFFSET);
1280 if (have_it(dec))
1281 msg_fb_it_size += IT_SCALING_TABLE_SIZE;
1282 if (!si_vid_create_buffer(dec->screen, &dec->msg_fb_it_buffers[i], msg_fb_it_size,
1283 PIPE_USAGE_STAGING)) {
1284 RVID_ERR("Can't allocated message buffers.\n");
1285 goto error;
1286 }
1287
1288 if (!si_vid_create_buffer(dec->screen, &dec->bs_buffers[i], bs_buf_size,
1289 PIPE_USAGE_STAGING)) {
1290 RVID_ERR("Can't allocated bitstream buffers.\n");
1291 goto error;
1292 }
1293 }
1294
1295 dpb_size = calc_dpb_size(dec);
1296 if (dpb_size) {
1297 if (!si_vid_create_buffer(dec->screen, &dec->dpb, dpb_size, PIPE_USAGE_DEFAULT)) {
1298 RVID_ERR("Can't allocated dpb.\n");
1299 goto error;
1300 }
1301 }
1302
1303 if (dec->stream_type == RUVD_CODEC_H264_PERF && sctx->family >= CHIP_POLARIS10) {
1304 unsigned ctx_size = calc_ctx_size_h264_perf(dec);
1305 if (!si_vid_create_buffer(dec->screen, &dec->ctx, ctx_size, PIPE_USAGE_DEFAULT)) {
1306 RVID_ERR("Can't allocated context buffer.\n");
1307 goto error;
1308 }
1309 }
1310
1311 if (sctx->family >= CHIP_POLARIS10) {
1312 if (!si_vid_create_buffer(dec->screen, &dec->sessionctx, UVD_SESSION_CONTEXT_SIZE,
1313 PIPE_USAGE_DEFAULT)) {
1314 RVID_ERR("Can't allocated session ctx.\n");
1315 goto error;
1316 }
1317 }
1318
1319 if (sctx->family >= CHIP_VEGA10) {
1320 dec->reg.data0 = RUVD_GPCOM_VCPU_DATA0_SOC15;
1321 dec->reg.data1 = RUVD_GPCOM_VCPU_DATA1_SOC15;
1322 dec->reg.cmd = RUVD_GPCOM_VCPU_CMD_SOC15;
1323 dec->reg.cntl = RUVD_ENGINE_CNTL_SOC15;
1324 } else {
1325 dec->reg.data0 = RUVD_GPCOM_VCPU_DATA0;
1326 dec->reg.data1 = RUVD_GPCOM_VCPU_DATA1;
1327 dec->reg.cmd = RUVD_GPCOM_VCPU_CMD;
1328 dec->reg.cntl = RUVD_ENGINE_CNTL;
1329 }
1330
1331 map_msg_fb_it_buf(dec);
1332 dec->msg->size = sizeof(*dec->msg);
1333 dec->msg->msg_type = RUVD_MSG_CREATE;
1334 dec->msg->stream_handle = dec->stream_handle;
1335 dec->msg->body.create.stream_type = dec->stream_type;
1336 dec->msg->body.create.width_in_samples = dec->base.width;
1337 dec->msg->body.create.height_in_samples = dec->base.height;
1338 dec->msg->body.create.dpb_size = dpb_size;
1339 send_msg_buf(dec);
1340 r = flush(dec, 0, NULL);
1341 if (r)
1342 goto error;
1343
1344 next_buffer(dec);
1345
1346 return &dec->base;
1347
1348 error:
1349 dec->ws->cs_destroy(&dec->cs);
1350
1351 for (i = 0; i < NUM_BUFFERS; ++i) {
1352 si_vid_destroy_buffer(&dec->msg_fb_it_buffers[i]);
1353 si_vid_destroy_buffer(&dec->bs_buffers[i]);
1354 }
1355
1356 si_vid_destroy_buffer(&dec->dpb);
1357 si_vid_destroy_buffer(&dec->ctx);
1358 si_vid_destroy_buffer(&dec->sessionctx);
1359
1360 FREE(dec);
1361
1362 return NULL;
1363 }
1364
1365 /* calculate top/bottom offset */
texture_offset(struct radeon_surf * surface,unsigned layer,enum ruvd_surface_type type)1366 static unsigned texture_offset(struct radeon_surf *surface, unsigned layer,
1367 enum ruvd_surface_type type)
1368 {
1369 switch (type) {
1370 default:
1371 case RUVD_SURFACE_TYPE_LEGACY:
1372 return (uint64_t)surface->u.legacy.level[0].offset_256B * 256 +
1373 layer * (uint64_t)surface->u.legacy.level[0].slice_size_dw * 4;
1374 break;
1375 case RUVD_SURFACE_TYPE_GFX9:
1376 return surface->u.gfx9.surf_offset + layer * surface->u.gfx9.surf_slice_size;
1377 break;
1378 }
1379 }
1380
1381 /* hw encode the aspect of macro tiles */
macro_tile_aspect(unsigned macro_tile_aspect)1382 static unsigned macro_tile_aspect(unsigned macro_tile_aspect)
1383 {
1384 switch (macro_tile_aspect) {
1385 default:
1386 case 1:
1387 macro_tile_aspect = 0;
1388 break;
1389 case 2:
1390 macro_tile_aspect = 1;
1391 break;
1392 case 4:
1393 macro_tile_aspect = 2;
1394 break;
1395 case 8:
1396 macro_tile_aspect = 3;
1397 break;
1398 }
1399 return macro_tile_aspect;
1400 }
1401
1402 /* hw encode the bank width and height */
bank_wh(unsigned bankwh)1403 static unsigned bank_wh(unsigned bankwh)
1404 {
1405 switch (bankwh) {
1406 default:
1407 case 1:
1408 bankwh = 0;
1409 break;
1410 case 2:
1411 bankwh = 1;
1412 break;
1413 case 4:
1414 bankwh = 2;
1415 break;
1416 case 8:
1417 bankwh = 3;
1418 break;
1419 }
1420 return bankwh;
1421 }
1422
1423 /**
1424 * fill decoding target field from the luma and chroma surfaces
1425 */
si_uvd_set_dt_surfaces(struct ruvd_msg * msg,struct radeon_surf * luma,struct radeon_surf * chroma,enum ruvd_surface_type type)1426 void si_uvd_set_dt_surfaces(struct ruvd_msg *msg, struct radeon_surf *luma,
1427 struct radeon_surf *chroma, enum ruvd_surface_type type)
1428 {
1429 switch (type) {
1430 default:
1431 case RUVD_SURFACE_TYPE_LEGACY:
1432 msg->body.decode.dt_pitch = luma->u.legacy.level[0].nblk_x * luma->blk_w;
1433 switch (luma->u.legacy.level[0].mode) {
1434 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1435 msg->body.decode.dt_tiling_mode = RUVD_TILE_LINEAR;
1436 msg->body.decode.dt_array_mode = RUVD_ARRAY_MODE_LINEAR;
1437 break;
1438 case RADEON_SURF_MODE_1D:
1439 msg->body.decode.dt_tiling_mode = RUVD_TILE_8X8;
1440 msg->body.decode.dt_array_mode = RUVD_ARRAY_MODE_1D_THIN;
1441 break;
1442 case RADEON_SURF_MODE_2D:
1443 msg->body.decode.dt_tiling_mode = RUVD_TILE_8X8;
1444 msg->body.decode.dt_array_mode = RUVD_ARRAY_MODE_2D_THIN;
1445 break;
1446 default:
1447 assert(0);
1448 break;
1449 }
1450
1451 msg->body.decode.dt_luma_top_offset = texture_offset(luma, 0, type);
1452 if (chroma)
1453 msg->body.decode.dt_chroma_top_offset = texture_offset(chroma, 0, type);
1454 if (msg->body.decode.dt_field_mode) {
1455 msg->body.decode.dt_luma_bottom_offset = texture_offset(luma, 1, type);
1456 if (chroma)
1457 msg->body.decode.dt_chroma_bottom_offset = texture_offset(chroma, 1, type);
1458 } else {
1459 msg->body.decode.dt_luma_bottom_offset = msg->body.decode.dt_luma_top_offset;
1460 msg->body.decode.dt_chroma_bottom_offset = msg->body.decode.dt_chroma_top_offset;
1461 }
1462
1463 if (chroma) {
1464 assert(luma->u.legacy.bankw == chroma->u.legacy.bankw);
1465 assert(luma->u.legacy.bankh == chroma->u.legacy.bankh);
1466 assert(luma->u.legacy.mtilea == chroma->u.legacy.mtilea);
1467 }
1468
1469 msg->body.decode.dt_surf_tile_config |= RUVD_BANK_WIDTH(bank_wh(luma->u.legacy.bankw));
1470 msg->body.decode.dt_surf_tile_config |= RUVD_BANK_HEIGHT(bank_wh(luma->u.legacy.bankh));
1471 msg->body.decode.dt_surf_tile_config |=
1472 RUVD_MACRO_TILE_ASPECT_RATIO(macro_tile_aspect(luma->u.legacy.mtilea));
1473 break;
1474 case RUVD_SURFACE_TYPE_GFX9:
1475 msg->body.decode.dt_pitch = luma->u.gfx9.surf_pitch * luma->blk_w;
1476 msg->body.decode.dt_wa_chroma_bottom_offset = luma->u.gfx9.swizzle_mode;
1477 msg->body.decode.dt_luma_top_offset = texture_offset(luma, 0, type);
1478 msg->body.decode.dt_chroma_top_offset = texture_offset(chroma, 0, type);
1479 if (msg->body.decode.dt_field_mode) {
1480 msg->body.decode.dt_luma_bottom_offset = texture_offset(luma, 1, type);
1481 msg->body.decode.dt_chroma_bottom_offset = texture_offset(chroma, 1, type);
1482 } else {
1483 msg->body.decode.dt_luma_bottom_offset = msg->body.decode.dt_luma_top_offset;
1484 msg->body.decode.dt_chroma_bottom_offset = msg->body.decode.dt_chroma_top_offset;
1485 }
1486 msg->body.decode.dt_surf_tile_config = 0;
1487 break;
1488 }
1489 }
1490