1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * SPDX-License-Identifier: MIT
5 */
6
7 #include "ac_rtld.h"
8 #include "amd_kernel_code_t.h"
9 #include "nir/tgsi_to_nir.h"
10 #include "si_build_pm4.h"
11 #include "si_shader_internal.h"
12 #include "util/u_async_debug.h"
13 #include "util/u_memory.h"
14 #include "util/u_upload_mgr.h"
15 #include "si_tracepoints.h"
16
17 #define COMPUTE_DBG(sscreen, fmt, args...) \
18 do { \
19 if ((sscreen->debug_flags & DBG(COMPUTE))) \
20 fprintf(stderr, fmt, ##args); \
21 } while (0);
22
23 struct dispatch_packet {
24 uint16_t header;
25 uint16_t setup;
26 uint16_t workgroup_size_x;
27 uint16_t workgroup_size_y;
28 uint16_t workgroup_size_z;
29 uint16_t reserved0;
30 uint32_t grid_size_x;
31 uint32_t grid_size_y;
32 uint32_t grid_size_z;
33 uint32_t group_segment_size;
34 uint64_t kernel_object;
35 uint64_t kernarg_address;
36 uint64_t reserved2;
37 };
38
si_compute_get_code_object(const struct si_compute * program,uint64_t symbol_offset)39 static const amd_kernel_code_t *si_compute_get_code_object(const struct si_compute *program,
40 uint64_t symbol_offset)
41 {
42 const struct si_shader_selector *sel = &program->sel;
43
44 if (program->ir_type != PIPE_SHADER_IR_NATIVE)
45 return NULL;
46
47 struct ac_rtld_binary rtld;
48 if (!ac_rtld_open(&rtld,
49 (struct ac_rtld_open_info){.info = &sel->screen->info,
50 .shader_type = MESA_SHADER_COMPUTE,
51 .num_parts = 1,
52 .elf_ptrs = &program->shader.binary.code_buffer,
53 .elf_sizes = &program->shader.binary.code_size}))
54 return NULL;
55
56 const amd_kernel_code_t *result = NULL;
57 const char *text;
58 size_t size;
59 if (!ac_rtld_get_section_by_name(&rtld, ".text", &text, &size))
60 goto out;
61
62 if (symbol_offset + sizeof(amd_kernel_code_t) > size)
63 goto out;
64
65 result = (const amd_kernel_code_t *)(text + symbol_offset);
66
67 out:
68 ac_rtld_close(&rtld);
69 return result;
70 }
71
code_object_to_config(const amd_kernel_code_t * code_object,struct ac_shader_config * out_config)72 static void code_object_to_config(const amd_kernel_code_t *code_object,
73 struct ac_shader_config *out_config)
74 {
75
76 uint32_t rsrc1 = code_object->compute_pgm_resource_registers;
77 uint32_t rsrc2 = code_object->compute_pgm_resource_registers >> 32;
78 out_config->num_sgprs = code_object->wavefront_sgpr_count;
79 out_config->num_vgprs = code_object->workitem_vgpr_count;
80 out_config->float_mode = G_00B028_FLOAT_MODE(rsrc1);
81 out_config->rsrc1 = rsrc1;
82 out_config->lds_size = MAX2(out_config->lds_size, G_00B84C_LDS_SIZE(rsrc2));
83 out_config->rsrc2 = rsrc2;
84 out_config->scratch_bytes_per_wave =
85 align(code_object->workitem_private_segment_byte_size * 64, 1024);
86 }
87
88 /* Asynchronous compute shader compilation. */
si_create_compute_state_async(void * job,void * gdata,int thread_index)89 static void si_create_compute_state_async(void *job, void *gdata, int thread_index)
90 {
91 struct si_compute *program = (struct si_compute *)job;
92 struct si_shader_selector *sel = &program->sel;
93 struct si_shader *shader = &program->shader;
94 struct ac_llvm_compiler **compiler;
95 struct util_debug_callback *debug = &sel->compiler_ctx_state.debug;
96 struct si_screen *sscreen = sel->screen;
97
98 assert(!debug->debug_message || debug->async);
99 assert(thread_index >= 0);
100 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
101 compiler = &sscreen->compiler[thread_index];
102
103 assert(program->ir_type == PIPE_SHADER_IR_NIR);
104 si_nir_scan_shader(sscreen, sel->nir, &sel->info, false);
105
106 if (!sel->nir->info.use_aco_amd && !*compiler)
107 *compiler = si_create_llvm_compiler(sscreen);
108
109 si_get_active_slot_masks(sscreen, &sel->info, &sel->active_const_and_shader_buffers,
110 &sel->active_samplers_and_images);
111
112 program->shader.is_monolithic = true;
113 program->shader.wave_size = si_determine_wave_size(sscreen, &program->shader);
114
115 /* Variable block sizes need 10 bits (1 + log2(SI_MAX_VARIABLE_THREADS_PER_BLOCK)) per dim.
116 * We pack them into a single user SGPR.
117 */
118 unsigned user_sgprs = SI_NUM_RESOURCE_SGPRS + (sel->info.uses_grid_size ? 3 : 0) +
119 (sel->info.uses_variable_block_size ? 1 : 0) +
120 sel->nir->info.cs.user_data_components_amd;
121
122 /* Fast path for compute shaders - some descriptors passed via user SGPRs. */
123 /* Shader buffers in user SGPRs. */
124 for (unsigned i = 0; i < MIN2(3, sel->nir->info.num_ssbos) && user_sgprs <= 12; i++) {
125 user_sgprs = align(user_sgprs, 4);
126 if (i == 0)
127 sel->cs_shaderbufs_sgpr_index = user_sgprs;
128 user_sgprs += 4;
129 sel->cs_num_shaderbufs_in_user_sgprs++;
130 }
131
132 /* Images in user SGPRs. */
133 unsigned non_fmask_images = u_bit_consecutive(0, sel->nir->info.num_images);
134
135 /* Remove images with FMASK from the bitmask. We only care about the first
136 * 3 anyway, so we can take msaa_images[0] and ignore the rest.
137 */
138 if (sscreen->info.gfx_level < GFX11)
139 non_fmask_images &= ~sel->nir->info.msaa_images[0];
140
141 for (unsigned i = 0; i < 3 && non_fmask_images & (1 << i); i++) {
142 unsigned num_sgprs = BITSET_TEST(sel->nir->info.image_buffers, i) ? 4 : 8;
143
144 if (align(user_sgprs, num_sgprs) + num_sgprs > 16)
145 break;
146
147 user_sgprs = align(user_sgprs, num_sgprs);
148 if (i == 0)
149 sel->cs_images_sgpr_index = user_sgprs;
150 user_sgprs += num_sgprs;
151 sel->cs_num_images_in_user_sgprs++;
152 }
153 sel->cs_images_num_sgprs = user_sgprs - sel->cs_images_sgpr_index;
154 assert(user_sgprs <= 16);
155
156 unsigned char ir_sha1_cache_key[20];
157 si_get_ir_cache_key(sel, false, false, shader->wave_size, ir_sha1_cache_key);
158
159 /* Try to load the shader from the shader cache. */
160 simple_mtx_lock(&sscreen->shader_cache_mutex);
161
162 if (si_shader_cache_load_shader(sscreen, ir_sha1_cache_key, shader)) {
163 simple_mtx_unlock(&sscreen->shader_cache_mutex);
164
165 shader->complete_shader_binary_size = si_get_shader_binary_size(sscreen, shader);
166
167 if (!si_shader_binary_upload(sscreen, shader, 0))
168 program->shader.compilation_failed = true;
169
170 si_shader_dump_stats_for_shader_db(sscreen, shader, debug);
171 si_shader_dump(sscreen, shader, debug, stderr, true);
172 } else {
173 simple_mtx_unlock(&sscreen->shader_cache_mutex);
174
175 if (!si_create_shader_variant(sscreen, *compiler, &program->shader, debug)) {
176 program->shader.compilation_failed = true;
177 return;
178 }
179
180 shader->config.rsrc1 = S_00B848_VGPRS((shader->config.num_vgprs - 1) /
181 ((shader->wave_size == 32 ||
182 sscreen->info.wave64_vgpr_alloc_granularity == 8) ? 8 : 4)) |
183 S_00B848_DX10_CLAMP(sscreen->info.gfx_level < GFX12) |
184 S_00B848_MEM_ORDERED(si_shader_mem_ordered(shader)) |
185 S_00B848_FLOAT_MODE(shader->config.float_mode) |
186 /* This is needed for CWSR, but it causes halts to work differently. */
187 S_00B848_PRIV(sscreen->info.gfx_level == GFX11);
188
189 if (sscreen->info.gfx_level < GFX10) {
190 shader->config.rsrc1 |= S_00B848_SGPRS((shader->config.num_sgprs - 1) / 8);
191 }
192
193 shader->config.rsrc2 = S_00B84C_USER_SGPR(user_sgprs) |
194 S_00B84C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0) |
195 S_00B84C_TGID_X_EN(sel->info.uses_block_id[0]) |
196 S_00B84C_TGID_Y_EN(sel->info.uses_block_id[1]) |
197 S_00B84C_TGID_Z_EN(sel->info.uses_block_id[2]) |
198 S_00B84C_TG_SIZE_EN(sel->info.uses_tg_size) |
199 S_00B84C_TIDIG_COMP_CNT(sel->info.uses_thread_id[2]
200 ? 2
201 : sel->info.uses_thread_id[1] ? 1 : 0) |
202 S_00B84C_LDS_SIZE(shader->config.lds_size);
203
204 /* COMPUTE_PGM_RSRC3 is only present on GFX10+ and GFX940+. */
205 shader->config.rsrc3 = S_00B8A0_SHARED_VGPR_CNT(shader->config.num_shared_vgprs / 8);
206
207 if (sscreen->info.gfx_level >= GFX12)
208 shader->config.rsrc3 |= S_00B8A0_INST_PREF_SIZE_GFX12(si_get_shader_prefetch_size(shader));
209 else if (sscreen->info.gfx_level >= GFX11)
210 shader->config.rsrc3 |= S_00B8A0_INST_PREF_SIZE_GFX11(si_get_shader_prefetch_size(shader));
211
212 simple_mtx_lock(&sscreen->shader_cache_mutex);
213 si_shader_cache_insert_shader(sscreen, ir_sha1_cache_key, shader, true);
214 simple_mtx_unlock(&sscreen->shader_cache_mutex);
215 }
216
217 ralloc_free(sel->nir);
218 sel->nir = NULL;
219 }
220
si_create_compute_state(struct pipe_context * ctx,const struct pipe_compute_state * cso)221 static void *si_create_compute_state(struct pipe_context *ctx, const struct pipe_compute_state *cso)
222 {
223 struct si_context *sctx = (struct si_context *)ctx;
224 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
225 struct si_compute *program = CALLOC_STRUCT(si_compute);
226 struct si_shader_selector *sel = &program->sel;
227
228 pipe_reference_init(&sel->base.reference, 1);
229 sel->stage = MESA_SHADER_COMPUTE;
230 sel->screen = sscreen;
231 simple_mtx_init(&sel->mutex, mtx_plain);
232 sel->const_and_shader_buf_descriptors_index =
233 si_const_and_shader_buffer_descriptors_idx(PIPE_SHADER_COMPUTE);
234 sel->sampler_and_images_descriptors_index =
235 si_sampler_and_image_descriptors_idx(PIPE_SHADER_COMPUTE);
236 sel->info.base.shared_size = cso->static_shared_mem;
237 program->shader.selector = &program->sel;
238 program->ir_type = cso->ir_type;
239 program->input_size = cso->req_input_mem;
240
241 if (cso->ir_type != PIPE_SHADER_IR_NATIVE) {
242 if (cso->ir_type == PIPE_SHADER_IR_TGSI) {
243 program->ir_type = PIPE_SHADER_IR_NIR;
244 sel->nir = tgsi_to_nir(cso->prog, ctx->screen, true);
245 } else {
246 assert(cso->ir_type == PIPE_SHADER_IR_NIR);
247 sel->nir = (struct nir_shader *)cso->prog;
248 }
249
250 sel->nir->info.shared_size = cso->static_shared_mem;
251
252 if (si_can_dump_shader(sscreen, sel->stage, SI_DUMP_INIT_NIR))
253 nir_print_shader(sel->nir, stderr);
254
255 sel->compiler_ctx_state.debug = sctx->debug;
256 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
257 p_atomic_inc(&sscreen->num_shaders_created);
258
259 si_schedule_initial_compile(sctx, MESA_SHADER_COMPUTE, &sel->ready, &sel->compiler_ctx_state,
260 program, si_create_compute_state_async);
261 } else {
262 const struct pipe_binary_program_header *header;
263 header = cso->prog;
264
265 program->shader.binary.type = SI_SHADER_BINARY_ELF;
266 program->shader.binary.code_size = header->num_bytes;
267 program->shader.binary.code_buffer = malloc(header->num_bytes);
268 if (!program->shader.binary.code_buffer) {
269 FREE(program);
270 return NULL;
271 }
272 memcpy((void *)program->shader.binary.code_buffer, header->blob, header->num_bytes);
273
274 const amd_kernel_code_t *code_object = si_compute_get_code_object(program, 0);
275 code_object_to_config(code_object, &program->shader.config);
276
277 if (AMD_HSA_BITS_GET(code_object->code_properties, AMD_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32))
278 program->shader.wave_size = 32;
279 else
280 program->shader.wave_size = 64;
281
282 bool ok = si_shader_binary_upload(sctx->screen, &program->shader, 0);
283 si_shader_dump(sctx->screen, &program->shader, &sctx->debug, stderr, true);
284
285 if (!ok) {
286 fprintf(stderr, "LLVM failed to upload shader\n");
287 free((void *)program->shader.binary.code_buffer);
288 FREE(program);
289 return NULL;
290 }
291 }
292
293 return program;
294 }
295
si_get_compute_state_info(struct pipe_context * ctx,void * state,struct pipe_compute_state_object_info * info)296 static void si_get_compute_state_info(struct pipe_context *ctx, void *state,
297 struct pipe_compute_state_object_info *info)
298 {
299 struct si_compute *program = (struct si_compute *)state;
300 struct si_shader_selector *sel = &program->sel;
301
302 assert(program->ir_type != PIPE_SHADER_IR_NATIVE);
303
304 /* Wait because we need the compilation to finish first */
305 util_queue_fence_wait(&sel->ready);
306
307 uint8_t wave_size = program->shader.wave_size;
308 info->private_memory = DIV_ROUND_UP(program->shader.config.scratch_bytes_per_wave, wave_size);
309 info->preferred_simd_size = wave_size;
310 info->simd_sizes = wave_size;
311 info->max_threads = si_get_max_workgroup_size(&program->shader);
312 }
313
si_bind_compute_state(struct pipe_context * ctx,void * state)314 static void si_bind_compute_state(struct pipe_context *ctx, void *state)
315 {
316 struct si_context *sctx = (struct si_context *)ctx;
317 struct si_compute *program = (struct si_compute *)state;
318 struct si_shader_selector *sel = &program->sel;
319
320 sctx->cs_shader_state.program = program;
321 if (!program)
322 return;
323
324 /* Wait because we need active slot usage masks. */
325 if (program->ir_type != PIPE_SHADER_IR_NATIVE)
326 util_queue_fence_wait(&sel->ready);
327
328 si_set_active_descriptors(sctx,
329 SI_DESCS_FIRST_COMPUTE + SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS,
330 sel->active_const_and_shader_buffers);
331 si_set_active_descriptors(sctx, SI_DESCS_FIRST_COMPUTE + SI_SHADER_DESCS_SAMPLERS_AND_IMAGES,
332 sel->active_samplers_and_images);
333
334 sctx->compute_shaderbuf_sgprs_dirty = true;
335 sctx->compute_image_sgprs_dirty = true;
336
337 if (unlikely((sctx->screen->debug_flags & DBG(SQTT)) && sctx->sqtt)) {
338 uint32_t pipeline_code_hash = _mesa_hash_data_with_seed(
339 program->shader.binary.code_buffer,
340 program->shader.binary.code_size,
341 0);
342
343 if (!si_sqtt_pipeline_is_registered(sctx->sqtt, pipeline_code_hash)) {
344 /* Short lived fake pipeline: we don't need to reupload the compute shaders,
345 * as we do for the gfx ones so just create a temp pipeline to be able to
346 * call si_sqtt_register_pipeline, and then drop it.
347 */
348 struct si_sqtt_fake_pipeline pipeline = { 0 };
349 pipeline.code_hash = pipeline_code_hash;
350 pipeline.bo = program->shader.bo;
351
352 si_sqtt_register_pipeline(sctx, &pipeline, NULL);
353 }
354
355 si_sqtt_describe_pipeline_bind(sctx, pipeline_code_hash, 1);
356 }
357 }
358
si_set_global_binding(struct pipe_context * ctx,unsigned first,unsigned n,struct pipe_resource ** resources,uint32_t ** handles)359 static void si_set_global_binding(struct pipe_context *ctx, unsigned first, unsigned n,
360 struct pipe_resource **resources, uint32_t **handles)
361 {
362 unsigned i;
363 struct si_context *sctx = (struct si_context *)ctx;
364
365 if (first + n > sctx->max_global_buffers) {
366 unsigned old_max = sctx->max_global_buffers;
367 sctx->max_global_buffers = first + n;
368 sctx->global_buffers = realloc(
369 sctx->global_buffers, sctx->max_global_buffers * sizeof(sctx->global_buffers[0]));
370 if (!sctx->global_buffers) {
371 fprintf(stderr, "radeonsi: failed to allocate compute global_buffers\n");
372 return;
373 }
374
375 memset(&sctx->global_buffers[old_max], 0,
376 (sctx->max_global_buffers - old_max) * sizeof(sctx->global_buffers[0]));
377 }
378
379 if (!resources) {
380 for (i = 0; i < n; i++) {
381 pipe_resource_reference(&sctx->global_buffers[first + i], NULL);
382 }
383 return;
384 }
385
386 for (i = 0; i < n; i++) {
387 uint64_t va;
388 uint32_t offset;
389 pipe_resource_reference(&sctx->global_buffers[first + i], resources[i]);
390 va = si_resource(resources[i])->gpu_address;
391 offset = util_le32_to_cpu(*handles[i]);
392 va += offset;
393 va = util_cpu_to_le64(va);
394 memcpy(handles[i], &va, sizeof(va));
395 }
396 }
397
si_setup_compute_scratch_buffer(struct si_context * sctx,struct si_shader * shader)398 static bool si_setup_compute_scratch_buffer(struct si_context *sctx, struct si_shader *shader)
399 {
400 uint64_t scratch_bo_size =
401 sctx->compute_scratch_buffer ? sctx->compute_scratch_buffer->b.b.width0 : 0;
402 uint64_t scratch_needed = sctx->max_seen_compute_scratch_bytes_per_wave *
403 sctx->screen->info.max_scratch_waves;
404 assert(scratch_needed);
405
406 if (scratch_bo_size < scratch_needed) {
407 si_resource_reference(&sctx->compute_scratch_buffer, NULL);
408
409 sctx->compute_scratch_buffer =
410 si_aligned_buffer_create(&sctx->screen->b,
411 PIPE_RESOURCE_FLAG_UNMAPPABLE | SI_RESOURCE_FLAG_DRIVER_INTERNAL |
412 SI_RESOURCE_FLAG_DISCARDABLE,
413 PIPE_USAGE_DEFAULT,
414 scratch_needed, sctx->screen->info.pte_fragment_size);
415
416 if (!sctx->compute_scratch_buffer)
417 return false;
418 }
419
420 /* Set the scratch address in the shader binary. */
421 if (!sctx->screen->info.has_scratch_base_registers) {
422 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
423
424 if (shader->scratch_va != scratch_va) {
425 if (!si_shader_binary_upload(sctx->screen, shader, scratch_va))
426 return false;
427
428 shader->scratch_va = scratch_va;
429 }
430 }
431
432 return true;
433 }
434
si_switch_compute_shader(struct si_context * sctx,struct si_compute * program,struct si_shader * shader,const amd_kernel_code_t * code_object,unsigned offset,bool * prefetch,unsigned variable_shared_size)435 static bool si_switch_compute_shader(struct si_context *sctx, struct si_compute *program,
436 struct si_shader *shader, const amd_kernel_code_t *code_object,
437 unsigned offset, bool *prefetch, unsigned variable_shared_size)
438 {
439 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
440 struct ac_shader_config inline_config = {0};
441 const struct ac_shader_config *config;
442 unsigned rsrc2;
443 uint64_t shader_va;
444 unsigned stage = shader->selector->info.base.stage;
445
446 *prefetch = false;
447
448 assert(variable_shared_size == 0 || stage == MESA_SHADER_KERNEL || program->ir_type == PIPE_SHADER_IR_NATIVE);
449 if (sctx->cs_shader_state.emitted_program == program && sctx->cs_shader_state.offset == offset &&
450 sctx->cs_shader_state.variable_shared_size == variable_shared_size)
451 return true;
452
453 if (program->ir_type != PIPE_SHADER_IR_NATIVE) {
454 config = &shader->config;
455 } else {
456 code_object_to_config(code_object, &inline_config);
457 config = &inline_config;
458 }
459 /* copy rsrc2 so we don't have to change it inside the si_shader object */
460 rsrc2 = config->rsrc2;
461
462 /* only do this for OpenCL */
463 if (program->ir_type == PIPE_SHADER_IR_NATIVE || stage == MESA_SHADER_KERNEL) {
464 unsigned shared_size = program->sel.info.base.shared_size + variable_shared_size;
465 unsigned lds_blocks;
466
467 /* Clover uses the compute API differently than other frontends and expects drivers to parse
468 * the shared_size out of the shader headers.
469 */
470 if (program->ir_type == PIPE_SHADER_IR_NATIVE) {
471 lds_blocks = config->lds_size;
472 } else {
473 lds_blocks = 0;
474 }
475
476 /* XXX: We are over allocating LDS. For GFX6, the shader reports
477 * LDS in blocks of 256 bytes, so if there are 4 bytes lds
478 * allocated in the shader and 4 bytes allocated by the state
479 * tracker, then we will set LDS_SIZE to 512 bytes rather than 256.
480 */
481 if (sctx->gfx_level <= GFX6) {
482 lds_blocks += align(shared_size, 256) >> 8;
483 } else {
484 lds_blocks += align(shared_size, 512) >> 9;
485 }
486
487 /* TODO: use si_multiwave_lds_size_workaround */
488 assert(lds_blocks <= 0xFF);
489
490 rsrc2 &= C_00B84C_LDS_SIZE;
491 rsrc2 |= S_00B84C_LDS_SIZE(lds_blocks);
492 }
493
494 if (config->scratch_bytes_per_wave) {
495 /* Prevent race conditions for accesses to shader->scratch_va and shader->bo, which
496 * can change when scratch_va is updated. Any accesses to shader->bo must also be inside
497 * the lock.
498 *
499 * TODO: This lock could be removed if the scratch address was passed via user SGPRs instead
500 * of the shader binary.
501 */
502 if (!sctx->screen->info.has_scratch_base_registers)
503 simple_mtx_lock(&shader->selector->mutex);
504
505 /* Update max_seen_compute_scratch_bytes_per_wave and compute_tmpring_size. */
506 ac_get_scratch_tmpring_size(&sctx->screen->info,
507 config->scratch_bytes_per_wave,
508 &sctx->max_seen_compute_scratch_bytes_per_wave,
509 &sctx->compute_tmpring_size);
510
511 if (!si_setup_compute_scratch_buffer(sctx, shader))
512 return false;
513
514 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, sctx->compute_scratch_buffer,
515 RADEON_USAGE_READWRITE | RADEON_PRIO_SCRATCH_BUFFER);
516 }
517
518 shader_va = shader->bo->gpu_address + offset;
519 if (program->ir_type == PIPE_SHADER_IR_NATIVE) {
520 /* Shader code is placed after the amd_kernel_code_t
521 * struct. */
522 shader_va += sizeof(amd_kernel_code_t);
523 }
524
525 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, shader->bo,
526 RADEON_USAGE_READ | RADEON_PRIO_SHADER_BINARY);
527
528 /* shader->bo can't be used after this if the scratch address is inserted into the shader
529 * binary.
530 */
531 if (config->scratch_bytes_per_wave && !sctx->screen->info.has_scratch_base_registers)
532 simple_mtx_unlock(&shader->selector->mutex);
533
534 if (sctx->gfx_level >= GFX12) {
535 gfx12_push_compute_sh_reg(R_00B830_COMPUTE_PGM_LO, shader_va >> 8);
536 gfx12_opt_push_compute_sh_reg(R_00B848_COMPUTE_PGM_RSRC1,
537 SI_TRACKED_COMPUTE_PGM_RSRC1, config->rsrc1);
538 gfx12_opt_push_compute_sh_reg(R_00B84C_COMPUTE_PGM_RSRC2,
539 SI_TRACKED_COMPUTE_PGM_RSRC2, rsrc2);
540 gfx12_opt_push_compute_sh_reg(R_00B8A0_COMPUTE_PGM_RSRC3,
541 SI_TRACKED_COMPUTE_PGM_RSRC3, config->rsrc3);
542 gfx12_opt_push_compute_sh_reg(R_00B860_COMPUTE_TMPRING_SIZE,
543 SI_TRACKED_COMPUTE_TMPRING_SIZE, sctx->compute_tmpring_size);
544 if (config->scratch_bytes_per_wave) {
545 gfx12_opt_push_compute_sh_reg(R_00B840_COMPUTE_DISPATCH_SCRATCH_BASE_LO,
546 SI_TRACKED_COMPUTE_DISPATCH_SCRATCH_BASE_LO,
547 sctx->compute_scratch_buffer->gpu_address >> 8);
548 gfx12_opt_push_compute_sh_reg(R_00B844_COMPUTE_DISPATCH_SCRATCH_BASE_HI,
549 SI_TRACKED_COMPUTE_DISPATCH_SCRATCH_BASE_HI,
550 sctx->compute_scratch_buffer->gpu_address >> 40);
551 }
552 } else if (sctx->screen->info.has_set_sh_pairs_packed) {
553 gfx11_push_compute_sh_reg(R_00B830_COMPUTE_PGM_LO, shader_va >> 8);
554 gfx11_opt_push_compute_sh_reg(R_00B848_COMPUTE_PGM_RSRC1,
555 SI_TRACKED_COMPUTE_PGM_RSRC1, config->rsrc1);
556 gfx11_opt_push_compute_sh_reg(R_00B84C_COMPUTE_PGM_RSRC2,
557 SI_TRACKED_COMPUTE_PGM_RSRC2, rsrc2);
558 gfx11_opt_push_compute_sh_reg(R_00B8A0_COMPUTE_PGM_RSRC3,
559 SI_TRACKED_COMPUTE_PGM_RSRC3, config->rsrc3);
560 gfx11_opt_push_compute_sh_reg(R_00B860_COMPUTE_TMPRING_SIZE,
561 SI_TRACKED_COMPUTE_TMPRING_SIZE, sctx->compute_tmpring_size);
562 if (config->scratch_bytes_per_wave) {
563 gfx11_opt_push_compute_sh_reg(R_00B840_COMPUTE_DISPATCH_SCRATCH_BASE_LO,
564 SI_TRACKED_COMPUTE_DISPATCH_SCRATCH_BASE_LO,
565 sctx->compute_scratch_buffer->gpu_address >> 8);
566 gfx11_opt_push_compute_sh_reg(R_00B844_COMPUTE_DISPATCH_SCRATCH_BASE_HI,
567 SI_TRACKED_COMPUTE_DISPATCH_SCRATCH_BASE_HI,
568 sctx->compute_scratch_buffer->gpu_address >> 40);
569 }
570 } else {
571 radeon_begin(cs);
572 radeon_set_sh_reg(R_00B830_COMPUTE_PGM_LO, shader_va >> 8);
573 radeon_opt_set_sh_reg2(R_00B848_COMPUTE_PGM_RSRC1,
574 SI_TRACKED_COMPUTE_PGM_RSRC1,
575 config->rsrc1, rsrc2);
576 radeon_opt_set_sh_reg(R_00B860_COMPUTE_TMPRING_SIZE,
577 SI_TRACKED_COMPUTE_TMPRING_SIZE, sctx->compute_tmpring_size);
578
579 if (config->scratch_bytes_per_wave && sctx->screen->info.has_scratch_base_registers) {
580 radeon_opt_set_sh_reg2(R_00B840_COMPUTE_DISPATCH_SCRATCH_BASE_LO,
581 SI_TRACKED_COMPUTE_DISPATCH_SCRATCH_BASE_LO,
582 sctx->compute_scratch_buffer->gpu_address >> 8,
583 sctx->compute_scratch_buffer->gpu_address >> 40);
584 }
585
586 if (sctx->gfx_level >= GFX10) {
587 radeon_opt_set_sh_reg(R_00B8A0_COMPUTE_PGM_RSRC3,
588 SI_TRACKED_COMPUTE_PGM_RSRC3, config->rsrc3);
589 }
590 radeon_end();
591 }
592
593 COMPUTE_DBG(sctx->screen,
594 "COMPUTE_PGM_RSRC1: 0x%08x "
595 "COMPUTE_PGM_RSRC2: 0x%08x\n",
596 config->rsrc1, config->rsrc2);
597
598 sctx->cs_shader_state.emitted_program = program;
599 sctx->cs_shader_state.offset = offset;
600 sctx->cs_shader_state.variable_shared_size = variable_shared_size;
601
602 *prefetch = true;
603 return true;
604 }
605
setup_scratch_rsrc_user_sgprs(struct si_context * sctx,const amd_kernel_code_t * code_object,unsigned user_sgpr)606 static void setup_scratch_rsrc_user_sgprs(struct si_context *sctx,
607 const amd_kernel_code_t *code_object, unsigned user_sgpr)
608 {
609 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
610 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
611
612 unsigned max_private_element_size =
613 AMD_HSA_BITS_GET(code_object->code_properties, AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE);
614
615 uint32_t scratch_dword0 = scratch_va & 0xffffffff;
616 uint32_t scratch_dword1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32);
617
618 if (sctx->gfx_level >= GFX11)
619 scratch_dword1 |= S_008F04_SWIZZLE_ENABLE_GFX11(1);
620 else
621 scratch_dword1 |= S_008F04_SWIZZLE_ENABLE_GFX6(1);
622
623 /* Disable address clamping */
624 uint32_t scratch_dword2 = 0xffffffff;
625 uint32_t index_stride = sctx->cs_shader_state.program->shader.wave_size == 32 ? 2 : 3;
626 uint32_t scratch_dword3 = S_008F0C_INDEX_STRIDE(index_stride) | S_008F0C_ADD_TID_ENABLE(1);
627
628 if (sctx->gfx_level >= GFX9) {
629 assert(max_private_element_size == 1); /* only 4 bytes on GFX9 */
630 } else {
631 scratch_dword3 |= S_008F0C_ELEMENT_SIZE(max_private_element_size);
632
633 if (sctx->gfx_level < GFX8) {
634 /* BUF_DATA_FORMAT is ignored, but it cannot be
635 * BUF_DATA_FORMAT_INVALID. */
636 scratch_dword3 |= S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_8);
637 }
638 }
639
640 radeon_begin(cs);
641 radeon_set_sh_reg_seq(R_00B900_COMPUTE_USER_DATA_0 + (user_sgpr * 4), 4);
642 radeon_emit(scratch_dword0);
643 radeon_emit(scratch_dword1);
644 radeon_emit(scratch_dword2);
645 radeon_emit(scratch_dword3);
646 radeon_end();
647 }
648
si_setup_user_sgprs_co_v2(struct si_context * sctx,const amd_kernel_code_t * code_object,const struct pipe_grid_info * info,uint64_t kernel_args_va)649 static void si_setup_user_sgprs_co_v2(struct si_context *sctx, const amd_kernel_code_t *code_object,
650 const struct pipe_grid_info *info, uint64_t kernel_args_va)
651 {
652 struct si_compute *program = sctx->cs_shader_state.program;
653 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
654
655 static const enum amd_code_property_mask_t workgroup_count_masks[] = {
656 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X,
657 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y,
658 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z};
659
660 unsigned i, user_sgpr = 0;
661 if (AMD_HSA_BITS_GET(code_object->code_properties,
662 AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER)) {
663 if (code_object->workitem_private_segment_byte_size > 0) {
664 setup_scratch_rsrc_user_sgprs(sctx, code_object, user_sgpr);
665 }
666 user_sgpr += 4;
667 }
668
669 radeon_begin(cs);
670
671 if (AMD_HSA_BITS_GET(code_object->code_properties, AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR)) {
672 struct dispatch_packet dispatch;
673 unsigned dispatch_offset;
674 struct si_resource *dispatch_buf = NULL;
675 uint64_t dispatch_va;
676
677 /* Upload dispatch ptr */
678 memset(&dispatch, 0, sizeof(dispatch));
679
680 dispatch.workgroup_size_x = util_cpu_to_le16(info->block[0]);
681 dispatch.workgroup_size_y = util_cpu_to_le16(info->block[1]);
682 dispatch.workgroup_size_z = util_cpu_to_le16(info->block[2]);
683
684 dispatch.grid_size_x = util_cpu_to_le32(info->grid[0] * info->block[0]);
685 dispatch.grid_size_y = util_cpu_to_le32(info->grid[1] * info->block[1]);
686 dispatch.grid_size_z = util_cpu_to_le32(info->grid[2] * info->block[2]);
687
688 dispatch.group_segment_size =
689 util_cpu_to_le32(program->sel.info.base.shared_size + info->variable_shared_mem);
690
691 dispatch.kernarg_address = util_cpu_to_le64(kernel_args_va);
692
693 u_upload_data(sctx->b.const_uploader, 0, sizeof(dispatch), 256, &dispatch, &dispatch_offset,
694 (struct pipe_resource **)&dispatch_buf);
695
696 if (!dispatch_buf) {
697 fprintf(stderr, "Error: Failed to allocate dispatch "
698 "packet.");
699 }
700 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, dispatch_buf,
701 RADEON_USAGE_READ | RADEON_PRIO_CONST_BUFFER);
702
703 dispatch_va = dispatch_buf->gpu_address + dispatch_offset;
704
705 radeon_set_sh_reg_seq(R_00B900_COMPUTE_USER_DATA_0 + (user_sgpr * 4), 2);
706 radeon_emit(dispatch_va);
707 radeon_emit(S_008F04_BASE_ADDRESS_HI(dispatch_va >> 32) | S_008F04_STRIDE(0));
708
709 si_resource_reference(&dispatch_buf, NULL);
710 user_sgpr += 2;
711 }
712
713 if (AMD_HSA_BITS_GET(code_object->code_properties,
714 AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR)) {
715 radeon_set_sh_reg_seq(R_00B900_COMPUTE_USER_DATA_0 + (user_sgpr * 4), 2);
716 radeon_emit(kernel_args_va);
717 radeon_emit(S_008F04_BASE_ADDRESS_HI(kernel_args_va >> 32) | S_008F04_STRIDE(0));
718 user_sgpr += 2;
719 }
720
721 for (i = 0; i < 3 && user_sgpr < 16; i++) {
722 if (code_object->code_properties & workgroup_count_masks[i]) {
723 radeon_set_sh_reg_seq(R_00B900_COMPUTE_USER_DATA_0 + (user_sgpr * 4), 1);
724 radeon_emit(info->grid[i]);
725 user_sgpr += 1;
726 }
727 }
728 radeon_end();
729 }
730
si_upload_compute_input(struct si_context * sctx,const amd_kernel_code_t * code_object,const struct pipe_grid_info * info)731 static bool si_upload_compute_input(struct si_context *sctx, const amd_kernel_code_t *code_object,
732 const struct pipe_grid_info *info)
733 {
734 struct si_compute *program = sctx->cs_shader_state.program;
735 struct si_resource *input_buffer = NULL;
736 uint32_t kernel_args_offset = 0;
737 uint32_t *kernel_args;
738 void *kernel_args_ptr;
739 uint64_t kernel_args_va;
740
741 u_upload_alloc(sctx->b.const_uploader, 0, program->input_size,
742 sctx->screen->info.tcc_cache_line_size, &kernel_args_offset,
743 (struct pipe_resource **)&input_buffer, &kernel_args_ptr);
744
745 if (unlikely(!kernel_args_ptr))
746 return false;
747
748 kernel_args = (uint32_t *)kernel_args_ptr;
749 kernel_args_va = input_buffer->gpu_address + kernel_args_offset;
750
751 memcpy(kernel_args, info->input, program->input_size);
752
753 for (unsigned i = 0; i < program->input_size / 4; i++) {
754 COMPUTE_DBG(sctx->screen, "input %u : %u\n", i, kernel_args[i]);
755 }
756
757 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, input_buffer,
758 RADEON_USAGE_READ | RADEON_PRIO_CONST_BUFFER);
759
760 si_setup_user_sgprs_co_v2(sctx, code_object, info, kernel_args_va);
761 si_resource_reference(&input_buffer, NULL);
762 return true;
763 }
764
si_setup_nir_user_data(struct si_context * sctx,const struct pipe_grid_info * info)765 static void si_setup_nir_user_data(struct si_context *sctx, const struct pipe_grid_info *info)
766 {
767 struct si_compute *program = sctx->cs_shader_state.program;
768 struct si_shader_selector *sel = &program->sel;
769 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
770 unsigned grid_size_reg = R_00B900_COMPUTE_USER_DATA_0 + 4 * SI_NUM_RESOURCE_SGPRS;
771 unsigned block_size_reg = grid_size_reg +
772 /* 12 bytes = 3 dwords. */
773 12 * sel->info.uses_grid_size;
774 unsigned cs_user_data_reg = block_size_reg + 4 * program->sel.info.uses_variable_block_size;
775
776 if (sel->info.uses_grid_size && info->indirect) {
777 for (unsigned i = 0; i < 3; ++i) {
778 si_cp_copy_data(sctx, &sctx->gfx_cs, COPY_DATA_REG, NULL, (grid_size_reg >> 2) + i,
779 COPY_DATA_SRC_MEM, si_resource(info->indirect),
780 info->indirect_offset + 4 * i);
781 }
782 }
783
784 if (sctx->gfx_level >= GFX12) {
785 if (sel->info.uses_grid_size && !info->indirect) {
786 gfx12_push_compute_sh_reg(grid_size_reg, info->grid[0]);
787 gfx12_push_compute_sh_reg(grid_size_reg + 4, info->grid[1]);
788 gfx12_push_compute_sh_reg(grid_size_reg + 8, info->grid[2]);
789 }
790
791 if (sel->info.uses_variable_block_size) {
792 uint32_t value = info->block[0] | (info->block[1] << 10) | (info->block[2] << 20);
793 gfx12_push_compute_sh_reg(block_size_reg, value);
794 }
795
796 if (sel->info.base.cs.user_data_components_amd) {
797 unsigned num = sel->info.base.cs.user_data_components_amd;
798 for (unsigned i = 0; i < num; i++)
799 gfx12_push_compute_sh_reg(cs_user_data_reg + i * 4, sctx->cs_user_data[i]);
800 }
801 } else if (sctx->screen->info.has_set_sh_pairs_packed) {
802 if (sel->info.uses_grid_size && !info->indirect) {
803 gfx11_push_compute_sh_reg(grid_size_reg, info->grid[0]);
804 gfx11_push_compute_sh_reg(grid_size_reg + 4, info->grid[1]);
805 gfx11_push_compute_sh_reg(grid_size_reg + 8, info->grid[2]);
806 }
807
808 if (sel->info.uses_variable_block_size) {
809 uint32_t value = info->block[0] | (info->block[1] << 10) | (info->block[2] << 20);
810 gfx11_push_compute_sh_reg(block_size_reg, value);
811 }
812
813 if (sel->info.base.cs.user_data_components_amd) {
814 unsigned num = sel->info.base.cs.user_data_components_amd;
815 for (unsigned i = 0; i < num; i++)
816 gfx11_push_compute_sh_reg(cs_user_data_reg + i * 4, sctx->cs_user_data[i]);
817 }
818 } else {
819 radeon_begin(cs);
820
821 if (sel->info.uses_grid_size && !info->indirect) {
822 radeon_set_sh_reg_seq(grid_size_reg, 3);
823 radeon_emit(info->grid[0]);
824 radeon_emit(info->grid[1]);
825 radeon_emit(info->grid[2]);
826 }
827
828 if (sel->info.uses_variable_block_size) {
829 uint32_t value = info->block[0] | (info->block[1] << 10) | (info->block[2] << 20);
830 radeon_set_sh_reg(block_size_reg, value);
831 }
832
833 if (sel->info.base.cs.user_data_components_amd) {
834 unsigned num = sel->info.base.cs.user_data_components_amd;
835 radeon_set_sh_reg_seq(cs_user_data_reg, num);
836 radeon_emit_array(sctx->cs_user_data, num);
837 }
838 radeon_end();
839 }
840 }
841
si_get_2d_interleave_size(const struct pipe_grid_info * info,unsigned * log_x,unsigned * log_y)842 static bool si_get_2d_interleave_size(const struct pipe_grid_info *info,
843 unsigned *log_x, unsigned *log_y)
844 {
845 /* The following code produces this behavior:
846 *
847 * WG size | WG block/SE | Thread block/SE
848 * ( 1, 32) = 32 | (16, 1) = 16 | ( 16, 32) = 512
849 * ( 2, 16) = 32 | ( 8, 2) = 16 | ( 16, 32) = 512
850 * ( 2, 32) = 64 | (16, 1) = 16 | ( 32, 32) = 1024
851 * ( 4, 8) = 32 | ( 4, 4) = 16 | ( 16, 32) = 512
852 * ( 4, 16) = 64 | ( 8, 2) = 16 | ( 32, 32) = 1024
853 * ( 4, 32) = 128 | ( 8, 1) = 8 | ( 32, 32) = 1024
854 * ( 8, 4) = 32 | ( 2, 8) = 16 | ( 16, 32) = 512
855 * ( 8, 8) = 64 | ( 4, 4) = 16 | ( 32, 32) = 1024
856 * ( 8, 16) = 128 | ( 4, 2) = 8 | ( 32, 32) = 1024
857 * ( 8, 32) = 256 | ( 4, 1) = 4 | ( 32, 32) = 1024
858 * (16, 2) = 32 | ( 1, 16) = 16 | ( 16, 32) = 512
859 * (16, 4) = 64 | ( 2, 8) = 16 | ( 32, 32) = 1024
860 * (16, 8) = 128 | ( 2, 4) = 8 | ( 32, 32) = 1024
861 * (16, 16) = 256 | ( 2, 2) = 4 | ( 32, 32) = 1024
862 * (16, 32) = 512 | ( 2, 1) = 2 | ( 32, 32) = 1024
863 * (32, 1) = 32 | ( 1, 16) = 16 | ( 32, 16) = 512
864 * (32, 2) = 64 | ( 1, 16) = 16 | ( 32, 32) = 1024
865 * (32, 4) = 128 | ( 1, 8) = 8 | ( 32, 32) = 1024
866 * (32, 8) = 256 | ( 1, 4) = 4 | ( 32, 32) = 1024
867 * (32, 16) = 512 | ( 1, 2) = 2 | ( 32, 32) = 1024
868 *
869 * For 3D workgroups, the total 2D thread count is divided by Z.
870 * Example with Z=8, showing only a 2D slice of the grid:
871 *
872 * WG size | WG block/SE | Thread block/SE
873 * ( 1, 32) = 32 | ( 4, 1) = 4 | ( 4, 32) = 128
874 * ( 2, 16) = 32 | ( 4, 1) = 4 | ( 8, 16) = 128
875 * ( 2, 32) = 64 | ( 2, 1) = 2 | ( 4, 32) = 128
876 * ( 4, 8) = 32 | ( 2, 2) = 4 | ( 8, 16) = 128
877 * ( 4, 16) = 64 | ( 2, 1) = 2 | ( 8, 16) = 128
878 * ( 8, 4) = 32 | ( 1, 4) = 4 | ( 8, 16) = 128
879 * ( 8, 8) = 64 | ( 1, 2) = 2 | ( 8, 16) = 128
880 * (16, 2) = 32 | ( 1, 4) = 4 | ( 16, 8) = 128
881 * (16, 4) = 64 | ( 1, 2) = 2 | ( 16, 8) = 128
882 * (32, 1) = 32 | ( 1, 4) = 4 | ( 32, 4) = 128
883 * (32, 2) = 64 | ( 1, 2) = 2 | ( 32, 4) = 128
884 *
885 * It tries to find a WG block size that corresponds to (N, N) or (N, 2*N) threads,
886 * but it's limited by the maximum WGs/SE, which is 16, and the number of threads/SE,
887 * which we set to 1024.
888 */
889 unsigned max_threads_per_se = 1024;
890 unsigned threads_per_threadgroup = info->block[0] * info->block[1] * info->block[2];
891 unsigned workgroups_per_se = MIN2(max_threads_per_se / threads_per_threadgroup, 16);
892 unsigned log_workgroups_per_se = util_logbase2(workgroups_per_se);
893
894 if (!log_workgroups_per_se)
895 return false;
896
897 assert(log_workgroups_per_se <= 4);
898
899 *log_x = MIN2(log_workgroups_per_se, 4);
900 *log_y = log_workgroups_per_se - *log_x;
901
902 while (*log_x > 0 && *log_y < 4 &&
903 info->block[0] * (1 << *log_x) > info->block[1] * (1 << *log_y)) {
904 (*log_x)--;
905 (*log_y)++;
906 }
907
908 assert(*log_x + *log_y <= 4);
909 return true;
910 }
911
si_emit_dispatch_packets(struct si_context * sctx,const struct pipe_grid_info * info)912 static void si_emit_dispatch_packets(struct si_context *sctx, const struct pipe_grid_info *info)
913 {
914 struct si_screen *sscreen = sctx->screen;
915 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
916 bool render_cond_bit = sctx->render_cond_enabled;
917 unsigned threads_per_threadgroup = info->block[0] * info->block[1] * info->block[2];
918 unsigned waves_per_threadgroup =
919 DIV_ROUND_UP(threads_per_threadgroup, sctx->cs_shader_state.program->shader.wave_size);
920 unsigned threadgroups_per_cu = 1;
921
922 if (sctx->gfx_level >= GFX10 && waves_per_threadgroup == 1)
923 threadgroups_per_cu = 2;
924
925 if (unlikely(sctx->sqtt_enabled)) {
926 if (info->indirect) {
927 si_sqtt_write_event_marker(sctx, &sctx->gfx_cs,
928 EventCmdDispatchIndirect,
929 UINT_MAX, UINT_MAX, UINT_MAX);
930 } else {
931 si_write_event_with_dims_marker(sctx, &sctx->gfx_cs,
932 EventCmdDispatch,
933 info->grid[0], info->grid[1], info->grid[2]);
934 }
935 }
936
937 radeon_begin(cs);
938 unsigned compute_resource_limits =
939 ac_get_compute_resource_limits(&sscreen->info, waves_per_threadgroup,
940 sctx->cs_max_waves_per_sh,
941 threadgroups_per_cu);
942
943 if (sctx->gfx_level >= GFX12) {
944 gfx12_opt_push_compute_sh_reg(R_00B854_COMPUTE_RESOURCE_LIMITS,
945 SI_TRACKED_COMPUTE_RESOURCE_LIMITS,
946 compute_resource_limits);
947 } else if (sctx->screen->info.has_set_sh_pairs_packed) {
948 gfx11_opt_push_compute_sh_reg(R_00B854_COMPUTE_RESOURCE_LIMITS,
949 SI_TRACKED_COMPUTE_RESOURCE_LIMITS,
950 compute_resource_limits);
951 } else {
952 radeon_opt_set_sh_reg(R_00B854_COMPUTE_RESOURCE_LIMITS,
953 SI_TRACKED_COMPUTE_RESOURCE_LIMITS,
954 compute_resource_limits);
955 }
956
957 unsigned dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1) | S_00B800_FORCE_START_AT_000(1) |
958 /* If the KMD allows it (there is a KMD hw register for it),
959 * allow launching waves out-of-order. (same as Vulkan)
960 * Not available in gfx940.
961 */
962 S_00B800_ORDER_MODE(!sctx->cs_shader_state.program->sel.info.uses_atomic_ordered_add &&
963 sctx->gfx_level >= GFX7 &&
964 (sctx->family < CHIP_GFX940 || sctx->screen->info.has_graphics)) |
965 S_00B800_CS_W32_EN(sctx->cs_shader_state.program->shader.wave_size == 32);
966
967 const uint *last_block = info->last_block;
968 bool partial_block_en = last_block[0] || last_block[1] || last_block[2];
969 uint32_t num_threads[3];
970
971 if (sctx->gfx_level >= GFX12) {
972 num_threads[0] = S_00B81C_NUM_THREAD_FULL_GFX12(info->block[0]);
973 num_threads[1] = S_00B820_NUM_THREAD_FULL_GFX12(info->block[1]);
974 } else {
975 num_threads[0] = S_00B81C_NUM_THREAD_FULL_GFX6(info->block[0]);
976 num_threads[1] = S_00B820_NUM_THREAD_FULL_GFX6(info->block[1]);
977 }
978 num_threads[2] = S_00B824_NUM_THREAD_FULL(info->block[2]);
979
980 if (partial_block_en) {
981 unsigned partial[3];
982
983 /* If no partial_block, these should be an entire block size, not 0. */
984 partial[0] = last_block[0] ? last_block[0] : info->block[0];
985 partial[1] = last_block[1] ? last_block[1] : info->block[1];
986 partial[2] = last_block[2] ? last_block[2] : info->block[2];
987
988 num_threads[0] |= S_00B81C_NUM_THREAD_PARTIAL(partial[0]);
989 num_threads[1] |= S_00B820_NUM_THREAD_PARTIAL(partial[1]);
990 num_threads[2] |= S_00B824_NUM_THREAD_PARTIAL(partial[2]);
991
992 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
993 }
994
995 if (sctx->gfx_level >= GFX12) {
996 /* Set PING_PONG_EN for every other dispatch.
997 * Only allowed on a gfx queue, and PARTIAL_TG_EN and USE_THREAD_DIMENSIONS must be 0.
998 */
999 if (sctx->has_graphics && !partial_block_en &&
1000 !sctx->cs_shader_state.program->sel.info.uses_atomic_ordered_add) {
1001 dispatch_initiator |= S_00B800_PING_PONG_EN(sctx->compute_ping_pong_launch);
1002 sctx->compute_ping_pong_launch ^= 1;
1003 }
1004
1005 /* Thread tiling within a workgroup. */
1006 switch (sctx->cs_shader_state.program->shader.selector->info.base.derivative_group) {
1007 case DERIVATIVE_GROUP_LINEAR:
1008 break;
1009 case DERIVATIVE_GROUP_QUADS:
1010 num_threads[0] |= S_00B81C_INTERLEAVE_BITS_X(1); /* 2x2 */
1011 num_threads[1] |= S_00B820_INTERLEAVE_BITS_Y(1);
1012 break;
1013 case DERIVATIVE_GROUP_NONE:
1014 /* These are the only legal combinations. */
1015 if (info->block[0] % 8 == 0 && info->block[1] % 8 == 0) {
1016 num_threads[0] |= S_00B81C_INTERLEAVE_BITS_X(3); /* 8x8 */
1017 num_threads[1] |= S_00B820_INTERLEAVE_BITS_Y(3);
1018 } else if (info->block[0] % 4 == 0 && info->block[1] % 8 == 0) {
1019 num_threads[0] |= S_00B81C_INTERLEAVE_BITS_X(2); /* 4x8 */
1020 num_threads[1] |= S_00B820_INTERLEAVE_BITS_Y(3);
1021 } else if (info->block[0] % 4 == 0 && info->block[1] % 4 == 0) {
1022 num_threads[0] |= S_00B81C_INTERLEAVE_BITS_X(2); /* 4x4 */
1023 num_threads[1] |= S_00B820_INTERLEAVE_BITS_Y(2);
1024 } else if (info->block[0] % 2 == 0 && info->block[1] % 2 == 0) {
1025 num_threads[0] |= S_00B81C_INTERLEAVE_BITS_X(1); /* 2x2 */
1026 num_threads[1] |= S_00B820_INTERLEAVE_BITS_Y(1);
1027 }
1028 break;
1029 }
1030
1031 /* How many threads should go to 1 SE before moving onto the next if INTERLEAVE_2D_EN == 0.
1032 * Only these values are valid: 0 (disabled), 64, 128, 256, 512
1033 * 64 = RT, 256 = non-RT (run benchmarks to be sure)
1034 */
1035 unsigned dispatch_interleave = S_00B8BC_INTERLEAVE_1D(256);
1036 unsigned log_x, log_y;
1037
1038 /* Launch a 2D subgrid on each SE instead of a 1D subgrid. If enabled, INTERLEAVE_1D is
1039 * ignored and each SE gets 1 subgrid up to a certain number of threads.
1040 *
1041 * Constraints:
1042 * - Only supported by the gfx queue.
1043 * - Max 16 workgroups per SE can be launched, max 4 in each dimension.
1044 * - PARTIAL_TG_EN, USE_THREAD_DIMENSIONS, and ORDERED_APPEND_ENBL must be 0.
1045 * - COMPUTE_START_X/Y are in units of 2D subgrids, not workgroups
1046 * (program COMPUTE_START_X to start_x >> log_x, COMPUTE_START_Y to start_y >> log_y).
1047 */
1048 if (sctx->has_graphics && !partial_block_en &&
1049 (info->indirect || info->grid[1] >= 4) && MIN2(info->block[0], info->block[1]) >= 4 &&
1050 si_get_2d_interleave_size(info, &log_x, &log_y)) {
1051 dispatch_interleave = S_00B8BC_INTERLEAVE_1D(1) || /* 1D is disabled */
1052 S_00B8BC_INTERLEAVE_2D_X_SIZE(log_x) |
1053 S_00B8BC_INTERLEAVE_2D_Y_SIZE(log_y);
1054 dispatch_initiator |= S_00B800_INTERLEAVE_2D_EN(1);
1055 }
1056
1057 if (sctx->has_graphics) {
1058 radeon_opt_set_sh_reg_idx(R_00B8BC_COMPUTE_DISPATCH_INTERLEAVE,
1059 SI_TRACKED_COMPUTE_DISPATCH_INTERLEAVE, 2, dispatch_interleave);
1060 } else {
1061 gfx12_opt_push_compute_sh_reg(R_00B8BC_COMPUTE_DISPATCH_INTERLEAVE,
1062 SI_TRACKED_COMPUTE_DISPATCH_INTERLEAVE, dispatch_interleave);
1063 }
1064 }
1065
1066 if (sctx->gfx_level >= GFX12) {
1067 gfx12_opt_push_compute_sh_reg(R_00B81C_COMPUTE_NUM_THREAD_X,
1068 SI_TRACKED_COMPUTE_NUM_THREAD_X, num_threads[0]);
1069 gfx12_opt_push_compute_sh_reg(R_00B820_COMPUTE_NUM_THREAD_Y,
1070 SI_TRACKED_COMPUTE_NUM_THREAD_Y, num_threads[1]);
1071 gfx12_opt_push_compute_sh_reg(R_00B824_COMPUTE_NUM_THREAD_Z,
1072 SI_TRACKED_COMPUTE_NUM_THREAD_Z, num_threads[2]);
1073 } else if (sctx->screen->info.has_set_sh_pairs_packed) {
1074 gfx11_opt_push_compute_sh_reg(R_00B81C_COMPUTE_NUM_THREAD_X,
1075 SI_TRACKED_COMPUTE_NUM_THREAD_X, num_threads[0]);
1076 gfx11_opt_push_compute_sh_reg(R_00B820_COMPUTE_NUM_THREAD_Y,
1077 SI_TRACKED_COMPUTE_NUM_THREAD_Y, num_threads[1]);
1078 gfx11_opt_push_compute_sh_reg(R_00B824_COMPUTE_NUM_THREAD_Z,
1079 SI_TRACKED_COMPUTE_NUM_THREAD_Z, num_threads[2]);
1080 } else {
1081 radeon_opt_set_sh_reg3(R_00B81C_COMPUTE_NUM_THREAD_X,
1082 SI_TRACKED_COMPUTE_NUM_THREAD_X,
1083 num_threads[0], num_threads[1], num_threads[2]);
1084 }
1085
1086 if (sctx->gfx_level >= GFX12 || sctx->screen->info.has_set_sh_pairs_packed) {
1087 radeon_end();
1088 si_emit_buffered_compute_sh_regs(sctx);
1089 radeon_begin_again(cs);
1090 }
1091
1092 if (info->indirect) {
1093 uint64_t base_va = si_resource(info->indirect)->gpu_address;
1094
1095 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, si_resource(info->indirect),
1096 RADEON_USAGE_READ | RADEON_PRIO_DRAW_INDIRECT);
1097
1098 radeon_emit(PKT3(PKT3_SET_BASE, 2, 0) | PKT3_SHADER_TYPE_S(1));
1099 radeon_emit(1);
1100 radeon_emit(base_va);
1101 radeon_emit(base_va >> 32);
1102
1103 unsigned pkt = PKT3_DISPATCH_INDIRECT;
1104
1105 if (sctx->gfx_level >= GFX12 && G_00B800_INTERLEAVE_2D_EN(dispatch_initiator))
1106 pkt = PKT3_DISPATCH_INDIRECT_INTERLEAVED;
1107
1108 radeon_emit(PKT3(pkt, 1, render_cond_bit) | PKT3_SHADER_TYPE_S(1));
1109 radeon_emit(info->indirect_offset);
1110 radeon_emit(dispatch_initiator);
1111 } else {
1112 unsigned pkt = PKT3_DISPATCH_DIRECT;
1113
1114 if (sctx->gfx_level >= GFX12 && G_00B800_INTERLEAVE_2D_EN(dispatch_initiator))
1115 pkt = PKT3_DISPATCH_DIRECT_INTERLEAVED;
1116
1117 radeon_emit(PKT3(pkt, 3, render_cond_bit) | PKT3_SHADER_TYPE_S(1));
1118 radeon_emit(info->grid[0]);
1119 radeon_emit(info->grid[1]);
1120 radeon_emit(info->grid[2]);
1121 radeon_emit(dispatch_initiator);
1122 }
1123
1124 if (unlikely(sctx->sqtt_enabled && sctx->gfx_level >= GFX9))
1125 radeon_event_write(V_028A90_THREAD_TRACE_MARKER);
1126
1127 radeon_end();
1128 }
1129
si_check_needs_implicit_sync(struct si_context * sctx,uint32_t usage)1130 static bool si_check_needs_implicit_sync(struct si_context *sctx, uint32_t usage)
1131 {
1132 /* If the compute shader is going to read from a texture/image written by a
1133 * previous draw, we must wait for its completion before continuing.
1134 * Buffers and image stores (from the draw) are not taken into consideration
1135 * because that's the app responsibility.
1136 *
1137 * The OpenGL 4.6 spec says:
1138 *
1139 * buffer object and texture stores performed by shaders are not
1140 * automatically synchronized
1141 *
1142 * TODO: Bindless textures are not handled, and thus are not synchronized.
1143 */
1144 struct si_shader_info *info = &sctx->cs_shader_state.program->sel.info;
1145 struct si_samplers *samplers = &sctx->samplers[PIPE_SHADER_COMPUTE];
1146 unsigned mask = samplers->enabled_mask & info->base.textures_used[0];
1147
1148 while (mask) {
1149 int i = u_bit_scan(&mask);
1150 struct si_sampler_view *sview = (struct si_sampler_view *)samplers->views[i];
1151
1152 struct si_resource *res = si_resource(sview->base.texture);
1153 if (sctx->ws->cs_is_buffer_referenced(&sctx->gfx_cs, res->buf, usage))
1154 return true;
1155 }
1156
1157 struct si_images *images = &sctx->images[PIPE_SHADER_COMPUTE];
1158 mask = u_bit_consecutive(0, info->base.num_images) & images->enabled_mask;
1159
1160 while (mask) {
1161 int i = u_bit_scan(&mask);
1162 struct pipe_image_view *sview = &images->views[i];
1163
1164 struct si_resource *res = si_resource(sview->resource);
1165 if (sctx->ws->cs_is_buffer_referenced(&sctx->gfx_cs, res->buf, usage))
1166 return true;
1167 }
1168 return false;
1169 }
1170
si_launch_grid(struct pipe_context * ctx,const struct pipe_grid_info * info)1171 static void si_launch_grid(struct pipe_context *ctx, const struct pipe_grid_info *info)
1172 {
1173 struct si_context *sctx = (struct si_context *)ctx;
1174 struct si_screen *sscreen = sctx->screen;
1175 struct si_compute *program = sctx->cs_shader_state.program;
1176 const amd_kernel_code_t *code_object = si_compute_get_code_object(program, info->pc);
1177 int i;
1178 bool cs_regalloc_hang = sscreen->info.has_cs_regalloc_hang_bug &&
1179 info->block[0] * info->block[1] * info->block[2] > 256;
1180
1181 if (cs_regalloc_hang) {
1182 sctx->barrier_flags |= SI_BARRIER_SYNC_PS | SI_BARRIER_SYNC_CS;
1183 si_mark_atom_dirty(sctx, &sctx->atoms.s.barrier);
1184 }
1185
1186 if (program->ir_type != PIPE_SHADER_IR_NATIVE && program->shader.compilation_failed)
1187 return;
1188
1189 si_check_dirty_buffers_textures(sctx);
1190
1191 if (sctx->has_graphics) {
1192 if (sctx->num_draw_calls_sh_coherent.with_cb != sctx->num_draw_calls ||
1193 sctx->num_draw_calls_sh_coherent.with_db != sctx->num_draw_calls) {
1194 bool sync_cb = sctx->force_shader_coherency.with_cb ||
1195 si_check_needs_implicit_sync(sctx, RADEON_USAGE_CB_NEEDS_IMPLICIT_SYNC);
1196 bool sync_db = sctx->gfx_level >= GFX12 &&
1197 (sctx->force_shader_coherency.with_db ||
1198 si_check_needs_implicit_sync(sctx, RADEON_USAGE_DB_NEEDS_IMPLICIT_SYNC));
1199
1200 si_fb_barrier_after_rendering(sctx,
1201 (sync_cb ? SI_FB_BARRIER_SYNC_CB : 0) |
1202 (sync_db ? SI_FB_BARRIER_SYNC_DB : 0));
1203
1204 if (sync_cb)
1205 sctx->num_draw_calls_sh_coherent.with_cb = sctx->num_draw_calls;
1206
1207 if (sync_db)
1208 sctx->num_draw_calls_sh_coherent.with_db = sctx->num_draw_calls;
1209 }
1210
1211 if (sctx->gfx_level < GFX11)
1212 gfx6_decompress_textures(sctx, 1 << PIPE_SHADER_COMPUTE);
1213 else if (sctx->gfx_level < GFX12)
1214 gfx11_decompress_textures(sctx, 1 << PIPE_SHADER_COMPUTE);
1215 }
1216
1217 if (info->indirect) {
1218 /* Indirect buffers are read through L2 on GFX9-GFX11, but not other hw. */
1219 if ((sctx->gfx_level <= GFX8 || sscreen->info.cp_sdma_ge_use_system_memory_scope) &&
1220 si_resource(info->indirect)->L2_cache_dirty) {
1221 sctx->barrier_flags |= SI_BARRIER_WB_L2 | SI_BARRIER_PFP_SYNC_ME;
1222 si_mark_atom_dirty(sctx, &sctx->atoms.s.barrier);
1223 si_resource(info->indirect)->L2_cache_dirty = false;
1224 }
1225 }
1226
1227 si_need_gfx_cs_space(sctx, 0, 0);
1228
1229 /* If we're using a secure context, determine if cs must be secure or not */
1230 if (unlikely(radeon_uses_secure_bos(sctx->ws))) {
1231 bool secure = si_compute_resources_check_encrypted(sctx);
1232 if (secure != sctx->ws->cs_is_secure(&sctx->gfx_cs)) {
1233 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW |
1234 RADEON_FLUSH_TOGGLE_SECURE_SUBMISSION,
1235 NULL);
1236 }
1237 }
1238
1239 if (u_trace_perfetto_active(&sctx->ds.trace_context))
1240 trace_si_begin_compute(&sctx->trace);
1241
1242 if (sctx->bo_list_add_all_compute_resources)
1243 si_compute_resources_add_all_to_bo_list(sctx);
1244
1245 /* Skipping setting redundant registers on compute queues breaks compute. */
1246 if (!sctx->has_graphics) {
1247 BITSET_CLEAR_RANGE(sctx->tracked_regs.reg_saved_mask,
1248 SI_FIRST_TRACKED_OTHER_REG, SI_NUM_ALL_TRACKED_REGS - 1);
1249 }
1250
1251 /* First emit registers. */
1252 bool prefetch;
1253 if (!si_switch_compute_shader(sctx, program, &program->shader, code_object, info->pc, &prefetch,
1254 info->variable_shared_mem))
1255 return;
1256
1257 si_emit_compute_shader_pointers(sctx);
1258
1259 if (program->ir_type == PIPE_SHADER_IR_NATIVE &&
1260 unlikely(!si_upload_compute_input(sctx, code_object, info)))
1261 return;
1262
1263 /* Global buffers */
1264 for (i = 0; i < sctx->max_global_buffers; i++) {
1265 struct si_resource *buffer = si_resource(sctx->global_buffers[i]);
1266 if (!buffer) {
1267 continue;
1268 }
1269 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, buffer,
1270 RADEON_USAGE_READWRITE | RADEON_PRIO_SHADER_RW_BUFFER);
1271 }
1272
1273 /* Registers that are not read from memory should be set before this: */
1274 si_emit_barrier_direct(sctx);
1275
1276 if (sctx->has_graphics && si_is_atom_dirty(sctx, &sctx->atoms.s.render_cond)) {
1277 sctx->atoms.s.render_cond.emit(sctx, -1);
1278 si_set_atom_dirty(sctx, &sctx->atoms.s.render_cond, false);
1279 }
1280
1281 /* Prefetch the compute shader to L2. */
1282 if (sctx->gfx_level >= GFX7 && sctx->screen->info.has_cp_dma && prefetch)
1283 si_cp_dma_prefetch(sctx, &program->shader.bo->b.b, 0, program->shader.bo->b.b.width0);
1284
1285 if (program->ir_type != PIPE_SHADER_IR_NATIVE)
1286 si_setup_nir_user_data(sctx, info);
1287
1288 si_emit_dispatch_packets(sctx, info);
1289
1290 if (unlikely(sctx->current_saved_cs)) {
1291 si_trace_emit(sctx);
1292 si_log_compute_state(sctx, sctx->log);
1293 }
1294
1295 if (sctx->gfx_level < GFX12) {
1296 /* Mark displayable DCC as dirty for bound images. */
1297 unsigned display_dcc_store_mask = sctx->images[PIPE_SHADER_COMPUTE].display_dcc_store_mask &
1298 BITFIELD_MASK(program->sel.info.base.num_images);
1299 while (display_dcc_store_mask) {
1300 struct si_texture *tex = (struct si_texture *)
1301 sctx->images[PIPE_SHADER_COMPUTE].views[u_bit_scan(&display_dcc_store_mask)].resource;
1302
1303 si_mark_display_dcc_dirty(sctx, tex);
1304 }
1305
1306 /* TODO: Bindless images don't set displayable_dcc_dirty after image stores. */
1307 }
1308
1309 sctx->compute_is_busy = true;
1310 sctx->num_compute_calls++;
1311
1312 if (u_trace_perfetto_active(&sctx->ds.trace_context))
1313 trace_si_end_compute(&sctx->trace, info->grid[0], info->grid[1], info->grid[2]);
1314
1315 if (cs_regalloc_hang) {
1316 sctx->barrier_flags |= SI_BARRIER_SYNC_CS;
1317 si_mark_atom_dirty(sctx, &sctx->atoms.s.barrier);
1318 }
1319 }
1320
si_destroy_compute(struct si_compute * program)1321 void si_destroy_compute(struct si_compute *program)
1322 {
1323 struct si_shader_selector *sel = &program->sel;
1324
1325 if (program->ir_type != PIPE_SHADER_IR_NATIVE) {
1326 util_queue_drop_job(&sel->screen->shader_compiler_queue, &sel->ready);
1327 util_queue_fence_destroy(&sel->ready);
1328 }
1329
1330 si_shader_destroy(&program->shader);
1331 ralloc_free(program->sel.nir);
1332 simple_mtx_destroy(&sel->mutex);
1333 FREE(program);
1334 }
1335
si_delete_compute_state(struct pipe_context * ctx,void * state)1336 static void si_delete_compute_state(struct pipe_context *ctx, void *state)
1337 {
1338 struct si_compute *program = (struct si_compute *)state;
1339 struct si_context *sctx = (struct si_context *)ctx;
1340
1341 if (!state)
1342 return;
1343
1344 if (program == sctx->cs_shader_state.program)
1345 sctx->cs_shader_state.program = NULL;
1346
1347 if (program == sctx->cs_shader_state.emitted_program)
1348 sctx->cs_shader_state.emitted_program = NULL;
1349
1350 si_compute_reference(&program, NULL);
1351 }
1352
si_set_compute_resources(struct pipe_context * ctx_,unsigned start,unsigned count,struct pipe_surface ** surfaces)1353 static void si_set_compute_resources(struct pipe_context *ctx_, unsigned start, unsigned count,
1354 struct pipe_surface **surfaces)
1355 {
1356 }
1357
si_init_compute_functions(struct si_context * sctx)1358 void si_init_compute_functions(struct si_context *sctx)
1359 {
1360 sctx->b.create_compute_state = si_create_compute_state;
1361 sctx->b.delete_compute_state = si_delete_compute_state;
1362 sctx->b.bind_compute_state = si_bind_compute_state;
1363 sctx->b.get_compute_state_info = si_get_compute_state_info;
1364 sctx->b.set_compute_resources = si_set_compute_resources;
1365 sctx->b.set_global_binding = si_set_global_binding;
1366 sctx->b.launch_grid = si_launch_grid;
1367
1368 #if 0 /* test for si_get_2d_interleave_size */
1369 static bool visited = false;
1370 if (visited)
1371 return;
1372
1373 visited = true;
1374 struct pipe_grid_info info = {};
1375 info.grid[0] = info.grid[1] = info.grid[2] = 1024;
1376 info.block[2] = 1;
1377
1378 for (unsigned block_3d = 0; block_3d < 2; block_3d++) {
1379 printf(" WG size | WG block/SE | Thread block/SE\n");
1380
1381 for (unsigned x = 1; x <= 32; x *= 2) {
1382 for (unsigned y = 1; y <= 32; y *= 2) {
1383 info.block[0] = x;
1384 info.block[1] = y;
1385 info.block[2] = block_3d ? 8 : 1;
1386
1387 if ((x * y) % 32)
1388 continue;
1389
1390 unsigned log_x, log_y;
1391 if (!si_get_2d_interleave_size(&info, &log_x, &log_y))
1392 continue;
1393
1394 printf(" (%2u, %2u) = %3u | (%2u, %2u) = %2u | (%3u,%3u) = %u\n",
1395 info.block[0], info.block[1], info.block[0] * info.block[1],
1396 1 << log_x, 1 << log_y, (1 << log_x) * (1 << log_y),
1397 info.block[0] * (1 << log_x), info.block[1] * (1 << log_y),
1398 info.block[0] * (1 << log_x) * info.block[1] * (1 << log_y));
1399 }
1400 }
1401 }
1402 #endif
1403 }
1404