1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
4 *
5 * SPDX-License-Identifier: MIT
6 */
7 #ifndef SI_PIPE_H
8 #define SI_PIPE_H
9
10 #include "si_shader.h"
11 #include "si_state.h"
12 #include "winsys/radeon_winsys.h"
13 #include "util/u_blitter.h"
14 #include "util/u_idalloc.h"
15 #include "util/u_log.h"
16 #include "util/u_suballoc.h"
17 #include "util/u_threaded_context.h"
18 #include "util/u_vertex_state_cache.h"
19 #include "util/perf/u_trace.h"
20 #include "ac_descriptors.h"
21 #include "ac_sqtt.h"
22 #include "ac_spm.h"
23 #include "si_perfetto.h"
24
25 #ifdef __cplusplus
26 extern "C" {
27 #endif
28
29 struct ac_llvm_compiler;
30
31 #define SHADER_DEBUG_LOG 0
32
33 #define ATI_VENDOR_ID 0x1002
34 #define SI_NOT_QUERY 0xffffffff
35
36 /* special primitive types */
37 #define SI_PRIM_RECTANGLE_LIST MESA_PRIM_COUNT
38
39 /* The primitive restart can be any number, but we must pick one which will
40 * mean "unknown" for the purpose of state tracking and the number shouldn't
41 * be a commonly-used one.
42 */
43 #define SI_RESTART_INDEX_UNKNOWN ((unsigned)INT_MIN)
44 #define SI_INSTANCE_COUNT_UNKNOWN ((unsigned)INT_MIN)
45 #define SI_NUM_SMOOTH_AA_SAMPLES 4
46 #define SI_MAX_POINT_SIZE 2048
47 #define SI_GS_PER_ES 128
48 /* Alignment for optimal CP DMA performance. */
49 #define SI_CPDMA_ALIGNMENT 32
50
51 /* Pipeline & streamout query start/stop events. */
52 #define SI_BARRIER_EVENT_PIPELINESTAT_START BITFIELD_BIT(0)
53 #define SI_BARRIER_EVENT_PIPELINESTAT_STOP BITFIELD_BIT(1)
54 /* Events only used by workarounds. These shouldn't be used for API barriers. */
55 #define SI_BARRIER_EVENT_FLUSH_AND_INV_DB_META BITFIELD_BIT(2)
56 #define SI_BARRIER_EVENT_VGT_FLUSH BITFIELD_BIT(3)
57 /* PFP waits for ME to finish. Used to sync for index and indirect buffers and render condition. */
58 #define SI_BARRIER_PFP_SYNC_ME BITFIELD_BIT(4)
59 /* Instruction cache. */
60 #define SI_BARRIER_INV_ICACHE BITFIELD_BIT(5)
61 /* Scalar cache. (GFX6-9: scalar L1; GFX10+: scalar L0)
62 * GFX10: This also invalidates the L1 shader array cache. */
63 #define SI_BARRIER_INV_SMEM BITFIELD_BIT(6)
64 /* Vector cache. (GFX6-9: vector L1; GFX10+: vector L0)
65 * GFX10: This also invalidates the L1 shader array cache. */
66 #define SI_BARRIER_INV_VMEM BITFIELD_BIT(7)
67 /* L2 cache + L2 metadata cache writeback & invalidate.
68 * GFX6-8: Used by shaders only. GFX9+: Used by everything. */
69 #define SI_BARRIER_INV_L2 BITFIELD_BIT(8)
70 /* L2 writeback (write dirty L2 lines to memory for non-L2 clients).
71 * Only used for coherency with non-L2 clients like CB, DB, CP on GFX6-8.
72 * GFX6-7 will do complete invalidation because the writeback is unsupported. */
73 #define SI_BARRIER_WB_L2 BITFIELD_BIT(9)
74 /* Writeback & invalidate the L2 metadata cache only. */
75 #define SI_BARRIER_INV_L2_METADATA BITFIELD_BIT(10)
76 /* These wait for shaders to finish. (SYNC_VS = wait for the whole geometry pipeline to finish) */
77 #define SI_BARRIER_SYNC_VS BITFIELD_BIT(11)
78 #define SI_BARRIER_SYNC_PS BITFIELD_BIT(12)
79 #define SI_BARRIER_SYNC_CS BITFIELD_BIT(13)
80 /* Framebuffer caches. */
81 #define SI_BARRIER_SYNC_AND_INV_DB BITFIELD_BIT(14)
82 #define SI_BARRIER_SYNC_AND_INV_CB BITFIELD_BIT(15)
83
84 #define SI_PREFETCH_LS (1 << 1)
85 #define SI_PREFETCH_HS (1 << 2)
86 #define SI_PREFETCH_ES (1 << 3)
87 #define SI_PREFETCH_GS (1 << 4)
88 #define SI_PREFETCH_VS (1 << 5)
89 #define SI_PREFETCH_PS (1 << 6)
90
91 #define SI_MAX_BORDER_COLORS 4096
92 #define SI_MAX_VIEWPORTS 16
93 #define SI_MAP_BUFFER_ALIGNMENT 64
94 /* We only support the minimum allowed value (512), so that we can pack a 3D block size
95 * in 1 SGPR. */
96 #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 512
97
98 #define SI_CONTEXT_FLAG_AUX (1u << 31)
99
100 #define SI_RESOURCE_FLAG_FORCE_LINEAR (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
101 #define SI_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
102 #define SI_RESOURCE_FLAG_GL2_BYPASS (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
103 #define SI_RESOURCE_FLAG_DISCARDABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 3) /* Discard instead of evict. */
104 #define SI_RESOURCE_FLAG_DRIVER_INTERNAL (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
105 #define SI_RESOURCE_AUX_PLANE (PIPE_RESOURCE_FLAG_DRV_PRIV << 5)
106 #define SI_RESOURCE_FLAG_32BIT (PIPE_RESOURCE_FLAG_DRV_PRIV << 6)
107 #define SI_RESOURCE_FLAG_CLEAR (PIPE_RESOURCE_FLAG_DRV_PRIV << 7)
108
109 enum si_has_gs {
110 GS_OFF,
111 GS_ON,
112 };
113
114 enum si_has_tess {
115 TESS_OFF,
116 TESS_ON,
117 };
118
119 enum si_has_ngg {
120 NGG_OFF,
121 NGG_ON,
122 };
123
124 #define DCC_CODE(x) (((x) << 24) | ((x) << 16) | ((x) << 8) | (x))
125
126 enum si_clear_code
127 {
128 /* Common clear codes. */
129 DCC_CLEAR_0000 = DCC_CODE(0x00), /* all bits are 0 */
130 DCC_UNCOMPRESSED = DCC_CODE(0xFF),
131
132 GFX8_DCC_CLEAR_0000 = DCC_CLEAR_0000,
133 GFX8_DCC_CLEAR_0001 = DCC_CODE(0x40),
134 GFX8_DCC_CLEAR_1110 = DCC_CODE(0x80),
135 GFX8_DCC_CLEAR_1111 = DCC_CODE(0xC0),
136 GFX8_DCC_CLEAR_REG = DCC_CODE(0x20),
137 GFX9_DCC_CLEAR_SINGLE = DCC_CODE(0x10),
138
139 GFX11_DCC_CLEAR_SINGLE = DCC_CODE(0x01),
140 GFX11_DCC_CLEAR_0000 = DCC_CLEAR_0000, /* all bits are 0 */
141 GFX11_DCC_CLEAR_1111_UNORM = DCC_CODE(0x02), /* all bits are 1 */
142 GFX11_DCC_CLEAR_1111_FP16 = DCC_CODE(0x04), /* all 16-bit words are 0x3c00, max 64bpp */
143 GFX11_DCC_CLEAR_1111_FP32 = DCC_CODE(0x06), /* all 32-bit words are 0x3f800000 */
144 /* Color bits are 0, alpha bits are 1; only 88, 8888, 16161616 */
145 GFX11_DCC_CLEAR_0001_UNORM = DCC_CODE(0x08),
146 /* Color bits are 1, alpha bits are 0, only 88, 8888, 16161616 */
147 GFX11_DCC_CLEAR_1110_UNORM = DCC_CODE(0x0A),
148 };
149
150 #define SI_IMAGE_ACCESS_DCC_OFF (1 << 8)
151 #define SI_IMAGE_ACCESS_ALLOW_DCC_STORE (1 << 9)
152 #define SI_IMAGE_ACCESS_BLOCK_FORMAT_AS_UINT (1 << 10) /* for compressed/subsampled images */
153
154 enum si_occlusion_query_mode {
155 SI_OCCLUSION_QUERY_MODE_DISABLE,
156 SI_OCCLUSION_QUERY_MODE_PRECISE_INTEGER,
157 SI_OCCLUSION_QUERY_MODE_PRECISE_BOOLEAN,
158 SI_OCCLUSION_QUERY_MODE_CONSERVATIVE_BOOLEAN,
159 };
160
161 /* Debug flags. */
162 enum
163 {
164 /* Shader logging options: */
165 DBG_VS = MESA_SHADER_VERTEX,
166 DBG_TCS = MESA_SHADER_TESS_CTRL,
167 DBG_TES = MESA_SHADER_TESS_EVAL,
168 DBG_GS = MESA_SHADER_GEOMETRY,
169 DBG_PS = MESA_SHADER_FRAGMENT,
170 DBG_CS = MESA_SHADER_COMPUTE,
171 DBG_INIT_NIR,
172 DBG_NIR,
173 DBG_INIT_LLVM,
174 DBG_LLVM,
175 DBG_INIT_ACO,
176 DBG_ACO,
177 DBG_ASM,
178 DBG_STATS,
179
180 /* Shader compiler options the shader cache should be aware of: */
181 DBG_W32_GE,
182 DBG_W32_PS,
183 DBG_W32_CS,
184 DBG_W64_GE,
185 DBG_W64_PS,
186 DBG_W64_CS,
187
188 /* Shader compiler options (with no effect on the shader cache): */
189 DBG_CHECK_IR,
190 DBG_MONOLITHIC_SHADERS,
191 DBG_NO_OPT_VARIANT,
192
193 /* Information logging options: */
194 DBG_INFO,
195 DBG_TEX,
196 DBG_COMPUTE,
197 DBG_VM,
198 DBG_CACHE_STATS,
199 DBG_IB,
200 DBG_VERTEX_ELEMENTS,
201
202 /* Driver options: */
203 DBG_NO_WC,
204 DBG_NO_WC_STREAM,
205 DBG_CHECK_VM,
206 DBG_RESERVE_VMID,
207 DBG_SHADOW_REGS,
208 DBG_NO_FAST_DISPLAY_LIST,
209 DBG_NO_DMA_SHADERS,
210
211 /* Multimedia options: */
212 DBG_NO_EFC,
213 DBG_LOW_LATENCY_ENCODE,
214
215 /* 3D engine options: */
216 DBG_NO_NGG,
217 DBG_ALWAYS_NGG_CULLING_ALL,
218 DBG_NO_NGG_CULLING,
219 DBG_SWITCH_ON_EOP,
220 DBG_NO_OUT_OF_ORDER,
221 DBG_NO_DPBB,
222 DBG_DPBB,
223 DBG_NO_HYPERZ,
224 DBG_NO_2D_TILING,
225 DBG_NO_TILING,
226 DBG_NO_DISPLAY_TILING,
227 DBG_NO_DISPLAY_DCC,
228 DBG_NO_EXPORTED_DCC,
229 DBG_NO_DCC,
230 DBG_NO_DCC_CLEAR,
231 DBG_NO_DCC_STORE,
232 DBG_DCC_STORE,
233 DBG_NO_DCC_MSAA,
234 DBG_NO_FMASK,
235 DBG_NO_DMA,
236
237 DBG_EXTRA_METADATA,
238
239 DBG_TMZ,
240 DBG_SQTT,
241 DBG_USE_ACO,
242 DBG_USE_LLVM,
243
244 DBG_COUNT
245 };
246
247 enum
248 {
249 /* Tests: */
250 DBG_TEST_CLEAR_BUFFER,
251 DBG_TEST_COPY_BUFFER,
252 DBG_TEST_IMAGE_COPY,
253 DBG_TEST_CB_RESOLVE,
254 DBG_TEST_COMPUTE_BLIT,
255 DBG_TEST_VMFAULT_CP,
256 DBG_TEST_VMFAULT_SHADER,
257 DBG_TEST_DMA_PERF,
258 DBG_TEST_MEM_PERF,
259 DBG_TEST_BLIT_PERF,
260 };
261
262 #define DBG_ALL_SHADERS (((1 << (DBG_CS + 1)) - 1))
263 #define DBG(name) (1ull << DBG_##name)
264
265 #define SI_BIND_CONSTANT_BUFFER_SHIFT 0
266 #define SI_BIND_SHADER_BUFFER_SHIFT 6
267 #define SI_BIND_IMAGE_BUFFER_SHIFT 12
268 #define SI_BIND_SAMPLER_BUFFER_SHIFT 18
269 #define SI_BIND_OTHER_BUFFER_SHIFT 24
270
271 /* Bind masks for all 6 shader stages. */
272 #define SI_BIND_CONSTANT_BUFFER_ALL (0x3f << SI_BIND_CONSTANT_BUFFER_SHIFT)
273 #define SI_BIND_SHADER_BUFFER_ALL (0x3f << SI_BIND_SHADER_BUFFER_SHIFT)
274 #define SI_BIND_IMAGE_BUFFER_ALL (0x3f << SI_BIND_IMAGE_BUFFER_SHIFT)
275 #define SI_BIND_SAMPLER_BUFFER_ALL (0x3f << SI_BIND_SAMPLER_BUFFER_SHIFT)
276
277 #define SI_BIND_CONSTANT_BUFFER(shader) ((1 << (shader)) << SI_BIND_CONSTANT_BUFFER_SHIFT)
278 #define SI_BIND_SHADER_BUFFER(shader) ((1 << (shader)) << SI_BIND_SHADER_BUFFER_SHIFT)
279 #define SI_BIND_IMAGE_BUFFER(shader) ((1 << (shader)) << SI_BIND_IMAGE_BUFFER_SHIFT)
280 #define SI_BIND_SAMPLER_BUFFER(shader) ((1 << (shader)) << SI_BIND_SAMPLER_BUFFER_SHIFT)
281 #define SI_BIND_VERTEX_BUFFER (1 << (SI_BIND_OTHER_BUFFER_SHIFT + 0))
282 #define SI_BIND_STREAMOUT_BUFFER (1 << (SI_BIND_OTHER_BUFFER_SHIFT + 1))
283
284 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
285 * at the moment.
286 */
287 struct si_resource {
288 struct threaded_resource b;
289
290 /* If we remove this seemingly useless padding, performance in Viewperf2020/catiav5test1
291 * decreases by 8%.
292 */
293 uint32_t _pad;
294
295 /* Winsys objects. */
296 struct pb_buffer_lean *buf;
297 uint64_t gpu_address;
298
299 /* Resource properties. */
300 uint64_t bo_size;
301 uint8_t bo_alignment_log2;
302 enum radeon_bo_domain domains:8;
303 enum radeon_bo_flag flags:16;
304 unsigned bind_history; /* bitmask of SI_BIND_xxx_BUFFER */
305
306 /* The buffer range which is initialized (with a write transfer,
307 * streamout, DMA, or as a random access target). The rest of
308 * the buffer is considered invalid and can be mapped unsynchronized.
309 *
310 * This allows unsynchronized mapping of a buffer range which hasn't
311 * been used yet. It's for applications which forget to use
312 * the unsynchronized map flag and expect the driver to figure it out.
313 */
314 struct util_range valid_buffer_range;
315
316 /* For buffers only. This indicates that a write operation has been
317 * performed by L2, but the cache hasn't been flushed.
318 * Any hw block which doesn't use or bypasses L2 should check this
319 * flag and flush the cache before using the buffer.
320 *
321 * For example, L2 must be flushed if a buffer which has been
322 * modified by a shader store instruction is about to be used as
323 * an index buffer. The reason is that VGT DMA index fetching doesn't
324 * use L2.
325 */
326 bool L2_cache_dirty;
327
328 /* Whether this resource is referenced by bindless handles. */
329 bool texture_handle_allocated;
330 bool image_handle_allocated;
331
332 /* Whether the resource has been exported via resource_get_handle. */
333 uint8_t external_usage; /* PIPE_HANDLE_USAGE_* */
334 };
335
336 struct si_transfer {
337 struct threaded_transfer b;
338 struct si_resource *staging;
339 };
340
341 struct si_texture {
342 struct si_resource buffer;
343
344 struct radeon_surf surface;
345 struct si_texture *flushed_depth_texture;
346
347 /* One texture allocation can contain these buffers:
348 * - image (pixel data)
349 * - FMASK buffer (MSAA compression)
350 * - CMASK buffer (MSAA compression and/or legacy fast color clear)
351 * - HTILE buffer (Z/S compression and fast Z/S clear)
352 * - DCC buffer (color compression and new fast color clear)
353 * - displayable DCC buffer (if the DCC buffer is not displayable)
354 */
355 uint64_t cmask_base_address_reg;
356 struct si_resource *cmask_buffer;
357 unsigned cb_color_info; /* fast clear enable bit */
358 unsigned color_clear_value[2]; /* not on gfx11 */
359 unsigned last_msaa_resolve_target_micro_mode;
360 bool swap_rgb_to_bgr_on_next_clear;
361 bool swap_rgb_to_bgr;
362 unsigned num_level0_transfers;
363 unsigned plane_index; /* other planes are different pipe_resources */
364 unsigned num_planes;
365 enum pipe_format multi_plane_format;
366
367 /* Depth buffer compression and fast clear. */
368 float depth_clear_value[RADEON_SURF_MAX_LEVELS];
369 uint8_t stencil_clear_value[RADEON_SURF_MAX_LEVELS];
370 uint16_t depth_cleared_level_mask_once; /* if it was cleared at least once */
371 uint16_t depth_cleared_level_mask; /* track if it's cleared (can be false negative) */
372 uint16_t stencil_cleared_level_mask_once; /* if it was cleared at least once */
373 uint16_t dirty_level_mask; /* each bit says if that mipmap is compressed */
374 uint16_t stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */
375 enum pipe_format db_render_format : 16;
376 bool fmask_is_identity : 1;
377 bool tc_compatible_htile : 1;
378 bool enable_tc_compatible_htile_next_clear : 1;
379 bool htile_stencil_disabled : 1;
380 bool upgraded_depth : 1; /* upgraded from unorm to Z32_FLOAT */
381 bool is_depth : 1;
382 bool db_compatible : 1;
383 bool can_sample_z : 1;
384 bool can_sample_s : 1;
385 bool need_flush_after_depth_decompression: 1;
386 bool force_disable_hiz_his : 1;
387
388 /* We need to track DCC dirtiness, because st/dri usually calls
389 * flush_resource twice per frame (not a bug) and we don't wanna
390 * decompress DCC twice.
391 */
392 bool displayable_dcc_dirty : 1;
393
394 /* Counter that should be non-zero if the texture is bound to a
395 * framebuffer.
396 */
397 unsigned framebuffers_bound;
398 };
399
400 /* State trackers create separate textures in a next-chain for extra planes
401 * even if those are planes created purely for modifiers. Because the linking
402 * of the chain happens outside of the driver, and NULL is interpreted as
403 * failure, let's create some dummy texture structs. We could use these
404 * later to use the offsets for linking if we really wanted to.
405 *
406 * For now just create a dummy struct and completely ignore it.
407 *
408 * Potentially in the future we could store stride/offset and use it during
409 * creation, though we might want to change how linking is done first.
410 */
411 struct si_auxiliary_texture {
412 struct threaded_resource b;
413 struct pb_buffer_lean *buffer;
414 uint32_t offset;
415 uint32_t stride;
416 };
417
418 struct si_surface {
419 struct pipe_surface base;
420
421 /* These can vary with block-compressed textures. */
422 uint16_t width0;
423 uint16_t height0;
424
425 bool color_initialized : 1;
426 bool depth_initialized : 1;
427
428 /* Misc. color flags. */
429 bool color_is_int8 : 1;
430 bool color_is_int10 : 1;
431 bool dcc_incompatible : 1;
432 uint8_t db_format_index : 3;
433
434 /* Color registers. */
435 struct ac_cb_surface cb;
436
437 unsigned spi_shader_col_format : 8; /* no blending, no alpha-to-coverage. */
438 unsigned spi_shader_col_format_alpha : 8; /* alpha-to-coverage */
439 unsigned spi_shader_col_format_blend : 8; /* blending without alpha. */
440 unsigned spi_shader_col_format_blend_alpha : 8; /* blending with alpha. */
441
442 /* DB registers. */
443 struct ac_ds_surface ds;
444 };
445
446 struct si_mmio_counter {
447 unsigned busy;
448 unsigned idle;
449 };
450
451 union si_mmio_counters {
452 struct si_mmio_counters_named {
453 /* For global GPU load including SDMA. */
454 struct si_mmio_counter gpu;
455
456 /* GRBM_STATUS */
457 struct si_mmio_counter spi;
458 struct si_mmio_counter gui;
459 struct si_mmio_counter ta;
460 struct si_mmio_counter gds;
461 struct si_mmio_counter vgt;
462 struct si_mmio_counter ia;
463 struct si_mmio_counter sx;
464 struct si_mmio_counter wd;
465 struct si_mmio_counter bci;
466 struct si_mmio_counter sc;
467 struct si_mmio_counter pa;
468 struct si_mmio_counter db;
469 struct si_mmio_counter cp;
470 struct si_mmio_counter cb;
471
472 /* SRBM_STATUS2 */
473 struct si_mmio_counter sdma;
474
475 /* CP_STAT */
476 struct si_mmio_counter pfp;
477 struct si_mmio_counter meq;
478 struct si_mmio_counter me;
479 struct si_mmio_counter surf_sync;
480 struct si_mmio_counter cp_dma;
481 struct si_mmio_counter scratch_ram;
482 } named;
483
484 unsigned array[sizeof(struct si_mmio_counters_named) / sizeof(unsigned)];
485 };
486
487 struct si_memory_object {
488 struct pipe_memory_object b;
489 struct pb_buffer_lean *buf;
490 uint32_t stride;
491 };
492
493 /* Saved CS data for debugging features. */
494 struct radeon_saved_cs {
495 uint32_t *ib;
496 unsigned num_dw;
497
498 struct radeon_bo_list_item *bo_list;
499 unsigned bo_count;
500 };
501
502 struct si_aux_context {
503 struct pipe_context *ctx;
504 struct u_log_context log;
505 mtx_t lock;
506 };
507
508 struct si_screen {
509 struct pipe_screen b;
510 struct radeon_winsys *ws;
511 struct disk_cache *disk_shader_cache;
512
513 struct radeon_info info;
514 struct nir_shader_compiler_options *nir_options;
515 uint64_t debug_flags;
516 char renderer_string[183];
517
518 unsigned pa_sc_raster_config;
519 unsigned pa_sc_raster_config_1;
520 unsigned se_tile_repeat;
521 unsigned gs_table_depth;
522 struct ac_hs_info hs;
523 unsigned eqaa_force_coverage_samples;
524 unsigned eqaa_force_z_samples;
525 unsigned eqaa_force_color_samples;
526 unsigned pbb_context_states_per_bin;
527 unsigned pbb_persistent_states_per_bin;
528 bool has_draw_indirect_multi;
529 bool dpbb_allowed;
530 bool use_ngg;
531 bool use_ngg_culling;
532 bool allow_dcc_msaa_clear_to_reg_for_bpp[5]; /* indexed by log2(Bpp) */
533 bool always_allow_dcc_stores;
534 bool use_aco;
535
536 /* Force a single shader to use ACO, debug usage. */
537 bool force_shader_use_aco;
538 blake3_hash use_aco_shader_blake;
539
540 struct {
541 #define OPT_BOOL(name, dflt, description) bool name : 1;
542 #define OPT_INT(name, dflt, description) int name;
543 #include "si_debug_options.h"
544 } options;
545
546 /* Whether shaders are monolithic (1-part) or separate (3-part). */
547 bool use_monolithic_shaders;
548 bool record_llvm_ir;
549 const char *context_roll_log_filename;
550
551 struct slab_parent_pool pool_transfers;
552
553 /* Texture filter settings. */
554 int force_aniso; /* -1 = disabled */
555
556 /* Auxiliary context. Used to initialize resources and upload shaders. */
557 union {
558 struct {
559 struct si_aux_context general;
560
561 /* Used by resource_create to clear/initialize memory.
562 *
563 * Note that there are no barriers around the clears, which enables parallelism between
564 * individual clears. If anything else uses this context, it should wait for idle before
565 * using any buffer/texture.
566 */
567 struct si_aux_context compute_resource_init;
568
569 /* Second auxiliary context for uploading shaders. When the first auxiliary context is
570 * locked and wants to compile and upload shaders, we need to use a second auxiliary
571 * context because the first one is locked.
572 */
573 struct si_aux_context shader_upload;
574 } aux_context;
575 struct si_aux_context aux_contexts[3];
576 };
577
578 /* Async compute context for DRI_PRIME copies. */
579 struct pipe_context *async_compute_context;
580 simple_mtx_t async_compute_context_lock;
581
582 /* This must be in the screen, because UE4 uses one context for
583 * compilation and another one for rendering.
584 */
585 unsigned num_compilations;
586 /* Along with ST_DEBUG=precompile, this should show if applications
587 * are loading shaders on demand. This is a monotonic counter.
588 */
589 unsigned num_shaders_created;
590 unsigned num_memory_shader_cache_hits;
591 unsigned num_memory_shader_cache_misses;
592 unsigned num_disk_shader_cache_hits;
593 unsigned num_disk_shader_cache_misses;
594
595 /* GPU load thread. */
596 simple_mtx_t gpu_load_mutex;
597 thrd_t gpu_load_thread;
598 bool gpu_load_thread_created;
599 union si_mmio_counters mmio_counters;
600 volatile unsigned gpu_load_stop_thread; /* bool */
601
602 /* Performance counters. */
603 struct si_perfcounters *perfcounters;
604
605 /* If pipe_screen wants to recompute and re-emit the framebuffer,
606 * sampler, and image states of all contexts, it should atomically
607 * increment this.
608 *
609 * Each context will compare this with its own last known value of
610 * the counter before drawing and re-emit the states accordingly.
611 */
612 unsigned dirty_tex_counter;
613 unsigned dirty_buf_counter;
614
615 /* Atomically increment this counter when an existing texture's
616 * metadata is enabled or disabled in a way that requires changing
617 * contexts' compressed texture binding masks.
618 */
619 unsigned compressed_colortex_counter;
620
621 simple_mtx_t shader_parts_mutex;
622 struct si_shader_part *ps_prologs;
623 struct si_shader_part *ps_epilogs;
624
625 /* Shader cache in memory.
626 *
627 * Design & limitations:
628 * - The shader cache is per screen (= per process), never saved to
629 * disk, and skips redundant shader compilations from NIR to bytecode.
630 * - It can only be used with one-variant-per-shader support, in which
631 * case only the main (typically middle) part of shaders is cached.
632 * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
633 * variants of VS and TES are cached, so LS and ES aren't.
634 * - GS and CS aren't cached, but it's certainly possible to cache
635 * those as well.
636 */
637 simple_mtx_t shader_cache_mutex;
638 struct hash_table *shader_cache;
639 /* Maximum and current size */
640 uint32_t shader_cache_size;
641 uint32_t shader_cache_max_size;
642
643 /* Shader cache of live shaders. */
644 struct util_live_shader_cache live_shader_cache;
645
646 /* Shader compiler queue for multithreaded compilation. */
647 struct util_queue shader_compiler_queue;
648 /* Compiler instances for asynchronous shader compilation of new shader CSOs,
649 * one for each thread of the shader compiler queue.
650 */
651 struct ac_llvm_compiler *compiler[24]; /* used by the queue only */
652
653 struct util_queue shader_compiler_queue_opt_variants;
654 /* Compiler instances for asynchronous shader compilation of optimized shader variants,
655 * one for each thread of the low-priority shader compiler queue. */
656 struct ac_llvm_compiler *compiler_lowp[10];
657
658 struct util_idalloc_mt buffer_ids;
659 struct util_vertex_state_cache vertex_state_cache;
660
661 struct si_resource *attribute_pos_prim_ring;
662
663 simple_mtx_t tess_ring_lock;
664 struct pipe_resource *tess_rings;
665 struct pipe_resource *tess_rings_tmz;
666
667 /* NGG streamout. */
668 simple_mtx_t gds_mutex;
669 struct pb_buffer_lean *gds_oa;
670 };
671
672 struct si_compute {
673 struct si_shader_selector sel;
674 struct si_shader shader;
675
676 unsigned ir_type;
677 unsigned input_size;
678 };
679
680 struct si_sampler_view {
681 struct pipe_sampler_view base;
682 /* [0..7] = image descriptor
683 * [4..7] = buffer descriptor */
684 uint32_t state[8];
685 uint32_t fmask_state[8];
686 const struct legacy_surf_level *base_level_info;
687 uint8_t block_width;
688 bool is_stencil_sampler;
689 bool dcc_incompatible;
690 };
691
692 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
693
694 struct si_sampler_state {
695 #ifndef NDEBUG
696 unsigned magic;
697 #endif
698 uint32_t val[4];
699 uint32_t upgraded_depth_val[4];
700 };
701
702 struct si_cs_shader_state {
703 struct si_compute *program;
704 struct si_compute *emitted_program;
705 unsigned offset;
706 uint32_t variable_shared_size;
707 };
708
709 struct si_samplers {
710 struct pipe_sampler_view *views[SI_NUM_SAMPLERS];
711 struct si_sampler_state *sampler_states[SI_NUM_SAMPLERS];
712
713 /* The i-th bit is set if that element is enabled (non-NULL resource). */
714 unsigned enabled_mask;
715 uint32_t has_depth_tex_mask;
716 uint32_t needs_depth_decompress_mask;
717 uint32_t needs_color_decompress_mask;
718 };
719
720 struct si_images {
721 struct pipe_image_view views[SI_NUM_IMAGES];
722 uint32_t needs_color_decompress_mask;
723 unsigned enabled_mask;
724 unsigned display_dcc_store_mask;
725 };
726
727 struct si_framebuffer {
728 struct pipe_framebuffer_state state;
729 unsigned colorbuf_enabled_4bit;
730 unsigned spi_shader_col_format;
731 unsigned spi_shader_col_format_alpha;
732 unsigned spi_shader_col_format_blend;
733 unsigned spi_shader_col_format_blend_alpha;
734 uint8_t nr_samples : 5; /* at most 16xAA */
735 uint8_t log_samples : 3; /* at most 4 = 16xAA */
736 uint8_t nr_color_samples; /* at most 8xAA */
737 uint8_t compressed_cb_mask;
738 uint8_t uncompressed_cb_mask;
739 uint8_t color_is_int8;
740 uint8_t color_is_int10;
741 uint8_t dirty_cbufs;
742 uint8_t min_bytes_per_pixel;
743 bool dirty_zsbuf;
744 bool any_dst_linear;
745 bool CB_has_shader_readable_metadata;
746 bool DB_has_shader_readable_metadata;
747 bool all_DCC_pipe_aligned;
748 bool has_dcc_msaa;
749 bool disable_vrs_flat_shading;
750 bool has_stencil;
751 bool has_hiz_his;
752 };
753
754 enum si_quant_mode
755 {
756 /* The small prim precision computation depends on the enum values to be like this. */
757 SI_QUANT_MODE_16_8_FIXED_POINT_1_256TH,
758 SI_QUANT_MODE_14_10_FIXED_POINT_1_1024TH,
759 SI_QUANT_MODE_12_12_FIXED_POINT_1_4096TH,
760 };
761
762 struct si_signed_scissor {
763 int minx;
764 int miny;
765 int maxx;
766 int maxy;
767 enum si_quant_mode quant_mode;
768 };
769
770 struct si_viewports {
771 struct pipe_viewport_state states[SI_MAX_VIEWPORTS];
772 struct si_signed_scissor as_scissor[SI_MAX_VIEWPORTS];
773 };
774
775 struct si_streamout_target {
776 struct pipe_stream_output_target b;
777
778 /* The buffer where BUFFER_FILLED_SIZE is stored. */
779 struct si_resource *buf_filled_size;
780 unsigned buf_filled_size_offset;
781 unsigned buf_filled_size_draw_count_offset;
782 bool buf_filled_size_valid; /* only for legacy streamout */
783
784 unsigned stride;
785 };
786
787 struct si_streamout {
788 enum mesa_prim output_prim;
789 uint8_t num_verts_per_prim;
790 bool begin_emitted;
791
792 unsigned enabled_mask;
793 unsigned num_targets;
794 struct si_streamout_target *targets[PIPE_MAX_SO_BUFFERS];
795
796 unsigned append_bitmask;
797 bool suspended;
798
799 /* External state which comes from the vertex shader,
800 * it must be set explicitly when binding a shader. */
801 uint8_t *stride_in_dw;
802 unsigned enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
803
804 /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
805 unsigned hw_enabled_mask;
806
807 /* The state of VGT_STRMOUT_(CONFIG|EN). */
808 bool streamout_enabled;
809 bool prims_gen_query_enabled;
810 int num_prims_gen_queries;
811 };
812
813 /* A shader state consists of the shader selector, which is a constant state
814 * object shared by multiple contexts and shouldn't be modified, and
815 * the current shader variant selected for this context.
816 */
817 struct si_shader_ctx_state {
818 struct si_shader_selector *cso;
819 struct si_shader *current;
820 /* The shader variant key representing the current state. */
821 union si_shader_key key;
822 };
823
824 #define SI_NUM_VGT_PARAM_KEY_BITS 12
825 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
826
827 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
828 * Some fields are set by state-change calls, most are set by draw_vbo.
829 */
830 union si_vgt_param_key {
831 struct {
832 #if UTIL_ARCH_LITTLE_ENDIAN
833 uint16_t prim : 4;
834 uint16_t uses_instancing : 1;
835 uint16_t multi_instances_smaller_than_primgroup : 1;
836 uint16_t primitive_restart : 1;
837 uint16_t count_from_stream_output : 1;
838 uint16_t line_stipple_enabled : 1;
839 uint16_t uses_tess : 1;
840 uint16_t tess_uses_prim_id : 1;
841 uint16_t uses_gs : 1;
842 uint16_t _pad : 16 - SI_NUM_VGT_PARAM_KEY_BITS;
843 #else /* UTIL_ARCH_BIG_ENDIAN */
844 uint16_t _pad : 16 - SI_NUM_VGT_PARAM_KEY_BITS;
845 uint16_t uses_gs : 1;
846 uint16_t tess_uses_prim_id : 1;
847 uint16_t uses_tess : 1;
848 uint16_t line_stipple_enabled : 1;
849 uint16_t count_from_stream_output : 1;
850 uint16_t primitive_restart : 1;
851 uint16_t multi_instances_smaller_than_primgroup : 1;
852 uint16_t uses_instancing : 1;
853 uint16_t prim : 4;
854 #endif
855 } u;
856 uint16_t index;
857 };
858
859 struct si_texture_handle {
860 unsigned desc_slot;
861 bool desc_dirty;
862 struct pipe_sampler_view *view;
863 struct si_sampler_state sstate;
864 };
865
866 struct si_image_handle {
867 unsigned desc_slot;
868 bool desc_dirty;
869 struct pipe_image_view view;
870 };
871
872 struct si_saved_cs {
873 struct pipe_reference reference;
874 struct si_context *ctx;
875 struct radeon_saved_cs gfx;
876 struct radeon_saved_cs compute;
877 struct si_resource *trace_buf;
878 unsigned trace_id;
879
880 unsigned gfx_last_dw;
881 bool flushed;
882 int64_t time_flush;
883 };
884
885 struct si_sqtt_fake_pipeline {
886 struct si_pm4_state pm4; /* base class */
887 uint64_t code_hash;
888 struct si_resource *bo;
889 };
890
891 struct si_small_prim_cull_info {
892 float scale[2], translate[2];
893 float scale_no_aa[2], translate_no_aa[2];
894 float clip_half_line_width[2]; /* line_width * 0.5 in clip space in X and Y directions */
895 };
896
897 struct si_vertex_state {
898 struct pipe_vertex_state b;
899 struct si_vertex_elements velems;
900 uint32_t descriptors[4 * SI_MAX_ATTRIBS];
901 };
902
903 /* The structure layout is identical to a pair of registers in SET_*_REG_PAIRS_PACKED. */
904 struct gfx11_reg_pair {
905 union {
906 /* A pair of register offsets. */
907 struct {
908 uint16_t reg_offset[2];
909 };
910 /* The same pair of register offsets as a dword. */
911 uint32_t reg_offsets;
912 };
913 /* A pair of register values for the register offsets above. */
914 uint32_t reg_value[2];
915 };
916
917 /* A pair of values for SET_*_REG_PAIRS. */
918 struct gfx12_reg {
919 uint32_t reg_offset;
920 uint32_t reg_value;
921 };
922
923 typedef void (*pipe_draw_vertex_state_func)(struct pipe_context *ctx,
924 struct pipe_vertex_state *vstate,
925 uint32_t partial_velem_mask,
926 struct pipe_draw_vertex_state_info info,
927 const struct pipe_draw_start_count_bias *draws,
928 unsigned num_draws);
929
930 struct si_context {
931 struct pipe_context b; /* base class */
932
933 enum radeon_family family;
934 enum amd_gfx_level gfx_level;
935
936 struct radeon_winsys *ws;
937 struct radeon_winsys_ctx *ctx;
938 struct radeon_cmdbuf gfx_cs; /* compute IB if graphics is disabled */
939 struct radeon_cmdbuf *sdma_cs;
940 struct pipe_fence_handle *last_gfx_fence;
941 struct si_resource *eop_bug_scratch;
942 struct si_resource *eop_bug_scratch_tmz;
943 struct u_upload_mgr *cached_gtt_allocator;
944 struct threaded_context *tc;
945 struct u_suballocator allocator_zeroed_memory;
946 struct slab_child_pool pool_transfers;
947 struct slab_child_pool pool_transfers_unsync; /* for threaded_context */
948 struct pipe_device_reset_callback device_reset_callback;
949 struct u_log_context *log;
950 void *query_result_shader;
951 void *sh_query_result_shader;
952 struct {
953 /* Memory where the shadowed registers will be saved and loaded from. */
954 struct si_resource *registers;
955 /* Context Save Area: scratch area to save other required data. Only
956 * used if info->has_fw_based_mcbp is true.
957 */
958 struct si_resource *csa;
959 } shadowing;
960
961 void (*emit_barrier)(struct si_context *ctx, struct radeon_cmdbuf *cs);
962
963 struct blitter_context *blitter;
964 void *noop_blend;
965 void *noop_dsa;
966 void *no_velems_state;
967 void *discard_rasterizer_state;
968 void *custom_dsa_flush;
969 void *custom_blend_resolve;
970 void *custom_blend_fmask_decompress;
971 void *custom_blend_eliminate_fastclear;
972 void *custom_blend_dcc_decompress;
973 void *vs_blit_pos;
974 void *vs_blit_pos_layered;
975 void *vs_blit_color;
976 void *vs_blit_color_layered;
977 void *vs_blit_texcoord;
978 void *cs_clear_buffer_rmw;
979 void *cs_ubyte_to_ushort;
980 void *cs_dcc_retile[32];
981 void *cs_fmask_expand[3][2]; /* [log2(samples)-1][is_array] */
982 struct hash_table_u64 *cs_dma_shaders; /* clear_buffer and copy_buffer shaders */
983 struct hash_table_u64 *cs_blit_shaders;
984 struct hash_table_u64 *ps_resolve_shaders;
985 struct si_screen *screen;
986 struct util_debug_callback debug;
987 struct ac_llvm_compiler *compiler; /* only non-threaded compilation */
988 struct hash_table *fixed_func_tcs_shader_cache;
989 struct si_resource *wait_mem_scratch;
990 struct si_resource *wait_mem_scratch_tmz;
991 unsigned wait_mem_number;
992 uint16_t prefetch_L2_mask;
993
994 bool blitter_running:1;
995 bool suppress_update_ps_colorbuf0_slot:1;
996 bool is_noop:1;
997 bool has_graphics:1;
998 bool gfx_flush_in_progress : 1;
999 bool gfx_last_ib_is_busy : 1;
1000 bool compute_is_busy : 1;
1001 bool gfx11_force_msaa_num_samples_zero:1;
1002 int8_t pipeline_stats_enabled; /* -1 = unknown, 0 = disabled, 1 = enabled */
1003
1004 unsigned num_gfx_cs_flushes;
1005 unsigned initial_gfx_cs_size;
1006 unsigned last_dirty_tex_counter;
1007 unsigned last_dirty_buf_counter;
1008 unsigned last_compressed_colortex_counter;
1009 struct {
1010 unsigned with_cb;
1011 unsigned with_db;
1012 } num_draw_calls_sh_coherent;
1013 unsigned barrier_flags;
1014
1015 /* Atoms (state emit functions). */
1016 union si_state_atoms atoms;
1017 uint64_t dirty_atoms; /* mask */
1018 union si_state queued;
1019 union si_state emitted;
1020
1021 /* Gfx11+: Buffered SH registers for SET_SH_REG_PAIRS_*. */
1022 unsigned num_buffered_gfx_sh_regs;
1023 unsigned num_buffered_compute_sh_regs;
1024 union {
1025 struct {
1026 struct gfx11_reg_pair buffered_gfx_sh_regs[32];
1027 struct gfx11_reg_pair buffered_compute_sh_regs[32];
1028 } gfx11;
1029
1030 struct {
1031 struct gfx12_reg buffered_gfx_sh_regs[64];
1032 struct gfx12_reg buffered_compute_sh_regs[64];
1033 } gfx12;
1034 };
1035
1036 /* Atom declarations. */
1037 struct si_framebuffer framebuffer;
1038 unsigned sample_locs_num_samples;
1039 uint16_t sample_mask;
1040 unsigned last_cb_target_mask;
1041 struct pipe_blend_color blend_color;
1042 struct pipe_clip_state clip_state;
1043 struct si_shader_data shader_pointers;
1044 struct si_stencil_ref stencil_ref;
1045 bool blend_color_any_nonzeros:1;
1046 bool clip_state_any_nonzeros:1;
1047 bool viewport0_y_inverted;
1048 struct pipe_scissor_state scissors[SI_MAX_VIEWPORTS];
1049 struct si_streamout streamout;
1050 struct si_viewports viewports;
1051 unsigned num_window_rectangles;
1052 bool window_rectangles_include;
1053 struct pipe_scissor_state window_rectangles[4];
1054
1055 /* Precomputed states. */
1056 struct si_pm4_state *cs_preamble_state;
1057 struct si_pm4_state *cs_preamble_state_tmz;
1058 uint16_t gs_ring_state_dw_offset;
1059 uint16_t gs_ring_state_dw_offset_tmz;
1060 bool cs_preamble_has_vgt_flush;
1061 bool cs_preamble_has_vgt_flush_tmz;
1062 uint32_t vgt_shader_stages_en;
1063 uint32_t ge_cntl;
1064
1065 /* shaders */
1066 union {
1067 struct {
1068 struct si_shader_ctx_state vs;
1069 struct si_shader_ctx_state tcs;
1070 struct si_shader_ctx_state tes;
1071 struct si_shader_ctx_state gs;
1072 struct si_shader_ctx_state ps;
1073 } shader;
1074 struct si_shader_ctx_state shaders[SI_NUM_GRAPHICS_SHADERS];
1075 };
1076 struct si_cs_shader_state cs_shader_state;
1077 bool compute_ping_pong_launch;
1078 /* if current tcs set by user */
1079 bool is_user_tcs;
1080
1081 /* video context */
1082 bool vcn_has_ctx;
1083 enum vcn_version vcn_ip_ver;
1084
1085 /* shader information */
1086 uint64_t ps_inputs_read_or_disabled;
1087 struct si_vertex_elements *vertex_elements;
1088 unsigned num_vertex_elements;
1089 unsigned cs_max_waves_per_sh;
1090 uint32_t compute_tmpring_size;
1091 bool uses_nontrivial_vs_inputs;
1092 bool force_trivial_vs_inputs;
1093 bool do_update_shaders;
1094 bool compute_shaderbuf_sgprs_dirty;
1095 bool compute_image_sgprs_dirty;
1096 bool vs_uses_base_instance;
1097 bool vs_uses_draw_id;
1098 uint8_t patch_vertices;
1099 bool has_tessellation; /* whether si_screen::tess_rings* are valid */
1100
1101 /* shader descriptors */
1102 struct si_descriptors descriptors[SI_NUM_DESCS];
1103 unsigned descriptors_dirty;
1104 unsigned shader_pointers_dirty;
1105 unsigned shader_needs_decompress_mask;
1106 unsigned shader_has_depth_tex;
1107 struct si_buffer_resources internal_bindings;
1108 struct si_buffer_resources const_and_shader_buffers[SI_NUM_SHADERS];
1109 struct si_samplers samplers[SI_NUM_SHADERS];
1110 struct si_images images[SI_NUM_SHADERS];
1111 bool bo_list_add_all_resident_resources;
1112 bool bo_list_add_all_compute_resources;
1113
1114 /* tracked buffers for OpenCL */
1115 int max_global_buffers;
1116 struct pipe_resource **global_buffers;
1117
1118 /* other shader resources */
1119 struct pipe_constant_buffer null_const_buf; /* used for set_constant_buffer(NULL) on GFX7 */
1120 struct pipe_resource *esgs_ring;
1121 struct pipe_resource *gsvs_ring;
1122 union pipe_color_union *border_color_table; /* in CPU memory, any endian */
1123 struct si_resource *border_color_buffer;
1124 union pipe_color_union *border_color_map; /* in VRAM (slow access), little endian */
1125 unsigned border_color_count;
1126 unsigned num_vs_blit_sgprs;
1127 uint32_t vs_blit_sh_data[MAX_SI_VS_BLIT_SGPRS];
1128 uint32_t cs_user_data[8];
1129
1130 /* Vertex buffers. */
1131 bool vertex_buffers_dirty;
1132 uint8_t num_vertex_buffers;
1133 uint16_t vertex_buffer_unaligned; /* bitmask of not dword-aligned buffers */
1134 struct pipe_vertex_buffer vertex_buffer[SI_NUM_VERTEX_BUFFERS];
1135
1136 /* Even though we don't need this variable, u_upload_alloc has an optimization that skips
1137 * reference counting when the new upload buffer is the same as the last one. So keep
1138 * the last upload buffer here and always pass &last_const_upload_buffer to u_upload_alloc.
1139 */
1140 struct si_resource *last_const_upload_buffer;
1141
1142 /* MSAA config state. */
1143 uint8_t ps_iter_samples;
1144 uint8_t last_ps_iter_samples;
1145 bool ps_uses_fbfetch;
1146 bool smoothing_enabled;
1147
1148 /* point smoothing state.*/
1149 bool point_smoothing_enabled;
1150
1151 /* DB render state. */
1152 unsigned ps_db_shader_control;
1153 unsigned ps_pa_sc_hisz_control;
1154 unsigned dbcb_copy_sample;
1155 bool dbcb_depth_copy_enabled : 1;
1156 bool dbcb_stencil_copy_enabled : 1;
1157 bool db_flush_depth_inplace : 1;
1158 bool db_flush_stencil_inplace : 1;
1159 bool db_depth_clear : 1;
1160 bool db_depth_disable_expclear : 1;
1161 bool db_stencil_clear : 1;
1162 bool db_stencil_disable_expclear : 1;
1163 bool occlusion_queries_disabled : 1;
1164 bool generate_mipmap_for_depth : 1;
1165 bool allow_flat_shading : 1;
1166
1167 /* Emitted draw state. */
1168 bool ngg : 1;
1169 bool disable_instance_packing : 1;
1170 uint16_t ngg_culling;
1171 unsigned last_index_size;
1172 unsigned last_instance_count;
1173 int last_primitive_restart_en;
1174 unsigned last_restart_index;
1175 unsigned last_prim;
1176 unsigned current_vs_state; /* all VS bits */
1177 unsigned current_gs_state; /* only GS and NGG bits */
1178 unsigned last_vs_state;
1179 unsigned last_gs_state;
1180 enum mesa_prim current_rast_prim; /* primitive type after TES, GS */
1181 unsigned gs_out_prim;
1182
1183 struct si_small_prim_cull_info last_small_prim_cull_info;
1184 struct si_resource *small_prim_cull_info_buf;
1185 uint64_t small_prim_cull_info_address;
1186
1187 /* Scratch buffer */
1188 struct si_resource *scratch_buffer;
1189 unsigned spi_tmpring_size;
1190 unsigned max_seen_scratch_bytes_per_wave;
1191 unsigned max_seen_compute_scratch_bytes_per_wave;
1192
1193 struct si_resource *compute_scratch_buffer;
1194
1195 /* Emitted derived tessellation state. */
1196 /* Local shader (VS), or HS if LS-HS are merged. */
1197 struct si_shader *last_ls;
1198 struct si_shader_selector *last_tcs;
1199 unsigned last_num_tcs_input_cp;
1200 unsigned last_tes_sh_base;
1201 bool last_tess_uses_primid;
1202 unsigned num_patches_per_workgroup;
1203 unsigned tcs_offchip_layout;
1204 unsigned tes_offchip_ring_va_sgpr;
1205 unsigned ls_hs_rsrc2;
1206 unsigned ls_hs_config;
1207
1208 /* Debug state. */
1209 bool is_debug;
1210 struct si_saved_cs *current_saved_cs;
1211 uint64_t dmesg_timestamp;
1212 unsigned apitrace_call_number;
1213
1214 /* Other state */
1215 bool need_check_render_feedback;
1216 bool decompression_enabled;
1217 bool dpbb_force_off;
1218 bool dpbb_force_off_profile_vs;
1219 bool dpbb_force_off_profile_ps;
1220 bool vs_writes_viewport_index;
1221 bool vs_disables_clipping_viewport;
1222 bool has_reset_been_notified;
1223
1224 /* The number of pixels outside the viewport that are not culled by the clipper.
1225 * Normally, the clipper clips everything outside the viewport, however, points and lines
1226 * can have vertices outside the viewport, but their edges can be inside the viewport. Those
1227 * shouldn't be culled. The problem is that the register setting (PA_CL_GB_*_DISC_ADJ) that
1228 * controls the discard distance, which depends on the point size and line width, applies to
1229 * all primitive types, and we would have to set 0 distance for triangles and non-zero for
1230 * points and lines whenever the primitive type changes, which would add overhead and cause
1231 * context rolls.
1232 *
1233 * To reduce that, whenever the discard distance changes for points and lines, we keep it
1234 * at that higher value up to a certain small number for all primitive types including all
1235 * points and lines within a specific size. This is slightly inefficient, but it eliminates
1236 * a lot of guardband state updates and context register changes.
1237 */
1238 float min_clip_discard_distance_watermark;
1239 float current_clip_discard_distance;
1240
1241 /* Precomputed IA_MULTI_VGT_PARAM */
1242 union si_vgt_param_key ia_multi_vgt_param_key;
1243 unsigned ia_multi_vgt_param[SI_NUM_VGT_PARAM_STATES];
1244
1245 /* Bindless descriptors. */
1246 struct si_descriptors bindless_descriptors;
1247 struct util_idalloc bindless_used_slots;
1248 unsigned num_bindless_descriptors;
1249 bool bindless_descriptors_dirty;
1250 bool graphics_internal_bindings_pointer_dirty;
1251 bool compute_internal_bindings_pointer_dirty;
1252 bool graphics_bindless_pointer_dirty;
1253 bool compute_bindless_pointer_dirty;
1254 bool gs_attribute_ring_pointer_dirty;
1255
1256 /* Allocated bindless handles */
1257 struct hash_table *tex_handles;
1258 struct hash_table *img_handles;
1259
1260 /* Resident bindless handles */
1261 struct util_dynarray resident_tex_handles;
1262 struct util_dynarray resident_img_handles;
1263
1264 /* Resident bindless handles which need decompression */
1265 struct util_dynarray resident_tex_needs_color_decompress;
1266 struct util_dynarray resident_img_needs_color_decompress;
1267 struct util_dynarray resident_tex_needs_depth_decompress;
1268
1269 /* Bindless state */
1270 bool uses_bindless_samplers;
1271 bool uses_bindless_images;
1272
1273 /* Misc stats. */
1274 unsigned num_draw_calls;
1275 unsigned num_decompress_calls;
1276 unsigned last_cb_flush_num_draw_calls;
1277 unsigned last_db_flush_num_draw_calls;
1278 unsigned last_ps_sync_num_draw_calls;
1279 unsigned last_vs_sync_num_draw_calls;
1280 unsigned last_cb_flush_num_decompress_calls;
1281 unsigned last_db_flush_num_decompress_calls;
1282 unsigned num_compute_calls;
1283 unsigned num_cp_dma_calls;
1284 unsigned num_vs_flushes;
1285 unsigned num_ps_flushes;
1286 unsigned num_cs_flushes;
1287 unsigned num_cb_cache_flushes;
1288 unsigned num_db_cache_flushes;
1289 unsigned num_L2_invalidates;
1290 unsigned num_L2_writebacks;
1291 unsigned num_resident_handles;
1292 uint64_t num_alloc_tex_transfer_bytes;
1293 unsigned last_tex_ps_draw_ratio; /* for query */
1294 unsigned context_roll;
1295
1296 /* Queries. */
1297 /* Maintain the list of active queries for pausing between IBs. */
1298 enum si_occlusion_query_mode occlusion_query_mode;
1299 int num_integer_occlusion_queries;
1300 int num_boolean_occlusion_queries;
1301 int num_conservative_occlusion_queries;
1302 int num_pipeline_stat_queries;
1303 int num_pipeline_stat_emulated_queries;
1304 int num_hw_pipestat_streamout_queries;
1305 struct list_head active_queries;
1306 unsigned num_cs_dw_queries_suspend;
1307 /* Shared buffer for pipeline stats queries implemented with an atomic op */
1308 struct si_resource *pipeline_stats_query_buf;
1309
1310 /* Render condition. */
1311 struct pipe_query *render_cond;
1312 unsigned render_cond_mode;
1313 bool render_cond_invert;
1314 bool render_cond_enabled; /* for u_blitter */
1315
1316 /* Shader-based queries. */
1317 struct list_head shader_query_buffers;
1318 unsigned num_active_shader_queries;
1319
1320 struct {
1321 bool with_cb;
1322 bool with_db;
1323 } force_shader_coherency;
1324
1325 struct si_tracked_regs tracked_regs;
1326
1327 /* Resources that need to be flushed, but will not get an explicit
1328 * flush_resource from the frontend and that will need to get flushed during
1329 * a context flush.
1330 */
1331 struct hash_table *dirty_implicit_resources;
1332
1333 pipe_draw_func draw_vbo[2][2][2];
1334 pipe_draw_vertex_state_func draw_vertex_state[2][2][2];
1335 /* When b.draw_vbo is a wrapper, real_draw_vbo is the real draw_vbo function */
1336 pipe_draw_func real_draw_vbo;
1337 pipe_draw_vertex_state_func real_draw_vertex_state;
1338 void (*emit_spi_map[33])(struct si_context *sctx, unsigned index);
1339
1340 /* SQTT */
1341 struct ac_sqtt *sqtt;
1342 struct ac_spm spm;
1343 struct pipe_fence_handle *last_sqtt_fence;
1344 enum rgp_sqtt_marker_event_type sqtt_next_event;
1345 bool sqtt_enabled;
1346
1347 unsigned context_flags;
1348
1349 /* Shaders. */
1350 void *cs_clear_image_dcc_single[2][3]; /* [is_msaa][wg_dim] */
1351 /* Only used for DCC MSAA clears with 4-8 fragments and 4-16 samples. */
1352 void *cs_clear_dcc_msaa[32][5][2][3][2]; /* [swizzle_mode][log2(bpe)][fragments == 8][log2(samples)-2][is_array] */
1353
1354 /* u_trace logging*/
1355 struct si_ds_device ds;
1356 /** Where tracepoints are recorded */
1357 struct u_trace trace;
1358 struct si_ds_queue ds_queue;
1359 uint32_t *last_timestamp_cmd;
1360 unsigned int last_timestamp_cmd_cdw;
1361 };
1362
1363 /* si_barrier.c */
1364 #define SI_FB_BARRIER_SYNC_CB BITFIELD_BIT(0)
1365 #define SI_FB_BARRIER_SYNC_DB BITFIELD_BIT(1)
1366 #define SI_FB_BARRIER_SYNC_ALL BITFIELD_RANGE(0, 2)
1367
1368 void si_barrier_before_internal_op(struct si_context *sctx, unsigned flags,
1369 unsigned num_buffers,
1370 const struct pipe_shader_buffer *buffers,
1371 unsigned writable_buffers_mask,
1372 unsigned num_images,
1373 const struct pipe_image_view *images);
1374 void si_barrier_after_internal_op(struct si_context *sctx, unsigned flags,
1375 unsigned num_buffers,
1376 const struct pipe_shader_buffer *buffers,
1377 unsigned writable_buffers_mask,
1378 unsigned num_images,
1379 const struct pipe_image_view *images);
1380 void si_barrier_before_simple_buffer_op(struct si_context *sctx, unsigned flags,
1381 struct pipe_resource *dst, struct pipe_resource *src);
1382 void si_barrier_after_simple_buffer_op(struct si_context *sctx, unsigned flags,
1383 struct pipe_resource *dst, struct pipe_resource *src);
1384 void si_fb_barrier_before_rendering(struct si_context *sctx);
1385 void si_fb_barrier_after_rendering(struct si_context *sctx, unsigned flags);
1386 void si_barrier_before_image_fast_clear(struct si_context *sctx, unsigned types);
1387 void si_barrier_after_image_fast_clear(struct si_context *sctx);
1388 void si_init_barrier_functions(struct si_context *sctx);
1389
1390 /* si_blit.c */
1391 enum si_blitter_op /* bitmask */
1392 {
1393 SI_SAVE_TEXTURES = 1,
1394 SI_SAVE_FRAMEBUFFER = 2,
1395 SI_SAVE_FRAGMENT_STATE = 4,
1396 SI_SAVE_FRAGMENT_CONSTANT = 8,
1397 SI_DISABLE_RENDER_COND = 16,
1398 };
1399
1400 void si_blitter_begin(struct si_context *sctx, enum si_blitter_op op);
1401 void si_blitter_end(struct si_context *sctx);
1402 void si_init_blit_functions(struct si_context *sctx);
1403 void gfx6_decompress_textures(struct si_context *sctx, unsigned shader_mask);
1404 void gfx11_decompress_textures(struct si_context *sctx, unsigned shader_mask);
1405 void si_decompress_subresource(struct pipe_context *ctx, struct pipe_resource *tex, unsigned planes,
1406 unsigned level, unsigned first_layer, unsigned last_layer,
1407 bool need_fmask_expand);
1408 void si_resource_copy_region(struct pipe_context *ctx, struct pipe_resource *dst,
1409 unsigned dst_level, unsigned dstx, unsigned dsty, unsigned dstz,
1410 struct pipe_resource *src, unsigned src_level,
1411 const struct pipe_box *src_box);
1412 void si_gfx_copy_image(struct si_context *sctx, struct pipe_resource *dst,
1413 unsigned dst_level, unsigned dstx, unsigned dsty, unsigned dstz,
1414 struct pipe_resource *src, unsigned src_level,
1415 const struct pipe_box *src_box);
1416 void si_decompress_dcc(struct si_context *sctx, struct si_texture *tex);
1417 void si_flush_implicit_resources(struct si_context *sctx);
1418 bool si_msaa_resolve_blit_via_CB(struct pipe_context *ctx, const struct pipe_blit_info *info,
1419 bool fail_if_slow);
1420 void si_gfx_blit(struct pipe_context *ctx, const struct pipe_blit_info *info);
1421
1422 /* si_nir_optim.c */
1423 bool si_nir_is_output_const_if_tex_is_const(struct nir_shader *shader, float *in, float *out, int *texunit);
1424
1425 /* si_buffer.c */
1426 bool si_cs_is_buffer_referenced(struct si_context *sctx, struct pb_buffer_lean *buf,
1427 unsigned usage);
1428 void *si_buffer_map(struct si_context *sctx, struct si_resource *resource,
1429 unsigned usage);
1430 void si_init_resource_fields(struct si_screen *sscreen, struct si_resource *res, uint64_t size,
1431 unsigned alignment);
1432 bool si_alloc_resource(struct si_screen *sscreen, struct si_resource *res);
1433 struct pipe_resource *pipe_aligned_buffer_create(struct pipe_screen *screen, unsigned flags,
1434 unsigned usage, unsigned size, unsigned alignment);
1435 struct si_resource *si_aligned_buffer_create(struct pipe_screen *screen, unsigned flags,
1436 unsigned usage, unsigned size, unsigned alignment);
1437 struct pipe_resource *si_buffer_from_winsys_buffer(struct pipe_screen *screen,
1438 const struct pipe_resource *templ,
1439 struct pb_buffer_lean *imported_buf,
1440 uint64_t offset);
1441 void si_replace_buffer_storage(struct pipe_context *ctx, struct pipe_resource *dst,
1442 struct pipe_resource *src, unsigned num_rebinds,
1443 uint32_t rebind_mask, uint32_t delete_buffer_id);
1444 void si_init_screen_buffer_functions(struct si_screen *sscreen);
1445 void si_init_buffer_functions(struct si_context *sctx);
1446
1447 /* si_clear.c */
1448 #define SI_CLEAR_TYPE_CMASK (1 << 0)
1449 #define SI_CLEAR_TYPE_DCC (1 << 1)
1450 #define SI_CLEAR_TYPE_HTILE (1 << 2)
1451
1452 struct si_clear_info {
1453 struct pipe_resource *resource;
1454 uint64_t offset;
1455 uint32_t size;
1456 uint32_t clear_value;
1457 uint32_t writemask;
1458 bool is_dcc_msaa; /* Clear it as a DCC MSAA image. */
1459 uint8_t level;
1460 enum pipe_format format;
1461 union pipe_color_union color;
1462 };
1463
1464 bool vi_dcc_get_clear_info(struct si_context *sctx, struct si_texture *tex, unsigned level,
1465 unsigned clear_value, struct si_clear_info *out);
1466 void si_init_buffer_clear(struct si_clear_info *info,
1467 struct pipe_resource *resource, uint64_t offset,
1468 uint32_t size, uint32_t clear_value);
1469 void si_execute_clears(struct si_context *sctx, struct si_clear_info *info,
1470 unsigned num_clears, bool render_condition_enabled);
1471 bool si_compute_fast_clear_image(struct si_context *sctx, struct pipe_resource *tex,
1472 enum pipe_format format, unsigned level, const struct pipe_box *box,
1473 const union pipe_color_union *color, bool render_condition_enable,
1474 bool fail_if_slow);
1475 void si_gfx_clear_render_target(struct pipe_context *ctx, struct pipe_surface *dst,
1476 const union pipe_color_union *color, unsigned dstx,
1477 unsigned dsty, unsigned width, unsigned height,
1478 bool render_condition_enabled);
1479 void si_init_clear_functions(struct si_context *sctx);
1480
1481 /* si_compute.c */
1482 void si_destroy_compute(struct si_compute *program);
1483
1484 /* si_compute_blit.c */
1485 bool si_should_blit_clamp_to_edge(const struct pipe_blit_info *info, unsigned coord_mask);
1486 void si_launch_grid_internal_ssbos(struct si_context *sctx, struct pipe_grid_info *info,
1487 void *shader, unsigned num_buffers,
1488 const struct pipe_shader_buffer *buffers,
1489 unsigned writeable_bitmask, bool render_condition_enable);
1490 bool si_compute_clear_copy_buffer(struct si_context *sctx, struct pipe_resource *dst,
1491 unsigned dst_offset, struct pipe_resource *src,
1492 unsigned src_offset, unsigned size,
1493 const uint32_t *clear_value, unsigned clear_value_size,
1494 unsigned dwords_per_thread, bool render_condition_enable,
1495 bool fail_if_slow);
1496 enum si_clear_method {
1497 SI_COMPUTE_CLEAR_METHOD,
1498 SI_AUTO_SELECT_CLEAR_METHOD
1499 };
1500 void si_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
1501 uint64_t offset, uint64_t size, uint32_t *clear_value,
1502 uint32_t clear_value_size, enum si_clear_method method,
1503 bool render_condition_enable);
1504 void si_compute_clear_buffer_rmw(struct si_context *sctx, struct pipe_resource *dst,
1505 unsigned dst_offset, unsigned size, uint32_t clear_value,
1506 uint32_t writebitmask, bool render_condition_enable);
1507 void si_copy_buffer(struct si_context *sctx, struct pipe_resource *dst, struct pipe_resource *src,
1508 uint64_t dst_offset, uint64_t src_offset, unsigned size);
1509 void si_compute_shorten_ubyte_buffer(struct si_context *sctx, struct pipe_resource *dst, struct pipe_resource *src,
1510 uint64_t dst_offset, uint64_t src_offset, unsigned size,
1511 bool render_condition_enable);
1512 void si_compute_clear_image_dcc_single(struct si_context *sctx, struct si_texture *tex,
1513 unsigned level, enum pipe_format format,
1514 const union pipe_color_union *color,
1515 bool render_condition_enable);
1516 void si_retile_dcc(struct si_context *sctx, struct si_texture *tex);
1517 void gfx9_clear_dcc_msaa(struct si_context *sctx, struct pipe_resource *res, uint32_t clear_value,
1518 bool render_condition_enable);
1519 void si_compute_expand_fmask(struct pipe_context *ctx, struct pipe_resource *tex);
1520 bool si_compute_clear_image(struct si_context *sctx, struct pipe_resource *tex,
1521 enum pipe_format format, unsigned level, const struct pipe_box *box,
1522 const union pipe_color_union *color, bool render_condition_enable,
1523 bool fail_if_slow);
1524 bool si_compute_copy_image(struct si_context *sctx, struct pipe_resource *dst, unsigned dst_level,
1525 struct pipe_resource *src, unsigned src_level, unsigned dstx,
1526 unsigned dsty, unsigned dstz, const struct pipe_box *src_box,
1527 bool fail_if_slow);
1528 bool si_compute_blit(struct si_context *sctx, const struct pipe_blit_info *info,
1529 const union pipe_color_union *clear_color, unsigned dst_access,
1530 unsigned src_access, bool fail_if_slow);
1531 void si_init_compute_blit_functions(struct si_context *sctx);
1532
1533 /* si_cp_dma.c */
1534 void si_cp_dma_wait_for_idle(struct si_context *sctx, struct radeon_cmdbuf *cs);
1535 void si_cp_dma_clear_buffer(struct si_context *sctx, struct radeon_cmdbuf *cs,
1536 struct pipe_resource *dst, uint64_t offset, uint64_t size,
1537 unsigned value);
1538 void si_cp_dma_copy_buffer(struct si_context *sctx, struct pipe_resource *dst,
1539 struct pipe_resource *src, uint64_t dst_offset, uint64_t src_offset,
1540 unsigned size);
1541 void si_cp_write_data(struct si_context *sctx, struct si_resource *buf, unsigned offset,
1542 unsigned size, unsigned dst_sel, unsigned engine, const void *data);
1543 void si_cp_copy_data(struct si_context *sctx, struct radeon_cmdbuf *cs, unsigned dst_sel,
1544 struct si_resource *dst, unsigned dst_offset, unsigned src_sel,
1545 struct si_resource *src, unsigned src_offset);
1546
1547 /* si_cp_reg_shadowing.c */
1548 void si_init_cp_reg_shadowing(struct si_context *sctx);
1549
1550 /* si_cp_utils.c */
1551 void si_cp_release_mem_pws(struct si_context *sctx, struct radeon_cmdbuf *cs,
1552 unsigned event_type, unsigned gcr_cntl);
1553 void si_cp_acquire_mem_pws(struct si_context *sctx, struct radeon_cmdbuf *cs,
1554 unsigned event_type, unsigned stage_sel, unsigned gcr_cntl,
1555 unsigned distance, unsigned sqtt_flush_flags);
1556 void si_cp_release_acquire_mem_pws(struct si_context *sctx, struct radeon_cmdbuf *cs,
1557 unsigned event_type, unsigned gcr_cntl, unsigned stage_sel,
1558 unsigned sqtt_flush_flags);
1559 void si_cp_acquire_mem(struct si_context *sctx, struct radeon_cmdbuf *cs, unsigned gcr_cntl,
1560 unsigned engine);
1561 void si_cp_pfp_sync_me(struct radeon_cmdbuf *cs);
1562
1563 /* si_debug.c */
1564 void si_gather_context_rolls(struct si_context *sctx);
1565 void si_save_cs(struct radeon_winsys *ws, struct radeon_cmdbuf *cs, struct radeon_saved_cs *saved,
1566 bool get_buffer_list);
1567 void si_destroy_saved_cs(struct si_saved_cs *scs);
1568 void si_auto_log_cs(void *data, struct u_log_context *log);
1569 void si_log_hw_flush(struct si_context *sctx);
1570 void si_log_draw_state(struct si_context *sctx, struct u_log_context *log);
1571 void si_log_compute_state(struct si_context *sctx, struct u_log_context *log);
1572 void si_init_debug_functions(struct si_context *sctx);
1573 void si_check_vm_faults(struct si_context *sctx, struct radeon_saved_cs *saved);
1574 bool si_replace_shader(unsigned num, struct si_shader_binary *binary);
1575 void si_print_current_ib(struct si_context *sctx, FILE *f);
1576
1577 /* si_fence.c */
1578 void si_cp_release_mem(struct si_context *ctx, struct radeon_cmdbuf *cs, unsigned event,
1579 unsigned event_flags, unsigned dst_sel, unsigned int_sel, unsigned data_sel,
1580 struct si_resource *buf, uint64_t va, uint32_t new_fence,
1581 unsigned query_type);
1582 unsigned si_cp_write_fence_dwords(struct si_screen *screen);
1583 void si_cp_wait_mem(struct si_context *ctx, struct radeon_cmdbuf *cs, uint64_t va, uint32_t ref,
1584 uint32_t mask, unsigned flags);
1585 void si_init_fence_functions(struct si_context *ctx);
1586 void si_init_screen_fence_functions(struct si_screen *screen);
1587 struct pipe_fence_handle *si_create_fence(struct pipe_context *ctx,
1588 struct tc_unflushed_batch_token *tc_token);
1589
1590 /* si_get.c */
1591 void si_init_screen_get_functions(struct si_screen *sscreen);
1592 void si_init_screen_caps(struct si_screen *sscreen);
1593
1594 bool si_sdma_copy_image(struct si_context *ctx, struct si_texture *dst, struct si_texture *src);
1595
1596 /* si_gfx_cs.c */
1597 void si_reset_debug_log_buffer(struct si_context *sctx);
1598 void si_flush_gfx_cs(struct si_context *ctx, unsigned flags, struct pipe_fence_handle **fence);
1599 void si_set_tracked_regs_to_clear_state(struct si_context *ctx);
1600 void si_begin_new_gfx_cs(struct si_context *ctx, bool first_cs);
1601 void si_trace_emit(struct si_context *sctx);
1602 void si_emit_ts(struct si_context *sctx, struct si_resource* buffer, unsigned int offset);
1603 /* Replace the sctx->b.draw_vbo function with a wrapper. This can be use to implement
1604 * optimizations without affecting the normal draw_vbo functions perf.
1605 */
1606 void si_install_draw_wrapper(struct si_context *sctx, pipe_draw_func wrapper,
1607 pipe_draw_vertex_state_func vstate_wrapper);
1608
1609 /* si_gpu_load.c */
1610 void si_gpu_load_kill_thread(struct si_screen *sscreen);
1611 uint64_t si_begin_counter(struct si_screen *sscreen, unsigned type);
1612 unsigned si_end_counter(struct si_screen *sscreen, unsigned type, uint64_t begin);
1613
1614 /* si_compute.c */
1615 void si_init_compute_functions(struct si_context *sctx);
1616
1617 /* si_pipe.c */
1618 struct ac_llvm_compiler *si_create_llvm_compiler(struct si_screen *sscreen);
1619 void si_init_aux_async_compute_ctx(struct si_screen *sscreen);
1620 struct si_context *si_get_aux_context(struct si_aux_context *ctx);
1621 void si_put_aux_context_flush(struct si_aux_context *ctx);
1622 void si_destroy_screen(struct pipe_screen *pscreen);
1623
1624 /* si_perfcounters.c */
1625 void si_init_perfcounters(struct si_screen *screen);
1626 void si_destroy_perfcounters(struct si_screen *screen);
1627 void si_inhibit_clockgating(struct si_context *sctx, struct radeon_cmdbuf *cs, bool inhibit);
1628 void si_pc_emit_shaders(struct radeon_cmdbuf *cs, unsigned shaders);
1629 void si_pc_emit_spm_start(struct radeon_cmdbuf *cs);
1630 void si_pc_emit_spm_stop(struct radeon_cmdbuf *cs, bool never_stop_sq_perf_counters,
1631 bool never_send_perfcounter_stop);
1632 void si_pc_emit_spm_reset(struct radeon_cmdbuf *cs);
1633 void si_emit_spm_setup(struct si_context *sctx, struct radeon_cmdbuf *cs);
1634 bool si_spm_init(struct si_context *sctx);
1635 void si_spm_finish(struct si_context *sctx);
1636
1637 /* si_query.c */
1638 void si_init_screen_query_functions(struct si_screen *sscreen);
1639 void si_init_query_functions(struct si_context *sctx);
1640 void si_suspend_queries(struct si_context *sctx);
1641 void si_resume_queries(struct si_context *sctx);
1642
1643 /* si_shaderlib_nir.c */
1644
1645 void *si_create_shader_state(struct si_context *sctx, struct nir_shader *nir);
1646 void *si_create_dcc_retile_cs(struct si_context *sctx, struct radeon_surf *surf);
1647 void *gfx9_create_clear_dcc_msaa_cs(struct si_context *sctx, struct si_texture *tex);
1648 void *si_create_passthrough_tcs(struct si_context *sctx);
1649 void *si_clear_image_dcc_single_shader(struct si_context *sctx, bool is_msaa, unsigned wg_dim);
1650 void *si_get_blitter_vs(struct si_context *sctx, enum blitter_attrib_type type,
1651 unsigned num_layers);
1652 void *si_create_ubyte_to_ushort_compute_shader(struct si_context *sctx);
1653 void *si_create_clear_buffer_rmw_cs(struct si_context *sctx);
1654 void *si_create_fmask_expand_cs(struct si_context *sctx, unsigned num_samples, bool is_array);
1655 void *si_create_query_result_cs(struct si_context *sctx);
1656 void *gfx11_create_sh_query_result_cs(struct si_context *sctx);
1657
1658 /* gfx11_query.c */
1659 void si_gfx11_init_query(struct si_context *sctx);
1660 void si_gfx11_destroy_query(struct si_context *sctx);
1661
1662 /* si_test_image_copy_region.c */
1663 void si_test_image_copy_region(struct si_screen *sscreen);
1664 void si_test_blit(struct si_screen *sscreen, unsigned test_flags);
1665
1666 /* si_test_dma_perf.c */
1667 void si_test_dma_perf(struct si_screen *sscreen);
1668 void si_test_mem_perf(struct si_screen *sscreen);
1669 void si_test_clear_buffer(struct si_screen *sscreen);
1670 void si_test_copy_buffer(struct si_screen *sscreen);
1671
1672 /* si_test_blit_perf.c */
1673 void si_test_blit_perf(struct si_screen *sscreen);
1674
1675 /* si_uvd.c */
1676 struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
1677 const struct pipe_video_codec *templ);
1678
1679 struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
1680 const struct pipe_video_buffer *tmpl);
1681 struct pipe_video_buffer *si_video_buffer_create_with_modifiers(struct pipe_context *pipe,
1682 const struct pipe_video_buffer *tmpl,
1683 const uint64_t *modifiers,
1684 unsigned int modifiers_count);
1685
1686 /* si_state_viewport.c */
1687 void si_update_vs_viewport_state(struct si_context *ctx);
1688 void si_init_viewport_functions(struct si_context *ctx);
1689
1690 /* si_texture.c */
1691 void si_eliminate_fast_color_clear(struct si_context *sctx, struct si_texture *tex,
1692 bool *ctx_flushed);
1693 void si_texture_discard_cmask(struct si_screen *sscreen, struct si_texture *tex);
1694 bool si_init_flushed_depth_texture(struct pipe_context *ctx, struct pipe_resource *texture);
1695 void si_print_texture_info(struct si_screen *sscreen, struct si_texture *tex,
1696 struct u_log_context *log);
1697 struct pipe_resource *si_texture_create(struct pipe_screen *screen,
1698 const struct pipe_resource *templ);
1699 bool si_texture_commit(struct si_context *ctx, struct si_resource *res, unsigned level,
1700 struct pipe_box *box, bool commit);
1701 bool vi_dcc_formats_compatible(struct si_screen *sscreen, enum pipe_format format1,
1702 enum pipe_format format2);
1703 bool vi_dcc_formats_are_incompatible(struct pipe_resource *tex, unsigned level,
1704 enum pipe_format view_format);
1705 void vi_disable_dcc_if_incompatible_format(struct si_context *sctx, struct pipe_resource *tex,
1706 unsigned level, enum pipe_format view_format);
1707 bool si_texture_disable_dcc(struct si_context *sctx, struct si_texture *tex);
1708 void si_init_screen_texture_functions(struct si_screen *sscreen);
1709 void si_init_context_texture_functions(struct si_context *sctx);
1710
1711 /* si_sqtt.c */
1712 void si_sqtt_write_event_marker(struct si_context* sctx, struct radeon_cmdbuf *rcs,
1713 enum rgp_sqtt_marker_event_type api_type,
1714 uint32_t vertex_offset_user_data,
1715 uint32_t instance_offset_user_data,
1716 uint32_t draw_index_user_data);
1717 bool si_sqtt_register_pipeline(struct si_context* sctx, struct si_sqtt_fake_pipeline *pipeline,
1718 uint32_t *gfx_sh_offsets);
1719 bool si_sqtt_pipeline_is_registered(struct ac_sqtt *sqtt,
1720 uint64_t pipeline_hash);
1721 void si_sqtt_describe_pipeline_bind(struct si_context* sctx, uint64_t pipeline_hash, int bind_point);
1722 void
1723 si_write_event_with_dims_marker(struct si_context* sctx, struct radeon_cmdbuf *rcs,
1724 enum rgp_sqtt_marker_event_type api_type,
1725 uint32_t x, uint32_t y, uint32_t z);
1726 void
1727 si_write_user_event(struct si_context* sctx, struct radeon_cmdbuf *rcs,
1728 enum rgp_sqtt_marker_user_event_type type,
1729 const char *str, int len);
1730 void
1731 si_sqtt_describe_barrier_start(struct si_context* sctx, struct radeon_cmdbuf *rcs);
1732 void
1733 si_sqtt_describe_barrier_end(struct si_context* sctx, struct radeon_cmdbuf *rcs, unsigned flags);
1734 bool si_init_sqtt(struct si_context *sctx);
1735 void si_destroy_sqtt(struct si_context *sctx);
1736 void si_handle_sqtt(struct si_context *sctx, struct radeon_cmdbuf *rcs);
1737
1738 /*
1739 * common helpers
1740 */
1741
1742 /* Use this helper when casting pipe_resouce::screen to get a real si_screen
1743 * instance (= this is only useful when intending to access si_screen members directly)
1744 */
1745 static inline struct si_screen *
si_screen(struct pipe_screen * pscreen)1746 si_screen(struct pipe_screen *pscreen)
1747 {
1748 struct pipe_screen *s =
1749 pscreen->get_driver_pipe_screen ? pscreen->get_driver_pipe_screen(pscreen) : pscreen;
1750 assert(s->destroy == si_destroy_screen);
1751 return (struct si_screen *)s;
1752 }
1753
si_compute_reference(struct si_compute ** dst,struct si_compute * src)1754 static inline void si_compute_reference(struct si_compute **dst, struct si_compute *src)
1755 {
1756 if (pipe_reference(&(*dst)->sel.base.reference, &src->sel.base.reference))
1757 si_destroy_compute(*dst);
1758
1759 *dst = src;
1760 }
1761
si_resource(struct pipe_resource * r)1762 static inline struct si_resource *si_resource(struct pipe_resource *r)
1763 {
1764 return (struct si_resource *)r;
1765 }
1766
si_resource_reference(struct si_resource ** ptr,struct si_resource * res)1767 static inline void si_resource_reference(struct si_resource **ptr, struct si_resource *res)
1768 {
1769 pipe_resource_reference((struct pipe_resource **)ptr, (struct pipe_resource *)res);
1770 }
1771
si_texture_reference(struct si_texture ** ptr,struct si_texture * res)1772 static inline void si_texture_reference(struct si_texture **ptr, struct si_texture *res)
1773 {
1774 pipe_resource_reference((struct pipe_resource **)ptr, &res->buffer.b.b);
1775 }
1776
1777 static inline void
si_shader_selector_reference(struct si_context * sctx,struct si_shader_selector ** dst,struct si_shader_selector * src)1778 si_shader_selector_reference(struct si_context *sctx, /* sctx can optionally be NULL */
1779 struct si_shader_selector **dst, struct si_shader_selector *src)
1780 {
1781 if (*dst == src)
1782 return;
1783
1784 struct si_screen *sscreen = src ? src->screen : (*dst)->screen;
1785 util_shader_reference(&sctx->b, &sscreen->live_shader_cache, (void **)dst, src);
1786 }
1787
vi_dcc_enabled(struct si_texture * tex,unsigned level)1788 static inline bool vi_dcc_enabled(struct si_texture *tex, unsigned level)
1789 {
1790 /* Gfx12 always returns false because DCC is transparent to the driver.
1791 * I think DCC doesn't have to be disabled if a color buffer is simultaneously bound as a sampler.
1792 */
1793 return !tex->is_depth && tex->surface.meta_offset && level < tex->surface.num_meta_levels;
1794 }
1795
si_get_atom_bit(struct si_context * sctx,struct si_atom * atom)1796 static inline uint64_t si_get_atom_bit(struct si_context *sctx, struct si_atom *atom)
1797 {
1798 return 1ull << (atom - sctx->atoms.array);
1799 }
1800
si_set_atom_dirty(struct si_context * sctx,struct si_atom * atom,bool dirty)1801 static inline void si_set_atom_dirty(struct si_context *sctx, struct si_atom *atom, bool dirty)
1802 {
1803 uint64_t bit = si_get_atom_bit(sctx, atom);
1804
1805 if (dirty)
1806 sctx->dirty_atoms |= bit;
1807 else
1808 sctx->dirty_atoms &= ~bit;
1809 }
1810
si_is_atom_dirty(struct si_context * sctx,struct si_atom * atom)1811 static inline bool si_is_atom_dirty(struct si_context *sctx, struct si_atom *atom)
1812 {
1813 return (sctx->dirty_atoms & si_get_atom_bit(sctx, atom)) != 0;
1814 }
1815
si_mark_atom_dirty(struct si_context * sctx,struct si_atom * atom)1816 static inline void si_mark_atom_dirty(struct si_context *sctx, struct si_atom *atom)
1817 {
1818 si_set_atom_dirty(sctx, atom, true);
1819 }
1820
1821 /* This should be evaluated at compile time if all parameters except sctx are constants. */
1822 static ALWAYS_INLINE struct si_shader_ctx_state *
si_get_vs_inline(struct si_context * sctx,enum si_has_tess has_tess,enum si_has_gs has_gs)1823 si_get_vs_inline(struct si_context *sctx, enum si_has_tess has_tess, enum si_has_gs has_gs)
1824 {
1825 if (has_gs)
1826 return &sctx->shader.gs;
1827 if (has_tess)
1828 return &sctx->shader.tes;
1829
1830 return &sctx->shader.vs;
1831 }
1832
si_get_vs(struct si_context * sctx)1833 static inline struct si_shader_ctx_state *si_get_vs(struct si_context *sctx)
1834 {
1835 return si_get_vs_inline(sctx, sctx->shader.tes.cso ? TESS_ON : TESS_OFF,
1836 sctx->shader.gs.cso ? GS_ON : GS_OFF);
1837 }
1838
si_get_strmout_en(struct si_context * sctx)1839 static inline bool si_get_strmout_en(struct si_context *sctx)
1840 {
1841 return sctx->streamout.streamout_enabled || sctx->streamout.prims_gen_query_enabled;
1842 }
1843
si_optimal_tcc_alignment(struct si_context * sctx,unsigned upload_size)1844 static inline unsigned si_optimal_tcc_alignment(struct si_context *sctx, unsigned upload_size)
1845 {
1846 unsigned alignment, tcc_cache_line_size;
1847
1848 /* If the upload size is less than the cache line size (e.g. 16, 32),
1849 * the whole thing will fit into a cache line if we align it to its size.
1850 * The idea is that multiple small uploads can share a cache line.
1851 * If the upload size is greater, align it to the cache line size.
1852 */
1853 alignment = util_next_power_of_two(upload_size);
1854 tcc_cache_line_size = sctx->screen->info.tcc_cache_line_size;
1855 return MIN2(alignment, tcc_cache_line_size);
1856 }
1857
si_saved_cs_reference(struct si_saved_cs ** dst,struct si_saved_cs * src)1858 static inline void si_saved_cs_reference(struct si_saved_cs **dst, struct si_saved_cs *src)
1859 {
1860 if (pipe_reference(&(*dst)->reference, &src->reference))
1861 si_destroy_saved_cs(*dst);
1862
1863 *dst = src;
1864 }
1865
si_make_CB_shader_coherent(struct si_context * sctx,unsigned num_samples,bool shaders_read_metadata,bool dcc_pipe_aligned)1866 static inline void si_make_CB_shader_coherent(struct si_context *sctx, unsigned num_samples,
1867 bool shaders_read_metadata, bool dcc_pipe_aligned)
1868 {
1869 sctx->barrier_flags |= SI_BARRIER_SYNC_AND_INV_CB | SI_BARRIER_INV_VMEM;
1870 sctx->force_shader_coherency.with_cb = false;
1871
1872 if (sctx->gfx_level >= GFX10 && sctx->gfx_level < GFX12) {
1873 if (sctx->screen->info.tcc_rb_non_coherent)
1874 sctx->barrier_flags |= SI_BARRIER_INV_L2;
1875 else if (shaders_read_metadata)
1876 sctx->barrier_flags |= SI_BARRIER_INV_L2_METADATA;
1877 } else if (sctx->gfx_level == GFX9) {
1878 /* Single-sample color is coherent with shaders on GFX9, but
1879 * L2 metadata must be flushed if shaders read metadata.
1880 * (DCC, CMASK).
1881 */
1882 if (num_samples >= 2 || (shaders_read_metadata && !dcc_pipe_aligned))
1883 sctx->barrier_flags |= SI_BARRIER_INV_L2;
1884 else if (shaders_read_metadata)
1885 sctx->barrier_flags |= SI_BARRIER_INV_L2_METADATA;
1886 } else if (sctx->gfx_level <= GFX8) {
1887 /* GFX6-GFX8 */
1888 sctx->barrier_flags |= SI_BARRIER_INV_L2;
1889 }
1890
1891 si_mark_atom_dirty(sctx, &sctx->atoms.s.barrier);
1892 }
1893
si_make_DB_shader_coherent(struct si_context * sctx,unsigned num_samples,bool include_stencil,bool shaders_read_metadata)1894 static inline void si_make_DB_shader_coherent(struct si_context *sctx, unsigned num_samples,
1895 bool include_stencil, bool shaders_read_metadata)
1896 {
1897 sctx->barrier_flags |= SI_BARRIER_SYNC_AND_INV_DB | SI_BARRIER_INV_VMEM;
1898 sctx->force_shader_coherency.with_db = false;
1899
1900 if (sctx->gfx_level >= GFX10 && sctx->gfx_level < GFX12) {
1901 if (sctx->screen->info.tcc_rb_non_coherent)
1902 sctx->barrier_flags |= SI_BARRIER_INV_L2;
1903 else if (shaders_read_metadata)
1904 sctx->barrier_flags |= SI_BARRIER_INV_L2_METADATA;
1905 } else if (sctx->gfx_level == GFX9) {
1906 /* Single-sample depth (not stencil) is coherent with shaders
1907 * on GFX9, but L2 metadata must be flushed if shaders read
1908 * metadata.
1909 */
1910 if (num_samples >= 2 || include_stencil)
1911 sctx->barrier_flags |= SI_BARRIER_INV_L2;
1912 else if (shaders_read_metadata)
1913 sctx->barrier_flags |= SI_BARRIER_INV_L2_METADATA;
1914 } else if (sctx->gfx_level <= GFX8) {
1915 /* GFX6-GFX8 */
1916 sctx->barrier_flags |= SI_BARRIER_INV_L2;
1917 }
1918
1919 si_mark_atom_dirty(sctx, &sctx->atoms.s.barrier);
1920 }
1921
si_can_sample_zs(struct si_texture * tex,bool stencil_sampler)1922 static inline bool si_can_sample_zs(struct si_texture *tex, bool stencil_sampler)
1923 {
1924 return (stencil_sampler && tex->can_sample_s) || (!stencil_sampler && tex->can_sample_z);
1925 }
1926
si_htile_enabled(struct si_texture * tex,unsigned level,unsigned zs_mask)1927 static inline bool si_htile_enabled(struct si_texture *tex, unsigned level, unsigned zs_mask)
1928 {
1929 struct si_screen *sscreen = si_screen(tex->buffer.b.b.screen);
1930
1931 /* Gfx12 should never call this. */
1932 assert(sscreen->info.gfx_level < GFX12);
1933
1934 if (zs_mask == PIPE_MASK_S && (tex->htile_stencil_disabled || !tex->surface.has_stencil))
1935 return false;
1936
1937 if (!tex->is_depth || !tex->surface.meta_offset)
1938 return false;
1939
1940 if (sscreen->info.gfx_level >= GFX8) {
1941 return level < tex->surface.num_meta_levels;
1942 } else {
1943 /* GFX6-7 don't have TC-compatible HTILE, which means they have to run
1944 * a decompression pass for every mipmap level before texturing, so compress
1945 * only one level to reduce the number of decompression passes to a minimum.
1946 */
1947 return level == 0;
1948 }
1949 }
1950
vi_tc_compat_htile_enabled(struct si_texture * tex,unsigned level,unsigned zs_mask)1951 static inline bool vi_tc_compat_htile_enabled(struct si_texture *tex, unsigned level,
1952 unsigned zs_mask)
1953 {
1954 struct si_screen *sscreen = si_screen(tex->buffer.b.b.screen);
1955
1956 /* Gfx12 should never call this. */
1957 assert(sscreen->info.gfx_level < GFX12);
1958
1959 assert(!tex->tc_compatible_htile || tex->surface.meta_offset);
1960 return tex->tc_compatible_htile && si_htile_enabled(tex, level, zs_mask);
1961 }
1962
si_get_ps_iter_samples(struct si_context * sctx)1963 static inline unsigned si_get_ps_iter_samples(struct si_context *sctx)
1964 {
1965 if (sctx->gfx11_force_msaa_num_samples_zero)
1966 return 1;
1967
1968 if (sctx->ps_uses_fbfetch)
1969 return sctx->framebuffer.nr_color_samples;
1970
1971 return MIN2(sctx->ps_iter_samples, sctx->framebuffer.nr_color_samples);
1972 }
1973
si_any_colorbuffer_written(struct si_context * sctx)1974 static inline bool si_any_colorbuffer_written(struct si_context *sctx)
1975 {
1976 if (sctx->queued.named.rasterizer->rasterizer_discard)
1977 return false;
1978
1979 struct si_shader_selector *ps = sctx->shader.ps.cso;
1980 if (!ps || !ps->info.colors_written_4bit)
1981 return false;
1982
1983 return (sctx->framebuffer.colorbuf_enabled_4bit &
1984 sctx->queued.named.blend->cb_target_enabled_4bit &
1985 (ps->info.color0_writes_all_cbufs ? ~0 : ps->info.colors_written_4bit)) != 0;
1986 }
1987
1988 #define UTIL_ALL_PRIM_LINE_MODES \
1989 ((1 << MESA_PRIM_LINES) | (1 << MESA_PRIM_LINE_LOOP) | (1 << MESA_PRIM_LINE_STRIP) | \
1990 (1 << MESA_PRIM_LINES_ADJACENCY) | (1 << MESA_PRIM_LINE_STRIP_ADJACENCY))
1991
1992 #define UTIL_ALL_PRIM_TRIANGLE_MODES \
1993 ((1 << MESA_PRIM_TRIANGLES) | (1 << MESA_PRIM_TRIANGLE_STRIP) | \
1994 (1 << MESA_PRIM_TRIANGLE_FAN) | (1 << MESA_PRIM_QUADS) | (1 << MESA_PRIM_QUAD_STRIP) | \
1995 (1 << MESA_PRIM_POLYGON) | (1 << MESA_PRIM_TRIANGLES_ADJACENCY) | \
1996 (1 << MESA_PRIM_TRIANGLE_STRIP_ADJACENCY))
1997
util_prim_is_lines(unsigned prim)1998 static inline bool util_prim_is_lines(unsigned prim)
1999 {
2000 return ((1 << prim) & UTIL_ALL_PRIM_LINE_MODES) != 0;
2001 }
2002
util_rast_prim_is_triangles(unsigned prim)2003 static inline bool util_rast_prim_is_triangles(unsigned prim)
2004 {
2005 return ((1 << prim) & UTIL_ALL_PRIM_TRIANGLE_MODES) != 0;
2006 }
2007
si_need_gfx_cs_space(struct si_context * ctx,unsigned num_draws,unsigned extra_dw_per_draw)2008 static inline void si_need_gfx_cs_space(struct si_context *ctx, unsigned num_draws,
2009 unsigned extra_dw_per_draw)
2010 {
2011 struct radeon_cmdbuf *cs = &ctx->gfx_cs;
2012 /* Don't count the needed CS space exactly and just use an upper bound.
2013 *
2014 * Also reserve space for stopping queries at the end of IB, because
2015 * the number of active queries is unlimited in theory.
2016 */
2017 unsigned reserve_dw = 2048 + ctx->num_cs_dw_queries_suspend +
2018 num_draws * (10 + extra_dw_per_draw);
2019
2020 if (!ctx->ws->cs_check_space(cs, reserve_dw))
2021 si_flush_gfx_cs(ctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
2022 }
2023
2024 /**
2025 * Add a buffer to the buffer list for the given command stream (CS).
2026 *
2027 * All buffers used by a CS must be added to the list. This tells the kernel
2028 * driver which buffers are used by GPU commands. Other buffers can
2029 * be swapped out (not accessible) during execution.
2030 *
2031 * The buffer list becomes empty after every context flush and must be
2032 * rebuilt.
2033 */
radeon_add_to_buffer_list(struct si_context * sctx,struct radeon_cmdbuf * cs,struct si_resource * bo,unsigned usage)2034 static inline void radeon_add_to_buffer_list(struct si_context *sctx, struct radeon_cmdbuf *cs,
2035 struct si_resource *bo, unsigned usage)
2036 {
2037 assert(usage);
2038 sctx->ws->cs_add_buffer(cs, bo->buf, usage | RADEON_USAGE_SYNCHRONIZED,
2039 bo->domains);
2040 }
2041
si_select_draw_vbo(struct si_context * sctx)2042 static inline void si_select_draw_vbo(struct si_context *sctx)
2043 {
2044 pipe_draw_func draw_vbo = sctx->draw_vbo[!!sctx->shader.tes.cso]
2045 [!!sctx->shader.gs.cso]
2046 [sctx->ngg];
2047 pipe_draw_vertex_state_func draw_vertex_state =
2048 sctx->draw_vertex_state[!!sctx->shader.tes.cso]
2049 [!!sctx->shader.gs.cso]
2050 [sctx->ngg];
2051 assert(draw_vbo);
2052 assert(draw_vertex_state);
2053
2054 if (unlikely(sctx->real_draw_vbo)) {
2055 assert(sctx->real_draw_vertex_state);
2056 sctx->real_draw_vbo = draw_vbo;
2057 sctx->real_draw_vertex_state = draw_vertex_state;
2058 } else {
2059 assert(!sctx->real_draw_vertex_state);
2060 sctx->b.draw_vbo = draw_vbo;
2061 sctx->b.draw_vertex_state = draw_vertex_state;
2062 }
2063 }
2064
2065 /* Return the number of samples that the rasterizer uses. */
si_get_num_coverage_samples(struct si_context * sctx)2066 static inline unsigned si_get_num_coverage_samples(struct si_context *sctx)
2067 {
2068 if (sctx->framebuffer.nr_samples > 1 &&
2069 sctx->queued.named.rasterizer->multisample_enable)
2070 return sctx->framebuffer.nr_samples;
2071
2072 /* Note that smoothing_enabled is set by si_update_shaders. */
2073 if (sctx->smoothing_enabled)
2074 return SI_NUM_SMOOTH_AA_SAMPLES;
2075
2076 return 1;
2077 }
2078
2079 static unsigned ALWAYS_INLINE
si_num_vbos_in_user_sgprs_inline(enum amd_gfx_level gfx_level)2080 si_num_vbos_in_user_sgprs_inline(enum amd_gfx_level gfx_level)
2081 {
2082 /* This decreases CPU overhead if all descriptors are in user SGPRs because we don't
2083 * have to allocate and count references for the upload buffer.
2084 */
2085 return gfx_level >= GFX9 ? 5 : 1;
2086 }
2087
2088 static inline
si_check_dirty_buffers_textures(struct si_context * sctx)2089 void si_check_dirty_buffers_textures(struct si_context *sctx)
2090 {
2091 /* Recompute and re-emit the texture resource states if needed. */
2092 unsigned dirty_tex_counter = p_atomic_read(&sctx->screen->dirty_tex_counter);
2093 if (unlikely(dirty_tex_counter != sctx->last_dirty_tex_counter)) {
2094 sctx->last_dirty_tex_counter = dirty_tex_counter;
2095 sctx->framebuffer.dirty_cbufs |= ((1 << sctx->framebuffer.state.nr_cbufs) - 1);
2096 sctx->framebuffer.dirty_zsbuf = true;
2097 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
2098 si_update_all_texture_descriptors(sctx);
2099 }
2100
2101 unsigned dirty_buf_counter = p_atomic_read(&sctx->screen->dirty_buf_counter);
2102 if (unlikely(dirty_buf_counter != sctx->last_dirty_buf_counter)) {
2103 sctx->last_dirty_buf_counter = dirty_buf_counter;
2104 /* Rebind all buffers unconditionally. */
2105 si_rebind_buffer(sctx, NULL);
2106 }
2107 }
2108
si_set_clip_discard_distance(struct si_context * sctx,float distance)2109 static inline void si_set_clip_discard_distance(struct si_context *sctx, float distance)
2110 {
2111 /* Determine whether the guardband registers change.
2112 *
2113 * When we see a value greater than min_clip_discard_distance_watermark, we increase it
2114 * up to a certain number to eliminate those state changes next time they happen.
2115 * See the comment at min_clip_discard_distance_watermark.
2116 */
2117 if (distance > sctx->min_clip_discard_distance_watermark) {
2118 /* The maximum number was determined from Viewperf. The number is in units of half-pixels. */
2119 sctx->min_clip_discard_distance_watermark = MIN2(distance, 6);
2120
2121 float old_distance = sctx->current_clip_discard_distance;
2122 float new_distance = MAX2(distance, sctx->min_clip_discard_distance_watermark);
2123
2124 if (old_distance != new_distance) {
2125 sctx->current_clip_discard_distance = new_distance;
2126 si_mark_atom_dirty(sctx, &sctx->atoms.s.guardband);
2127 }
2128 }
2129 }
2130
2131 /* Update these two GS_STATE fields. They depend on whatever the last shader before PS is
2132 * and the rasterizer state.
2133 *
2134 * It's expected that hw_vs and ngg are inline constants in draw_vbo after optimizations.
2135 */
2136 static inline void
si_update_ngg_sgpr_state_provoking_vtx(struct si_context * sctx,struct si_shader * hw_vs,bool ngg)2137 si_update_ngg_sgpr_state_provoking_vtx(struct si_context *sctx, struct si_shader *hw_vs, bool ngg)
2138 {
2139 if (ngg && hw_vs && hw_vs->uses_vs_state_provoking_vertex) {
2140 SET_FIELD(sctx->current_gs_state, GS_STATE_PROVOKING_VTX_FIRST,
2141 sctx->queued.named.rasterizer->flatshade_first);
2142 }
2143 }
2144
2145 static inline void
si_update_ngg_sgpr_state_out_prim(struct si_context * sctx,struct si_shader * hw_vs,bool ngg)2146 si_update_ngg_sgpr_state_out_prim(struct si_context *sctx, struct si_shader *hw_vs, bool ngg)
2147 {
2148 if (ngg && hw_vs && hw_vs->uses_gs_state_outprim)
2149 SET_FIELD(sctx->current_gs_state, GS_STATE_OUTPRIM, sctx->gs_out_prim);
2150 }
2151
2152 static inline void
si_update_ngg_cull_face_state(struct si_context * sctx)2153 si_update_ngg_cull_face_state(struct si_context *sctx)
2154 {
2155 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
2156
2157 if (sctx->viewport0_y_inverted) {
2158 SET_FIELD(sctx->current_gs_state, GS_STATE_CULL_FACE_FRONT, rs->ngg_cull_back);
2159 SET_FIELD(sctx->current_gs_state, GS_STATE_CULL_FACE_BACK, rs->ngg_cull_front);
2160 } else {
2161 SET_FIELD(sctx->current_gs_state, GS_STATE_CULL_FACE_FRONT, rs->ngg_cull_front);
2162 SET_FIELD(sctx->current_gs_state, GS_STATE_CULL_FACE_BACK, rs->ngg_cull_back);
2163 }
2164 }
2165
2166 /* Set the primitive type seen by the rasterizer. GS and tessellation affect this.
2167 * It's expected that hw_vs and ngg are inline constants in draw_vbo after optimizations.
2168 */
2169 static ALWAYS_INLINE void
si_set_rasterized_prim(struct si_context * sctx,enum mesa_prim rast_prim,struct si_shader * hw_vs,bool ngg)2170 si_set_rasterized_prim(struct si_context *sctx, enum mesa_prim rast_prim,
2171 struct si_shader *hw_vs, bool ngg)
2172 {
2173 if (rast_prim != sctx->current_rast_prim) {
2174 bool is_rect = rast_prim == SI_PRIM_RECTANGLE_LIST;
2175 bool is_points = rast_prim == MESA_PRIM_POINTS;
2176 bool is_lines = util_prim_is_lines(rast_prim);
2177
2178 if (is_points) {
2179 si_set_clip_discard_distance(sctx, sctx->queued.named.rasterizer->max_point_size);
2180 sctx->gs_out_prim = V_028A6C_POINTLIST;
2181 } else if (is_lines) {
2182 si_set_clip_discard_distance(sctx, sctx->queued.named.rasterizer->line_width);
2183 sctx->gs_out_prim = V_028A6C_LINESTRIP;
2184 } else if (is_rect) {
2185 /* Don't change the clip discard distance for rectangles. */
2186 sctx->gs_out_prim = V_028A6C_RECTLIST;
2187 } else {
2188 si_set_clip_discard_distance(sctx, 0);
2189 sctx->gs_out_prim = V_028A6C_TRISTRIP;
2190 }
2191
2192 sctx->current_rast_prim = rast_prim;
2193 si_vs_ps_key_update_rast_prim_smooth_stipple(sctx);
2194 si_update_ngg_sgpr_state_out_prim(sctx, hw_vs, ngg);
2195 }
2196 }
2197
2198 /* There are 3 ways to flush caches and all of them are correct.
2199 *
2200 * 1) sctx->flags |= ...;
2201 * si_mark_atom_dirty(sctx, &sctx->atoms.s.barrier); // deferred
2202 *
2203 * 2) sctx->flags |= ...;
2204 * si_emit_barrier_direct(sctx); // immediate
2205 *
2206 * 3) sctx->flags |= ...;
2207 * sctx->emit_barrier(sctx, cs); // immediate (2 is better though)
2208 */
si_emit_barrier_direct(struct si_context * sctx)2209 static inline void si_emit_barrier_direct(struct si_context *sctx)
2210 {
2211 if (sctx->barrier_flags) {
2212 sctx->emit_barrier(sctx, &sctx->gfx_cs);
2213 sctx->dirty_atoms &= ~SI_ATOM_BIT(barrier);
2214 }
2215 }
2216
2217 #define PRINT_ERR(fmt, args...) \
2218 fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
2219
2220 #ifdef __cplusplus
2221 }
2222 #endif
2223
2224 #endif
2225