1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * SPDX-License-Identifier: MIT
5 */
6
7 #ifndef SI_STATE_H
8 #define SI_STATE_H
9
10 #include "si_pm4.h"
11 #include "util/format/u_format.h"
12 #include "util/bitset.h"
13
14 #ifdef __cplusplus
15 extern "C" {
16 #endif
17
18 #define SI_NUM_GRAPHICS_SHADERS (PIPE_SHADER_FRAGMENT + 1)
19 #define SI_NUM_SHADERS (PIPE_SHADER_COMPUTE + 1)
20
21 #define SI_NUM_VERTEX_BUFFERS SI_MAX_ATTRIBS
22 #define SI_NUM_SAMPLERS 32 /* OpenGL textures units per shader */
23 #define SI_NUM_CONST_BUFFERS 16
24 #define SI_NUM_IMAGES 16
25 #define SI_NUM_IMAGE_SLOTS (SI_NUM_IMAGES * 2) /* the second half are FMASK slots */
26 #define SI_NUM_SHADER_BUFFERS 32
27
28 struct si_screen;
29 struct si_shader;
30 struct si_shader_ctx_state;
31 struct si_shader_selector;
32 struct si_texture;
33 struct si_qbo_state;
34 struct legacy_surf_level;
35 struct pb_slab_entry;
36
37 struct si_state_blend {
38 struct si_pm4_state pm4;
39 uint32_t cb_target_mask;
40 /* Set 0xf or 0x0 (4 bits) per render target if the following is
41 * true. ANDed with spi_shader_col_format.
42 */
43 unsigned cb_target_enabled_4bit;
44 unsigned blend_enable_4bit;
45 unsigned need_src_alpha_4bit;
46 unsigned commutative_4bit;
47 unsigned dcc_msaa_corruption_4bit;
48 bool alpha_to_coverage : 1;
49 bool alpha_to_one : 1;
50 bool dual_src_blend : 1;
51 bool logicop_enable : 1;
52 bool allows_noop_optimization : 1;
53 };
54
55 struct si_state_rasterizer {
56 struct si_pm4_state pm4;
57
58 /* Register values. */
59 unsigned spi_interp_control_0;
60 unsigned pa_su_point_size;
61 unsigned pa_su_point_minmax;
62 unsigned pa_su_line_cntl;
63 unsigned pa_sc_mode_cntl_0;
64 unsigned pa_su_sc_mode_cntl;
65 unsigned pa_cl_ngg_cntl;
66 unsigned pa_sc_edgerule;
67 unsigned pa_su_poly_offset_db_fmt_cntl[3];
68 unsigned pa_su_poly_offset_clamp;
69 unsigned pa_su_poly_offset_frontback_scale;
70 unsigned pa_su_poly_offset_frontback_offset[3];
71
72 unsigned pa_sc_line_stipple;
73 unsigned pa_cl_clip_cntl;
74 float line_width;
75 float max_point_size;
76 unsigned ngg_cull_flags_tris : 16;
77 unsigned ngg_cull_flags_lines : 16;
78 unsigned sprite_coord_enable : 8;
79 unsigned clip_plane_enable : 8;
80 bool ngg_cull_front : 1;
81 bool ngg_cull_back : 1;
82 unsigned half_pixel_center : 1;
83 unsigned flatshade : 1;
84 unsigned flatshade_first : 1;
85 unsigned two_side : 1;
86 unsigned multisample_enable : 1;
87 unsigned line_stipple_enable : 1;
88 unsigned poly_stipple_enable : 1;
89 unsigned line_smooth : 1;
90 unsigned poly_smooth : 1;
91 unsigned point_smooth : 1;
92 unsigned uses_poly_offset : 1;
93 unsigned clamp_fragment_color : 1;
94 unsigned clamp_vertex_color : 1;
95 unsigned rasterizer_discard : 1;
96 unsigned scissor_enable : 1;
97 unsigned clip_halfz : 1;
98 unsigned polygon_mode_is_lines : 1;
99 unsigned polygon_mode_is_points : 1;
100 unsigned perpendicular_end_caps : 1;
101 unsigned bottom_edge_rule : 1;
102 int force_front_face_input : 2;
103 };
104
105 struct si_dsa_stencil_ref_part {
106 uint8_t valuemask[2];
107 uint8_t writemask[2];
108 };
109
110 struct si_dsa_order_invariance {
111 /** Whether the final result in Z/S buffers is guaranteed to be
112 * invariant under changes to the order in which fragments arrive. */
113 bool zs : 1;
114
115 /** Whether the set of fragments that pass the combined Z/S test is
116 * guaranteed to be invariant under changes to the order in which
117 * fragments arrive. */
118 bool pass_set : 1;
119 };
120
121 struct si_state_dsa {
122 struct si_pm4_state pm4;
123 struct si_dsa_stencil_ref_part stencil_ref;
124
125 /* Register values. */
126 unsigned db_depth_control;
127 unsigned db_stencil_control;
128 unsigned db_depth_bounds_min;
129 unsigned db_depth_bounds_max;
130 unsigned spi_shader_user_data_ps_alpha_ref;
131 unsigned db_stencil_read_mask;
132 unsigned db_stencil_write_mask;
133 unsigned db_render_override; /* only gfx12 */
134
135 /* 0 = without stencil buffer, 1 = when both Z and S buffers are present */
136 struct si_dsa_order_invariance order_invariance[2];
137
138 uint8_t alpha_func : 3;
139 bool depth_enabled : 1;
140 bool depth_write_enabled : 1;
141 bool stencil_enabled : 1;
142 bool stencil_write_enabled : 1;
143 bool db_can_write : 1;
144 bool depth_bounds_enabled : 1;
145 };
146
147 struct si_stencil_ref {
148 struct pipe_stencil_ref state;
149 struct si_dsa_stencil_ref_part dsa_part;
150 };
151
152 struct si_vertex_elements {
153 struct si_resource *instance_divisor_factor_buffer;
154
155 /* Bitmask of elements that always need a fixup to be applied. */
156 uint16_t fix_fetch_always;
157
158 /* Bitmask of elements whose fetch should always be opencoded. */
159 uint16_t fix_fetch_opencode;
160
161 /* Bitmask of elements which need to be opencoded if the vertex buffer
162 * is unaligned. */
163 uint16_t fix_fetch_unaligned;
164
165 /* For elements in fix_fetch_unaligned: whether the effective
166 * element load size as seen by the hardware is a dword (as opposed
167 * to a short).
168 */
169 uint16_t hw_load_is_dword;
170
171 /* Bitmask of vertex buffers requiring alignment check */
172 uint16_t vb_alignment_check_mask;
173
174 uint8_t count;
175
176 /* Vertex buffer descriptor list size aligned for optimal prefetch. */
177 uint16_t vb_desc_list_alloc_size;
178 uint16_t instance_divisor_is_one; /* bitmask of inputs */
179 uint16_t instance_divisor_is_fetched; /* bitmask of inputs */
180
181 uint8_t fix_fetch[SI_MAX_ATTRIBS];
182 uint8_t vertex_buffer_index[SI_MAX_ATTRIBS];
183
184 struct {
185 uint32_t rsrc_word3;
186 uint16_t src_offset;
187 uint16_t stride;
188 uint8_t format_size;
189 } elem[SI_MAX_ATTRIBS];
190 };
191
192 union si_state {
193 struct si_state_named {
194 struct si_state_blend *blend;
195 struct si_state_rasterizer *rasterizer;
196 struct si_state_dsa *dsa;
197 struct si_shader *ls;
198 struct si_shader *hs;
199 struct si_shader *es;
200 struct si_shader *gs;
201 struct si_shader *vs;
202 struct si_shader *ps;
203 struct si_sqtt_fake_pipeline *sqtt_pipeline;
204 } named;
205 struct si_pm4_state *array[sizeof(struct si_state_named) / sizeof(struct si_pm4_state *)];
206 };
207
208 #define SI_STATE_IDX(name) (offsetof(union si_state, named.name) / sizeof(struct si_pm4_state *))
209 #define SI_STATE_BIT(name) (1ull << SI_STATE_IDX(name))
210 #define SI_NUM_STATES (sizeof(union si_state) / sizeof(struct si_pm4_state *))
211
212 union si_state_atoms {
213 struct si_atoms_s {
214 /* This must be first. */
215 struct si_atom pm4_states[SI_NUM_STATES];
216 struct si_atom gfx_add_all_to_bo_list;
217 struct si_atom streamout_enable;
218 struct si_atom framebuffer;
219 struct si_atom sample_locations;
220 struct si_atom db_render_state;
221 struct si_atom dpbb_state;
222 struct si_atom msaa_config;
223 struct si_atom sample_mask;
224 struct si_atom cb_render_state;
225 struct si_atom blend_color;
226 struct si_atom clip_regs;
227 struct si_atom clip_state;
228 struct si_atom gfx_shader_pointers;
229 struct si_atom guardband;
230 struct si_atom scissors;
231 struct si_atom viewports;
232 struct si_atom stencil_ref;
233 struct si_atom spi_map;
234 struct si_atom scratch_state;
235 struct si_atom window_rectangles;
236 struct si_atom shader_query;
237 struct si_atom ngg_cull_state;
238 struct si_atom vgt_pipeline_state;
239 struct si_atom tess_io_layout;
240 struct si_atom barrier;
241 struct si_atom streamout_begin; /* this must be done after barrier */
242 struct si_atom render_cond; /* this must be after barrier */
243 struct si_atom spi_ge_ring_state; /* this must be last because it waits for idle. */
244 } s;
245 struct si_atom array[sizeof(struct si_atoms_s) / sizeof(struct si_atom)];
246 };
247
248 #define SI_ATOM_BIT(name) (1ull << (offsetof(union si_state_atoms, s.name) / sizeof(struct si_atom)))
249 #define SI_NUM_ATOMS (sizeof(union si_state_atoms) / sizeof(struct si_atom))
250
si_atoms_that_always_roll_context(void)251 static inline uint64_t si_atoms_that_always_roll_context(void)
252 {
253 return SI_STATE_BIT(blend) |
254 SI_ATOM_BIT(streamout_begin) | SI_ATOM_BIT(streamout_enable) | SI_ATOM_BIT(framebuffer) |
255 SI_ATOM_BIT(sample_locations) | SI_ATOM_BIT(sample_mask) | SI_ATOM_BIT(blend_color)|
256 SI_ATOM_BIT(clip_state) | SI_ATOM_BIT(scissors) | SI_ATOM_BIT(viewports)|
257 SI_ATOM_BIT(stencil_ref) | SI_ATOM_BIT(scratch_state) | SI_ATOM_BIT(window_rectangles);
258 }
259
260 struct si_shader_data {
261 uint32_t sh_base[SI_NUM_SHADERS];
262 };
263
264 /* Registers whose values are tracked by si_context. */
265 enum si_tracked_reg
266 {
267 /* CONTEXT registers. */
268 /* 2 consecutive registers (GFX6-11), or separate registers (GFX12) */
269 SI_TRACKED_DB_RENDER_CONTROL,
270 SI_TRACKED_DB_COUNT_CONTROL,
271
272 SI_TRACKED_DB_DEPTH_CONTROL,
273 SI_TRACKED_DB_STENCIL_CONTROL,
274 /* 2 consecutive registers */
275 SI_TRACKED_DB_DEPTH_BOUNDS_MIN,
276 SI_TRACKED_DB_DEPTH_BOUNDS_MAX,
277
278 SI_TRACKED_SPI_INTERP_CONTROL_0,
279 SI_TRACKED_PA_SU_POINT_SIZE,
280 SI_TRACKED_PA_SU_POINT_MINMAX,
281 SI_TRACKED_PA_SU_LINE_CNTL,
282 SI_TRACKED_PA_SC_MODE_CNTL_0,
283 SI_TRACKED_PA_SU_SC_MODE_CNTL,
284 SI_TRACKED_PA_SC_EDGERULE,
285
286 /* 6 consecutive registers */
287 SI_TRACKED_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
288 SI_TRACKED_PA_SU_POLY_OFFSET_CLAMP,
289 SI_TRACKED_PA_SU_POLY_OFFSET_FRONT_SCALE,
290 SI_TRACKED_PA_SU_POLY_OFFSET_FRONT_OFFSET,
291 SI_TRACKED_PA_SU_POLY_OFFSET_BACK_SCALE,
292 SI_TRACKED_PA_SU_POLY_OFFSET_BACK_OFFSET,
293
294 /* 2 consecutive registers */
295 SI_TRACKED_PA_SC_LINE_CNTL,
296 SI_TRACKED_PA_SC_AA_CONFIG,
297
298 /* 5 consecutive registers (GFX6-11) */
299 SI_TRACKED_PA_SU_VTX_CNTL,
300 /* 4 consecutive registers (GFX12) */
301 SI_TRACKED_PA_CL_GB_VERT_CLIP_ADJ,
302 SI_TRACKED_PA_CL_GB_VERT_DISC_ADJ,
303 SI_TRACKED_PA_CL_GB_HORZ_CLIP_ADJ,
304 SI_TRACKED_PA_CL_GB_HORZ_DISC_ADJ,
305
306 /* Non-consecutive register */
307 SI_TRACKED_SPI_SHADER_POS_FORMAT,
308
309 /* 5 consecutive registers (GFX12), or 2 consecutive registers (GFX6-11) */
310 SI_TRACKED_SPI_SHADER_Z_FORMAT,
311 SI_TRACKED_SPI_SHADER_COL_FORMAT,
312
313 /* 2 consecutive registers. */
314 SI_TRACKED_SPI_PS_INPUT_ENA,
315 SI_TRACKED_SPI_PS_INPUT_ADDR,
316
317 SI_TRACKED_DB_EQAA,
318 SI_TRACKED_DB_RENDER_OVERRIDE2,
319 SI_TRACKED_DB_SHADER_CONTROL,
320 SI_TRACKED_CB_SHADER_MASK,
321 SI_TRACKED_CB_TARGET_MASK,
322 SI_TRACKED_PA_CL_CLIP_CNTL,
323 SI_TRACKED_PA_CL_VS_OUT_CNTL,
324 SI_TRACKED_PA_CL_VTE_CNTL,
325 SI_TRACKED_PA_SC_CLIPRECT_RULE,
326 SI_TRACKED_PA_SC_LINE_STIPPLE,
327 SI_TRACKED_PA_SC_MODE_CNTL_1,
328 SI_TRACKED_PA_SU_HARDWARE_SCREEN_OFFSET,
329 SI_TRACKED_SPI_PS_IN_CONTROL,
330 SI_TRACKED_VGT_GS_INSTANCE_CNT,
331 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
332 SI_TRACKED_VGT_SHADER_STAGES_EN,
333 SI_TRACKED_VGT_LS_HS_CONFIG,
334 SI_TRACKED_VGT_TF_PARAM,
335 SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL, /* GFX8-9 (only with has_small_prim_filter_sample_loc_bug) */
336 SI_TRACKED_PA_SC_BINNER_CNTL_0, /* GFX9+ */
337 SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP, /* GFX10+ - the SMALL_PRIM_FILTER slot above can be reused */
338 SI_TRACKED_GE_NGG_SUBGRP_CNTL, /* GFX10+ */
339 SI_TRACKED_PA_CL_NGG_CNTL, /* GFX10+ */
340 SI_TRACKED_DB_PA_SC_VRS_OVERRIDE_CNTL, /* GFX10.3+ */
341
342 /* 3 consecutive registers */
343 SI_TRACKED_SX_PS_DOWNCONVERT, /* GFX8+ */
344 SI_TRACKED_SX_BLEND_OPT_EPSILON, /* GFX8+ */
345 SI_TRACKED_SX_BLEND_OPT_CONTROL, /* GFX8+ */
346
347 /* The slots below can be reused by other generations. */
348 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE, /* GFX6-8 (GFX9+ can reuse this slot) */
349 SI_TRACKED_VGT_REUSE_OFF, /* GFX6-8,10.3 */
350 SI_TRACKED_IA_MULTI_VGT_PARAM, /* GFX6-8 (GFX9+ can reuse this slot) */
351
352 SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP, /* GFX9 - the slots above can be reused */
353 SI_TRACKED_VGT_GS_ONCHIP_CNTL, /* GFX9-10 - the slots above can be reused */
354
355 SI_TRACKED_VGT_GSVS_RING_ITEMSIZE, /* GFX6-10 (GFX11+ can reuse this slot) */
356 SI_TRACKED_VGT_GS_MODE, /* GFX6-10 (GFX11+ can reuse this slot) */
357 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL, /* GFX6-10 (GFX11+ can reuse this slot) */
358 SI_TRACKED_VGT_GS_OUT_PRIM_TYPE, /* GFX6-10 (GFX11+ can reuse this slot) */
359
360 /* 3 consecutive registers */
361 SI_TRACKED_VGT_GSVS_RING_OFFSET_1, /* GFX6-10 (GFX11+ can reuse this slot) */
362 SI_TRACKED_VGT_GSVS_RING_OFFSET_2, /* GFX6-10 (GFX11+ can reuse this slot) */
363 SI_TRACKED_VGT_GSVS_RING_OFFSET_3, /* GFX6-10 (GFX11+ can reuse this slot) */
364
365 /* 4 consecutive registers */
366 SI_TRACKED_VGT_GS_VERT_ITEMSIZE, /* GFX6-10 (GFX11+ can reuse this slot) */
367 SI_TRACKED_VGT_GS_VERT_ITEMSIZE_1, /* GFX6-10 (GFX11+ can reuse this slot) */
368 SI_TRACKED_VGT_GS_VERT_ITEMSIZE_2, /* GFX6-10 (GFX11+ can reuse this slot) */
369 SI_TRACKED_VGT_GS_VERT_ITEMSIZE_3, /* GFX6-10 (GFX11+ can reuse this slot) */
370
371 SI_TRACKED_SPI_VS_OUT_CONFIG, /* GFX6-11 */
372 SI_TRACKED_DB_RENDER_OVERRIDE = SI_TRACKED_SPI_VS_OUT_CONFIG, /* GFX12+ (slot reused) */
373 SI_TRACKED_VGT_PRIMITIVEID_EN, /* GFX6-11 */
374 SI_TRACKED_CB_DCC_CONTROL, /* GFX8-11 */
375 SI_TRACKED_DB_STENCIL_READ_MASK, /* GFX12+ */
376 SI_TRACKED_DB_STENCIL_WRITE_MASK, /* GFX12+ */
377 SI_TRACKED_PA_SC_HISZ_CONTROL, /* GFX12+ */
378 SI_TRACKED_PA_SC_LINE_STIPPLE_RESET, /* GFX12+ */
379
380 SI_NUM_TRACKED_CONTEXT_REGS,
381 SI_FIRST_TRACKED_OTHER_REG = SI_NUM_TRACKED_CONTEXT_REGS,
382
383 /* SH and UCONFIG registers. */
384 SI_TRACKED_GE_PC_ALLOC = SI_FIRST_TRACKED_OTHER_REG, /* GFX10-11 */
385 SI_TRACKED_SPI_SHADER_PGM_RSRC3_GS, /* GFX7-11 */
386 SI_TRACKED_SPI_SHADER_PGM_RSRC4_GS, /* GFX10+ */
387 SI_TRACKED_VGT_GS_OUT_PRIM_TYPE_UCONFIG, /* GFX11+ */
388 SI_TRACKED_SPI_SHADER_GS_OUT_CONFIG_PS, /* GFX12+ */
389 SI_TRACKED_VGT_PRIMITIVEID_EN_UCONFIG, /* GFX12+ */
390
391 SI_TRACKED_IA_MULTI_VGT_PARAM_UCONFIG, /* GFX9 only */
392 SI_TRACKED_GE_CNTL = SI_TRACKED_IA_MULTI_VGT_PARAM_UCONFIG, /* GFX10+ */
393
394 SI_TRACKED_SPI_SHADER_PGM_RSRC2_HS, /* GFX9+ (not tracked on previous chips) */
395 SI_TRACKED_SPI_SHADER_USER_DATA_PS__ALPHA_REF,
396
397 /* 3 consecutive registers. */
398 SI_TRACKED_SPI_SHADER_USER_DATA_HS__TCS_OFFCHIP_LAYOUT,
399 SI_TRACKED_SPI_SHADER_USER_DATA_HS__TCS_OFFCHIP_ADDR,
400 SI_TRACKED_SPI_SHADER_USER_DATA_HS__VS_STATE_BITS, /* GFX6-8 */
401
402 SI_TRACKED_SPI_SHADER_USER_DATA_LS__BASE_VERTEX,
403 SI_TRACKED_SPI_SHADER_USER_DATA_LS__DRAWID,
404 SI_TRACKED_SPI_SHADER_USER_DATA_LS__START_INSTANCE,
405
406 SI_TRACKED_SPI_SHADER_USER_DATA_ES__BASE_VERTEX,
407 SI_TRACKED_SPI_SHADER_USER_DATA_ES__DRAWID,
408 SI_TRACKED_SPI_SHADER_USER_DATA_ES__START_INSTANCE,
409
410 SI_TRACKED_SPI_SHADER_USER_DATA_VS__BASE_VERTEX, /* GFX6-10 */
411 SI_TRACKED_SPI_SHADER_USER_DATA_VS__DRAWID, /* GFX6-10 */
412 SI_TRACKED_SPI_SHADER_USER_DATA_VS__START_INSTANCE, /* GFX6-10 */
413
414 SI_TRACKED_COMPUTE_RESOURCE_LIMITS,
415 SI_TRACKED_COMPUTE_DISPATCH_INTERLEAVE, /* GFX12+ (not tracked on previous chips) */
416 SI_TRACKED_COMPUTE_NUM_THREAD_X,
417 SI_TRACKED_COMPUTE_NUM_THREAD_Y,
418 SI_TRACKED_COMPUTE_NUM_THREAD_Z,
419 SI_TRACKED_COMPUTE_TMPRING_SIZE,
420 SI_TRACKED_COMPUTE_PGM_RSRC3, /* GFX11+ */
421
422 /* 2 consecutive registers. */
423 SI_TRACKED_COMPUTE_PGM_RSRC1,
424 SI_TRACKED_COMPUTE_PGM_RSRC2,
425
426 /* 2 consecutive registers. */
427 SI_TRACKED_COMPUTE_DISPATCH_SCRATCH_BASE_LO, /* GFX11+ */
428 SI_TRACKED_COMPUTE_DISPATCH_SCRATCH_BASE_HI, /* GFX11+ */
429
430 SI_NUM_ALL_TRACKED_REGS,
431 };
432
433 /* For 3 draw constants: BaseVertex, DrawID, StartInstance */
434 #define BASEVERTEX_MASK 0x1
435 #define DRAWID_MASK 0x2
436 #define STARTINSTANCE_MASK 0x4
437 #define BASEVERTEX_DRAWID_MASK (BASEVERTEX_MASK | DRAWID_MASK)
438 #define BASEVERTEX_DRAWID_STARTINSTANCE_MASK (BASEVERTEX_MASK | DRAWID_MASK | STARTINSTANCE_MASK)
439
440 struct si_tracked_regs {
441 BITSET_DECLARE(reg_saved_mask, SI_NUM_ALL_TRACKED_REGS);
442 uint32_t reg_value[SI_NUM_ALL_TRACKED_REGS];
443 uint32_t spi_ps_input_cntl[32];
444 };
445
446 /* Private read-write buffer slots. */
447 enum
448 {
449 SI_VS_STREAMOUT_BUF0,
450 SI_VS_STREAMOUT_BUF1,
451 SI_VS_STREAMOUT_BUF2,
452 SI_VS_STREAMOUT_BUF3,
453
454 /* Image descriptor of color buffer 0 for KHR_blend_equation_advanced. */
455 SI_PS_IMAGE_COLORBUF0,
456 SI_PS_IMAGE_COLORBUF0_HI,
457 SI_PS_IMAGE_COLORBUF0_FMASK, /* gfx6-10 */
458 SI_PS_IMAGE_COLORBUF0_FMASK_HI, /* gfx6-10 */
459
460 /* Internal constant buffers. */
461 SI_HS_CONST_DEFAULT_TESS_LEVELS,
462 SI_VS_CONST_INSTANCE_DIVISORS,
463 SI_VS_CONST_CLIP_PLANES,
464 SI_PS_CONST_POLY_STIPPLE,
465
466 SI_RING_ESGS, /* gfx6-8 */
467 SI_RING_GSVS, /* gfx6-10 */
468 SI_GS_QUERY_EMULATED_COUNTERS_BUF, /* gfx10+ */
469 SI_RING_SHADER_LOG,
470
471 SI_NUM_INTERNAL_BINDINGS,
472
473 /* Aliases to reuse slots that are unused on other generations. */
474 SI_GS_QUERY_BUF = SI_RING_ESGS, /* gfx10+ */
475 SI_STREAMOUT_STATE_BUF = SI_RING_GSVS, /* gfx12+ */
476 };
477
478 /* Indices into sctx->descriptors, laid out so that gfx and compute pipelines
479 * are contiguous:
480 *
481 * 0 - rw buffers
482 * 1 - vertex const and shader buffers
483 * 2 - vertex samplers and images
484 * 3 - fragment const and shader buffer
485 * ...
486 * 11 - compute const and shader buffers
487 * 12 - compute samplers and images
488 */
489 enum
490 {
491 SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS,
492 SI_SHADER_DESCS_SAMPLERS_AND_IMAGES,
493 SI_NUM_SHADER_DESCS,
494 };
495
496 #define SI_DESCS_INTERNAL 0
497 #define SI_DESCS_FIRST_SHADER 1
498 #define SI_DESCS_FIRST_COMPUTE (SI_DESCS_FIRST_SHADER + PIPE_SHADER_COMPUTE * SI_NUM_SHADER_DESCS)
499 #define SI_NUM_DESCS (SI_DESCS_FIRST_SHADER + SI_NUM_SHADERS * SI_NUM_SHADER_DESCS)
500
501 #define SI_DESCS_SHADER_MASK(name) \
502 u_bit_consecutive(SI_DESCS_FIRST_SHADER + PIPE_SHADER_##name * SI_NUM_SHADER_DESCS, \
503 SI_NUM_SHADER_DESCS)
504
si_const_and_shader_buffer_descriptors_idx(unsigned shader)505 static inline unsigned si_const_and_shader_buffer_descriptors_idx(unsigned shader)
506 {
507 return SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS +
508 SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS;
509 }
510
si_sampler_and_image_descriptors_idx(unsigned shader)511 static inline unsigned si_sampler_and_image_descriptors_idx(unsigned shader)
512 {
513 return SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS +
514 SI_SHADER_DESCS_SAMPLERS_AND_IMAGES;
515 }
516
517 /* This represents descriptors in memory, such as buffer resources,
518 * image resources, and sampler states.
519 */
520 struct si_descriptors {
521 /* The list of descriptors in malloc'd memory. */
522 uint32_t *list;
523 /* The list in mapped GPU memory. */
524 uint32_t *gpu_list;
525
526 /* The buffer where the descriptors have been uploaded. */
527 struct si_resource *buffer;
528 uint64_t gpu_address;
529
530 /* The maximum number of descriptors. */
531 uint32_t num_elements;
532
533 /* Slots that are used by currently-bound shaders.
534 * It determines which slots are uploaded.
535 */
536 uint32_t first_active_slot;
537 uint32_t num_active_slots;
538
539 /* The SH register offset relative to USER_DATA*_0 where the pointer
540 * to the descriptor array will be stored. */
541 short shader_userdata_offset;
542 /* The size of one descriptor. */
543 uint8_t element_dw_size;
544 /* If there is only one slot enabled, bind it directly instead of
545 * uploading descriptors. -1 if disabled. */
546 signed char slot_index_to_bind_directly;
547 };
548
549 struct si_buffer_resources {
550 struct pipe_resource **buffers; /* this has num_buffers elements */
551 unsigned *offsets; /* this has num_buffers elements */
552
553 unsigned priority;
554 unsigned priority_constbuf;
555
556 /* The i-th bit is set if that element is enabled (non-NULL resource). */
557 uint64_t enabled_mask;
558 uint64_t writable_mask;
559 };
560
561 #define si_pm4_state_changed(sctx, member) \
562 ((sctx)->queued.named.member != (sctx)->emitted.named.member)
563
564 #define si_pm4_state_enabled_and_changed(sctx, member) \
565 ((sctx)->queued.named.member && si_pm4_state_changed(sctx, member))
566
567 #define si_pm4_bind_state(sctx, member, value) \
568 do { \
569 (sctx)->queued.named.member = (value); \
570 if (value && value != (sctx)->emitted.named.member) \
571 (sctx)->dirty_atoms |= SI_STATE_BIT(member); \
572 else \
573 (sctx)->dirty_atoms &= ~SI_STATE_BIT(member); \
574 } while (0)
575
576 /* si_descriptors.c */
577 void si_get_inline_uniform_state(union si_shader_key *key, enum pipe_shader_type shader,
578 bool *inline_uniforms, uint32_t **inlined_values);
579 void si_set_mutable_tex_desc_fields(struct si_screen *sscreen, struct si_texture *tex,
580 const struct legacy_surf_level *base_level_info,
581 unsigned base_level, unsigned first_level, unsigned block_width,
582 /* restrict decreases overhead of si_set_sampler_view_desc ~8x. */
583 bool is_stencil, uint16_t access, uint32_t * restrict state);
584 void si_update_ps_colorbuf0_slot(struct si_context *sctx);
585 void si_force_disable_ps_colorbuf0_slot(struct si_context *sctx);
586 void si_invalidate_inlinable_uniforms(struct si_context *sctx, enum pipe_shader_type shader);
587 void si_get_pipe_constant_buffer(struct si_context *sctx, uint shader, uint slot,
588 struct pipe_constant_buffer *cbuf);
589 void si_set_shader_buffers(struct pipe_context *ctx, enum pipe_shader_type shader,
590 unsigned start_slot, unsigned count,
591 const struct pipe_shader_buffer *sbuffers,
592 unsigned writable_bitmask, bool internal_blit);
593 void si_get_shader_buffers(struct si_context *sctx, enum pipe_shader_type shader, uint start_slot,
594 uint count, struct pipe_shader_buffer *sbuf);
595 void si_set_ring_buffer(struct si_context *sctx, uint slot, struct pipe_resource *buffer,
596 unsigned stride, unsigned num_records, bool add_tid, bool swizzle,
597 unsigned element_size, unsigned index_stride, uint64_t offset);
598 void si_init_all_descriptors(struct si_context *sctx);
599 void si_release_all_descriptors(struct si_context *sctx);
600 void si_compute_resources_add_all_to_bo_list(struct si_context *sctx);
601 bool si_gfx_resources_check_encrypted(struct si_context *sctx);
602 bool si_compute_resources_check_encrypted(struct si_context *sctx);
603 void si_shader_pointers_mark_dirty(struct si_context *sctx);
604 void si_add_all_descriptors_to_bo_list(struct si_context *sctx);
605 void si_update_all_texture_descriptors(struct si_context *sctx);
606 void si_shader_change_notify(struct si_context *sctx);
607 void si_update_needs_color_decompress_masks(struct si_context *sctx);
608 void si_emit_compute_shader_pointers(struct si_context *sctx);
609 void si_set_internal_const_buffer(struct si_context *sctx, uint slot,
610 const struct pipe_constant_buffer *input);
611 void si_set_internal_shader_buffer(struct si_context *sctx, uint slot,
612 const struct pipe_shader_buffer *sbuffer);
613 void si_set_active_descriptors(struct si_context *sctx, unsigned desc_idx,
614 uint64_t new_active_mask);
615 void si_set_active_descriptors_for_shader(struct si_context *sctx, struct si_shader_selector *sel);
616 void si_rebind_buffer(struct si_context *sctx, struct pipe_resource *buf);
617 /* si_state.c */
618 void si_make_texture_descriptor(struct si_screen *screen, struct si_texture *tex,
619 bool sampler, enum pipe_texture_target target,
620 enum pipe_format pipe_format,
621 const unsigned char state_swizzle[4], unsigned first_level,
622 unsigned last_level, unsigned first_layer,
623 unsigned last_layer, unsigned width, unsigned height,
624 unsigned depth, bool get_bo_metadata,
625 uint32_t *state, uint32_t *fmask_state);
626 void si_init_state_compute_functions(struct si_context *sctx);
627 void si_init_state_functions(struct si_context *sctx);
628 void si_init_screen_state_functions(struct si_screen *sscreen);
629 void si_init_gfx_preamble_state(struct si_context *sctx);
630 void si_make_buffer_descriptor(struct si_screen *screen, struct si_resource *buf,
631 enum pipe_format format, unsigned offset, unsigned num_elements,
632 uint32_t *state);
633 void si_mark_display_dcc_dirty(struct si_context *sctx, struct si_texture *tex);
634 void si_update_ps_iter_samples(struct si_context *sctx);
635 void si_save_qbo_state(struct si_context *sctx, struct si_qbo_state *st);
636 void si_restore_qbo_state(struct si_context *sctx, struct si_qbo_state *st);
637
638 /* si_state_binning.c */
639 void si_emit_dpbb_state(struct si_context *sctx, unsigned index);
640
641 /* si_state_shaders.cpp */
642 void si_get_ir_cache_key(struct si_shader_selector *sel, bool ngg, bool es,
643 unsigned wave_size, unsigned char ir_sha1_cache_key[20]);
644 bool si_shader_cache_load_shader(struct si_screen *sscreen, unsigned char ir_sha1_cache_key[20],
645 struct si_shader *shader);
646 void si_shader_cache_insert_shader(struct si_screen *sscreen, unsigned char ir_sha1_cache_key[20],
647 struct si_shader *shader, bool insert_into_disk_cache);
648 bool si_shader_mem_ordered(struct si_shader *shader);
649 void si_init_screen_live_shader_cache(struct si_screen *sscreen);
650 void si_init_shader_functions(struct si_context *sctx);
651 bool si_init_shader_cache(struct si_screen *sscreen);
652 void si_destroy_shader_cache(struct si_screen *sscreen);
653 void si_schedule_initial_compile(struct si_context *sctx, gl_shader_stage stage,
654 struct util_queue_fence *ready_fence,
655 struct si_compiler_ctx_state *compiler_ctx_state, void *job,
656 util_queue_execute_func execute);
657 void si_get_active_slot_masks(struct si_screen *sscreen, const struct si_shader_info *info,
658 uint64_t *const_and_shader_buffers, uint64_t *samplers_and_images);
659 int si_shader_select(struct pipe_context *ctx, struct si_shader_ctx_state *state);
660 void si_vs_key_update_inputs(struct si_context *sctx);
661 void si_update_ps_inputs_read_or_disabled(struct si_context *sctx);
662 void si_update_vrs_flat_shading(struct si_context *sctx);
663 unsigned si_get_input_prim(const struct si_shader_selector *gs, const union si_shader_key *key,
664 bool return_unknown);
665 unsigned si_get_num_vertices_per_output_prim(struct si_shader *shader);
666 bool si_update_ngg(struct si_context *sctx);
667 void si_vs_ps_key_update_rast_prim_smooth_stipple(struct si_context *sctx);
668 void si_ps_key_update_framebuffer(struct si_context *sctx);
669 void si_ps_key_update_framebuffer_blend_dsa_rasterizer(struct si_context *sctx);
670 void si_ps_key_update_rasterizer(struct si_context *sctx);
671 void si_ps_key_update_dsa(struct si_context *sctx);
672 void si_ps_key_update_sample_shading(struct si_context *sctx);
673 void si_ps_key_update_framebuffer_rasterizer_sample_shading(struct si_context *sctx);
674 void si_init_tess_factor_ring(struct si_context *sctx);
675 bool si_update_gs_ring_buffers(struct si_context *sctx);
676 bool si_update_spi_tmpring_size(struct si_context *sctx, unsigned bytes);
677 bool si_set_tcs_to_fixed_func_shader(struct si_context *sctx);
678 void si_update_tess_io_layout_state(struct si_context *sctx);
679
680 /* si_state_draw.cpp */
681 void si_cp_dma_prefetch(struct si_context *sctx, struct pipe_resource *buf,
682 unsigned offset, unsigned size);
683 void si_set_vertex_buffer_descriptor(struct si_screen *sscreen, struct si_vertex_elements *velems,
684 const struct pipe_vertex_buffer *vb, unsigned element_index,
685 uint32_t *out);
686 void si_emit_buffered_compute_sh_regs(struct si_context *sctx);
687 void si_init_draw_functions_GFX6(struct si_context *sctx);
688 void si_init_draw_functions_GFX7(struct si_context *sctx);
689 void si_init_draw_functions_GFX8(struct si_context *sctx);
690 void si_init_draw_functions_GFX9(struct si_context *sctx);
691 void si_init_draw_functions_GFX10(struct si_context *sctx);
692 void si_init_draw_functions_GFX10_3(struct si_context *sctx);
693 void si_init_draw_functions_GFX11(struct si_context *sctx);
694 void si_init_draw_functions_GFX11_5(struct si_context *sctx);
695 void si_init_draw_functions_GFX12(struct si_context *sctx);
696
697 /* si_state_msaa.c */
698 extern unsigned si_msaa_max_distance[5];
699 void si_init_msaa_functions(struct si_context *sctx);
700
701 /* si_state_streamout.c */
702 void si_streamout_buffers_dirty(struct si_context *sctx);
703 void si_emit_streamout_end(struct si_context *sctx);
704 void si_update_prims_generated_query_state(struct si_context *sctx, unsigned type, int diff);
705 void si_init_streamout_functions(struct si_context *sctx);
706
si_get_constbuf_slot(unsigned slot)707 static inline unsigned si_get_constbuf_slot(unsigned slot)
708 {
709 /* Constant buffers are in slots [32..47], ascending */
710 return SI_NUM_SHADER_BUFFERS + slot;
711 }
712
si_get_shaderbuf_slot(unsigned slot)713 static inline unsigned si_get_shaderbuf_slot(unsigned slot)
714 {
715 /* shader buffers are in slots [31..0], descending */
716 return SI_NUM_SHADER_BUFFERS - 1 - slot;
717 }
718
si_get_sampler_slot(unsigned slot)719 static inline unsigned si_get_sampler_slot(unsigned slot)
720 {
721 /* 32 samplers are in sampler slots [16..47], 16 dw per slot, ascending */
722 /* those are equivalent to image slots [32..95], 8 dw per slot, ascending */
723 return SI_NUM_IMAGE_SLOTS / 2 + slot;
724 }
725
si_get_image_slot(unsigned slot)726 static inline unsigned si_get_image_slot(unsigned slot)
727 {
728 /* image slots are in [31..0] (sampler slots [15..0]), descending */
729 /* images are in slots [31..16], while FMASKs are in slots [15..0] */
730 return SI_NUM_IMAGE_SLOTS - 1 - slot;
731 }
732
si_clamp_texture_texel_count(unsigned max_texel_buffer_elements,enum pipe_format format,uint32_t size)733 static inline unsigned si_clamp_texture_texel_count(unsigned max_texel_buffer_elements,
734 enum pipe_format format,
735 uint32_t size)
736 {
737 /* The spec says:
738 * The number of texels in the texel array is then clamped to the value of
739 * the implementation-dependent limit GL_MAX_TEXTURE_BUFFER_SIZE.
740 *
741 * So compute the number of texels, compare to GL_MAX_TEXTURE_BUFFER_SIZE and update it.
742 */
743 unsigned stride = util_format_get_blocksize(format);
744 return MIN2(max_texel_buffer_elements, size / stride);
745 }
746
747 #ifdef __cplusplus
748 }
749 #endif
750
751 #endif
752