1 /* 2 * Copyright © 2024 Advanced Micro Devices, Inc. 3 * 4 * SPDX-License-Identifier: MIT 5 */ 6 7 #ifndef AMDGPU_USERQ_H 8 #define AMDGPU_USERQ_H 9 10 #ifdef __cplusplus 11 extern "C" { 12 #endif 13 14 /* ring size should be power of 2 and enough to hold AMDGPU_FENCE_RING_SIZE ibs */ 15 #define AMDGPU_USERQ_RING_SIZE 0x10000 16 #define AMDGPU_USERQ_RING_SIZE_DW (AMDGPU_USERQ_RING_SIZE >> 2) 17 #define AMDGPU_USERQ_RING_SIZE_DW_MASK (AMDGPU_USERQ_RING_SIZE_DW - 1) 18 19 /* An offset into doorbell page. Any number will work. */ 20 #define AMDGPU_USERQ_DOORBELL_INDEX 4 21 22 #define amdgpu_pkt_begin() uint32_t *__ring_ptr = userq->ring_ptr; \ 23 uint64_t __next_wptr = userq->next_wptr; 24 25 #define amdgpu_pkt_add_dw(value) do { \ 26 *(__ring_ptr + (__next_wptr & AMDGPU_USERQ_RING_SIZE_DW_MASK)) = value; \ 27 __next_wptr++; \ 28 } while (0) 29 30 #define amdgpu_pkt_end() do { \ 31 assert(__next_wptr - *userq->user_fence_ptr <= AMDGPU_USERQ_RING_SIZE_DW); \ 32 userq->next_wptr = __next_wptr; \ 33 } while (0) 34 35 struct amdgpu_winsys; 36 37 struct amdgpu_userq_gfx_data { 38 struct pb_buffer_lean *csa_bo; 39 struct pb_buffer_lean *shadow_bo; 40 }; 41 42 struct amdgpu_userq_compute_data { 43 struct pb_buffer_lean *eop_bo; 44 }; 45 46 struct amdgpu_userq_sdma_data { 47 struct pb_buffer_lean *csa_bo; 48 }; 49 50 /* For gfx, compute and sdma ip there will be one userqueue per process. 51 * i.e. commands from all context will be submitted to single userqueue. 52 * There will be one struct amdgpu_userq per gfx, compute and sdma ip. 53 */ 54 struct amdgpu_userq { 55 struct pb_buffer_lean *gtt_bo; 56 uint8_t *gtt_bo_map; 57 58 uint32_t *ring_ptr; 59 uint64_t *user_fence_ptr; 60 uint64_t user_fence_va; 61 uint64_t user_fence_seq_num; 62 63 struct pb_buffer_lean *wptr_bo; 64 uint64_t *wptr_bo_map; 65 /* Holds the wptr value for the in-progress submission. When we're ready 66 * to submit it, this value will be written to the door bell. 67 * (this avoids writing multiple times to the door bell for the same 68 * submission) */ 69 uint64_t next_wptr; 70 struct pb_buffer_lean *rptr_bo; 71 72 struct pb_buffer_lean *doorbell_bo; 73 uint64_t *doorbell_bo_map; 74 75 uint32_t userq_handle; 76 enum amd_ip_type ip_type; 77 simple_mtx_t lock; 78 79 union { 80 struct amdgpu_userq_gfx_data gfx_data; 81 struct amdgpu_userq_compute_data compute_data; 82 struct amdgpu_userq_sdma_data sdma_data; 83 }; 84 }; 85 86 bool 87 amdgpu_userq_init(struct amdgpu_winsys *aws, struct amdgpu_userq *userq, enum amd_ip_type ip_type); 88 void 89 amdgpu_userq_deinit(struct amdgpu_winsys *aws, struct amdgpu_userq *userq); 90 91 #ifdef __cplusplus 92 } 93 #endif 94 95 #endif 96