1 /* 2 * Copyright © 2011 Red Hat All Rights Reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining 5 * a copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 13 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 14 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 15 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS 16 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 */ 25 /* 26 * Authors: 27 * Jérôme Glisse <jglisse@redhat.com> 28 */ 29 #ifndef RADEON_SURFACE_H 30 #define RADEON_SURFACE_H 31 32 #include <stdint.h> 33 34 /* Note : 35 * 36 * For texture array, the n layer are stored one after the other within each 37 * mipmap level. 0 value for field than can be hint is always valid. 38 */ 39 40 #define RADEON_SURF_MAX_LEVEL 32 41 42 #define RADEON_SURF_TYPE_MASK 0xFF 43 #define RADEON_SURF_TYPE_SHIFT 0 44 #define RADEON_SURF_TYPE_1D 0 45 #define RADEON_SURF_TYPE_2D 1 46 #define RADEON_SURF_TYPE_3D 2 47 #define RADEON_SURF_TYPE_CUBEMAP 3 48 #define RADEON_SURF_TYPE_1D_ARRAY 4 49 #define RADEON_SURF_TYPE_2D_ARRAY 5 50 #define RADEON_SURF_MODE_MASK 0xFF 51 #define RADEON_SURF_MODE_SHIFT 8 52 #define RADEON_SURF_MODE_LINEAR 0 53 #define RADEON_SURF_MODE_LINEAR_ALIGNED 1 54 #define RADEON_SURF_MODE_1D 2 55 #define RADEON_SURF_MODE_2D 3 56 #define RADEON_SURF_SCANOUT (1 << 16) 57 #define RADEON_SURF_ZBUFFER (1 << 17) 58 #define RADEON_SURF_SBUFFER (1 << 18) 59 #define RADEON_SURF_Z_OR_SBUFFER (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER) 60 #define RADEON_SURF_HAS_SBUFFER_MIPTREE (1 << 19) 61 #define RADEON_SURF_HAS_TILE_MODE_INDEX (1 << 20) 62 #define RADEON_SURF_FMASK (1 << 21) 63 64 #define RADEON_SURF_GET(v, field) (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK) 65 #define RADEON_SURF_SET(v, field) (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT) 66 #define RADEON_SURF_CLR(v, field) ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT)) 67 68 /* first field up to mode need to match r6 struct so that we can reuse 69 * same function for linear & linear aligned 70 */ 71 struct radeon_surface_level { 72 uint64_t offset; 73 uint64_t slice_size; 74 uint32_t npix_x; 75 uint32_t npix_y; 76 uint32_t npix_z; 77 uint32_t nblk_x; 78 uint32_t nblk_y; 79 uint32_t nblk_z; 80 uint32_t pitch_bytes; 81 uint32_t mode; 82 }; 83 84 enum si_tiling_mode { 85 SI_TILING_AUTO = 0, 86 87 SI_TILING_COLOR_1D, 88 SI_TILING_COLOR_1D_SCANOUT, 89 SI_TILING_COLOR_2D_8BPP, 90 SI_TILING_COLOR_2D_16BPP, 91 SI_TILING_COLOR_2D_32BPP, 92 SI_TILING_COLOR_2D_64BPP, 93 SI_TILING_COLOR_2D_SCANOUT_16BPP, 94 SI_TILING_COLOR_2D_SCANOUT_32BPP, 95 SI_TILING_COLOR_LINEAR, 96 97 SI_TILING_STENCIL_1D, 98 SI_TILING_STENCIL_2D, 99 SI_TILING_STENCIL_2D_2AA, 100 SI_TILING_STENCIL_2D_4AA, 101 SI_TILING_STENCIL_2D_8AA, 102 103 SI_TILING_DEPTH_1D, 104 SI_TILING_DEPTH_2D, 105 SI_TILING_DEPTH_2D_2AA, 106 SI_TILING_DEPTH_2D_4AA, 107 SI_TILING_DEPTH_2D_8AA, 108 109 SI_TILING_LAST_MODE, 110 }; 111 112 struct radeon_surface { 113 uint32_t npix_x; 114 uint32_t npix_y; 115 uint32_t npix_z; 116 uint32_t blk_w; 117 uint32_t blk_h; 118 uint32_t blk_d; 119 uint32_t array_size; 120 uint32_t last_level; 121 uint32_t bpe; 122 uint32_t nsamples; 123 uint32_t flags; 124 /* Following is updated/fill by the allocator. It's allowed to 125 * set some of the value but they are use as hint and can be 126 * overridden (things lile bankw/bankh on evergreen for 127 * instance). 128 */ 129 uint64_t bo_size; 130 uint64_t bo_alignment; 131 /* apply to eg */ 132 uint32_t bankw; 133 uint32_t bankh; 134 uint32_t mtilea; 135 uint32_t tile_split; 136 uint32_t stencil_tile_split; 137 uint64_t stencil_offset; 138 struct radeon_surface_level level[RADEON_SURF_MAX_LEVEL]; 139 struct radeon_surface_level stencil_level[RADEON_SURF_MAX_LEVEL]; 140 uint32_t tiling_index[RADEON_SURF_MAX_LEVEL]; 141 uint32_t stencil_tiling_index[RADEON_SURF_MAX_LEVEL]; 142 }; 143 144 struct radeon_surface_manager *radeon_surface_manager_new(int fd); 145 void radeon_surface_manager_free(struct radeon_surface_manager *surf_man); 146 int radeon_surface_init(struct radeon_surface_manager *surf_man, 147 struct radeon_surface *surf); 148 int radeon_surface_best(struct radeon_surface_manager *surf_man, 149 struct radeon_surface *surf); 150 151 #endif 152