1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /** @file
25 *
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
28 */
29
30 #include "brw_eu.h"
31 #include "brw_disasm_info.h"
32 #include "brw_fs.h"
33 #include "brw_generator.h"
34 #include "brw_cfg.h"
35 #include "dev/intel_debug.h"
36 #include "util/mesa-sha1.h"
37 #include "util/half_float.h"
38
39 static uint32_t
brw_math_function(enum opcode op)40 brw_math_function(enum opcode op)
41 {
42 switch (op) {
43 case SHADER_OPCODE_RCP:
44 return BRW_MATH_FUNCTION_INV;
45 case SHADER_OPCODE_RSQ:
46 return BRW_MATH_FUNCTION_RSQ;
47 case SHADER_OPCODE_SQRT:
48 return BRW_MATH_FUNCTION_SQRT;
49 case SHADER_OPCODE_EXP2:
50 return BRW_MATH_FUNCTION_EXP;
51 case SHADER_OPCODE_LOG2:
52 return BRW_MATH_FUNCTION_LOG;
53 case SHADER_OPCODE_POW:
54 return BRW_MATH_FUNCTION_POW;
55 case SHADER_OPCODE_SIN:
56 return BRW_MATH_FUNCTION_SIN;
57 case SHADER_OPCODE_COS:
58 return BRW_MATH_FUNCTION_COS;
59 case SHADER_OPCODE_INT_QUOTIENT:
60 return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
61 case SHADER_OPCODE_INT_REMAINDER:
62 return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
63 default:
64 unreachable("not reached: unknown math function");
65 }
66 }
67
68 static struct brw_reg
normalize_brw_reg_for_encoding(brw_reg * reg)69 normalize_brw_reg_for_encoding(brw_reg *reg)
70 {
71 struct brw_reg brw_reg;
72
73 switch (reg->file) {
74 case ADDRESS:
75 case ARF:
76 case FIXED_GRF:
77 case IMM:
78 assert(reg->offset == 0);
79 brw_reg = *reg;
80 break;
81 case BAD_FILE:
82 /* Probably unused. */
83 brw_reg = brw_null_reg();
84 break;
85 case VGRF:
86 case ATTR:
87 case UNIFORM:
88 unreachable("not reached");
89 }
90
91 return brw_reg;
92 }
93
brw_generator(const struct brw_compiler * compiler,const struct brw_compile_params * params,struct brw_stage_prog_data * prog_data,gl_shader_stage stage)94 brw_generator::brw_generator(const struct brw_compiler *compiler,
95 const struct brw_compile_params *params,
96 struct brw_stage_prog_data *prog_data,
97 gl_shader_stage stage)
98
99 : compiler(compiler), params(params),
100 devinfo(compiler->devinfo),
101 prog_data(prog_data), dispatch_width(0),
102 debug_flag(false),
103 shader_name(NULL), stage(stage), mem_ctx(params->mem_ctx)
104 {
105 p = rzalloc(mem_ctx, struct brw_codegen);
106 brw_init_codegen(&compiler->isa, p, mem_ctx);
107 }
108
~brw_generator()109 brw_generator::~brw_generator()
110 {
111 }
112
113 class ip_record : public exec_node {
114 public:
115 DECLARE_RALLOC_CXX_OPERATORS(ip_record)
116
ip_record(int ip)117 ip_record(int ip)
118 {
119 this->ip = ip;
120 }
121
122 int ip;
123 };
124
125 bool
patch_halt_jumps()126 brw_generator::patch_halt_jumps()
127 {
128 if (this->discard_halt_patches.is_empty())
129 return false;
130
131 int scale = brw_jump_scale(p->devinfo);
132
133 /* There is a somewhat strange undocumented requirement of using
134 * HALT, according to the simulator. If some channel has HALTed to
135 * a particular UIP, then by the end of the program, every channel
136 * must have HALTed to that UIP. Furthermore, the tracking is a
137 * stack, so you can't do the final halt of a UIP after starting
138 * halting to a new UIP.
139 *
140 * Symptoms of not emitting this instruction on actual hardware
141 * included GPU hangs and sparkly rendering on the piglit discard
142 * tests.
143 */
144 brw_eu_inst *last_halt = brw_HALT(p);
145 brw_eu_inst_set_uip(p->devinfo, last_halt, 1 * scale);
146 brw_eu_inst_set_jip(p->devinfo, last_halt, 1 * scale);
147
148 int ip = p->nr_insn;
149
150 foreach_in_list(ip_record, patch_ip, &discard_halt_patches) {
151 brw_eu_inst *patch = &p->store[patch_ip->ip];
152
153 assert(brw_eu_inst_opcode(p->isa, patch) == BRW_OPCODE_HALT);
154 /* HALT takes a half-instruction distance from the pre-incremented IP. */
155 brw_eu_inst_set_uip(p->devinfo, patch, (ip - patch_ip->ip) * scale);
156 }
157
158 this->discard_halt_patches.make_empty();
159
160 return true;
161 }
162
163 void
generate_send(fs_inst * inst,struct brw_reg dst,struct brw_reg desc,struct brw_reg ex_desc,struct brw_reg payload,struct brw_reg payload2)164 brw_generator::generate_send(fs_inst *inst,
165 struct brw_reg dst,
166 struct brw_reg desc,
167 struct brw_reg ex_desc,
168 struct brw_reg payload,
169 struct brw_reg payload2)
170 {
171 const bool gather = inst->opcode == SHADER_OPCODE_SEND_GATHER;
172 if (gather) {
173 assert(payload.file == ARF);
174 assert(payload.nr == BRW_ARF_SCALAR);
175 assert(payload2.file == ARF);
176 assert(payload2.nr == BRW_ARF_NULL);
177 }
178
179 if (ex_desc.file == IMM && ex_desc.ud == 0) {
180 brw_send_indirect_message(p, inst->sfid, dst, payload, desc, inst->eot, gather);
181 if (inst->check_tdr)
182 brw_eu_inst_set_opcode(p->isa, brw_last_inst, BRW_OPCODE_SENDC);
183 } else {
184 /* If we have any sort of extended descriptor, then we need SENDS. This
185 * also covers the dual-payload case because ex_mlen goes in ex_desc.
186 */
187 brw_send_indirect_split_message(p, inst->sfid, dst, payload, payload2,
188 desc, ex_desc, inst->ex_mlen,
189 inst->send_ex_bso, inst->eot, gather);
190 if (inst->check_tdr)
191 brw_eu_inst_set_opcode(p->isa, brw_last_inst,
192 devinfo->ver >= 12 ? BRW_OPCODE_SENDC : BRW_OPCODE_SENDSC);
193 }
194 }
195
196 void
generate_mov_indirect(fs_inst * inst,struct brw_reg dst,struct brw_reg reg,struct brw_reg indirect_byte_offset)197 brw_generator::generate_mov_indirect(fs_inst *inst,
198 struct brw_reg dst,
199 struct brw_reg reg,
200 struct brw_reg indirect_byte_offset)
201 {
202 assert(indirect_byte_offset.type == BRW_TYPE_UD);
203 assert(indirect_byte_offset.file == FIXED_GRF);
204 assert(!reg.abs && !reg.negate);
205
206 /* Gen12.5 adds the following region restriction:
207 *
208 * "Vx1 and VxH indirect addressing for Float, Half-Float, Double-Float
209 * and Quad-Word data must not be used."
210 *
211 * We require the source and destination types to match so stomp to an
212 * unsigned integer type.
213 */
214 assert(reg.type == dst.type);
215 reg.type = dst.type =
216 brw_type_with_size(BRW_TYPE_UD, brw_type_size_bits(reg.type));
217
218 unsigned imm_byte_offset = reg.nr * REG_SIZE + reg.subnr;
219
220 if (indirect_byte_offset.file == IMM) {
221 imm_byte_offset += indirect_byte_offset.ud;
222
223 reg.nr = imm_byte_offset / REG_SIZE;
224 reg.subnr = imm_byte_offset % REG_SIZE;
225 if (brw_type_size_bytes(reg.type) > 4 && !devinfo->has_64bit_int) {
226 brw_MOV(p, subscript(dst, BRW_TYPE_D, 0),
227 subscript(reg, BRW_TYPE_D, 0));
228 brw_set_default_swsb(p, tgl_swsb_null());
229 brw_MOV(p, subscript(dst, BRW_TYPE_D, 1),
230 subscript(reg, BRW_TYPE_D, 1));
231 } else {
232 brw_MOV(p, dst, reg);
233 }
234 } else {
235 /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */
236 struct brw_reg addr = vec8(brw_address_reg(0));
237
238 /* Whether we can use destination dependency control without running the
239 * risk of a hang if an instruction gets shot down.
240 */
241 const bool use_dep_ctrl = !inst->predicate &&
242 inst->exec_size == dispatch_width;
243 brw_eu_inst *insn;
244
245 /* The destination stride of an instruction (in bytes) must be greater
246 * than or equal to the size of the rest of the instruction. Since the
247 * address register is of type UW, we can't use a D-type instruction.
248 * In order to get around this, re retype to UW and use a stride.
249 */
250 indirect_byte_offset =
251 retype(spread(indirect_byte_offset, 2), BRW_TYPE_UW);
252
253 /* There are a number of reasons why we don't use the base offset here.
254 * One reason is that the field is only 9 bits which means we can only
255 * use it to access the first 16 GRFs. Also, from the Haswell PRM
256 * section "Register Region Restrictions":
257 *
258 * "The lower bits of the AddressImmediate must not overflow to
259 * change the register address. The lower 5 bits of Address
260 * Immediate when added to lower 5 bits of address register gives
261 * the sub-register offset. The upper bits of Address Immediate
262 * when added to upper bits of address register gives the register
263 * address. Any overflow from sub-register offset is dropped."
264 *
265 * Since the indirect may cause us to cross a register boundary, this
266 * makes the base offset almost useless. We could try and do something
267 * clever where we use a actual base offset if base_offset % 32 == 0 but
268 * that would mean we were generating different code depending on the
269 * base offset. Instead, for the sake of consistency, we'll just do the
270 * add ourselves. This restriction is only listed in the Haswell PRM
271 * but empirical testing indicates that it applies on all older
272 * generations and is lifted on Broadwell.
273 *
274 * In the end, while base_offset is nice to look at in the generated
275 * code, using it saves us 0 instructions and would require quite a bit
276 * of case-by-case work. It's just not worth it.
277 *
278 * Due to a hardware bug some platforms (particularly Gfx11+) seem to
279 * require the address components of all channels to be valid whether or
280 * not they're active, which causes issues if we use VxH addressing
281 * under non-uniform control-flow. We can easily work around that by
282 * initializing the whole address register with a pipelined NoMask MOV
283 * instruction.
284 */
285 insn = brw_MOV(p, addr, brw_imm_uw(imm_byte_offset));
286 brw_eu_inst_set_mask_control(devinfo, insn, BRW_MASK_DISABLE);
287 brw_eu_inst_set_pred_control(devinfo, insn, BRW_PREDICATE_NONE);
288 if (devinfo->ver >= 12)
289 brw_set_default_swsb(p, tgl_swsb_null());
290 else
291 brw_eu_inst_set_no_dd_clear(devinfo, insn, use_dep_ctrl);
292
293 insn = brw_ADD(p, addr, indirect_byte_offset, brw_imm_uw(imm_byte_offset));
294 if (devinfo->ver >= 12)
295 brw_set_default_swsb(p, tgl_swsb_regdist(1));
296 else
297 brw_eu_inst_set_no_dd_check(devinfo, insn, use_dep_ctrl);
298
299 if (brw_type_size_bytes(reg.type) > 4 &&
300 (intel_device_info_is_9lp(devinfo) || !devinfo->has_64bit_int)) {
301 /* From the Cherryview PRM Vol 7. "Register Region Restrictions":
302 *
303 * "When source or destination datatype is 64b or operation is
304 * integer DWord multiply, indirect addressing must not be used."
305 *
306 * We may also not support Q/UQ types.
307 *
308 * To work around both of these, we do two integer MOVs instead
309 * of one 64-bit MOV. Because no double value should ever cross
310 * a register boundary, it's safe to use the immediate offset in
311 * the indirect here to handle adding 4 bytes to the offset and
312 * avoid the extra ADD to the register file.
313 */
314 brw_MOV(p, subscript(dst, BRW_TYPE_D, 0),
315 retype(brw_VxH_indirect(0, 0), BRW_TYPE_D));
316 brw_set_default_swsb(p, tgl_swsb_null());
317 brw_MOV(p, subscript(dst, BRW_TYPE_D, 1),
318 retype(brw_VxH_indirect(0, 4), BRW_TYPE_D));
319 } else {
320 struct brw_reg ind_src = brw_VxH_indirect(0, 0);
321
322 brw_MOV(p, dst, retype(ind_src, reg.type));
323 }
324 }
325 }
326
327 void
generate_shuffle(fs_inst * inst,struct brw_reg dst,struct brw_reg src,struct brw_reg idx)328 brw_generator::generate_shuffle(fs_inst *inst,
329 struct brw_reg dst,
330 struct brw_reg src,
331 struct brw_reg idx)
332 {
333 assert(src.file == FIXED_GRF);
334 assert(!src.abs && !src.negate);
335
336 /* Ivy bridge has some strange behavior that makes this a real pain to
337 * implement for 64-bit values so we just don't bother.
338 */
339 assert(devinfo->has_64bit_float || brw_type_size_bytes(src.type) <= 4);
340
341 /* Gen12.5 adds the following region restriction:
342 *
343 * "Vx1 and VxH indirect addressing for Float, Half-Float, Double-Float
344 * and Quad-Word data must not be used."
345 *
346 * We require the source and destination types to match so stomp to an
347 * unsigned integer type.
348 */
349 assert(src.type == dst.type);
350 src.type = dst.type =
351 brw_type_with_size(BRW_TYPE_UD, brw_type_size_bits(src.type));
352
353 /* Because we're using the address register, we're limited to 16-wide
354 * by the address register file and 8-wide for 64-bit types. We could try
355 * and make this instruction splittable higher up in the compiler but that
356 * gets weird because it reads all of the channels regardless of execution
357 * size. It's easier just to split it here.
358 */
359 unsigned lower_width = MIN2(16, inst->exec_size);
360 if (devinfo->ver < 20 && (element_sz(src) > 4 || element_sz(dst) > 4)) {
361 lower_width = 8;
362 }
363
364 brw_set_default_exec_size(p, cvt(lower_width) - 1);
365 for (unsigned group = 0; group < inst->exec_size; group += lower_width) {
366 brw_set_default_group(p, group);
367
368 if ((src.vstride == 0 && src.hstride == 0) ||
369 idx.file == IMM) {
370 /* Trivial, the source is already uniform or the index is a constant.
371 * We will typically not get here if the optimizer is doing its job,
372 * but asserting would be mean.
373 */
374 const unsigned i = idx.file == IMM ? idx.ud : 0;
375 struct brw_reg group_src = stride(suboffset(src, i), 0, 1, 0);
376 struct brw_reg group_dst = suboffset(dst, group << (dst.hstride - 1));
377 brw_MOV(p, group_dst, group_src);
378 } else {
379 /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */
380 struct brw_reg addr = vec8(brw_address_reg(0));
381
382 struct brw_reg group_idx = suboffset(idx, group);
383
384 if (lower_width == 8 && group_idx.width == BRW_WIDTH_16) {
385 /* Things get grumpy if the register is too wide. */
386 group_idx.width--;
387 group_idx.vstride--;
388 }
389
390 assert(brw_type_size_bytes(group_idx.type) <= 4);
391 if (brw_type_size_bytes(group_idx.type) == 4) {
392 /* The destination stride of an instruction (in bytes) must be
393 * greater than or equal to the size of the rest of the
394 * instruction. Since the address register is of type UW, we
395 * can't use a D-type instruction. In order to get around this,
396 * re retype to UW and use a stride.
397 */
398 group_idx = retype(spread(group_idx, 2), BRW_TYPE_W);
399 }
400
401 uint32_t src_start_offset = src.nr * REG_SIZE + src.subnr;
402
403 /* From the Haswell PRM:
404 *
405 * "When a sequence of NoDDChk and NoDDClr are used, the last
406 * instruction that completes the scoreboard clear must have a
407 * non-zero execution mask. This means, if any kind of predication
408 * can change the execution mask or channel enable of the last
409 * instruction, the optimization must be avoided. This is to
410 * avoid instructions being shot down the pipeline when no writes
411 * are required."
412 *
413 * Whenever predication is enabled or the instructions being emitted
414 * aren't the full width, it's possible that it will be run with zero
415 * channels enabled so we can't use dependency control without
416 * running the risk of a hang if an instruction gets shot down.
417 */
418 const bool use_dep_ctrl = !inst->predicate &&
419 lower_width == dispatch_width;
420 brw_eu_inst *insn;
421
422 /* Due to a hardware bug some platforms (particularly Gfx11+) seem
423 * to require the address components of all channels to be valid
424 * whether or not they're active, which causes issues if we use VxH
425 * addressing under non-uniform control-flow. We can easily work
426 * around that by initializing the whole address register with a
427 * pipelined NoMask MOV instruction.
428 */
429 insn = brw_MOV(p, addr, brw_imm_uw(src_start_offset));
430 brw_eu_inst_set_mask_control(devinfo, insn, BRW_MASK_DISABLE);
431 brw_eu_inst_set_pred_control(devinfo, insn, BRW_PREDICATE_NONE);
432 if (devinfo->ver >= 12)
433 brw_set_default_swsb(p, tgl_swsb_null());
434 else
435 brw_eu_inst_set_no_dd_clear(devinfo, insn, use_dep_ctrl);
436
437 /* Take into account the component size and horizontal stride. */
438 assert(src.vstride == src.hstride + src.width);
439 insn = brw_SHL(p, addr, group_idx,
440 brw_imm_uw(util_logbase2(brw_type_size_bytes(src.type)) +
441 src.hstride - 1));
442 if (devinfo->ver >= 12)
443 brw_set_default_swsb(p, tgl_swsb_regdist(1));
444 else
445 brw_eu_inst_set_no_dd_check(devinfo, insn, use_dep_ctrl);
446
447 /* Add on the register start offset */
448 brw_ADD(p, addr, addr, brw_imm_uw(src_start_offset));
449 brw_MOV(p, suboffset(dst, group << (dst.hstride - 1)),
450 retype(brw_VxH_indirect(0, 0), src.type));
451 }
452
453 brw_set_default_swsb(p, tgl_swsb_null());
454 }
455 }
456
457 void
generate_quad_swizzle(const fs_inst * inst,struct brw_reg dst,struct brw_reg src,unsigned swiz)458 brw_generator::generate_quad_swizzle(const fs_inst *inst,
459 struct brw_reg dst, struct brw_reg src,
460 unsigned swiz)
461 {
462 /* Requires a quad. */
463 assert(inst->exec_size >= 4);
464
465 if (src.file == IMM ||
466 has_scalar_region(src)) {
467 /* The value is uniform across all channels */
468 brw_MOV(p, dst, src);
469
470 } else if (devinfo->ver < 11 && brw_type_size_bytes(src.type) == 4) {
471 /* This only works on 8-wide 32-bit values */
472 assert(inst->exec_size == 8);
473 assert(src.hstride == BRW_HORIZONTAL_STRIDE_1);
474 assert(src.vstride == src.width + 1);
475 brw_set_default_access_mode(p, BRW_ALIGN_16);
476 struct brw_reg swiz_src = stride(src, 4, 4, 1);
477 swiz_src.swizzle = swiz;
478 brw_MOV(p, dst, swiz_src);
479
480 } else {
481 assert(src.hstride == BRW_HORIZONTAL_STRIDE_1);
482 assert(src.vstride == src.width + 1);
483 const struct brw_reg src_0 = suboffset(src, BRW_GET_SWZ(swiz, 0));
484
485 switch (swiz) {
486 case BRW_SWIZZLE_XXXX:
487 case BRW_SWIZZLE_YYYY:
488 case BRW_SWIZZLE_ZZZZ:
489 case BRW_SWIZZLE_WWWW:
490 brw_MOV(p, dst, stride(src_0, 4, 4, 0));
491 break;
492
493 case BRW_SWIZZLE_XXZZ:
494 case BRW_SWIZZLE_YYWW:
495 brw_MOV(p, dst, stride(src_0, 2, 2, 0));
496 break;
497
498 case BRW_SWIZZLE_XYXY:
499 case BRW_SWIZZLE_ZWZW:
500 assert(inst->exec_size == 4);
501 brw_MOV(p, dst, stride(src_0, 0, 2, 1));
502 break;
503
504 default:
505 assert(inst->force_writemask_all);
506 brw_set_default_exec_size(p, cvt(inst->exec_size / 4) - 1);
507
508 for (unsigned c = 0; c < 4; c++) {
509 brw_eu_inst *insn = brw_MOV(
510 p, stride(suboffset(dst, c),
511 4 * inst->dst.stride, 1, 4 * inst->dst.stride),
512 stride(suboffset(src, BRW_GET_SWZ(swiz, c)), 4, 1, 0));
513
514 if (devinfo->ver < 12) {
515 brw_eu_inst_set_no_dd_clear(devinfo, insn, c < 3);
516 brw_eu_inst_set_no_dd_check(devinfo, insn, c > 0);
517 }
518
519 brw_set_default_swsb(p, tgl_swsb_null());
520 }
521
522 break;
523 }
524 }
525 }
526
527 void
generate_barrier(fs_inst *,struct brw_reg src)528 brw_generator::generate_barrier(fs_inst *, struct brw_reg src)
529 {
530 brw_barrier(p, src);
531 if (devinfo->ver >= 12) {
532 brw_set_default_swsb(p, tgl_swsb_null());
533 brw_SYNC(p, TGL_SYNC_BAR);
534 } else {
535 brw_WAIT(p);
536 }
537 }
538
539 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
540 * looking like:
541 *
542 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
543 *
544 * Ideally, we want to produce:
545 *
546 * DDX DDY
547 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
548 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
549 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
550 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
551 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
552 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
553 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
554 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
555 *
556 * and add another set of two more subspans if in 16-pixel dispatch mode.
557 *
558 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
559 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
560 * pair. But the ideal approximation may impose a huge performance cost on
561 * sample_d. On at least Haswell, sample_d instruction does some
562 * optimizations if the same LOD is used for all pixels in the subspan.
563 *
564 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
565 * appropriate swizzling.
566 */
567 void
generate_ddx(const fs_inst * inst,struct brw_reg dst,struct brw_reg src)568 brw_generator::generate_ddx(const fs_inst *inst,
569 struct brw_reg dst, struct brw_reg src)
570 {
571 unsigned vstride, width;
572
573 if (inst->opcode == FS_OPCODE_DDX_FINE) {
574 /* produce accurate derivatives */
575 vstride = BRW_VERTICAL_STRIDE_2;
576 width = BRW_WIDTH_2;
577 } else {
578 /* replicate the derivative at the top-left pixel to other pixels */
579 vstride = BRW_VERTICAL_STRIDE_4;
580 width = BRW_WIDTH_4;
581 }
582
583 struct brw_reg src0 = byte_offset(src, brw_type_size_bytes(src.type));;
584 struct brw_reg src1 = src;
585
586 src0.vstride = vstride;
587 src0.width = width;
588 src0.hstride = BRW_HORIZONTAL_STRIDE_0;
589 src1.vstride = vstride;
590 src1.width = width;
591 src1.hstride = BRW_HORIZONTAL_STRIDE_0;
592
593 brw_ADD(p, dst, src0, negate(src1));
594 }
595
596 /* The negate_value boolean is used to negate the derivative computation for
597 * FBOs, since they place the origin at the upper left instead of the lower
598 * left.
599 */
600 void
generate_ddy(const fs_inst * inst,struct brw_reg dst,struct brw_reg src)601 brw_generator::generate_ddy(const fs_inst *inst,
602 struct brw_reg dst, struct brw_reg src)
603 {
604 const uint32_t type_size = brw_type_size_bytes(src.type);
605
606 if (inst->opcode == FS_OPCODE_DDY_FINE) {
607 /* produce accurate derivatives.
608 *
609 * From the Broadwell PRM, Volume 7 (3D-Media-GPGPU)
610 * "Register Region Restrictions", Section "1. Special Restrictions":
611 *
612 * "In Align16 mode, the channel selects and channel enables apply to
613 * a pair of half-floats, because these parameters are defined for
614 * DWord elements ONLY. This is applicable when both source and
615 * destination are half-floats."
616 *
617 * So for half-float operations we use the Gfx11+ Align1 path. CHV
618 * inherits its FP16 hardware from SKL, so it is not affected.
619 */
620 if (devinfo->ver >= 11) {
621 src = stride(src, 0, 2, 1);
622
623 brw_push_insn_state(p);
624 brw_set_default_exec_size(p, BRW_EXECUTE_4);
625 for (uint32_t g = 0; g < inst->exec_size; g += 4) {
626 brw_set_default_group(p, inst->group + g);
627 brw_ADD(p, byte_offset(dst, g * type_size),
628 negate(byte_offset(src, g * type_size)),
629 byte_offset(src, (g + 2) * type_size));
630 brw_set_default_swsb(p, tgl_swsb_null());
631 }
632 brw_pop_insn_state(p);
633 } else {
634 struct brw_reg src0 = stride(src, 4, 4, 1);
635 struct brw_reg src1 = stride(src, 4, 4, 1);
636 src0.swizzle = BRW_SWIZZLE_XYXY;
637 src1.swizzle = BRW_SWIZZLE_ZWZW;
638
639 brw_push_insn_state(p);
640 brw_set_default_access_mode(p, BRW_ALIGN_16);
641 brw_ADD(p, dst, negate(src0), src1);
642 brw_pop_insn_state(p);
643 }
644 } else {
645 /* replicate the derivative at the top-left pixel to other pixels */
646 struct brw_reg src0 = byte_offset(stride(src, 4, 4, 0), 0 * type_size);
647 struct brw_reg src1 = byte_offset(stride(src, 4, 4, 0), 2 * type_size);
648
649 brw_ADD(p, dst, negate(src0), src1);
650 }
651 }
652
653 void
generate_halt(fs_inst *)654 brw_generator::generate_halt(fs_inst *)
655 {
656 /* This HALT will be patched up at FB write time to point UIP at the end of
657 * the program, and at brw_uip_jip() JIP will be set to the end of the
658 * current block (or the program).
659 */
660 this->discard_halt_patches.push_tail(new(mem_ctx) ip_record(p->nr_insn));
661 brw_HALT(p);
662 }
663
664 /* The A32 messages take a buffer base address in header.5:[31:0] (See
665 * MH1_A32_PSM for typed messages or MH_A32_GO for byte/dword scattered
666 * and OWord block messages in the SKL PRM Vol. 2d for more details.)
667 * Unfortunately, there are a number of subtle differences:
668 *
669 * For the block read/write messages:
670 *
671 * - We always stomp header.2 to fill in the actual scratch address (in
672 * units of OWORDs) so we don't care what's in there.
673 *
674 * - They rely on per-thread scratch space value in header.3[3:0] to do
675 * bounds checking so that needs to be valid. The upper bits of
676 * header.3 are ignored, though, so we can copy all of g0.3.
677 *
678 * - They ignore header.5[9:0] and assumes the address is 1KB aligned.
679 *
680 *
681 * For the byte/dword scattered read/write messages:
682 *
683 * - We want header.2 to be zero because that gets added to the per-channel
684 * offset in the non-header portion of the message.
685 *
686 * - Contrary to what the docs claim, they don't do any bounds checking so
687 * the value of header.3[3:0] doesn't matter.
688 *
689 * - They consider all of header.5 for the base address and header.5[9:0]
690 * are not ignored. This means that we can't copy g0.5 verbatim because
691 * g0.5[9:0] contains the FFTID on most platforms. Instead, we have to
692 * use an AND to mask off the bottom 10 bits.
693 *
694 *
695 * For block messages, just copying g0 gives a valid header because all the
696 * garbage gets ignored except for header.2 which we stomp as part of message
697 * setup. For byte/dword scattered messages, we can just zero out the header
698 * and copy over the bits we need from g0.5. This opcode, however, tries to
699 * satisfy the requirements of both by starting with 0 and filling out the
700 * information required by either set of opcodes.
701 */
702 void
generate_scratch_header(fs_inst * inst,struct brw_reg dst,struct brw_reg src)703 brw_generator::generate_scratch_header(fs_inst *inst,
704 struct brw_reg dst,
705 struct brw_reg src)
706 {
707 assert(inst->exec_size == 8 && inst->force_writemask_all);
708 assert(dst.file == FIXED_GRF);
709 assert(src.file == FIXED_GRF);
710 assert(src.type == BRW_TYPE_UD);
711
712 dst.type = BRW_TYPE_UD;
713
714 brw_eu_inst *insn = brw_MOV(p, dst, brw_imm_ud(0));
715 if (devinfo->ver >= 12)
716 brw_set_default_swsb(p, tgl_swsb_null());
717 else
718 brw_eu_inst_set_no_dd_clear(p->devinfo, insn, true);
719
720 /* Copy the per-thread scratch space size from g0.3[3:0] */
721 brw_set_default_exec_size(p, BRW_EXECUTE_1);
722 insn = brw_AND(p, suboffset(dst, 3), component(src, 3),
723 brw_imm_ud(INTEL_MASK(3, 0)));
724 if (devinfo->ver < 12) {
725 brw_eu_inst_set_no_dd_clear(p->devinfo, insn, true);
726 brw_eu_inst_set_no_dd_check(p->devinfo, insn, true);
727 }
728
729 /* Copy the scratch base address from g0.5[31:10] */
730 insn = brw_AND(p, suboffset(dst, 5), component(src, 5),
731 brw_imm_ud(INTEL_MASK(31, 10)));
732 if (devinfo->ver < 12)
733 brw_eu_inst_set_no_dd_check(p->devinfo, insn, true);
734 }
735
736 void
enable_debug(const char * shader_name)737 brw_generator::enable_debug(const char *shader_name)
738 {
739 debug_flag = true;
740 this->shader_name = shader_name;
741 }
742
743 static gfx12_systolic_depth
translate_systolic_depth(unsigned d)744 translate_systolic_depth(unsigned d)
745 {
746 /* Could also return (ffs(d) - 1) & 3. */
747 switch (d) {
748 case 2: return BRW_SYSTOLIC_DEPTH_2;
749 case 4: return BRW_SYSTOLIC_DEPTH_4;
750 case 8: return BRW_SYSTOLIC_DEPTH_8;
751 case 16: return BRW_SYSTOLIC_DEPTH_16;
752 default: unreachable("Invalid systolic depth.");
753 }
754 }
755
756 int
generate_code(const cfg_t * cfg,int dispatch_width,struct brw_shader_stats shader_stats,const brw::performance & perf,struct brw_compile_stats * stats,unsigned max_polygons)757 brw_generator::generate_code(const cfg_t *cfg, int dispatch_width,
758 struct brw_shader_stats shader_stats,
759 const brw::performance &perf,
760 struct brw_compile_stats *stats,
761 unsigned max_polygons)
762 {
763 /* align to 64 byte boundary. */
764 brw_realign(p, 64);
765
766 this->dispatch_width = dispatch_width;
767
768 int start_offset = p->next_insn_offset;
769
770 int loop_count = 0, send_count = 0, nop_count = 0, sync_nop_count = 0;
771 bool is_accum_used = false;
772
773 struct disasm_info *disasm_info = disasm_initialize(p->isa, cfg);
774
775 fs_inst *prev_inst = NULL;
776 foreach_block_and_inst (block, fs_inst, inst, cfg) {
777 if (inst->opcode == SHADER_OPCODE_UNDEF)
778 continue;
779
780 struct brw_reg src[4], dst;
781 unsigned int last_insn_offset = p->next_insn_offset;
782 bool multiple_instructions_emitted = false;
783 tgl_swsb swsb = inst->sched;
784
785 /* From the Broadwell PRM, Volume 7, "3D-Media-GPGPU", in the
786 * "Register Region Restrictions" section: for BDW, SKL:
787 *
788 * "A POW/FDIV operation must not be followed by an instruction
789 * that requires two destination registers."
790 *
791 * The documentation is often lacking annotations for Atom parts,
792 * and empirically this affects CHV as well.
793 */
794 if (devinfo->ver <= 9 &&
795 p->nr_insn > 1 &&
796 brw_eu_inst_opcode(p->isa, brw_last_inst) == BRW_OPCODE_MATH &&
797 brw_eu_inst_math_function(devinfo, brw_last_inst) == BRW_MATH_FUNCTION_POW &&
798 inst->dst.component_size(inst->exec_size) > REG_SIZE) {
799 brw_NOP(p);
800 last_insn_offset = p->next_insn_offset;
801
802 /* In order to avoid spurious instruction count differences when the
803 * instruction schedule changes, keep track of the number of inserted
804 * NOPs.
805 */
806 nop_count++;
807 }
808
809 /* Wa_14010017096:
810 *
811 * Clear accumulator register before end of thread.
812 */
813 if (inst->eot && is_accum_used &&
814 intel_needs_workaround(devinfo, 14010017096)) {
815 brw_set_default_exec_size(p, BRW_EXECUTE_16);
816 brw_set_default_group(p, 0);
817 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
818 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
819 brw_set_default_flag_reg(p, 0, 0);
820 brw_set_default_swsb(p, tgl_swsb_src_dep(swsb));
821 brw_MOV(p, brw_acc_reg(8), brw_imm_f(0.0f));
822 last_insn_offset = p->next_insn_offset;
823 swsb = tgl_swsb_dst_dep(swsb, 1);
824 }
825
826 if (!is_accum_used && !inst->eot) {
827 is_accum_used = inst->writes_accumulator_implicitly(devinfo) ||
828 inst->dst.is_accumulator();
829 }
830
831 /* Wa_14013672992:
832 *
833 * Always use @1 SWSB for EOT.
834 */
835 if (inst->eot && intel_needs_workaround(devinfo, 14013672992)) {
836 if (tgl_swsb_src_dep(swsb).mode) {
837 brw_set_default_exec_size(p, BRW_EXECUTE_1);
838 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
839 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
840 brw_set_default_flag_reg(p, 0, 0);
841 brw_set_default_swsb(p, tgl_swsb_src_dep(swsb));
842 brw_SYNC(p, TGL_SYNC_NOP);
843 last_insn_offset = p->next_insn_offset;
844 }
845
846 swsb = tgl_swsb_dst_dep(swsb, 1);
847 }
848
849 if (unlikely(debug_flag))
850 disasm_annotate(disasm_info, inst, p->next_insn_offset);
851
852 if (devinfo->ver >= 20 && inst->group % 8 != 0) {
853 assert(inst->force_writemask_all);
854 assert(!inst->predicate && !inst->conditional_mod);
855 assert(!inst->writes_accumulator_implicitly(devinfo) &&
856 !inst->reads_accumulator_implicitly());
857 assert(inst->opcode != SHADER_OPCODE_SEL_EXEC);
858 brw_set_default_group(p, 0);
859 } else {
860 brw_set_default_group(p, inst->group);
861 }
862
863 /* For SEND_GATHER, the payload sources are represented inside the
864 * scalar register in src[2], so we can skip them.
865 */
866 const unsigned num_sources =
867 inst->opcode == SHADER_OPCODE_SEND_GATHER ? 3 : inst->sources;
868 assert(num_sources <= ARRAY_SIZE(src));
869
870 for (unsigned int i = 0; i < num_sources; i++) {
871 src[i] = normalize_brw_reg_for_encoding(&inst->src[i]);
872 /* The accumulator result appears to get used for the
873 * conditional modifier generation. When negating a UD
874 * value, there is a 33rd bit generated for the sign in the
875 * accumulator value, so now you can't check, for example,
876 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
877 */
878 assert(!inst->conditional_mod ||
879 inst->src[i].type != BRW_TYPE_UD ||
880 !inst->src[i].negate);
881 }
882 dst = normalize_brw_reg_for_encoding(&inst->dst);
883
884 brw_set_default_access_mode(p, BRW_ALIGN_1);
885 brw_set_default_predicate_control(p, inst->predicate);
886 brw_set_default_predicate_inverse(p, inst->predicate_inverse);
887 /* On gfx7 and above, hardware automatically adds the group onto the
888 * flag subregister number.
889 */
890 const unsigned flag_subreg = inst->flag_subreg;
891 brw_set_default_flag_reg(p, flag_subreg / 2, flag_subreg % 2);
892 brw_set_default_saturate(p, inst->saturate);
893 brw_set_default_mask_control(p, inst->force_writemask_all);
894 if (devinfo->ver >= 20 && inst->writes_accumulator) {
895 assert(inst->dst.is_accumulator() ||
896 inst->opcode == BRW_OPCODE_ADDC ||
897 inst->opcode == BRW_OPCODE_MACH ||
898 inst->opcode == BRW_OPCODE_SUBB);
899 } else {
900 brw_set_default_acc_write_control(p, inst->writes_accumulator);
901 }
902 brw_set_default_swsb(p, swsb);
903
904 unsigned exec_size = inst->exec_size;
905
906 brw_set_default_exec_size(p, cvt(exec_size) - 1);
907
908 assert(inst->force_writemask_all || inst->exec_size >= 4);
909 assert(inst->force_writemask_all || inst->group % inst->exec_size == 0);
910 assert(inst->mlen <= BRW_MAX_MSG_LENGTH * reg_unit(devinfo));
911
912 switch (inst->opcode) {
913 case BRW_OPCODE_NOP:
914 brw_NOP(p);
915 break;
916 case BRW_OPCODE_SYNC:
917 assert(src[0].file == IMM);
918 brw_SYNC(p, tgl_sync_function(src[0].ud));
919
920 if (tgl_sync_function(src[0].ud) == TGL_SYNC_NOP)
921 ++sync_nop_count;
922
923 break;
924 case BRW_OPCODE_MOV:
925 brw_MOV(p, dst, src[0]);
926 break;
927 case BRW_OPCODE_ADD:
928 brw_ADD(p, dst, src[0], src[1]);
929 break;
930 case BRW_OPCODE_MUL:
931 brw_MUL(p, dst, src[0], src[1]);
932 break;
933 case BRW_OPCODE_AVG:
934 brw_AVG(p, dst, src[0], src[1]);
935 break;
936 case BRW_OPCODE_MACH:
937 brw_MACH(p, dst, src[0], src[1]);
938 break;
939
940 case BRW_OPCODE_DP4A:
941 assert(devinfo->ver >= 12);
942 brw_DP4A(p, dst, src[0], src[1], src[2]);
943 break;
944
945 case BRW_OPCODE_LINE:
946 brw_LINE(p, dst, src[0], src[1]);
947 break;
948
949 case BRW_OPCODE_DPAS:
950 assert(devinfo->verx10 >= 125);
951 brw_DPAS(p, translate_systolic_depth(inst->sdepth), inst->rcount,
952 dst, src[0], src[1], src[2]);
953 break;
954
955 case BRW_OPCODE_MAD:
956 if (devinfo->ver < 10)
957 brw_set_default_access_mode(p, BRW_ALIGN_16);
958 brw_MAD(p, dst, src[0], src[1], src[2]);
959 break;
960
961 case BRW_OPCODE_LRP:
962 assert(devinfo->ver <= 10);
963 if (devinfo->ver < 10)
964 brw_set_default_access_mode(p, BRW_ALIGN_16);
965 brw_LRP(p, dst, src[0], src[1], src[2]);
966 break;
967
968 case BRW_OPCODE_ADD3:
969 assert(devinfo->verx10 >= 125);
970 brw_ADD3(p, dst, src[0], src[1], src[2]);
971 break;
972
973 case BRW_OPCODE_FRC:
974 brw_FRC(p, dst, src[0]);
975 break;
976 case BRW_OPCODE_RNDD:
977 brw_RNDD(p, dst, src[0]);
978 break;
979 case BRW_OPCODE_RNDE:
980 brw_RNDE(p, dst, src[0]);
981 break;
982 case BRW_OPCODE_RNDZ:
983 brw_RNDZ(p, dst, src[0]);
984 break;
985
986 case BRW_OPCODE_AND:
987 brw_AND(p, dst, src[0], src[1]);
988 break;
989 case BRW_OPCODE_OR:
990 brw_OR(p, dst, src[0], src[1]);
991 break;
992 case BRW_OPCODE_XOR:
993 brw_XOR(p, dst, src[0], src[1]);
994 break;
995 case BRW_OPCODE_NOT:
996 brw_NOT(p, dst, src[0]);
997 break;
998 case BRW_OPCODE_ASR:
999 brw_ASR(p, dst, src[0], src[1]);
1000 break;
1001 case BRW_OPCODE_SHR:
1002 brw_SHR(p, dst, src[0], src[1]);
1003 break;
1004 case BRW_OPCODE_SHL:
1005 brw_SHL(p, dst, src[0], src[1]);
1006 break;
1007 case BRW_OPCODE_ROL:
1008 assert(devinfo->ver >= 11);
1009 assert(src[0].type == dst.type);
1010 brw_ROL(p, dst, src[0], src[1]);
1011 break;
1012 case BRW_OPCODE_ROR:
1013 assert(devinfo->ver >= 11);
1014 assert(src[0].type == dst.type);
1015 brw_ROR(p, dst, src[0], src[1]);
1016 break;
1017 case BRW_OPCODE_CMP:
1018 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1019 break;
1020 case BRW_OPCODE_CMPN:
1021 brw_CMPN(p, dst, inst->conditional_mod, src[0], src[1]);
1022 break;
1023 case BRW_OPCODE_SEL:
1024 brw_SEL(p, dst, src[0], src[1]);
1025 break;
1026 case BRW_OPCODE_CSEL:
1027 if (devinfo->ver < 10)
1028 brw_set_default_access_mode(p, BRW_ALIGN_16);
1029 brw_CSEL(p, dst, src[0], src[1], src[2]);
1030 break;
1031 case BRW_OPCODE_BFREV:
1032 brw_BFREV(p, retype(dst, BRW_TYPE_UD), retype(src[0], BRW_TYPE_UD));
1033 break;
1034 case BRW_OPCODE_FBH:
1035 brw_FBH(p, retype(dst, src[0].type), src[0]);
1036 break;
1037 case BRW_OPCODE_FBL:
1038 brw_FBL(p, retype(dst, BRW_TYPE_UD), retype(src[0], BRW_TYPE_UD));
1039 break;
1040 case BRW_OPCODE_LZD:
1041 brw_LZD(p, dst, src[0]);
1042 break;
1043 case BRW_OPCODE_CBIT:
1044 brw_CBIT(p, retype(dst, BRW_TYPE_UD), retype(src[0], BRW_TYPE_UD));
1045 break;
1046 case BRW_OPCODE_ADDC:
1047 brw_ADDC(p, dst, src[0], src[1]);
1048 break;
1049 case BRW_OPCODE_SUBB:
1050 brw_SUBB(p, dst, src[0], src[1]);
1051 break;
1052 case BRW_OPCODE_MAC:
1053 brw_MAC(p, dst, src[0], src[1]);
1054 break;
1055
1056 case BRW_OPCODE_BFE:
1057 if (devinfo->ver < 10)
1058 brw_set_default_access_mode(p, BRW_ALIGN_16);
1059 brw_BFE(p, dst, src[0], src[1], src[2]);
1060 break;
1061
1062 case BRW_OPCODE_BFI1:
1063 brw_BFI1(p, dst, src[0], src[1]);
1064 break;
1065 case BRW_OPCODE_BFI2:
1066 if (devinfo->ver < 10)
1067 brw_set_default_access_mode(p, BRW_ALIGN_16);
1068 brw_BFI2(p, dst, src[0], src[1], src[2]);
1069 break;
1070
1071 case BRW_OPCODE_IF:
1072 brw_IF(p, brw_get_default_exec_size(p));
1073 break;
1074
1075 case BRW_OPCODE_ELSE:
1076 brw_ELSE(p);
1077 break;
1078 case BRW_OPCODE_ENDIF:
1079 brw_ENDIF(p);
1080 break;
1081
1082 case BRW_OPCODE_DO:
1083 brw_DO(p, brw_get_default_exec_size(p));
1084 break;
1085
1086 case BRW_OPCODE_BREAK:
1087 brw_BREAK(p);
1088 break;
1089 case BRW_OPCODE_CONTINUE:
1090 brw_CONT(p);
1091 break;
1092
1093 case BRW_OPCODE_WHILE:
1094 /* Workaround for an issue with branch prediction for WHILE
1095 * instructions that may lead to misrendering or GPU hangs.
1096 * See HSDs 22020521218 and 16026360541.
1097 */
1098 if (devinfo->ver >= 20 && prev_inst &&
1099 unlikely(prev_inst->is_control_flow()))
1100 brw_NOP(p);
1101
1102 brw_WHILE(p);
1103 loop_count++;
1104 break;
1105
1106 case SHADER_OPCODE_RCP:
1107 case SHADER_OPCODE_RSQ:
1108 case SHADER_OPCODE_SQRT:
1109 case SHADER_OPCODE_EXP2:
1110 case SHADER_OPCODE_LOG2:
1111 case SHADER_OPCODE_SIN:
1112 case SHADER_OPCODE_COS:
1113 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1114 assert(inst->mlen == 0);
1115 gfx6_math(p, dst, brw_math_function(inst->opcode),
1116 src[0], retype(brw_null_reg(), src[0].type));
1117 break;
1118 case SHADER_OPCODE_INT_QUOTIENT:
1119 case SHADER_OPCODE_INT_REMAINDER:
1120 case SHADER_OPCODE_POW:
1121 assert(devinfo->verx10 < 125);
1122 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1123 assert(inst->mlen == 0);
1124 assert(inst->opcode == SHADER_OPCODE_POW || inst->exec_size == 8);
1125 gfx6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
1126 break;
1127 case BRW_OPCODE_PLN:
1128 /* PLN reads:
1129 * / in SIMD16 \
1130 * -----------------------------------
1131 * | src1+0 | src1+1 | src1+2 | src1+3 |
1132 * |-----------------------------------|
1133 * |(x0, x1)|(y0, y1)|(x2, x3)|(y2, y3)|
1134 * -----------------------------------
1135 */
1136 brw_PLN(p, dst, src[0], src[1]);
1137 break;
1138 case FS_OPCODE_PIXEL_X:
1139 assert(src[0].type == BRW_TYPE_UW);
1140 assert(src[1].type == BRW_TYPE_UW);
1141 src[0].subnr = 0 * brw_type_size_bytes(src[0].type);
1142 if (src[1].file == IMM) {
1143 assert(src[1].ud == 0);
1144 brw_MOV(p, dst, stride(src[0], 8, 4, 1));
1145 } else {
1146 /* Coarse pixel case */
1147 brw_ADD(p, dst, stride(src[0], 8, 4, 1), src[1]);
1148 }
1149 break;
1150 case FS_OPCODE_PIXEL_Y:
1151 assert(src[0].type == BRW_TYPE_UW);
1152 assert(src[1].type == BRW_TYPE_UW);
1153 src[0].subnr = 4 * brw_type_size_bytes(src[0].type);
1154 if (src[1].file == IMM) {
1155 assert(src[1].ud == 0);
1156 brw_MOV(p, dst, stride(src[0], 8, 4, 1));
1157 } else {
1158 /* Coarse pixel case */
1159 brw_ADD(p, dst, stride(src[0], 8, 4, 1), src[1]);
1160 }
1161 break;
1162
1163 case SHADER_OPCODE_SEND:
1164 case SHADER_OPCODE_SEND_GATHER:
1165 generate_send(inst, dst, src[0], src[1], src[2],
1166 inst->ex_mlen > 0 ? src[3] : brw_null_reg());
1167 send_count++;
1168 break;
1169
1170 case FS_OPCODE_DDX_COARSE:
1171 case FS_OPCODE_DDX_FINE:
1172 generate_ddx(inst, dst, src[0]);
1173 break;
1174 case FS_OPCODE_DDY_COARSE:
1175 case FS_OPCODE_DDY_FINE:
1176 generate_ddy(inst, dst, src[0]);
1177 break;
1178
1179 case SHADER_OPCODE_SCRATCH_HEADER:
1180 generate_scratch_header(inst, dst, src[0]);
1181 break;
1182
1183 case SHADER_OPCODE_MOV_INDIRECT:
1184 generate_mov_indirect(inst, dst, src[0], src[1]);
1185 break;
1186
1187 case SHADER_OPCODE_MOV_RELOC_IMM:
1188 assert(src[0].file == IMM);
1189 assert(src[1].file == IMM);
1190 brw_MOV_reloc_imm(p, dst, dst.type, src[0].ud, src[1].ud);
1191 break;
1192
1193 case BRW_OPCODE_HALT:
1194 generate_halt(inst);
1195 break;
1196
1197 case SHADER_OPCODE_INTERLOCK:
1198 case SHADER_OPCODE_MEMORY_FENCE: {
1199 assert(src[1].file == IMM);
1200 assert(src[2].file == IMM);
1201
1202 const enum opcode send_op = inst->opcode == SHADER_OPCODE_INTERLOCK ?
1203 BRW_OPCODE_SENDC : BRW_OPCODE_SEND;
1204
1205 brw_memory_fence(p, dst, src[0], send_op,
1206 brw_message_target(inst->sfid),
1207 inst->desc,
1208 /* commit_enable */ src[1].ud,
1209 /* bti */ src[2].ud);
1210 send_count++;
1211 break;
1212 }
1213
1214 case FS_OPCODE_SCHEDULING_FENCE:
1215 if (inst->sources == 0 && swsb.regdist == 0 &&
1216 swsb.mode == TGL_SBID_NULL) {
1217 if (unlikely(debug_flag))
1218 disasm_info->use_tail = true;
1219 break;
1220 }
1221
1222 if (devinfo->ver >= 12) {
1223 /* Use the available SWSB information to stall. A single SYNC is
1224 * sufficient since if there were multiple dependencies, the
1225 * scoreboard algorithm already injected other SYNCs before this
1226 * instruction.
1227 */
1228 brw_SYNC(p, TGL_SYNC_NOP);
1229 } else {
1230 for (unsigned i = 0; i < inst->sources; i++) {
1231 /* Emit a MOV to force a stall until the instruction producing the
1232 * registers finishes.
1233 */
1234 brw_MOV(p, retype(brw_null_reg(), BRW_TYPE_UW),
1235 retype(src[i], BRW_TYPE_UW));
1236 }
1237
1238 if (inst->sources > 1)
1239 multiple_instructions_emitted = true;
1240 }
1241
1242 break;
1243
1244 case SHADER_OPCODE_FIND_LIVE_CHANNEL:
1245 case SHADER_OPCODE_FIND_LAST_LIVE_CHANNEL:
1246 case SHADER_OPCODE_LOAD_LIVE_CHANNELS:
1247 unreachable("Should be lowered by lower_find_live_channel()");
1248 break;
1249
1250 case FS_OPCODE_LOAD_LIVE_CHANNELS: {
1251 assert(inst->force_writemask_all && inst->group == 0);
1252 assert(inst->dst.file == BAD_FILE);
1253 brw_set_default_exec_size(p, BRW_EXECUTE_1);
1254 brw_set_default_swsb(p, tgl_swsb_dst_dep(swsb, 1));
1255 brw_MOV(p, retype(brw_flag_subreg(inst->flag_subreg), BRW_TYPE_UD),
1256 retype(brw_mask_reg(0), BRW_TYPE_UD));
1257 /* Reading certain ARF registers (like 'ce', the mask register) on
1258 * Gfx12+ requires requires a dependency on all pipes on the read
1259 * instruction and the next instructions
1260 */
1261 if (devinfo->ver >= 12)
1262 brw_SYNC(p, TGL_SYNC_NOP);
1263 break;
1264 }
1265 case SHADER_OPCODE_BROADCAST:
1266 assert(inst->force_writemask_all);
1267 brw_broadcast(p, dst, src[0], src[1]);
1268 break;
1269
1270 case SHADER_OPCODE_SHUFFLE:
1271 generate_shuffle(inst, dst, src[0], src[1]);
1272 break;
1273
1274 case SHADER_OPCODE_SEL_EXEC:
1275 assert(inst->force_writemask_all);
1276 assert(devinfo->has_64bit_float || brw_type_size_bytes(dst.type) <= 4);
1277 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1278 brw_MOV(p, dst, src[1]);
1279 brw_set_default_mask_control(p, BRW_MASK_ENABLE);
1280 brw_set_default_swsb(p, tgl_swsb_null());
1281 brw_MOV(p, dst, src[0]);
1282 break;
1283
1284 case SHADER_OPCODE_QUAD_SWIZZLE:
1285 assert(src[1].file == IMM);
1286 assert(src[1].type == BRW_TYPE_UD);
1287 generate_quad_swizzle(inst, dst, src[0], src[1].ud);
1288 break;
1289
1290 case SHADER_OPCODE_CLUSTER_BROADCAST: {
1291 assert((!intel_device_info_is_9lp(devinfo) &&
1292 devinfo->has_64bit_float) || brw_type_size_bytes(src[0].type) <= 4);
1293 assert(!src[0].negate && !src[0].abs);
1294 assert(src[1].file == IMM);
1295 assert(src[1].type == BRW_TYPE_UD);
1296 assert(src[2].file == IMM);
1297 assert(src[2].type == BRW_TYPE_UD);
1298 const unsigned component = src[1].ud;
1299 const unsigned cluster_size = src[2].ud;
1300 assert(inst->src[0].file != ARF);
1301
1302 unsigned s;
1303 if (inst->src[0].file == FIXED_GRF) {
1304 s = inst->src[0].hstride ? 1 << (inst->src[0].hstride - 1) : 0;
1305 } else {
1306 s = inst->src[0].stride;
1307 }
1308 unsigned vstride = cluster_size * s;
1309 unsigned width = cluster_size;
1310
1311 /* The maximum exec_size is 32, but the maximum width is only 16. */
1312 if (inst->exec_size == width) {
1313 vstride = 0;
1314 width = 1;
1315 }
1316
1317 struct brw_reg strided = stride(suboffset(src[0], component * s),
1318 vstride, width, 0);
1319 brw_MOV(p, dst, strided);
1320 break;
1321 }
1322
1323 case SHADER_OPCODE_HALT_TARGET:
1324 /* This is the place where the final HALT needs to be inserted if
1325 * we've emitted any discards. If not, this will emit no code.
1326 */
1327 if (!patch_halt_jumps()) {
1328 if (unlikely(debug_flag)) {
1329 disasm_info->use_tail = true;
1330 }
1331 }
1332 break;
1333
1334 case SHADER_OPCODE_BARRIER:
1335 generate_barrier(inst, src[0]);
1336 send_count++;
1337 break;
1338
1339 case SHADER_OPCODE_RND_MODE: {
1340 assert(src[0].file == IMM);
1341 /*
1342 * Changes the floating point rounding mode updating the control
1343 * register field defined at cr0.0[5-6] bits.
1344 */
1345 enum brw_rnd_mode mode =
1346 (enum brw_rnd_mode) (src[0].d << BRW_CR0_RND_MODE_SHIFT);
1347 brw_float_controls_mode(p, mode, BRW_CR0_RND_MODE_MASK);
1348 }
1349 break;
1350
1351 case SHADER_OPCODE_FLOAT_CONTROL_MODE:
1352 assert(src[0].file == IMM);
1353 assert(src[1].file == IMM);
1354 brw_float_controls_mode(p, src[0].d, src[1].d);
1355 break;
1356
1357 case SHADER_OPCODE_READ_ARCH_REG:
1358 if (devinfo->ver >= 12) {
1359 /* There is a SWSB restriction that requires that any time sr0 is
1360 * accessed both the instruction doing the access and the next one
1361 * have SWSB set to RegDist(1).
1362 */
1363 if (brw_get_default_swsb(p).mode != TGL_SBID_NULL)
1364 brw_SYNC(p, TGL_SYNC_NOP);
1365 brw_set_default_swsb(p, tgl_swsb_regdist(1));
1366 brw_MOV(p, dst, src[0]);
1367 brw_set_default_swsb(p, tgl_swsb_regdist(1));
1368 brw_AND(p, dst, dst, brw_imm_ud(0xffffffff));
1369 } else {
1370 brw_MOV(p, dst, src[0]);
1371 }
1372 break;
1373
1374 default:
1375 unreachable("Unsupported opcode");
1376
1377 case SHADER_OPCODE_LOAD_PAYLOAD:
1378 unreachable("Should be lowered by lower_load_payload()");
1379 }
1380 prev_inst = inst;
1381
1382 if (multiple_instructions_emitted)
1383 continue;
1384
1385 if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
1386 assert(p->next_insn_offset == last_insn_offset + 16 ||
1387 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
1388 "emitting more than 1 instruction");
1389
1390 brw_eu_inst *last = &p->store[last_insn_offset / 16];
1391
1392 if (inst->conditional_mod)
1393 brw_eu_inst_set_cond_modifier(p->devinfo, last, inst->conditional_mod);
1394 if (devinfo->ver < 12) {
1395 brw_eu_inst_set_no_dd_clear(p->devinfo, last, inst->no_dd_clear);
1396 brw_eu_inst_set_no_dd_check(p->devinfo, last, inst->no_dd_check);
1397 }
1398 }
1399
1400 /* When enabled, insert sync NOP after every instruction and make sure
1401 * that current instruction depends on the previous instruction.
1402 */
1403 if (INTEL_DEBUG(DEBUG_SWSB_STALL) && devinfo->ver >= 12) {
1404 brw_set_default_swsb(p, tgl_swsb_regdist(1));
1405 brw_SYNC(p, TGL_SYNC_NOP);
1406 }
1407 }
1408
1409 brw_set_uip_jip(p, start_offset);
1410
1411 /* end of program sentinel */
1412 disasm_new_inst_group(disasm_info, p->next_insn_offset);
1413
1414 /* `send_count` explicitly does not include spills or fills, as we'd
1415 * like to use it as a metric for intentional memory access or other
1416 * shared function use. Otherwise, subtle changes to scheduling or
1417 * register allocation could cause it to fluctuate wildly - and that
1418 * effect is already counted in spill/fill counts.
1419 */
1420 send_count -= shader_stats.spill_count;
1421 send_count -= shader_stats.fill_count;
1422
1423 #ifndef NDEBUG
1424 bool validated =
1425 #else
1426 if (unlikely(debug_flag))
1427 #endif
1428 brw_validate_instructions(&compiler->isa, p->store,
1429 start_offset,
1430 p->next_insn_offset,
1431 disasm_info);
1432
1433 int before_size = p->next_insn_offset - start_offset;
1434 brw_compact_instructions(p, start_offset, disasm_info);
1435 int after_size = p->next_insn_offset - start_offset;
1436
1437 bool dump_shader_bin = brw_should_dump_shader_bin();
1438 unsigned char sha1[21];
1439 char sha1buf[41];
1440
1441 if (unlikely(debug_flag || dump_shader_bin)) {
1442 _mesa_sha1_compute(p->store + start_offset / sizeof(brw_eu_inst),
1443 after_size, sha1);
1444 _mesa_sha1_format(sha1buf, sha1);
1445 }
1446
1447 if (unlikely(dump_shader_bin))
1448 brw_dump_shader_bin(p->store, start_offset, p->next_insn_offset,
1449 sha1buf);
1450
1451 if (unlikely(debug_flag)) {
1452 fprintf(stderr, "Native code for %s (src_hash 0x%08x) (sha1 %s)\n"
1453 "SIMD%d shader: %d instructions. %d loops. %u cycles. "
1454 "%d:%d spills:fills, %u sends, "
1455 "scheduled with mode %s. "
1456 "Promoted %u constants. "
1457 "Non-SSA regs (after NIR): %u. "
1458 "Compacted %d to %d bytes (%.0f%%)\n",
1459 shader_name, params->source_hash, sha1buf,
1460 dispatch_width,
1461 before_size / 16 - nop_count - sync_nop_count,
1462 loop_count, perf.latency,
1463 shader_stats.spill_count,
1464 shader_stats.fill_count,
1465 send_count,
1466 shader_stats.scheduler_mode,
1467 shader_stats.promoted_constants,
1468 shader_stats.non_ssa_registers_after_nir,
1469 before_size, after_size,
1470 100.0f * (before_size - after_size) / before_size);
1471
1472 /* overriding the shader makes disasm_info invalid */
1473 if (!brw_try_override_assembly(p, start_offset, sha1buf)) {
1474 dump_assembly(p->store, start_offset, p->next_insn_offset,
1475 disasm_info, perf.block_latency);
1476 } else {
1477 fprintf(stderr, "Successfully overrode shader with sha1 %s\n\n", sha1buf);
1478 }
1479 }
1480 ralloc_free(disasm_info);
1481 #ifndef NDEBUG
1482 if (!validated && !debug_flag) {
1483 fprintf(stderr,
1484 "Validation failed. Rerun with INTEL_DEBUG=shaders to get more information.\n");
1485 }
1486 #endif
1487 assert(validated);
1488
1489 brw_shader_debug_log(compiler, params->log_data,
1490 "%s SIMD%d shader: %d inst, %d loops, %u cycles, "
1491 "%d:%d spills:fills, %u sends, "
1492 "scheduled with mode %s, "
1493 "Promoted %u constants, "
1494 "compacted %d to %d bytes.\n",
1495 _mesa_shader_stage_to_abbrev(stage),
1496 dispatch_width,
1497 before_size / 16 - nop_count - sync_nop_count,
1498 loop_count, perf.latency,
1499 shader_stats.spill_count,
1500 shader_stats.fill_count,
1501 send_count,
1502 shader_stats.scheduler_mode,
1503 shader_stats.promoted_constants,
1504 before_size, after_size);
1505 if (stats) {
1506 stats->dispatch_width = dispatch_width;
1507 stats->max_polygons = max_polygons;
1508 stats->max_dispatch_width = dispatch_width;
1509 stats->instructions = before_size / 16 - nop_count - sync_nop_count;
1510 stats->sends = send_count;
1511 stats->loops = loop_count;
1512 stats->cycles = perf.latency;
1513 stats->spills = shader_stats.spill_count;
1514 stats->fills = shader_stats.fill_count;
1515 stats->max_live_registers = shader_stats.max_register_pressure;
1516 stats->non_ssa_registers_after_nir = shader_stats.non_ssa_registers_after_nir;
1517 }
1518
1519 return start_offset;
1520 }
1521
1522 void
add_const_data(void * data,unsigned size)1523 brw_generator::add_const_data(void *data, unsigned size)
1524 {
1525 assert(prog_data->const_data_size == 0);
1526 if (size > 0) {
1527 prog_data->const_data_size = size;
1528 prog_data->const_data_offset = brw_append_data(p, data, size, 32);
1529 }
1530 }
1531
1532 void
add_resume_sbt(unsigned num_resume_shaders,uint64_t * sbt)1533 brw_generator::add_resume_sbt(unsigned num_resume_shaders, uint64_t *sbt)
1534 {
1535 assert(brw_shader_stage_is_bindless(stage));
1536 struct brw_bs_prog_data *bs_prog_data = brw_bs_prog_data(prog_data);
1537 if (num_resume_shaders > 0) {
1538 bs_prog_data->resume_sbt_offset =
1539 brw_append_data(p, sbt, num_resume_shaders * sizeof(uint64_t), 32);
1540 for (unsigned i = 0; i < num_resume_shaders; i++) {
1541 size_t offset = bs_prog_data->resume_sbt_offset + i * sizeof(*sbt);
1542 assert(offset <= UINT32_MAX);
1543 brw_add_reloc(p, BRW_SHADER_RELOC_SHADER_START_OFFSET,
1544 BRW_SHADER_RELOC_TYPE_U32,
1545 (uint32_t)offset, (uint32_t)sbt[i]);
1546 }
1547 }
1548 }
1549
1550 const unsigned *
get_assembly()1551 brw_generator::get_assembly()
1552 {
1553 prog_data->relocs = brw_get_shader_relocs(p, &prog_data->num_relocs);
1554
1555 return brw_get_program(p, &prog_data->program_size);
1556 }
1557