1 /*
2 * Copyright 2024 Intel Corporation
3 * SPDX-License-Identifier: MIT
4 */
5
6 #include <gtest/gtest.h>
7 #include "brw_fs.h"
8 #include "brw_builder.h"
9 #include "brw_cfg.h"
10
11 using namespace brw;
12
13 class cse_test : public ::testing::Test {
14 protected:
15 cse_test();
16 ~cse_test() override;
17
18 struct brw_compiler *compiler;
19 struct brw_compile_params params;
20 struct intel_device_info *devinfo;
21 void *ctx;
22 struct brw_wm_prog_data *prog_data;
23 struct gl_shader_program *shader_prog;
24 fs_visitor *v;
25 brw_builder bld;
26 };
27
cse_test()28 cse_test::cse_test()
29 : bld(NULL, 0)
30 {
31 ctx = ralloc_context(NULL);
32 compiler = rzalloc(ctx, struct brw_compiler);
33 devinfo = rzalloc(ctx, struct intel_device_info);
34 compiler->devinfo = devinfo;
35
36 params = {};
37 params.mem_ctx = ctx;
38
39 prog_data = ralloc(ctx, struct brw_wm_prog_data);
40 nir_shader *shader =
41 nir_shader_create(ctx, MESA_SHADER_FRAGMENT, NULL, NULL);
42
43 v = new fs_visitor(compiler, ¶ms, NULL, &prog_data->base, shader,
44 16, false, false);
45
46 bld = brw_builder(v).at_end();
47
48 devinfo->verx10 = 125;
49 devinfo->ver = devinfo->verx10 / 10;
50 }
51
~cse_test()52 cse_test::~cse_test()
53 {
54 delete v;
55 v = NULL;
56
57 ralloc_free(ctx);
58 ctx = NULL;
59 }
60
61
62 static fs_inst *
instruction(bblock_t * block,int num)63 instruction(bblock_t *block, int num)
64 {
65 fs_inst *inst = (fs_inst *)block->start();
66 for (int i = 0; i < num; i++) {
67 inst = (fs_inst *)inst->next;
68 }
69 return inst;
70 }
71
72 static bool
cse(fs_visitor * v)73 cse(fs_visitor *v)
74 {
75 const bool print = false;
76
77 if (print) {
78 fprintf(stderr, "= Before =\n");
79 v->cfg->dump();
80 }
81
82 bool ret = brw_opt_cse_defs(*v);
83
84 if (print) {
85 fprintf(stderr, "\n= After =\n");
86 v->cfg->dump();
87 }
88
89 return ret;
90 }
91
TEST_F(cse_test,add3_invalid)92 TEST_F(cse_test, add3_invalid)
93 {
94 brw_reg dst0 = bld.null_reg_d();
95 brw_reg src0 = bld.vgrf(BRW_TYPE_D);
96 brw_reg src1 = bld.vgrf(BRW_TYPE_D);
97 brw_reg src2 = bld.vgrf(BRW_TYPE_D);
98 brw_reg src3 = bld.vgrf(BRW_TYPE_D);
99
100 bld.ADD3(dst0, src0, src1, src2)
101 ->conditional_mod = BRW_CONDITIONAL_NZ;
102 bld.ADD3(dst0, src0, src1, src3)
103 ->conditional_mod = BRW_CONDITIONAL_NZ;
104
105 /* = Before =
106 *
107 * 0: add3.nz(16) null src0 src1 src2
108 * 1: add3.nz(16) null src0 src1 src3
109 *
110 * = After =
111 * Same
112 */
113
114 brw_calculate_cfg(*v);
115 bblock_t *block0 = v->cfg->blocks[0];
116
117 EXPECT_EQ(0, block0->start_ip);
118 EXPECT_EQ(1, block0->end_ip);
119
120 EXPECT_FALSE(cse(v));
121 EXPECT_EQ(0, block0->start_ip);
122 EXPECT_EQ(1, block0->end_ip);
123 EXPECT_EQ(BRW_OPCODE_ADD3, instruction(block0, 0)->opcode);
124 EXPECT_EQ(BRW_OPCODE_ADD3, instruction(block0, 1)->opcode);
125 }
126