1 /*
2 * Copyright 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdarg.h>
26 #include <stdio.h>
27 #include <inttypes.h>
28
29 #include "dev/intel_debug.h"
30 #include "genxml/genX_bits.h"
31 #include "util/log.h"
32 #include "util/u_math.h"
33
34 #include "isl.h"
35 #include "isl_gfx4.h"
36 #include "isl_gfx6.h"
37 #include "isl_gfx7.h"
38 #include "isl_gfx8.h"
39 #include "isl_gfx9.h"
40 #include "isl_gfx12.h"
41 #include "isl_gfx20.h"
42 #include "isl_priv.h"
43
44 isl_genX_declare_get_func(surf_fill_state_s)
isl_genX_declare_get_func(buffer_fill_state_s)45 isl_genX_declare_get_func(buffer_fill_state_s)
46 isl_genX_declare_get_func(emit_depth_stencil_hiz_s)
47 isl_genX_declare_get_func(null_fill_state_s)
48 isl_genX_declare_get_func(emit_cpb_control_s)
49
50 void
51 isl_memcpy_linear_to_tiled(uint32_t xt1, uint32_t xt2,
52 uint32_t yt1, uint32_t yt2,
53 char *dst, const char *src,
54 uint32_t dst_pitch, int32_t src_pitch,
55 bool has_swizzling,
56 enum isl_tiling tiling,
57 isl_memcpy_type copy_type)
58 {
59 #ifdef USE_SSE41
60 if (copy_type == ISL_MEMCPY_STREAMING_LOAD) {
61 _isl_memcpy_linear_to_tiled_sse41(
62 xt1, xt2, yt1, yt2, dst, src, dst_pitch, src_pitch, has_swizzling,
63 tiling, copy_type);
64 return;
65 }
66 #endif
67
68 _isl_memcpy_linear_to_tiled(
69 xt1, xt2, yt1, yt2, dst, src, dst_pitch, src_pitch, has_swizzling,
70 tiling, copy_type);
71 }
72
73 void
isl_memcpy_tiled_to_linear(uint32_t xt1,uint32_t xt2,uint32_t yt1,uint32_t yt2,char * dst,const char * src,int32_t dst_pitch,uint32_t src_pitch,bool has_swizzling,enum isl_tiling tiling,isl_memcpy_type copy_type)74 isl_memcpy_tiled_to_linear(uint32_t xt1, uint32_t xt2,
75 uint32_t yt1, uint32_t yt2,
76 char *dst, const char *src,
77 int32_t dst_pitch, uint32_t src_pitch,
78 bool has_swizzling,
79 enum isl_tiling tiling,
80 isl_memcpy_type copy_type)
81 {
82 #ifdef USE_SSE41
83 if (copy_type == ISL_MEMCPY_STREAMING_LOAD) {
84 _isl_memcpy_tiled_to_linear_sse41(
85 xt1, xt2, yt1, yt2, dst, src, dst_pitch, src_pitch, has_swizzling,
86 tiling, copy_type);
87 return;
88 }
89 #endif
90
91 _isl_memcpy_tiled_to_linear(
92 xt1, xt2, yt1, yt2, dst, src, dst_pitch, src_pitch, has_swizzling,
93 tiling, copy_type);
94 }
95
96 void PRINTFLIKE(3, 4) UNUSED
__isl_finishme(const char * file,int line,const char * fmt,...)97 __isl_finishme(const char *file, int line, const char *fmt, ...)
98 {
99 va_list ap;
100 char buf[512];
101
102 va_start(ap, fmt);
103 vsnprintf(buf, sizeof(buf), fmt, ap);
104 va_end(ap);
105
106 fprintf(stderr, "%s:%d: FINISHME: %s\n", file, line, buf);
107 }
108
109 static void
isl_device_setup_mocs(struct isl_device * dev)110 isl_device_setup_mocs(struct isl_device *dev)
111 {
112 dev->mocs.protected_mask = 0;
113
114 if (dev->info->ver >= 20) {
115 /* L3+L4=WB; BSpec: 71582 */
116 dev->mocs.internal = 1 << 1;
117 dev->mocs.external = 1 << 1;
118 dev->mocs.protected_mask = 1 << 0;
119 /* TODO: Setting to uncached
120 * WA 14018443005:
121 * Ensure that any compression-enabled resource from gfx memory subject
122 * to app recycling (e.g. OGL sparse resource backing memory or
123 * Vulkan heaps) is never PAT/MOCS'ed as L3:UC.
124 */
125 dev->mocs.blitter_dst = 1 << 1;
126 dev->mocs.blitter_src = 1 << 1;
127 } else if (dev->info->ver >= 12) {
128 if (intel_device_info_is_mtl_or_arl(dev->info)) {
129 /* Cached L3+L4; BSpec: 45101 */
130 dev->mocs.internal = 1 << 1;
131 /* Displayables cached to L3+L4:WT */
132 dev->mocs.external = 14 << 1;
133 /* Uncached - GO:Mem */
134 dev->mocs.uncached = 5 << 1;
135 /* TODO: XY_BLOCK_COPY_BLT don't mention what should be the L4 cache
136 * mode so for now it is setting L4 as uncached following what is
137 * asked for L3
138 */
139 dev->mocs.blitter_dst = 9 << 1;
140 dev->mocs.blitter_src = 9 << 1;
141 } else if (intel_device_info_is_dg2(dev->info)) {
142 /* L3CC=WB; BSpec: 45101 */
143 dev->mocs.internal = 3 << 1;
144 dev->mocs.external = 3 << 1;
145 /* UC - Coherent; GO:Memory */
146 dev->mocs.uncached = 1 << 1;
147
148 /* XY_BLOCK_COPY_BLT MOCS fields have programming notes which say:
149 *
150 * "Destination MOCS value, which is used to program MOCS index
151 * for writing to memory, should select a MOCS register having
152 * "L3 Cacheability Control" programmed as uncacheable(UC) and
153 * "Global GO" parameter set as GOMemory (pushes GO point to
154 * memory). The MOCS Register may have L3 Lookup programmed as
155 * UCL3LKDIS for better efficiency."
156 *
157 * The GO:Memory setting requires us to use MOCS 1 or 2. MOCS 2
158 * has LKUP set to 0 and is marked "Non-Coherent", which we assume
159 * is probably the "better efficiency" they mention...
160 *
161 * "Source MOCS value, which is used to program MOCS index for
162 * reading from memory, should select a MOCS register having
163 * "L3 Cacheability Control" programmed as uncacheable(UC).
164 * The MOCS Register may have L3 Lookup programmed as UCL3LKDIS
165 * for better efficiency."
166 *
167 * Any MOCS except 3 should work. We use MOCS 2...
168 */
169 dev->mocs.blitter_dst = 2 << 1;
170 dev->mocs.blitter_src = 2 << 1;
171 } else if (dev->info->platform == INTEL_PLATFORM_DG1) {
172 /* L3CC=WB */
173 dev->mocs.internal = 5 << 1;
174 /* Displayables on DG1 are free to cache in L3 since L3 is transient
175 * and flushed at bottom of each submission.
176 */
177 dev->mocs.external = 5 << 1;
178 /* UC */
179 dev->mocs.uncached = 1 << 1;
180 dev->mocs.blitter_dst = 1 << 1;
181 dev->mocs.blitter_src = 1 << 1;
182 } else {
183 /* TC=1/LLC Only, LeCC=1/UC, LRUM=0, L3CC=3/WB */
184 dev->mocs.external = 61 << 1;
185 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
186 dev->mocs.internal = 2 << 1;
187 /* Uncached */
188 dev->mocs.uncached = 3 << 1;
189
190 /* L1 - HDC:L1 + L3 + LLC */
191 dev->mocs.l1_hdc_l3_llc = 48 << 1;
192
193 /* Uncached */
194 dev->mocs.blitter_dst = 3 << 1;
195 dev->mocs.blitter_src = 3 << 1;
196 }
197 /* Protected is just an additional flag. */
198 dev->mocs.protected_mask = 1 << 0;
199 } else if (dev->info->ver >= 9) {
200 /* TC=LLC/eLLC, LeCC=PTE, LRUM=3, L3CC=WB */
201 dev->mocs.external = 1 << 1;
202 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
203 dev->mocs.internal = 2 << 1;
204 /* Uncached */
205 dev->mocs.uncached = (dev->info->ver >= 11 ? 3 : 0) << 1;
206 } else if (dev->info->ver >= 8) {
207 /* MEMORY_OBJECT_CONTROL_STATE:
208 * .MemoryTypeLLCeLLCCacheabilityControl = UCwithFenceifcoherentcycle,
209 * .TargetCache = L3DefertoPATforLLCeLLCselection,
210 * .AgeforQUADLRU = 0
211 */
212 dev->mocs.external = 0x18;
213 /* MEMORY_OBJECT_CONTROL_STATE:
214 * .MemoryTypeLLCeLLCCacheabilityControl = WB,
215 * .TargetCache = L3DefertoPATforLLCeLLCselection,
216 * .AgeforQUADLRU = 0
217 */
218 dev->mocs.internal = 0x78;
219 if (dev->info->platform == INTEL_PLATFORM_CHV) {
220 /* MEMORY_OBJECT_CONTROL_STATE:
221 * .MemoryType = UC,
222 * .TargetCache = NoCaching,
223 */
224 dev->mocs.uncached = 0;
225 } else {
226 /* MEMORY_OBJECT_CONTROL_STATE:
227 * .MemoryTypeLLCeLLCCacheabilityControl = UCUncacheable,
228 * .TargetCache = eLLCOnlywheneDRAMispresentelsegetsallocatedinLLC,
229 * .AgeforQUADLRU = 0
230 */
231 dev->mocs.uncached = 0x20;
232 }
233 } else if (dev->info->ver >= 7) {
234 if (dev->info->platform == INTEL_PLATFORM_HSW) {
235 /* MEMORY_OBJECT_CONTROL_STATE:
236 * .LLCeLLCCacheabilityControlLLCCC = 0,
237 * .L3CacheabilityControlL3CC = 1,
238 */
239 dev->mocs.internal = 1;
240 dev->mocs.external = 1;
241 /* MEMORY_OBJECT_CONTROL_STATE:
242 * .LLCeLLCCacheabilityControlLLCCC = 1,
243 * .L3CacheabilityControlL3CC = 0,
244 */
245 dev->mocs.uncached = 2;
246 } else {
247 /* MEMORY_OBJECT_CONTROL_STATE:
248 * .GraphicsDataTypeGFDT = 0,
249 * .LLCCacheabilityControlLLCCC = 0,
250 * .L3CacheabilityControlL3CC = 1,
251 */
252 dev->mocs.internal = 1;
253 dev->mocs.external = 1;
254 /* MEMORY_OBJECT_CONTROL_STATE:
255 * .GraphicsDataTypeGFDT = 0,
256 * .LLCCacheabilityControlLLCCC = 0,
257 * .L3CacheabilityControlL3CC = 0,
258 */
259 dev->mocs.uncached = 0;
260 }
261 } else {
262 dev->mocs.internal = 0;
263 dev->mocs.external = 0;
264 dev->mocs.uncached = 0;
265 }
266 }
267
268 /**
269 * Return an appropriate MOCS entry for the given usage flags.
270 */
271 uint32_t
isl_mocs(const struct isl_device * dev,isl_surf_usage_flags_t usage,bool external)272 isl_mocs(const struct isl_device *dev, isl_surf_usage_flags_t usage,
273 bool external)
274 {
275 uint32_t mask = (usage & ISL_SURF_USAGE_PROTECTED_BIT) ?
276 dev->mocs.protected_mask : 0;
277
278 if (usage & ISL_SURF_USAGE_BLITTER_SRC_BIT)
279 return dev->mocs.blitter_src | mask;
280
281 if (usage & ISL_SURF_USAGE_BLITTER_DST_BIT)
282 return dev->mocs.blitter_dst | mask;
283
284 if (external)
285 return dev->mocs.external | mask;
286
287 if (intel_device_info_is_mtl_or_arl(dev->info) &&
288 (usage & ISL_SURF_USAGE_STREAM_OUT_BIT))
289 return dev->mocs.uncached | mask;
290
291 if (dev->info->verx10 == 120 && dev->info->platform != INTEL_PLATFORM_DG1) {
292 if (usage & ISL_SURF_USAGE_STAGING_BIT)
293 return dev->mocs.internal | mask;
294
295 if (usage & ISL_SURF_USAGE_CPB_BIT)
296 return dev->mocs.internal | mask;
297
298 /* Using L1:HDC for storage buffers breaks Vulkan memory model
299 * tests that use shader atomics. This isn't likely to work out,
300 * and we can't know a priori whether they'll be used. So just
301 * continue with ordinary internal MOCS for now.
302 */
303 if (usage & ISL_SURF_USAGE_STORAGE_BIT)
304 return dev->mocs.internal | mask;
305
306 if (usage & (ISL_SURF_USAGE_CONSTANT_BUFFER_BIT |
307 ISL_SURF_USAGE_RENDER_TARGET_BIT |
308 ISL_SURF_USAGE_TEXTURE_BIT))
309 return dev->mocs.l1_hdc_l3_llc | mask;
310 }
311
312 return dev->mocs.internal | mask;
313 }
314
315 void
isl_device_init(struct isl_device * dev,const struct intel_device_info * info)316 isl_device_init(struct isl_device *dev,
317 const struct intel_device_info *info)
318 {
319 /* Gfx8+ don't have bit6 swizzling, ensure callsite is not confused. */
320 assert(!(info->has_bit6_swizzle && info->ver >= 8));
321
322 dev->info = info;
323 dev->use_separate_stencil = ISL_GFX_VER(dev) >= 6;
324 dev->has_bit6_swizzling = info->has_bit6_swizzle;
325 dev->buffer_length_in_aux_addr = false;
326 dev->sampler_route_to_lsc = false;
327
328 /* The ISL_DEV macros may be defined in the CFLAGS, thus hardcoding some
329 * device properties at buildtime. Verify that the macros with the device
330 * properties chosen during runtime.
331 */
332 ISL_GFX_VER_SANITIZE(dev);
333 ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(dev);
334
335 /* Did we break hiz or stencil? */
336 if (ISL_DEV_USE_SEPARATE_STENCIL(dev))
337 assert(info->has_hiz_and_separate_stencil);
338 if (info->must_use_separate_stencil)
339 assert(ISL_DEV_USE_SEPARATE_STENCIL(dev));
340
341 dev->ss.size = RENDER_SURFACE_STATE_length(info) * 4;
342 dev->ss.align = isl_align(dev->ss.size, 32);
343
344 dev->ss.clear_color_state_size = CLEAR_COLOR_length(info) * 4;
345 dev->ss.clear_color_state_offset =
346 RENDER_SURFACE_STATE_ClearValueAddress_start(info) / 32 * 4;
347
348 dev->ss.clear_value_size =
349 isl_align(RENDER_SURFACE_STATE_RedClearColor_bits(info) +
350 RENDER_SURFACE_STATE_GreenClearColor_bits(info) +
351 RENDER_SURFACE_STATE_BlueClearColor_bits(info) +
352 RENDER_SURFACE_STATE_AlphaClearColor_bits(info), 32) / 8;
353
354 dev->ss.clear_value_offset =
355 RENDER_SURFACE_STATE_RedClearColor_start(info) / 32 * 4;
356
357 assert(RENDER_SURFACE_STATE_SurfaceBaseAddress_start(info) % 8 == 0);
358 dev->ss.addr_offset =
359 RENDER_SURFACE_STATE_SurfaceBaseAddress_start(info) / 8;
360
361 /* The "Auxiliary Surface Base Address" field starts a bit higher up
362 * because the bottom 12 bits are used for other things. Round down to
363 * the nearest dword before.
364 */
365 dev->ss.aux_addr_offset =
366 (RENDER_SURFACE_STATE_AuxiliarySurfaceBaseAddress_start(info) & ~31) / 8;
367
368 dev->ds.size = _3DSTATE_DEPTH_BUFFER_length(info) * 4;
369 assert(_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start(info) % 8 == 0);
370 dev->ds.depth_offset =
371 _3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start(info) / 8;
372
373 if (dev->use_separate_stencil) {
374 dev->ds.size += _3DSTATE_STENCIL_BUFFER_length(info) * 4 +
375 _3DSTATE_HIER_DEPTH_BUFFER_length(info) * 4 +
376 _3DSTATE_CLEAR_PARAMS_length(info) * 4;
377
378 assert(_3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_start(info) % 8 == 0);
379 dev->ds.stencil_offset =
380 _3DSTATE_DEPTH_BUFFER_length(info) * 4 +
381 _3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_start(info) / 8;
382
383 assert(_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_start(info) % 8 == 0);
384 dev->ds.hiz_offset =
385 _3DSTATE_DEPTH_BUFFER_length(info) * 4 +
386 _3DSTATE_STENCIL_BUFFER_length(info) * 4 +
387 _3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_start(info) / 8;
388 } else {
389 dev->ds.stencil_offset = 0;
390 dev->ds.hiz_offset = 0;
391 }
392
393 /* From the IVB PRM, SURFACE_STATE::Height,
394 *
395 * For typed buffer and structured buffer surfaces, the number
396 * of entries in the buffer ranges from 1 to 2^27. For raw buffer
397 * surfaces, the number of entries in the buffer is the number of bytes
398 * which can range from 1 to 2^30.
399 *
400 * From the SKL PRM, SURFACE_STATE::Width/Height/Depth for RAW buffers,
401 *
402 * Width : bits [6:0]
403 * Height : bits [20:7]
404 * Depth : bits [31:21]
405 *
406 * So we can address 4Gb
407 *
408 * This limit is only concerned with raw buffers.
409 */
410 if (ISL_GFX_VER(dev) >= 9) {
411 dev->max_buffer_size = 1ull << 32;
412 } else if (ISL_GFX_VER(dev) >= 7) {
413 dev->max_buffer_size = 1ull << 30;
414 } else {
415 dev->max_buffer_size = 1ull << 27;
416 }
417
418 dev->cpb.size = _3DSTATE_CPSIZE_CONTROL_BUFFER_length(info) * 4;
419 dev->cpb.offset =
420 _3DSTATE_CPSIZE_CONTROL_BUFFER_SurfaceBaseAddress_start(info) / 8;
421
422 isl_device_setup_mocs(dev);
423
424 dev->surf_fill_state_s = isl_surf_fill_state_s_get_func(dev);
425 dev->buffer_fill_state_s = isl_buffer_fill_state_s_get_func(dev);
426 dev->emit_depth_stencil_hiz_s = isl_emit_depth_stencil_hiz_s_get_func(dev);
427 dev->null_fill_state_s = isl_null_fill_state_s_get_func(dev);
428 dev->emit_cpb_control_s = isl_emit_cpb_control_s_get_func(dev);
429 }
430
431 /**
432 * @brief Query the set of multisamples supported by the device.
433 *
434 * This function always returns non-zero, as ISL_SAMPLE_COUNT_1_BIT is always
435 * supported.
436 */
437 isl_sample_count_mask_t ATTRIBUTE_CONST
isl_device_get_sample_counts(const struct isl_device * dev)438 isl_device_get_sample_counts(const struct isl_device *dev)
439 {
440 if (ISL_GFX_VER(dev) >= 9) {
441 return ISL_SAMPLE_COUNT_1_BIT |
442 ISL_SAMPLE_COUNT_2_BIT |
443 ISL_SAMPLE_COUNT_4_BIT |
444 ISL_SAMPLE_COUNT_8_BIT |
445 ISL_SAMPLE_COUNT_16_BIT;
446 } else if (ISL_GFX_VER(dev) >= 8) {
447 return ISL_SAMPLE_COUNT_1_BIT |
448 ISL_SAMPLE_COUNT_2_BIT |
449 ISL_SAMPLE_COUNT_4_BIT |
450 ISL_SAMPLE_COUNT_8_BIT;
451 } else if (ISL_GFX_VER(dev) >= 7) {
452 return ISL_SAMPLE_COUNT_1_BIT |
453 ISL_SAMPLE_COUNT_4_BIT |
454 ISL_SAMPLE_COUNT_8_BIT;
455 } else if (ISL_GFX_VER(dev) >= 6) {
456 return ISL_SAMPLE_COUNT_1_BIT |
457 ISL_SAMPLE_COUNT_4_BIT;
458 } else {
459 return ISL_SAMPLE_COUNT_1_BIT;
460 }
461 }
462
463 uint64_t
isl_get_sampler_clear_field_offset(const struct intel_device_info * devinfo,enum isl_format format)464 isl_get_sampler_clear_field_offset(const struct intel_device_info *devinfo,
465 enum isl_format format)
466 {
467 assert(devinfo->ver == 11 || devinfo->ver == 12);
468
469 /* For 32bpc formats, the sampler fetches the raw clear color dwords
470 * used for rendering instead of the converted pixel dwords typically
471 * used for sampling. The CLEAR_COLOR struct page documents this for
472 * 128bpp formats, but not for 32bpp and 64bpp formats.
473 *
474 * Note that although the sampler doesn't use the converted clear color
475 * field with 32bpc formats, the hardware will still convert the clear
476 * color to a pixel when the surface format size is less than 128bpp.
477 */
478 if (isl_format_get_layout(format)->channels.r.bits == 32)
479 return 0;
480
481 /* According to Wa_2201730850, the gfx120 sampler reads the
482 * U24_X8-formatted pixel from the first raw clear color dword.
483 */
484 if (devinfo->verx10 == 120 && format == ISL_FORMAT_R24_UNORM_X8_TYPELESS)
485 return 0;
486
487 return 16;
488 }
489
490 static uint32_t
isl_get_miptail_base_row(enum isl_tiling tiling)491 isl_get_miptail_base_row(enum isl_tiling tiling)
492 {
493 /* Miptails base levels can depend on the number of samples, but since we
494 * don't support levels > 1 with multisampling, the base miptail level is
495 * really simple :
496 */
497 if (tiling == ISL_TILING_SKL_Yf ||
498 tiling == ISL_TILING_ICL_Yf)
499 return 4;
500 else
501 return 0;
502 }
503
504 static const uint8_t skl_std_y_2d_miptail_offset_el[][5][2] = {
505 /* 128 bpb 64 bpb 32 bpb 16 bpb 8 bpb */
506 { {32, 0}, {64, 0}, {64, 0}, {128, 0}, {128, 0} },
507 { { 0, 32}, { 0, 32}, { 0, 64}, { 0, 64}, { 0,128} },
508 { {16, 0}, {32, 0}, {32, 0}, { 64, 0}, { 64, 0} },
509 { { 0, 16}, { 0, 16}, { 0, 32}, { 0, 32}, { 0, 64} },
510 { { 8, 0}, {16, 0}, {16, 0}, { 32, 0}, { 32, 0} },
511 { { 4, 8}, { 8, 8}, { 8, 16}, { 16, 16}, { 16, 32} },
512 { { 0, 12}, { 0, 12}, { 0, 24}, { 0, 24}, { 0, 48} },
513 { { 0, 8}, { 0, 8}, { 0, 16}, { 0, 16}, { 0, 32} },
514 { { 4, 4}, { 8, 4}, { 8, 8}, { 16, 8}, { 16, 16} },
515 { { 4, 0}, { 8, 0}, { 8, 0}, { 16, 0}, { 16, 0} },
516 { { 0, 4}, { 0, 4}, { 0, 8}, { 0, 8}, { 0, 16} },
517 { { 3, 0}, { 6, 0}, { 4, 4}, { 8, 4}, { 0, 12} },
518 { { 2, 0}, { 4, 0}, { 4, 0}, { 8, 0}, { 0, 8} },
519 { { 1, 0}, { 2, 0}, { 0, 4}, { 0, 4}, { 0, 4} },
520 { { 0, 0}, { 0, 0}, { 0, 0}, { 0, 0}, { 0, 0} },
521 };
522
523 static const uint8_t icl_std_y_2d_miptail_offset_el[][5][2] = {
524 /* 128 bpb 64 bpb 32 bpb 16 bpb 8 bpb */
525 { {32, 0}, {64, 0}, {64, 0}, {128, 0}, {128, 0} },
526 { { 0, 32}, { 0, 32}, { 0, 64}, { 0, 64}, { 0, 128} },
527 { {16, 0}, {32, 0}, {32, 0}, { 64, 0}, { 64, 0} },
528 { { 0, 16}, { 0, 16}, { 0, 32}, { 0, 32}, { 0, 64} },
529 { { 8, 0}, {16, 0}, {16, 0}, { 32, 0}, { 32, 0} },
530 { { 4, 8}, { 8, 8}, { 8, 16}, { 16, 16}, { 16, 32} },
531 { { 0, 12}, { 0, 12}, { 0, 24}, { 0, 24}, { 0, 48} },
532 { { 0, 8}, { 0, 8}, { 0, 16}, { 0, 16}, { 0, 32} },
533 { { 4, 4}, { 8, 4}, { 8, 8}, { 16, 8}, { 16, 16} },
534 { { 4, 0}, { 8, 0}, { 8, 0}, { 16, 0}, { 16, 0} },
535 { { 0, 4}, { 0, 4}, { 0, 8}, { 0, 8}, { 0, 16} },
536 { { 0, 0}, { 0, 0}, { 0, 0}, { 0, 0}, { 0, 0} },
537 { { 1, 0}, { 2, 0}, { 0, 4}, { 0, 4}, { 0, 4} },
538 { { 2, 0}, { 4, 0}, { 4, 0}, { 8, 0}, { 0, 8} },
539 { { 3, 0}, { 6, 0}, { 4, 4}, { 8, 4}, { 0, 12} },
540 };
541
542 static const uint8_t skl_std_y_3d_miptail_offset_el[][5][3] = {
543 /* 128 bpb 64 bpb 32 bpb 16 bpb 8 bpb */
544 { {8, 0, 0}, {16, 0, 0}, {16, 0, 0}, {16, 0, 0}, {32, 0, 0} },
545 { {0, 8, 0}, { 0, 8, 0}, { 0, 16, 0}, { 0, 16, 0}, { 0, 16, 0} },
546 { {0, 0, 8}, { 0, 0, 8}, { 0, 0, 8}, { 0, 0, 16}, { 0, 0, 16} },
547 { {4, 0, 0}, { 8, 0, 0}, { 8, 0, 0}, { 8, 0, 0}, {16, 0, 0} },
548 { {0, 4, 0}, { 0, 4, 0}, { 0, 8, 0}, { 0, 8, 0}, { 0, 8, 0} },
549 { {0, 0, 4}, { 0, 0, 4}, { 0, 0, 4}, { 0, 0, 8}, { 0, 0, 8} },
550 { {3, 0, 0}, { 6, 0, 0}, { 4, 4, 0}, { 0, 4, 4}, { 0, 4, 4} },
551 { {2, 0, 0}, { 4, 0, 0}, { 0, 4, 0}, { 0, 4, 0}, { 0, 4, 0} },
552 { {1, 0, 3}, { 2, 0, 3}, { 4, 0, 3}, { 0, 0, 7}, { 0, 0, 7} },
553 { {1, 0, 2}, { 2, 0, 2}, { 4, 0, 2}, { 0, 0, 6}, { 0, 0, 6} },
554 { {1, 0, 1}, { 2, 0, 1}, { 4, 0, 1}, { 0, 0, 5}, { 0, 0, 5} },
555 { {1, 0, 0}, { 2, 0, 0}, { 4, 0, 0}, { 0, 0, 4}, { 0, 0, 4} },
556 { {0, 0, 3}, { 0, 0, 3}, { 0, 0, 3}, { 0, 0, 3}, { 0, 0, 3} },
557 { {0, 0, 2}, { 0, 0, 2}, { 0, 0, 2}, { 0, 0, 2}, { 0, 0, 2} },
558 { {0, 0, 1}, { 0, 0, 1}, { 0, 0, 1}, { 0, 0, 1}, { 0, 0, 1} },
559 { {0, 0, 0}, { 0, 0, 0}, { 0, 0, 0}, { 0, 0, 0}, { 0, 0, 0} },
560 };
561
562 static const uint8_t icl_std_y_3d_miptail_offset_el[][5][3] = {
563 /* 128 bpb 64 bpb 32 bpb 16 bpb 8 bpb */
564 { {8, 0, 0}, {16, 0, 0}, {16, 0, 0}, {16, 0, 0}, {32, 0, 0} },
565 { {0, 8, 0}, { 0, 8, 0}, { 0, 16, 0}, { 0, 16, 0}, { 0, 16, 0} },
566 { {0, 0, 8}, { 0, 0, 8}, { 0, 0, 8}, { 0, 0, 16}, { 0, 0, 16} },
567 { {4, 0, 0}, { 8, 0, 0}, { 8, 0, 0}, { 8, 0, 0}, {16, 0, 0} },
568 { {0, 4, 0}, { 0, 4, 0}, { 0, 8, 0}, { 0, 8, 0}, { 0, 8, 0} },
569 { {2, 0, 4}, { 4, 0, 4}, { 4, 0, 4}, { 4, 0, 8}, { 8, 0, 8} },
570 { {0, 2, 4}, { 0, 2, 4}, { 0, 4, 4}, { 0, 4, 8}, { 0, 4, 8} },
571 { {0, 0, 4}, { 0, 0, 4}, { 0, 0, 4}, { 0, 0, 8}, { 0, 0, 8} },
572 { {2, 2, 0}, { 4, 2, 0}, { 4, 4, 0}, { 4, 4, 0}, { 8, 4, 0} },
573 { {2, 0, 0}, { 4, 0, 0}, { 4, 0, 0}, { 4, 0, 0}, { 8, 0, 0} },
574 { {0, 2, 0}, { 0, 2, 0}, { 0, 4, 0}, { 0, 4, 0}, { 0, 4, 0} },
575 { {1, 0, 2}, { 2, 0, 2}, { 2, 0, 2}, { 2, 0, 4}, { 4, 0, 4} },
576 { {0, 0, 2}, { 0, 0, 2}, { 0, 0, 2}, { 0, 0, 4}, { 0, 0, 4} },
577 { {1, 0, 0}, { 2, 0, 0}, { 2, 0, 0}, { 2, 0, 0}, { 4, 0, 0} },
578 { {0, 0, 0}, { 0, 0, 0}, { 0, 0, 0}, { 0, 0, 0}, { 0, 0, 0} },
579 };
580
581 static const uint8_t acm_tile64_3d_miptail_offset_el[][5][3] = {
582 /* 128 bpb 64 bpb 32 bpb 16 bpb 8 bpb */
583 { {8, 0, 0}, {16, 0, 0}, {16, 0, 0}, {16, 0, 0}, {32, 0, 0}, },
584 { {0, 8, 0}, { 0, 8, 0}, { 0, 16, 0}, { 0, 16, 0}, { 0, 16, 0}, },
585 { {0, 0, 8}, { 0, 0, 8}, { 0, 0, 8}, { 0, 0, 16}, { 0, 0, 16}, },
586 { {4, 0, 0}, { 8, 0, 0}, { 8, 0, 0}, { 8, 0, 0}, {16, 0, 0}, },
587 { {0, 4, 0}, { 0, 4, 0}, { 0, 8, 0}, { 0, 8, 0}, { 0, 8, 0}, },
588 { {2, 0, 4}, { 4, 0, 4}, { 4, 0, 4}, { 0, 4, 8}, { 0, 4, 8}, },
589 { {1, 0, 4}, { 2, 0, 4}, { 0, 4, 4}, { 0, 0, 12}, { 0, 0, 12}, },
590 { {0, 0, 4}, { 0, 0, 4}, { 0, 0, 4}, { 0, 0, 8}, { 0, 0, 8}, },
591 { {3, 0, 0}, { 6, 0, 0}, { 4, 4, 0}, { 0, 4, 4}, { 0, 4, 4}, },
592 { {2, 0, 0}, { 4, 0, 0}, { 4, 0, 0}, { 0, 4, 0}, { 0, 4, 0}, },
593 { {1, 0, 0}, { 2, 0, 0}, { 0, 4, 0}, { 0, 0, 4}, { 0, 0, 4}, },
594 { {0, 0, 0}, { 0, 0, 0}, { 0, 0, 0}, { 0, 0, 0}, { 0, 0, 0}, },
595 { {0, 0, 1}, { 0, 0, 1}, { 0, 0, 1}, { 0, 0, 1}, { 0, 0, 1}, },
596 { {0, 0, 2}, { 0, 0, 2}, { 0, 0, 2}, { 0, 0, 2}, { 0, 0, 2}, },
597 { {0, 0, 3}, { 0, 0, 3}, { 0, 0, 3}, { 0, 0, 3}, { 0, 0, 3}, },
598 };
599
600 static uint32_t
tiling_max_mip_tail(enum isl_tiling tiling,enum isl_surf_dim dim,uint32_t samples)601 tiling_max_mip_tail(enum isl_tiling tiling,
602 enum isl_surf_dim dim,
603 uint32_t samples)
604 {
605 /* In theory, miptails work for multisampled images, but we don't support
606 * mipmapped multisampling.
607 *
608 * BSpec 58770: Xe2 does not support miptails on multisampled images.
609 */
610 if (samples > 1)
611 return 0;
612
613 int num_2d_table_rows;
614 int num_3d_table_rows;
615
616 switch (tiling) {
617 case ISL_TILING_LINEAR:
618 case ISL_TILING_X:
619 case ISL_TILING_Y0:
620 case ISL_TILING_4:
621 case ISL_TILING_W:
622 case ISL_TILING_HIZ:
623 case ISL_TILING_CCS:
624 /* There is no miptail for those tilings */
625 return 0;
626
627 case ISL_TILING_SKL_Yf:
628 case ISL_TILING_SKL_Ys:
629 /* SKL PRMs, Volume 5: Memory Views :
630 *
631 * Given by the last row of the table in the following sections:
632 *
633 * - Tiling and Mip Tail for 1D Surfaces
634 * - Tiling and Mip Tail for 2D Surfaces
635 * - Tiling and Mip Tail for 3D Surfaces
636 */
637 num_2d_table_rows = ARRAY_SIZE(skl_std_y_2d_miptail_offset_el);
638 num_3d_table_rows = ARRAY_SIZE(skl_std_y_3d_miptail_offset_el);
639 break;
640
641 case ISL_TILING_ICL_Yf:
642 case ISL_TILING_ICL_Ys:
643 /* ICL PRMs, Volume 5: Memory Views :
644 *
645 * - Tiling and Mip Tail for 1D Surfaces :
646 * "There is no MIP Tail allowed for 1D surfaces because they are
647 * not allowed to be tiled. They must be declared as linear."
648 * - Tiling and Mip Tail for 2D Surfaces
649 * - Tiling and Mip Tail for 3D Surfaces
650 */
651 num_2d_table_rows = ARRAY_SIZE(icl_std_y_2d_miptail_offset_el);
652 num_3d_table_rows = ARRAY_SIZE(icl_std_y_3d_miptail_offset_el);
653 break;
654
655 case ISL_TILING_64:
656 case ISL_TILING_64_XE2:
657 /* ATS-M PRMS, Volume 5: Memory Data Formats :
658 *
659 * - Tiling and Mip Tail for 1D Surfaces :
660 * "There is no MIP Tail allowed for 1D surfaces because they are
661 * not allowed to be tiled. They must be declared as linear."
662 * - Tiling and Mip Tail for 2D Surfaces
663 * - Tiling and Mip Tail for 3D Surfaces
664 */
665 num_2d_table_rows = ARRAY_SIZE(icl_std_y_2d_miptail_offset_el);
666 num_3d_table_rows = ARRAY_SIZE(acm_tile64_3d_miptail_offset_el);
667 break;
668
669 default:
670 unreachable("Invalid tiling");
671 }
672
673 assert(dim != ISL_SURF_DIM_1D);
674 const int num_rows = dim == ISL_SURF_DIM_2D ? num_2d_table_rows :
675 num_3d_table_rows;
676 return num_rows - isl_get_miptail_base_row(tiling);
677 }
678
679 /**
680 * Returns an isl_tile_info representation of the given isl_tiling when
681 * combined when used in the given configuration.
682 *
683 * :param tiling: |in| The tiling format to introspect
684 * :param dim: |in| The dimensionality of the surface being tiled
685 * :param msaa_layout: |in| The layout of samples in the surface being tiled
686 * :param format_bpb: |in| The number of bits per surface element (block) for
687 * the surface being tiled
688 * :param samples: |in| The samples in the surface being tiled
689 * :param tile_info: |out| Return parameter for the tiling information
690 */
691 void
isl_tiling_get_info(enum isl_tiling tiling,enum isl_surf_dim dim,enum isl_msaa_layout msaa_layout,uint32_t format_bpb,uint32_t samples,struct isl_tile_info * tile_info)692 isl_tiling_get_info(enum isl_tiling tiling,
693 enum isl_surf_dim dim,
694 enum isl_msaa_layout msaa_layout,
695 uint32_t format_bpb,
696 uint32_t samples,
697 struct isl_tile_info *tile_info)
698 {
699 const uint32_t bs = format_bpb / 8;
700 struct isl_extent4d logical_el;
701 struct isl_extent2d phys_B;
702
703 if (tiling != ISL_TILING_LINEAR && !isl_is_pow2(format_bpb)) {
704 /* It is possible to have non-power-of-two formats in a tiled buffer.
705 * The easiest way to handle this is to treat the tile as if it is three
706 * times as wide. This way no pixel will ever cross a tile boundary.
707 * This really only works on a subset of tiling formats.
708 */
709 assert(tiling == ISL_TILING_X || tiling == ISL_TILING_Y0 ||
710 tiling == ISL_TILING_4);
711 assert(bs % 3 == 0 && isl_is_pow2(format_bpb / 3));
712 isl_tiling_get_info(tiling, dim, msaa_layout, format_bpb / 3, samples,
713 tile_info);
714 return;
715 }
716
717 switch (tiling) {
718 case ISL_TILING_LINEAR:
719 assert(bs > 0);
720 logical_el = isl_extent4d(1, 1, 1, 1);
721 phys_B = isl_extent2d(bs, 1);
722 break;
723
724 case ISL_TILING_X:
725 assert(bs > 0);
726 logical_el = isl_extent4d(512 / bs, 8, 1, 1);
727 phys_B = isl_extent2d(512, 8);
728 break;
729
730 case ISL_TILING_Y0:
731 case ISL_TILING_4:
732 assert(bs > 0);
733 logical_el = isl_extent4d(128 / bs, 32, 1, 1);
734 phys_B = isl_extent2d(128, 32);
735 break;
736
737 case ISL_TILING_W:
738 assert(bs == 1);
739 logical_el = isl_extent4d(64, 64, 1, 1);
740 /* From the Broadwell PRM Vol 2d, RENDER_SURFACE_STATE::SurfacePitch:
741 *
742 * "If the surface is a stencil buffer (and thus has Tile Mode set
743 * to TILEMODE_WMAJOR), the pitch must be set to 2x the value
744 * computed based on width, as the stencil buffer is stored with two
745 * rows interleaved."
746 *
747 * This, together with the fact that stencil buffers are referred to as
748 * being Y-tiled in the PRMs for older hardware implies that the
749 * physical size of a W-tile is actually the same as for a Y-tile.
750 */
751 phys_B = isl_extent2d(128, 32);
752 break;
753
754 case ISL_TILING_SKL_Yf:
755 case ISL_TILING_SKL_Ys:
756 case ISL_TILING_ICL_Yf:
757 case ISL_TILING_ICL_Ys: {
758 bool is_Ys = tiling == ISL_TILING_SKL_Ys ||
759 tiling == ISL_TILING_ICL_Ys;
760 assert(format_bpb >= 8);
761
762 switch (dim) {
763 case ISL_SURF_DIM_2D:
764 /* See the BSpec Memory Data Formats » Common Surface Formats »
765 * Surface Layout and Tiling [SKL+] » 2D Surfaces SKL+ » 2D/CUBE
766 * Alignment Requirement [SKL+]
767 *
768 * Or, look in the SKL PRM under Memory Views > Common Surface
769 * Formats > Surface Layout and Tiling > 2D Surfaces > 2D/CUBE
770 * Alignment Requirements.
771 */
772 logical_el = (struct isl_extent4d) {
773 .w = 1 << (6 - ((ffs(format_bpb) - 4) / 2) + (2 * is_Ys)),
774 .h = 1 << (6 - ((ffs(format_bpb) - 3) / 2) + (2 * is_Ys)),
775 .d = 1,
776 .a = 1,
777 };
778
779 if (samples > 1 && tiling != ISL_TILING_SKL_Yf) {
780 /* SKL PRMs, Volume 5: Memory Views, 2D/CUBE Alignment
781 * Requirement:
782 *
783 * "For MSFMT_MSS type multi-sampled TileYS surfaces, the
784 * alignments given above must be divided by the appropriate
785 * value from the table below."
786 *
787 * The formulas below reproduce those values.
788 */
789 if (msaa_layout == ISL_MSAA_LAYOUT_ARRAY) {
790 logical_el.w >>= (ffs(samples) - 0) / 2;
791 logical_el.h >>= (ffs(samples) - 1) / 2;
792 logical_el.a = samples;
793 }
794 }
795 break;
796
797 case ISL_SURF_DIM_3D:
798 /* See the BSpec Memory Data Formats » Common Surface Formats »
799 * Surface Layout and Tiling [SKL+] » 3D Surfaces SKL+ » 3D Alignment
800 * Requirements [SKL+]
801 *
802 * Or, look in the SKL PRM under Memory Views > Common Surface
803 * Formats > Surface Layout and Tiling > 3D Surfaces > 3D Alignment
804 * Requirements.
805 */
806 logical_el = (struct isl_extent4d) {
807 .w = 1 << (4 - ((ffs(format_bpb) - 2) / 3) + (2 * is_Ys)),
808 .h = 1 << (4 - ((ffs(format_bpb) - 4) / 3) + (1 * is_Ys)),
809 .d = 1 << (4 - ((ffs(format_bpb) - 3) / 3) + (1 * is_Ys)),
810 .a = 1,
811 };
812 break;
813 default:
814 unreachable("Invalid dimension");
815 }
816
817 uint32_t tile_size_B = is_Ys ? (1 << 16) : (1 << 12);
818
819 phys_B.w = logical_el.width * bs;
820 phys_B.h = tile_size_B / phys_B.w;
821 break;
822 }
823 case ISL_TILING_64:
824 /* The tables below are taken from the "2D Surfaces" & "3D Surfaces"
825 * pages in the Bspec which are formulated in terms of the Cv and Cu
826 * constants. This is different from the tables in the "Tile64 Format"
827 * page which should be equivalent but are usually in terms of pixels.
828 * Also note that Cv and Cu are HxW order to match the Bspec table, not
829 * WxH order like you might expect.
830 *
831 * From the Bspec's or ATS-M PRMs Volume 5: Memory Data Formats, "Tile64
832 * Format" :
833 *
834 * MSAA Depth/Stencil surface use IMS (Interleaved Multi Samples)
835 * which means:
836 *
837 * - Use the 1X MSAA (non-MSRT) version of the Tile64 equations and
838 * let the client unit do the swizzling internally
839 *
840 * Surfaces using the IMS layout will use the mapping for 1x MSAA.
841 */
842 #define tile_extent2d(bs, cv, cu, a) \
843 isl_extent4d((1 << cu) / bs, 1 << cv, 1, a)
844 #define tile_extent3d(bs, cr, cv, cu) \
845 isl_extent4d((1 << cu) / bs, 1 << cv, 1 << cr, 1)
846
847 if (dim == ISL_SURF_DIM_3D) {
848 switch (format_bpb) {
849 case 128: logical_el = tile_extent3d(bs, 4, 4, 8); break;
850 case 64: logical_el = tile_extent3d(bs, 4, 4, 8); break;
851 case 32: logical_el = tile_extent3d(bs, 4, 5, 7); break;
852 case 16: logical_el = tile_extent3d(bs, 5, 5, 6); break;
853 case 8: logical_el = tile_extent3d(bs, 5, 5, 6); break;
854 default: unreachable("Unsupported format size for 3D");
855 }
856 } else {
857 if (samples == 1 || msaa_layout == ISL_MSAA_LAYOUT_INTERLEAVED) {
858 switch (format_bpb) {
859 case 128: logical_el = tile_extent2d(bs, 6, 10, 1); break;
860 case 64: logical_el = tile_extent2d(bs, 6, 10, 1); break;
861 case 32: logical_el = tile_extent2d(bs, 7, 9, 1); break;
862 case 16: logical_el = tile_extent2d(bs, 7, 9, 1); break;
863 case 8: logical_el = tile_extent2d(bs, 8, 8, 1); break;
864 default: unreachable("Unsupported format size.");
865 }
866 } else if (samples == 2) {
867 switch (format_bpb) {
868 case 128: logical_el = tile_extent2d(bs, 6, 9, 2); break;
869 case 64: logical_el = tile_extent2d(bs, 6, 9, 2); break;
870 case 32: logical_el = tile_extent2d(bs, 7, 8, 2); break;
871 case 16: logical_el = tile_extent2d(bs, 7, 8, 2); break;
872 case 8: logical_el = tile_extent2d(bs, 8, 7, 2); break;
873 default: unreachable("Unsupported format size.");
874 }
875 } else {
876 switch (format_bpb) {
877 case 128: logical_el = tile_extent2d(bs, 5, 9, 4); break;
878 case 64: logical_el = tile_extent2d(bs, 5, 9, 4); break;
879 case 32: logical_el = tile_extent2d(bs, 6, 8, 4); break;
880 case 16: logical_el = tile_extent2d(bs, 6, 8, 4); break;
881 case 8: logical_el = tile_extent2d(bs, 7, 7, 4); break;
882 default: unreachable("Unsupported format size.");
883 }
884 }
885 }
886
887 #undef tile_extent2d
888 #undef tile_extent3d
889
890 phys_B.w = logical_el.w * bs;
891 phys_B.h = 64 * 1024 / phys_B.w;
892 break;
893
894 case ISL_TILING_64_XE2:
895 /* The tables below are taken from BSpec 58767 which are formulated in
896 * terms of the Cv and Cu constants. This is different from the tables in
897 * the "Tile64 Format" page which should be equivalent but are usually in
898 * terms of pixels.
899 *
900 * Also note that Cv and Cu are HxW order to match the Bspec table, not
901 * WxH order like you might expect.
902 */
903 #define tile_extent2d(bs, cv, cu, a) \
904 isl_extent4d((1 << cu) / bs, 1 << cv, 1, a)
905 #define tile_extent3d(bs, cr, cv, cu) \
906 isl_extent4d((1 << cu) / bs, 1 << cv, 1 << cr, 1)
907
908 if (dim == ISL_SURF_DIM_3D) {
909 switch (format_bpb) {
910 case 128: logical_el = tile_extent3d(bs, 4, 4, 8); break;
911 case 64: logical_el = tile_extent3d(bs, 4, 4, 8); break;
912 case 32: logical_el = tile_extent3d(bs, 4, 5, 7); break;
913 case 16: logical_el = tile_extent3d(bs, 5, 5, 6); break;
914 case 8: logical_el = tile_extent3d(bs, 5, 5, 6); break;
915 default: unreachable("Unsupported format size for 3D");
916 }
917 } else {
918 if (samples == 1 || msaa_layout == ISL_MSAA_LAYOUT_INTERLEAVED) {
919 switch (format_bpb) {
920 case 128: logical_el = tile_extent2d(bs, 6, 10, 1); break;
921 case 64: logical_el = tile_extent2d(bs, 6, 10, 1); break;
922 case 32: logical_el = tile_extent2d(bs, 7, 9, 1); break;
923 case 16: logical_el = tile_extent2d(bs, 7, 9, 1); break;
924 case 8: logical_el = tile_extent2d(bs, 8, 8, 1); break;
925 default: unreachable("Unsupported format size.");
926 }
927 } else if (samples == 2) {
928 switch (format_bpb) {
929 case 128: logical_el = tile_extent2d(bs, 5, 10, 2); break;
930 case 64: logical_el = tile_extent2d(bs, 6, 9, 2); break;
931 case 32: logical_el = tile_extent2d(bs, 7, 8, 2); break;
932 case 16: logical_el = tile_extent2d(bs, 7, 8, 2); break;
933 case 8: logical_el = tile_extent2d(bs, 8, 7, 2); break;
934 default: unreachable("Unsupported format size.");
935 }
936 } else if (samples == 4) {
937 switch (format_bpb) {
938 case 128: logical_el = tile_extent2d(bs, 5, 9, 4); break;
939 case 64: logical_el = tile_extent2d(bs, 5, 9, 4); break;
940 case 32: logical_el = tile_extent2d(bs, 6, 8, 4); break;
941 case 16: logical_el = tile_extent2d(bs, 6, 8, 4); break;
942 case 8: logical_el = tile_extent2d(bs, 7, 7, 4); break;
943 default: unreachable("Unsupported format size.");
944 }
945 } else if (samples == 8) {
946 switch (format_bpb) {
947 case 128: logical_el = tile_extent2d(bs, 5, 8, 8); break;
948 case 64: logical_el = tile_extent2d(bs, 5, 8, 8); break;
949 case 32: logical_el = tile_extent2d(bs, 5, 8, 8); break;
950 case 16: logical_el = tile_extent2d(bs, 6, 7, 8); break;
951 case 8: logical_el = tile_extent2d(bs, 6, 7, 8); break;
952 default: unreachable("Unsupported format size.");
953 }
954 } else if (samples == 16) {
955 switch (format_bpb) {
956 case 128: logical_el = tile_extent2d(bs, 4, 8, 16); break;
957 case 64: logical_el = tile_extent2d(bs, 5, 7, 16); break;
958 case 32: logical_el = tile_extent2d(bs, 5, 7, 16); break;
959 case 16: logical_el = tile_extent2d(bs, 5, 7, 16); break;
960 case 8: logical_el = tile_extent2d(bs, 6, 6, 16); break;
961 default: unreachable("Unsupported format size.");
962 }
963 }
964 }
965
966 #undef tile_extent2d
967 #undef tile_extent3d
968
969 phys_B.w = logical_el.w * bs;
970 phys_B.h = 64 * 1024 / phys_B.w;
971 break;
972
973 case ISL_TILING_HIZ:
974 /* HiZ buffers are required to have a 128bpb HiZ format. The tiling has
975 * the same physical dimensions as Y-tiling but actually has two HiZ
976 * columns per Y-tiled column.
977 */
978 assert(bs == 16);
979 logical_el = isl_extent4d(16, 16, 1, 1);
980 phys_B = isl_extent2d(128, 32);
981 break;
982
983 case ISL_TILING_CCS:
984 /* CCS surfaces are required to have one of the GENX_CCS_* formats which
985 * have a block size of 1 or 2 bits per block and each CCS element
986 * corresponds to one cache-line pair in the main surface. From the Sky
987 * Lake PRM Vol. 12 in the section on planes:
988 *
989 * "The Color Control Surface (CCS) contains the compression status
990 * of the cache-line pairs. The compression state of the cache-line
991 * pair is specified by 2 bits in the CCS. Each CCS cache-line
992 * represents an area on the main surface of 16x16 sets of 128 byte
993 * Y-tiled cache-line-pairs. CCS is always Y tiled."
994 *
995 * The CCS being Y-tiled implies that it's an 8x8 grid of cache-lines.
996 * Since each cache line corresponds to a 16x16 set of cache-line pairs,
997 * that yields total tile area of 128x128 cache-line pairs or CCS
998 * elements. On older hardware, each CCS element is 1 bit and the tile
999 * is 128x256 elements.
1000 */
1001 assert(format_bpb == 1 || format_bpb == 2);
1002 logical_el = isl_extent4d(128, 256 / format_bpb, 1, 1);
1003 phys_B = isl_extent2d(128, 32);
1004 break;
1005
1006 default:
1007 unreachable("not reached");
1008 } /* end switch */
1009
1010 *tile_info = (struct isl_tile_info) {
1011 .tiling = tiling,
1012 .format_bpb = format_bpb,
1013 .logical_extent_el = logical_el,
1014 .phys_extent_B = phys_B,
1015 .max_miptail_levels = tiling_max_mip_tail(tiling, dim, samples),
1016 };
1017 }
1018
1019 bool
isl_color_value_is_zero(union isl_color_value value,enum isl_format format)1020 isl_color_value_is_zero(union isl_color_value value,
1021 enum isl_format format)
1022 {
1023 const struct isl_format_layout *fmtl = isl_format_get_layout(format);
1024
1025 #define RETURN_FALSE_IF_NOT_0(c, i) \
1026 if (fmtl->channels.c.bits && value.u32[i] != 0) \
1027 return false
1028
1029 RETURN_FALSE_IF_NOT_0(r, 0);
1030 RETURN_FALSE_IF_NOT_0(g, 1);
1031 RETURN_FALSE_IF_NOT_0(b, 2);
1032 RETURN_FALSE_IF_NOT_0(a, 3);
1033
1034 #undef RETURN_FALSE_IF_NOT_0
1035
1036 return true;
1037 }
1038
1039 bool
isl_color_value_is_zero_one(union isl_color_value value,enum isl_format format)1040 isl_color_value_is_zero_one(union isl_color_value value,
1041 enum isl_format format)
1042 {
1043 const struct isl_format_layout *fmtl = isl_format_get_layout(format);
1044
1045 #define RETURN_FALSE_IF_NOT_0_1(c, i, field) \
1046 if (fmtl->channels.c.bits && value.field[i] != 0 && value.field[i] != 1) \
1047 return false
1048
1049 if (isl_format_has_int_channel(format)) {
1050 RETURN_FALSE_IF_NOT_0_1(r, 0, u32);
1051 RETURN_FALSE_IF_NOT_0_1(g, 1, u32);
1052 RETURN_FALSE_IF_NOT_0_1(b, 2, u32);
1053 RETURN_FALSE_IF_NOT_0_1(a, 3, u32);
1054 } else {
1055 RETURN_FALSE_IF_NOT_0_1(r, 0, f32);
1056 RETURN_FALSE_IF_NOT_0_1(g, 1, f32);
1057 RETURN_FALSE_IF_NOT_0_1(b, 2, f32);
1058 RETURN_FALSE_IF_NOT_0_1(a, 3, f32);
1059 }
1060
1061 #undef RETURN_FALSE_IF_NOT_0_1
1062
1063 return true;
1064 }
1065
1066 /**
1067 * @param[out] tiling is set only on success
1068 */
1069 static bool
isl_surf_choose_tiling(const struct isl_device * dev,const struct isl_surf_init_info * restrict info,enum isl_tiling * tiling)1070 isl_surf_choose_tiling(const struct isl_device *dev,
1071 const struct isl_surf_init_info *restrict info,
1072 enum isl_tiling *tiling)
1073 {
1074 isl_tiling_flags_t tiling_flags = info->tiling_flags;
1075
1076 /* HiZ surfaces always use the HiZ tiling */
1077 if (info->usage & ISL_SURF_USAGE_HIZ_BIT) {
1078 assert(isl_format_is_hiz(info->format));
1079 assert(tiling_flags == ISL_TILING_HIZ_BIT);
1080 *tiling = isl_tiling_flag_to_enum(tiling_flags);
1081 return true;
1082 }
1083
1084 /* CCS surfaces always use the CCS tiling */
1085 if (info->usage & ISL_SURF_USAGE_CCS_BIT) {
1086 assert(isl_format_get_layout(info->format)->txc == ISL_TXC_CCS);
1087 assert(tiling_flags == ISL_TILING_CCS_BIT);
1088 *tiling = isl_tiling_flag_to_enum(tiling_flags);
1089 return true;
1090 }
1091
1092 if (ISL_GFX_VERX10(dev) >= 200) {
1093 isl_gfx20_filter_tiling(dev, info, &tiling_flags);
1094 } else if (ISL_GFX_VERX10(dev) >= 125) {
1095 isl_gfx125_filter_tiling(dev, info, &tiling_flags);
1096 } else if (ISL_GFX_VER(dev) >= 6) {
1097 isl_gfx6_filter_tiling(dev, info, &tiling_flags);
1098 } else {
1099 isl_gfx4_filter_tiling(dev, info, &tiling_flags);
1100 }
1101
1102 #define CHOOSE(__tiling) \
1103 do { \
1104 if (tiling_flags & (1u << (__tiling))) { \
1105 *tiling = (__tiling); \
1106 return true; \
1107 } \
1108 } while (0)
1109
1110 /* Of the tiling modes remaining, choose the one that offers the best
1111 * performance.
1112 */
1113
1114 if (info->dim == ISL_SURF_DIM_1D) {
1115 /* Prefer linear for 1D surfaces because they do not benefit from
1116 * tiling. To the contrary, tiling leads to wasted memory and poor
1117 * memory locality due to the swizzling and alignment restrictions
1118 * required in tiled surfaces.
1119 */
1120 CHOOSE(ISL_TILING_LINEAR);
1121 }
1122
1123 if (intel_needs_workaround(dev->info, 22015614752) &&
1124 _isl_surf_info_supports_ccs(dev, info->format, info->usage) &&
1125 (info->usage & ISL_SURF_USAGE_MULTI_ENGINE_PAR_BIT) &&
1126 (info->levels > 1 || info->depth > 1 || info->array_len > 1)) {
1127 /* There are issues with multiple engines accessing the same CCS
1128 * cacheline in parallel. This can happen if this image has multiple
1129 * subresources. If possible, avoid such conflicts by picking a tiling
1130 * that will increase the subresource alignment to 64k. If we can't use
1131 * such a tiling, we'll prevent CCS from being enabled later on via
1132 * isl_surf_supports_ccs.
1133 */
1134 CHOOSE(ISL_TILING_64);
1135 }
1136
1137 /* For sparse images, prefer the formats that use the standard block
1138 * shapes.
1139 */
1140 if (info->usage & ISL_SURF_USAGE_SPARSE_BIT) {
1141 CHOOSE(ISL_TILING_64_XE2);
1142 CHOOSE(ISL_TILING_64);
1143 CHOOSE(ISL_TILING_ICL_Ys);
1144 CHOOSE(ISL_TILING_SKL_Ys);
1145 }
1146
1147 /* Choose suggested 4K tilings first, then 64K tilings:
1148 *
1149 * Then following quotes can be found in the SKL PRMs,
1150 * Volume 5: Memory Views, Address Tiling Function Introduction
1151 * and from the ATS-M PRMs,
1152 * Volume 5: Memory Data Formats, Address Tiling Function Introduction
1153 *
1154 * "TileY: Used for most tiled surfaces when TR_MODE=TR_NONE."
1155 * "Tile4: 4KB tiling mode based on previously-supported TileY"
1156 * "TileYF: 4KB tiling mode based on TileY"
1157 * "TileYS: 64KB tiling mode based on TileY"
1158 * "Tile64: 64KB tiling mode which support standard-tiling including
1159 * Mip Tails"
1160 *
1161 * When TileYF and TileYS are used TR_MODE != TR_NONE.
1162 */
1163 CHOOSE(ISL_TILING_Y0);
1164 CHOOSE(ISL_TILING_4);
1165 CHOOSE(ISL_TILING_SKL_Yf);
1166 CHOOSE(ISL_TILING_ICL_Yf);
1167 CHOOSE(ISL_TILING_SKL_Ys);
1168 CHOOSE(ISL_TILING_ICL_Ys);
1169 CHOOSE(ISL_TILING_64);
1170 CHOOSE(ISL_TILING_64_XE2);
1171
1172 CHOOSE(ISL_TILING_X);
1173 CHOOSE(ISL_TILING_W);
1174 CHOOSE(ISL_TILING_LINEAR);
1175
1176 #undef CHOOSE
1177
1178 /* No tiling mode accommodates the inputs. */
1179 assert(tiling_flags == 0);
1180 return notify_failure(info, "no supported tiling");
1181 }
1182
1183 static bool
isl_choose_msaa_layout(const struct isl_device * dev,const struct isl_surf_init_info * info,enum isl_tiling tiling,enum isl_msaa_layout * msaa_layout)1184 isl_choose_msaa_layout(const struct isl_device *dev,
1185 const struct isl_surf_init_info *info,
1186 enum isl_tiling tiling,
1187 enum isl_msaa_layout *msaa_layout)
1188 {
1189 if (ISL_GFX_VER(dev) >= 8) {
1190 return isl_gfx8_choose_msaa_layout(dev, info, tiling, msaa_layout);
1191 } else if (ISL_GFX_VER(dev) >= 7) {
1192 return isl_gfx7_choose_msaa_layout(dev, info, tiling, msaa_layout);
1193 } else if (ISL_GFX_VER(dev) >= 6) {
1194 return isl_gfx6_choose_msaa_layout(dev, info, tiling, msaa_layout);
1195 } else {
1196 return isl_gfx4_choose_msaa_layout(dev, info, tiling, msaa_layout);
1197 }
1198 }
1199
1200 struct isl_extent2d
isl_get_interleaved_msaa_px_size_sa(uint32_t samples)1201 isl_get_interleaved_msaa_px_size_sa(uint32_t samples)
1202 {
1203 assert(isl_is_pow2(samples));
1204
1205 /* From the Broadwell PRM >> Volume 5: Memory Views >> Computing Mip Level
1206 * Sizes (p133):
1207 *
1208 * If the surface is multisampled and it is a depth or stencil surface
1209 * or Multisampled Surface StorageFormat in SURFACE_STATE is
1210 * MSFMT_DEPTH_STENCIL, W_L and H_L must be adjusted as follows before
1211 * proceeding: [...]
1212 */
1213 return (struct isl_extent2d) {
1214 .width = 1 << ((ffs(samples) - 0) / 2),
1215 .height = 1 << ((ffs(samples) - 1) / 2),
1216 };
1217 }
1218
1219 static void
isl_msaa_interleaved_scale_px_to_sa(uint32_t samples,uint32_t * width,uint32_t * height)1220 isl_msaa_interleaved_scale_px_to_sa(uint32_t samples,
1221 uint32_t *width, uint32_t *height)
1222 {
1223 const struct isl_extent2d px_size_sa =
1224 isl_get_interleaved_msaa_px_size_sa(samples);
1225
1226 if (width)
1227 *width = isl_align(*width, 2) * px_size_sa.width;
1228 if (height)
1229 *height = isl_align(*height, 2) * px_size_sa.height;
1230 }
1231
1232 static enum isl_array_pitch_span
isl_choose_array_pitch_span(const struct isl_device * dev,const struct isl_surf_init_info * restrict info,enum isl_dim_layout dim_layout,const struct isl_extent4d * phys_level0_sa)1233 isl_choose_array_pitch_span(const struct isl_device *dev,
1234 const struct isl_surf_init_info *restrict info,
1235 enum isl_dim_layout dim_layout,
1236 const struct isl_extent4d *phys_level0_sa)
1237 {
1238 switch (dim_layout) {
1239 case ISL_DIM_LAYOUT_GFX9_1D:
1240 case ISL_DIM_LAYOUT_GFX4_2D:
1241 if (ISL_GFX_VER(dev) >= 8) {
1242 /* QPitch becomes programmable in Broadwell. So choose the
1243 * most compact QPitch possible in order to conserve memory.
1244 *
1245 * From the Broadwell PRM >> Volume 2d: Command Reference: Structures
1246 * >> RENDER_SURFACE_STATE Surface QPitch (p325):
1247 *
1248 * - Software must ensure that this field is set to a value
1249 * sufficiently large such that the array slices in the surface
1250 * do not overlap. Refer to the Memory Data Formats section for
1251 * information on how surfaces are stored in memory.
1252 *
1253 * - This field specifies the distance in rows between array
1254 * slices. It is used only in the following cases:
1255 *
1256 * - Surface Array is enabled OR
1257 * - Number of Mulitsamples is not NUMSAMPLES_1 and
1258 * Multisampled Surface Storage Format set to MSFMT_MSS OR
1259 * - Surface Type is SURFTYPE_CUBE
1260 */
1261 return ISL_ARRAY_PITCH_SPAN_COMPACT;
1262 } else if (ISL_GFX_VER(dev) >= 7) {
1263 /* Note that Ivybridge introduces
1264 * RENDER_SURFACE_STATE.SurfaceArraySpacing, which provides the
1265 * driver more control over the QPitch.
1266 */
1267
1268 if (phys_level0_sa->array_len == 1) {
1269 /* The hardware will never use the QPitch. So choose the most
1270 * compact QPitch possible in order to conserve memory.
1271 */
1272 return ISL_ARRAY_PITCH_SPAN_COMPACT;
1273 }
1274
1275 if (isl_surf_usage_is_depth_or_stencil(info->usage) ||
1276 (info->usage & ISL_SURF_USAGE_HIZ_BIT)) {
1277 /* From the Ivybridge PRM >> Volume 1 Part 1: Graphics Core >>
1278 * Section 6.18.4.7: Surface Arrays (p112):
1279 *
1280 * If Surface Array Spacing is set to ARYSPC_FULL (note that
1281 * the depth buffer and stencil buffer have an implied value of
1282 * ARYSPC_FULL):
1283 */
1284 return ISL_ARRAY_PITCH_SPAN_FULL;
1285 }
1286
1287 if (info->levels == 1) {
1288 /* We are able to set RENDER_SURFACE_STATE.SurfaceArraySpacing
1289 * to ARYSPC_LOD0.
1290 */
1291 return ISL_ARRAY_PITCH_SPAN_COMPACT;
1292 }
1293
1294 return ISL_ARRAY_PITCH_SPAN_FULL;
1295 } else if ((ISL_GFX_VER(dev) == 5 || ISL_GFX_VER(dev) == 6) &&
1296 ISL_DEV_USE_SEPARATE_STENCIL(dev) &&
1297 isl_surf_usage_is_stencil(info->usage)) {
1298 /* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
1299 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
1300 *
1301 * The separate stencil buffer does not support mip mapping, thus
1302 * the storage for LODs other than LOD 0 is not needed.
1303 */
1304 assert(info->levels == 1);
1305 return ISL_ARRAY_PITCH_SPAN_COMPACT;
1306 } else {
1307 if ((ISL_GFX_VER(dev) == 5 || ISL_GFX_VER(dev) == 6) &&
1308 ISL_DEV_USE_SEPARATE_STENCIL(dev) &&
1309 isl_surf_usage_is_stencil(info->usage)) {
1310 /* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
1311 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
1312 *
1313 * The separate stencil buffer does not support mip mapping,
1314 * thus the storage for LODs other than LOD 0 is not needed.
1315 */
1316 assert(info->levels == 1);
1317 assert(phys_level0_sa->array_len == 1);
1318 return ISL_ARRAY_PITCH_SPAN_COMPACT;
1319 }
1320
1321 if (phys_level0_sa->array_len == 1) {
1322 /* The hardware will never use the QPitch. So choose the most
1323 * compact QPitch possible in order to conserve memory.
1324 */
1325 return ISL_ARRAY_PITCH_SPAN_COMPACT;
1326 }
1327
1328 return ISL_ARRAY_PITCH_SPAN_FULL;
1329 }
1330
1331 case ISL_DIM_LAYOUT_GFX4_3D:
1332 /* The hardware will never use the QPitch. So choose the most
1333 * compact QPitch possible in order to conserve memory.
1334 */
1335 return ISL_ARRAY_PITCH_SPAN_COMPACT;
1336
1337 case ISL_DIM_LAYOUT_GFX6_STENCIL_HIZ:
1338 /* Each array image in the gfx6 stencil of HiZ surface is compact in the
1339 * sense that every LOD is a compact array of the same size as LOD0.
1340 */
1341 return ISL_ARRAY_PITCH_SPAN_COMPACT;
1342 }
1343
1344 unreachable("bad isl_dim_layout");
1345 return ISL_ARRAY_PITCH_SPAN_FULL;
1346 }
1347
1348 static void
isl_choose_image_alignment_el(const struct isl_device * dev,const struct isl_surf_init_info * restrict info,const struct isl_tile_info * tile_info,enum isl_dim_layout dim_layout,enum isl_msaa_layout msaa_layout,struct isl_extent3d * image_align_el)1349 isl_choose_image_alignment_el(const struct isl_device *dev,
1350 const struct isl_surf_init_info *restrict info,
1351 const struct isl_tile_info *tile_info,
1352 enum isl_dim_layout dim_layout,
1353 enum isl_msaa_layout msaa_layout,
1354 struct isl_extent3d *image_align_el)
1355 {
1356 enum isl_tiling tiling = tile_info->tiling;
1357 const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
1358 if (fmtl->txc == ISL_TXC_MCS) {
1359 /*
1360 * IvyBrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
1361 *
1362 * Height, width, and layout of MCS buffer in this case must match with
1363 * Render Target height, width, and layout. MCS buffer is tiledY.
1364 *
1365 * Pick a vertical and horizontal alignment that matches the main render
1366 * target. Vertical alignment is important for properly spacing an array
1367 * of MCS images. Horizontal alignment is not expected to matter because
1368 * MCS is not mipmapped. Regardless, we pick a valid value here.
1369 */
1370 if (ISL_GFX_VERX10(dev) >= 125) {
1371 *image_align_el = isl_extent3d(128 * 8 / fmtl->bpb, 4, 1);
1372 } else if (ISL_GFX_VER(dev) >= 8) {
1373 *image_align_el = isl_extent3d(16, 4, 1);
1374 } else {
1375 *image_align_el = isl_extent3d(4, 4, 1);
1376 }
1377 return;
1378 } else if (fmtl->txc == ISL_TXC_HIZ) {
1379 assert(ISL_GFX_VER(dev) >= 6);
1380 if (ISL_GFX_VER(dev) == 6) {
1381 /* HiZ surfaces on Sandy Bridge are packed tightly. */
1382 *image_align_el = isl_extent3d(1, 1, 1);
1383 } else if (ISL_GFX_VER(dev) < 12) {
1384 /* On gfx7+, HiZ surfaces are always aligned to 16x8 pixels in the
1385 * primary surface which works out to 2x2 HiZ elements.
1386 */
1387 *image_align_el = isl_extent3d(2, 2, 1);
1388 } else {
1389 /* We choose the alignments based on the docs and what we've seen on
1390 * prior platforms. From the TGL PRM Vol. 9, "Hierarchical Depth
1391 * Buffer":
1392 *
1393 * The height and width of the hierarchical depth buffer that must
1394 * be allocated are computed by the following formulas, where HZ
1395 * is the hierarchical depth buffer and Z is the depth buffer. The
1396 * Z_Height, Z_Width, and Z_Depth values given in these formulas
1397 * are those present in 3DSTATE_DEPTH_BUFFER incremented by one.
1398 *
1399 * The note about 3DSTATE_DEPTH_BUFFER tells us that the dimensions
1400 * in the following formula refers to the base level. The key formula
1401 * for the horizontal alignment is:
1402 *
1403 * HZ_Width (bytes) [=]
1404 * ceiling(Z_Width / 16) * 16
1405 *
1406 * This type of formula is used when sizing compression blocks. So,
1407 * the docs seem to say that the HiZ format has a block width of 16,
1408 * and thus, the surface has a minimum horizontal alignment of 16
1409 * pixels. This formula hasn't changed from prior platforms (where
1410 * we've chosen a horizontal alignment of 16), so we should be on the
1411 * right track. As for the vertical alignment, we're told:
1412 *
1413 * To compute the minimum QPitch for the HZ surface, the height of
1414 * each LOD in pixels is determined using the equations for hL in
1415 * the GPU Overview volume, using a vertical alignment j=16.
1416 *
1417 * We're not calculating the QPitch right now, but the vertical
1418 * alignment is plainly given as 16 rows in the depth buffer.
1419 *
1420 * As a result, we believe that HiZ surfaces are aligned to 16x16
1421 * pixels in the primary surface. We divide this area by the HiZ
1422 * block dimensions to get the alignment in terms of HiZ blocks.
1423 */
1424 *image_align_el = isl_extent3d(16 / fmtl->bw, 16 / fmtl->bh, 1);
1425 }
1426 return;
1427 }
1428
1429 if (ISL_GFX_VERX10(dev) >= 200) {
1430 isl_gfx20_choose_image_alignment_el(dev, info, tile_info, dim_layout,
1431 msaa_layout, image_align_el);
1432 } else if (ISL_GFX_VERX10(dev) >= 125) {
1433 isl_gfx125_choose_image_alignment_el(dev, info, tile_info, dim_layout,
1434 msaa_layout, image_align_el);
1435 } else if (ISL_GFX_VER(dev) >= 12) {
1436 isl_gfx12_choose_image_alignment_el(dev, info, tile_info, dim_layout,
1437 msaa_layout, image_align_el);
1438 } else if (ISL_GFX_VER(dev) >= 9) {
1439 isl_gfx9_choose_image_alignment_el(dev, info, tile_info, dim_layout,
1440 msaa_layout, image_align_el);
1441 } else if (ISL_GFX_VER(dev) >= 8) {
1442 isl_gfx8_choose_image_alignment_el(dev, info, tiling, dim_layout,
1443 msaa_layout, image_align_el);
1444 } else if (ISL_GFX_VER(dev) >= 7) {
1445 isl_gfx7_choose_image_alignment_el(dev, info, tiling, dim_layout,
1446 msaa_layout, image_align_el);
1447 } else if (ISL_GFX_VER(dev) >= 6) {
1448 isl_gfx6_choose_image_alignment_el(dev, info, tiling, dim_layout,
1449 msaa_layout, image_align_el);
1450 } else {
1451 isl_gfx4_choose_image_alignment_el(dev, info, tiling, dim_layout,
1452 msaa_layout, image_align_el);
1453 }
1454 }
1455
1456 static enum isl_dim_layout
isl_surf_choose_dim_layout(const struct isl_device * dev,enum isl_surf_dim logical_dim,enum isl_tiling tiling,isl_surf_usage_flags_t usage)1457 isl_surf_choose_dim_layout(const struct isl_device *dev,
1458 enum isl_surf_dim logical_dim,
1459 enum isl_tiling tiling,
1460 isl_surf_usage_flags_t usage)
1461 {
1462 /* Sandy bridge needs a special layout for HiZ and stencil. */
1463 if (ISL_GFX_VER(dev) == 6 &&
1464 (tiling == ISL_TILING_W || tiling == ISL_TILING_HIZ))
1465 return ISL_DIM_LAYOUT_GFX6_STENCIL_HIZ;
1466
1467 if (ISL_GFX_VER(dev) >= 9) {
1468 switch (logical_dim) {
1469 case ISL_SURF_DIM_1D:
1470 /* From the Sky Lake PRM Vol. 5, "1D Surfaces":
1471 *
1472 * One-dimensional surfaces use a tiling mode of linear.
1473 * Technically, they are not tiled resources, but the Tiled
1474 * Resource Mode field in RENDER_SURFACE_STATE is still used to
1475 * indicate the alignment requirements for this linear surface
1476 * (See 1D Alignment requirements for how 4K and 64KB Tiled
1477 * Resource Modes impact alignment). Alternatively, a 1D surface
1478 * can be defined as a 2D tiled surface (e.g. TileY or TileX) with
1479 * a height of 0.
1480 *
1481 * In other words, ISL_DIM_LAYOUT_GFX9_1D is only used for linear
1482 * surfaces and, for tiled surfaces, ISL_DIM_LAYOUT_GFX4_2D is used.
1483 */
1484 if (tiling == ISL_TILING_LINEAR)
1485 return ISL_DIM_LAYOUT_GFX9_1D;
1486 else
1487 return ISL_DIM_LAYOUT_GFX4_2D;
1488 case ISL_SURF_DIM_2D:
1489 case ISL_SURF_DIM_3D:
1490 return ISL_DIM_LAYOUT_GFX4_2D;
1491 }
1492 } else {
1493 switch (logical_dim) {
1494 case ISL_SURF_DIM_1D:
1495 case ISL_SURF_DIM_2D:
1496 /* From the G45 PRM Vol. 1a, "6.17.4.1 Hardware Cube Map Layout":
1497 *
1498 * The cube face textures are stored in the same way as 3D surfaces
1499 * are stored (see section 6.17.5 for details). For cube surfaces,
1500 * however, the depth is equal to the number of faces (always 6) and
1501 * is not reduced for each MIP.
1502 */
1503 if (ISL_GFX_VER(dev) == 4 && (usage & ISL_SURF_USAGE_CUBE_BIT))
1504 return ISL_DIM_LAYOUT_GFX4_3D;
1505
1506 return ISL_DIM_LAYOUT_GFX4_2D;
1507 case ISL_SURF_DIM_3D:
1508 return ISL_DIM_LAYOUT_GFX4_3D;
1509 }
1510 }
1511
1512 unreachable("bad isl_surf_dim");
1513 return ISL_DIM_LAYOUT_GFX4_2D;
1514 }
1515
1516 /**
1517 * Calculate the physical extent of the surface's first level, in units of
1518 * surface samples.
1519 */
1520 static void
isl_calc_phys_level0_extent_sa(const struct isl_device * dev,const struct isl_surf_init_info * restrict info,enum isl_dim_layout dim_layout,enum isl_tiling tiling,enum isl_msaa_layout msaa_layout,struct isl_extent4d * phys_level0_sa)1521 isl_calc_phys_level0_extent_sa(const struct isl_device *dev,
1522 const struct isl_surf_init_info *restrict info,
1523 enum isl_dim_layout dim_layout,
1524 enum isl_tiling tiling,
1525 enum isl_msaa_layout msaa_layout,
1526 struct isl_extent4d *phys_level0_sa)
1527 {
1528 const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
1529
1530 if (isl_format_is_planar(info->format))
1531 unreachable("Planar formats unsupported");
1532
1533 switch (info->dim) {
1534 case ISL_SURF_DIM_1D:
1535 assert(info->height == 1);
1536 assert(info->depth == 1);
1537 assert(info->samples == 1);
1538
1539 switch (dim_layout) {
1540 case ISL_DIM_LAYOUT_GFX4_3D:
1541 unreachable("bad isl_dim_layout");
1542
1543 case ISL_DIM_LAYOUT_GFX9_1D:
1544 case ISL_DIM_LAYOUT_GFX4_2D:
1545 case ISL_DIM_LAYOUT_GFX6_STENCIL_HIZ:
1546 *phys_level0_sa = (struct isl_extent4d) {
1547 .w = info->width,
1548 .h = 1,
1549 .d = 1,
1550 .a = info->array_len,
1551 };
1552 break;
1553 }
1554 break;
1555
1556 case ISL_SURF_DIM_2D:
1557 if (ISL_GFX_VER(dev) == 4 && (info->usage & ISL_SURF_USAGE_CUBE_BIT))
1558 assert(dim_layout == ISL_DIM_LAYOUT_GFX4_3D);
1559 else
1560 assert(dim_layout == ISL_DIM_LAYOUT_GFX4_2D ||
1561 dim_layout == ISL_DIM_LAYOUT_GFX6_STENCIL_HIZ);
1562
1563 switch (msaa_layout) {
1564 case ISL_MSAA_LAYOUT_NONE:
1565 assert(info->depth == 1);
1566 assert(info->samples == 1);
1567
1568 *phys_level0_sa = (struct isl_extent4d) {
1569 .w = info->width,
1570 .h = info->height,
1571 .d = 1,
1572 .a = info->array_len,
1573 };
1574 break;
1575
1576 case ISL_MSAA_LAYOUT_ARRAY:
1577 assert(info->depth == 1);
1578 assert(info->levels == 1);
1579 assert(isl_format_supports_multisampling(dev->info, info->format));
1580 assert(fmtl->bw == 1 && fmtl->bh == 1);
1581
1582 *phys_level0_sa = (struct isl_extent4d) {
1583 .w = info->width,
1584 .h = info->height,
1585 .d = 1,
1586 .a = info->array_len * info->samples,
1587 };
1588 break;
1589
1590 case ISL_MSAA_LAYOUT_INTERLEAVED:
1591 assert(info->depth == 1);
1592 assert(info->levels == 1);
1593 assert(isl_format_supports_multisampling(dev->info, info->format));
1594
1595 *phys_level0_sa = (struct isl_extent4d) {
1596 .w = info->width,
1597 .h = info->height,
1598 .d = 1,
1599 .a = info->array_len,
1600 };
1601
1602 isl_msaa_interleaved_scale_px_to_sa(info->samples,
1603 &phys_level0_sa->w,
1604 &phys_level0_sa->h);
1605 break;
1606 }
1607 break;
1608
1609 case ISL_SURF_DIM_3D:
1610 assert(info->array_len == 1);
1611 assert(info->samples == 1);
1612
1613 if (fmtl->bd > 1) {
1614 isl_finishme("%s:%s: compression block with depth > 1",
1615 __FILE__, __func__);
1616 }
1617
1618 switch (dim_layout) {
1619 case ISL_DIM_LAYOUT_GFX9_1D:
1620 case ISL_DIM_LAYOUT_GFX6_STENCIL_HIZ:
1621 unreachable("bad isl_dim_layout");
1622
1623 case ISL_DIM_LAYOUT_GFX4_2D:
1624 case ISL_DIM_LAYOUT_GFX4_3D:
1625 *phys_level0_sa = (struct isl_extent4d) {
1626 .w = info->width,
1627 .h = info->height,
1628 .d = info->depth,
1629 .a = 1,
1630 };
1631 break;
1632 }
1633 break;
1634 }
1635 }
1636
1637 static void
isl_get_miptail_level_offset_el(enum isl_tiling tiling,enum isl_surf_dim dim,uint32_t format_bpb,uint32_t level,uint32_t * x_offset_el,uint32_t * y_offset_el,uint32_t * z_offset_el)1638 isl_get_miptail_level_offset_el(enum isl_tiling tiling,
1639 enum isl_surf_dim dim,
1640 uint32_t format_bpb,
1641 uint32_t level,
1642 uint32_t *x_offset_el,
1643 uint32_t *y_offset_el,
1644 uint32_t *z_offset_el)
1645 {
1646 uint32_t row = isl_get_miptail_base_row(tiling) + level;
1647 uint32_t col = 8 - ffs(format_bpb);
1648
1649 switch (dim) {
1650 case ISL_SURF_DIM_2D:
1651 switch (tiling) {
1652 case ISL_TILING_64:
1653 case ISL_TILING_64_XE2:
1654 case ISL_TILING_ICL_Yf:
1655 case ISL_TILING_ICL_Ys:
1656 assert(row < ARRAY_SIZE(icl_std_y_2d_miptail_offset_el));
1657 assert(col < ARRAY_SIZE(icl_std_y_2d_miptail_offset_el[0]));
1658 *x_offset_el = icl_std_y_2d_miptail_offset_el[row][col][0];
1659 *y_offset_el = icl_std_y_2d_miptail_offset_el[row][col][1];
1660 break;
1661 case ISL_TILING_SKL_Yf:
1662 case ISL_TILING_SKL_Ys:
1663 assert(row < ARRAY_SIZE(skl_std_y_2d_miptail_offset_el));
1664 assert(col < ARRAY_SIZE(skl_std_y_2d_miptail_offset_el[0]));
1665 *x_offset_el = skl_std_y_2d_miptail_offset_el[row][col][0];
1666 *y_offset_el = skl_std_y_2d_miptail_offset_el[row][col][1];
1667 break;
1668 default:
1669 unreachable("invalid tiling");
1670 }
1671 *z_offset_el = 0;
1672 break;
1673
1674 case ISL_SURF_DIM_3D:
1675 switch (tiling) {
1676 case ISL_TILING_64:
1677 case ISL_TILING_64_XE2:
1678 assert(row < ARRAY_SIZE(acm_tile64_3d_miptail_offset_el));
1679 assert(col < ARRAY_SIZE(acm_tile64_3d_miptail_offset_el[0]));
1680 *x_offset_el = acm_tile64_3d_miptail_offset_el[row][col][0];
1681 *y_offset_el = acm_tile64_3d_miptail_offset_el[row][col][1];
1682 *z_offset_el = acm_tile64_3d_miptail_offset_el[row][col][2];
1683 break;
1684 case ISL_TILING_ICL_Yf:
1685 case ISL_TILING_ICL_Ys:
1686 assert(row < ARRAY_SIZE(icl_std_y_3d_miptail_offset_el));
1687 assert(col < ARRAY_SIZE(icl_std_y_3d_miptail_offset_el[0]));
1688 *x_offset_el = icl_std_y_3d_miptail_offset_el[row][col][0];
1689 *y_offset_el = icl_std_y_3d_miptail_offset_el[row][col][1];
1690 *z_offset_el = icl_std_y_3d_miptail_offset_el[row][col][2];
1691 break;
1692 case ISL_TILING_SKL_Yf:
1693 case ISL_TILING_SKL_Ys:
1694 assert(row < ARRAY_SIZE(skl_std_y_3d_miptail_offset_el));
1695 assert(col < ARRAY_SIZE(skl_std_y_3d_miptail_offset_el[0]));
1696 *x_offset_el = skl_std_y_3d_miptail_offset_el[row][col][0];
1697 *y_offset_el = skl_std_y_3d_miptail_offset_el[row][col][1];
1698 *z_offset_el = skl_std_y_3d_miptail_offset_el[row][col][2];
1699 break;
1700 default:
1701 unreachable("invalid tiling");
1702 }
1703 break;
1704
1705 case ISL_SURF_DIM_1D:
1706 unreachable("invalid dimension");
1707 }
1708 }
1709
1710 static uint32_t
isl_choose_miptail_start_level(const struct isl_device * dev,const struct isl_surf_init_info * restrict info,const struct isl_tile_info * tile_info)1711 isl_choose_miptail_start_level(const struct isl_device *dev,
1712 const struct isl_surf_init_info *restrict info,
1713 const struct isl_tile_info *tile_info)
1714 {
1715 const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
1716
1717 if (tile_info->max_miptail_levels == 0)
1718 return info->levels;
1719
1720 /* SKL PRMs, Volume 5: Memory Views, YUV 4:2:0 Format Memory Organization :
1721 *
1722 * "Planar YUV does not support MIP Tails as part of Standard Tiling.
1723 * The MIP Tail Start field in RENDER_SURFACE_STATE must be programmed
1724 * to 15."
1725 */
1726 if (isl_format_is_planar(info->format))
1727 return 15;
1728
1729 /* TODO: figure out why having YUV formats in the miptail on Gfx12 does not
1730 * work.
1731 */
1732 if (ISL_GFX_VER(dev) == 12 && isl_format_is_yuv(info->format))
1733 return 15;
1734
1735 if (intel_needs_workaround(dev->info, 22015614752) &&
1736 (info->usage & ISL_SURF_USAGE_MULTI_ENGINE_PAR_BIT) &&
1737 _isl_surf_info_supports_ccs(dev, info->format, info->usage)) {
1738 /* There are issues with multiple engines accessing the same CCS
1739 * cacheline in parallel. If we're here, Tile64 is use, providing enough
1740 * spacing between each miplevel. We must disable miptails to maintain
1741 * the necessary alignment between miplevels.
1742 */
1743 assert(tile_info->tiling == ISL_TILING_64);
1744 return 15;
1745 }
1746
1747 if ((ISL_GFX_VER(dev) == 9 ||
1748 intel_needs_workaround(dev->info, 1207137018)) &&
1749 info->dim == ISL_SURF_DIM_3D &&
1750 isl_tiling_is_std_y(tile_info->tiling) &&
1751 _isl_surf_info_supports_ccs(dev, info->format, info->usage)) {
1752 /* From the workarounds section in the SKL PRM:
1753 *
1754 * "RCC cacheline is composed of X-adjacent 64B fragments instead of
1755 * memory adjacent. This causes a single 128B cacheline to straddle
1756 * multiple LODs inside the TYF MIPtail for 3D surfaces (beyond a
1757 * certain slot number), leading to corruption when CCS is enabled
1758 * for these LODs and RT is later bound as texture. WA: If
1759 * RENDER_SURFACE_STATE.Surface Type = 3D and
1760 * RENDER_SURFACE_STATE.Auxiliary Surface Mode != AUX_NONE and
1761 * RENDER_SURFACE_STATE.Tiled ResourceMode is TYF or TYS, Set the
1762 * value of RENDER_SURFACE_STATE.Mip Tail Start LOD to a mip that
1763 * larger than those present in the surface (i.e. 15)"
1764 *
1765 * Referred to as Wa_1207137018 on ICL+. Disable miptails as suggested.
1766 */
1767 return 15;
1768 }
1769
1770 assert(isl_tiling_is_64(tile_info->tiling) ||
1771 isl_tiling_is_std_y(tile_info->tiling));
1772 assert(info->samples == 1);
1773
1774 uint32_t max_miptail_levels = tile_info->max_miptail_levels;
1775
1776 if (max_miptail_levels > 11 &&
1777 _isl_surf_info_supports_ccs(dev, info->format, info->usage)) {
1778 /* SKL PRMs, Volume 5: Memory Views, Tiling and Mip Tails for 2D
1779 * Surfaces:
1780 *
1781 * "Lossless compression must not be used on surfaces which have MIP
1782 * Tail which contains MIPs for Slots greater than 11."
1783 *
1784 * Reduce the slot consumption to keep compression enabled.
1785 */
1786 max_miptail_levels = 11;
1787 }
1788
1789 /* Start with the minimum number of levels that will fit in the tile */
1790 uint32_t min_miptail_start =
1791 info->levels > max_miptail_levels ? info->levels - max_miptail_levels : 0;
1792
1793 /* Account for the specified minimum */
1794 min_miptail_start = MAX(min_miptail_start, info->min_miptail_start_level);
1795
1796 struct isl_extent3d level0_extent_el = {
1797 .w = isl_align_div_npot(info->width, fmtl->bw),
1798 .h = isl_align_div_npot(info->height, fmtl->bh),
1799 .d = isl_align_div_npot(info->depth, fmtl->bd),
1800 };
1801
1802 /* The first miptail slot takes up the entire right side of the tile. So,
1803 * the extent is just the distance from the offset of the first level to
1804 * the corner of the tile.
1805 */
1806 uint32_t level0_x_offset_el, level0_y_offset_el, level0_z_offset_el;
1807 isl_get_miptail_level_offset_el(tile_info->tiling, info->dim,
1808 fmtl->bpb, 0, /* level */
1809 &level0_x_offset_el,
1810 &level0_y_offset_el,
1811 &level0_z_offset_el);
1812 struct isl_extent3d miptail_level0_extent_el = {
1813 .w = tile_info->logical_extent_el.w - level0_x_offset_el,
1814 .h = tile_info->logical_extent_el.h - level0_y_offset_el,
1815 .d = tile_info->logical_extent_el.d - level0_z_offset_el,
1816 };
1817
1818 /* Now find the first level that fits the maximum miptail size requirement.
1819 */
1820 for (uint32_t s = min_miptail_start; s < info->levels; s++) {
1821 if (isl_minify(level0_extent_el.w, s) <= miptail_level0_extent_el.w &&
1822 isl_minify(level0_extent_el.h, s) <= miptail_level0_extent_el.h &&
1823 isl_minify(level0_extent_el.d, s) <= miptail_level0_extent_el.d)
1824 return s;
1825 }
1826
1827 return info->levels;
1828 }
1829
1830 /**
1831 * Calculate the pitch between physical array slices, in units of rows of
1832 * surface elements.
1833 */
1834 static uint32_t
isl_calc_array_pitch_el_rows_gfx4_2d(const struct isl_device * dev,const struct isl_surf_init_info * restrict info,const struct isl_tile_info * tile_info,const struct isl_extent3d * image_align_sa,const struct isl_extent4d * phys_level0_sa,enum isl_array_pitch_span array_pitch_span,const struct isl_extent2d * phys_slice0_sa)1835 isl_calc_array_pitch_el_rows_gfx4_2d(
1836 const struct isl_device *dev,
1837 const struct isl_surf_init_info *restrict info,
1838 const struct isl_tile_info *tile_info,
1839 const struct isl_extent3d *image_align_sa,
1840 const struct isl_extent4d *phys_level0_sa,
1841 enum isl_array_pitch_span array_pitch_span,
1842 const struct isl_extent2d *phys_slice0_sa)
1843 {
1844 const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
1845 uint32_t pitch_sa_rows = 0;
1846
1847 switch (array_pitch_span) {
1848 case ISL_ARRAY_PITCH_SPAN_COMPACT:
1849 pitch_sa_rows = isl_align_npot(phys_slice0_sa->h, image_align_sa->h);
1850 break;
1851 case ISL_ARRAY_PITCH_SPAN_FULL: {
1852 /* The QPitch equation is found in the Broadwell PRM >> Volume 5:
1853 * Memory Views >> Common Surface Formats >> Surface Layout >> 2D
1854 * Surfaces >> Surface Arrays.
1855 */
1856 uint32_t H0_sa = phys_level0_sa->h;
1857 uint32_t H1_sa = isl_minify(H0_sa, 1);
1858
1859 uint32_t h0_sa = isl_align_npot(H0_sa, image_align_sa->h);
1860 uint32_t h1_sa = isl_align_npot(H1_sa, image_align_sa->h);
1861
1862 uint32_t m;
1863 if (ISL_GFX_VER(dev) >= 7) {
1864 /* The QPitch equation changed slightly in Ivybridge. */
1865 m = 12;
1866 } else {
1867 m = 11;
1868 }
1869
1870 pitch_sa_rows = h0_sa + h1_sa + (m * image_align_sa->h);
1871
1872 if (ISL_GFX_VER(dev) == 6 && info->samples > 1 &&
1873 (info->height % 4 == 1)) {
1874 /* [SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
1875 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
1876 *
1877 * [SNB] Errata: Sampler MSAA Qpitch will be 4 greater than
1878 * the value calculated in the equation above , for every
1879 * other odd Surface Height starting from 1 i.e. 1,5,9,13.
1880 *
1881 * XXX(chadv): Is the errata natural corollary of the physical
1882 * layout of interleaved samples?
1883 */
1884 pitch_sa_rows += 4;
1885 }
1886
1887 pitch_sa_rows = isl_align_npot(pitch_sa_rows, fmtl->bh);
1888 } /* end case */
1889 break;
1890 }
1891
1892 assert(pitch_sa_rows % fmtl->bh == 0);
1893 uint32_t pitch_el_rows = pitch_sa_rows / fmtl->bh;
1894
1895 if (ISL_GFX_VER(dev) >= 9 && fmtl->txc == ISL_TXC_CCS) {
1896 /*
1897 * From the Sky Lake PRM Vol 7, "MCS Buffer for Render Target(s)" (p. 632):
1898 *
1899 * "Mip-mapped and arrayed surfaces are supported with MCS buffer
1900 * layout with these alignments in the RT space: Horizontal
1901 * Alignment = 128 and Vertical Alignment = 64."
1902 *
1903 * From the Sky Lake PRM Vol. 2d, "RENDER_SURFACE_STATE" (p. 435):
1904 *
1905 * "For non-multisampled render target's CCS auxiliary surface,
1906 * QPitch must be computed with Horizontal Alignment = 128 and
1907 * Surface Vertical Alignment = 256. These alignments are only for
1908 * CCS buffer and not for associated render target."
1909 *
1910 * The first restriction is already handled by isl_choose_image_alignment_el
1911 * but the second restriction, which is an extension of the first, only
1912 * applies to qpitch and must be applied here.
1913 */
1914 assert(fmtl->bh == 4);
1915 pitch_el_rows = isl_align(pitch_el_rows, 256 / 4);
1916 }
1917
1918 if (ISL_GFX_VER(dev) >= 9 &&
1919 info->dim == ISL_SURF_DIM_3D &&
1920 tile_info->tiling != ISL_TILING_LINEAR) {
1921 /* From the Skylake BSpec >> RENDER_SURFACE_STATE >> Surface QPitch:
1922 *
1923 * Tile Mode != Linear: This field must be set to an integer multiple
1924 * of the tile height
1925 */
1926 pitch_el_rows = isl_align(pitch_el_rows, tile_info->logical_extent_el.height);
1927 }
1928
1929 if (isl_surf_usage_is_depth(info->usage) &&
1930 _isl_surf_info_supports_ccs(dev, info->format, info->usage)) {
1931 /* From the TGL PRM, Vol 9, "Compressed Depth Buffers" (under the
1932 * "Texture performant" and "ZCS" columns):
1933 *
1934 * Update with clear at either 16x8 or 8x4 granularity, based on
1935 * fs_clr or otherwise.
1936 *
1937 * When fast-clearing, hardware behaves in unexpected ways if the clear
1938 * rectangle, aligned to 16x8, could cover neighboring LODs. Align the
1939 * array pitch to 8 in order to increase the number of aligned LODs.
1940 */
1941 pitch_el_rows = isl_align(pitch_el_rows, 8);
1942 }
1943
1944 return pitch_el_rows;
1945 }
1946
1947 /**
1948 * A variant of isl_calc_phys_slice0_extent_sa() specific to
1949 * ISL_DIM_LAYOUT_GFX4_2D.
1950 */
1951 static void
isl_calc_phys_slice0_extent_sa_gfx4_2d(const struct isl_device * dev,const struct isl_surf_init_info * restrict info,const struct isl_tile_info * tile_info,enum isl_msaa_layout msaa_layout,const struct isl_extent3d * image_align_sa,const struct isl_extent4d * phys_level0_sa,uint32_t miptail_start_level,struct isl_extent2d * phys_slice0_sa)1952 isl_calc_phys_slice0_extent_sa_gfx4_2d(
1953 const struct isl_device *dev,
1954 const struct isl_surf_init_info *restrict info,
1955 const struct isl_tile_info *tile_info,
1956 enum isl_msaa_layout msaa_layout,
1957 const struct isl_extent3d *image_align_sa,
1958 const struct isl_extent4d *phys_level0_sa,
1959 uint32_t miptail_start_level,
1960 struct isl_extent2d *phys_slice0_sa)
1961 {
1962 ASSERTED const struct isl_format_layout *fmtl =
1963 isl_format_get_layout(info->format);
1964
1965 if (info->levels == 1 && miptail_start_level > 0) {
1966 /* Do not pad the surface to the image alignment.
1967 *
1968 * For tiled surfaces, using a reduced alignment here avoids wasting CPU
1969 * cycles on the below mipmap layout caluclations. Reducing the
1970 * alignment here is safe because we later align the row pitch and array
1971 * pitch to the tile boundary. It is safe even for
1972 * ISL_MSAA_LAYOUT_INTERLEAVED, because phys_level0_sa is already scaled
1973 * to accommodate the interleaved samples.
1974 *
1975 * For linear surfaces, reducing the alignment here permits us to later
1976 * choose an arbitrary, non-aligned row pitch. If the surface backs
1977 * a VkBuffer, then an arbitrary pitch may be needed to accommodate
1978 * VkBufferImageCopy::bufferRowLength.
1979 */
1980 *phys_slice0_sa = (struct isl_extent2d) {
1981 .w = phys_level0_sa->w,
1982 .h = phys_level0_sa->h,
1983 };
1984 return;
1985 }
1986
1987 uint32_t slice_top_w = 0;
1988 uint32_t slice_bottom_w = 0;
1989 uint32_t slice_left_h = 0;
1990 uint32_t slice_right_h = 0;
1991
1992 uint32_t W0 = phys_level0_sa->w;
1993 uint32_t H0 = phys_level0_sa->h;
1994
1995 for (uint32_t l = 0; l < info->levels; ++l) {
1996 uint32_t W = isl_minify(W0, l);
1997 uint32_t H = isl_minify(H0, l);
1998
1999 uint32_t w = isl_align_npot(W, image_align_sa->w);
2000 uint32_t h = isl_align_npot(H, image_align_sa->h);
2001
2002 if (l == 0) {
2003 slice_top_w = w;
2004 slice_left_h = h;
2005 slice_right_h = h;
2006 } else if (l == 1) {
2007 slice_bottom_w = w;
2008 slice_left_h += h;
2009 } else if (l == 2) {
2010 slice_bottom_w += w;
2011 slice_right_h += h;
2012 } else {
2013 slice_right_h += h;
2014 }
2015
2016 if (l >= miptail_start_level) {
2017 assert(l == miptail_start_level);
2018 assert(isl_tiling_is_64(tile_info->tiling) ||
2019 isl_tiling_is_std_y(tile_info->tiling));
2020 assert(w == tile_info->logical_extent_el.w * fmtl->bw);
2021 assert(h == tile_info->logical_extent_el.h * fmtl->bh);
2022 /* If we've gone into the miptail, we're done. All higher miplevels
2023 * will be tucked into the same tile as this one.
2024 */
2025 break;
2026 }
2027 }
2028
2029 *phys_slice0_sa = (struct isl_extent2d) {
2030 .w = MAX(slice_top_w, slice_bottom_w),
2031 .h = MAX(slice_left_h, slice_right_h),
2032 };
2033 }
2034
2035 static void
isl_calc_phys_total_extent_el_gfx4_2d(const struct isl_device * dev,const struct isl_surf_init_info * restrict info,const struct isl_tile_info * tile_info,enum isl_msaa_layout msaa_layout,const struct isl_extent3d * image_align_sa,const struct isl_extent4d * phys_level0_sa,enum isl_array_pitch_span array_pitch_span,uint32_t miptail_start_level,uint32_t * array_pitch_el_rows,struct isl_extent4d * phys_total_el)2036 isl_calc_phys_total_extent_el_gfx4_2d(
2037 const struct isl_device *dev,
2038 const struct isl_surf_init_info *restrict info,
2039 const struct isl_tile_info *tile_info,
2040 enum isl_msaa_layout msaa_layout,
2041 const struct isl_extent3d *image_align_sa,
2042 const struct isl_extent4d *phys_level0_sa,
2043 enum isl_array_pitch_span array_pitch_span,
2044 uint32_t miptail_start_level,
2045 uint32_t *array_pitch_el_rows,
2046 struct isl_extent4d *phys_total_el)
2047 {
2048 const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
2049
2050 struct isl_extent2d phys_slice0_sa;
2051 isl_calc_phys_slice0_extent_sa_gfx4_2d(dev, info, tile_info, msaa_layout,
2052 image_align_sa, phys_level0_sa,
2053 miptail_start_level,
2054 &phys_slice0_sa);
2055 *array_pitch_el_rows =
2056 isl_calc_array_pitch_el_rows_gfx4_2d(dev, info, tile_info,
2057 image_align_sa, phys_level0_sa,
2058 array_pitch_span,
2059 &phys_slice0_sa);
2060
2061 if (isl_tiling_is_64(tile_info->tiling) ||
2062 isl_tiling_is_std_y(tile_info->tiling)) {
2063 *phys_total_el = (struct isl_extent4d) {
2064 .w = isl_align_div_npot(phys_slice0_sa.w, fmtl->bw),
2065 .h = isl_align_div_npot(phys_slice0_sa.h, fmtl->bh),
2066 .d = isl_align_div_npot(phys_level0_sa->d, fmtl->bd),
2067 .a = phys_level0_sa->array_len,
2068 };
2069 } else {
2070 uint32_t array_len = MAX(phys_level0_sa->d, phys_level0_sa->a);
2071 *phys_total_el = (struct isl_extent4d) {
2072 .w = isl_align_div_npot(phys_slice0_sa.w, fmtl->bw),
2073 .h = *array_pitch_el_rows * (array_len - 1) +
2074 isl_align_div_npot(phys_slice0_sa.h, fmtl->bh),
2075 .d = 1,
2076 .a = 1,
2077 };
2078 }
2079 }
2080
2081 /**
2082 * A variant of isl_calc_phys_slice0_extent_sa() specific to
2083 * ISL_DIM_LAYOUT_GFX4_3D.
2084 */
2085 static void
isl_calc_phys_total_extent_el_gfx4_3d(const struct isl_device * dev,const struct isl_surf_init_info * restrict info,const struct isl_extent3d * image_align_sa,const struct isl_extent4d * phys_level0_sa,uint32_t * array_pitch_el_rows,struct isl_extent4d * phys_total_el)2086 isl_calc_phys_total_extent_el_gfx4_3d(
2087 const struct isl_device *dev,
2088 const struct isl_surf_init_info *restrict info,
2089 const struct isl_extent3d *image_align_sa,
2090 const struct isl_extent4d *phys_level0_sa,
2091 uint32_t *array_pitch_el_rows,
2092 struct isl_extent4d *phys_total_el)
2093 {
2094 const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
2095
2096 assert(info->samples == 1);
2097
2098 if (info->dim != ISL_SURF_DIM_3D) {
2099 /* From the G45 PRM Vol. 1a, "6.17.4.1 Hardware Cube Map Layout":
2100 *
2101 * The cube face textures are stored in the same way as 3D surfaces
2102 * are stored (see section 6.17.5 for details). For cube surfaces,
2103 * however, the depth is equal to the number of faces (always 6) and
2104 * is not reduced for each MIP.
2105 */
2106 assert(ISL_GFX_VER(dev) == 4);
2107 assert(info->usage & ISL_SURF_USAGE_CUBE_BIT);
2108 assert(phys_level0_sa->array_len == 6);
2109 } else {
2110 assert(phys_level0_sa->array_len == 1);
2111 }
2112
2113 uint32_t total_w = 0;
2114 uint32_t total_h = 0;
2115
2116 uint32_t W0 = phys_level0_sa->w;
2117 uint32_t H0 = phys_level0_sa->h;
2118 uint32_t D0 = phys_level0_sa->d;
2119 uint32_t A0 = phys_level0_sa->a;
2120
2121 for (uint32_t l = 0; l < info->levels; ++l) {
2122 uint32_t level_w = isl_align_npot(isl_minify(W0, l), image_align_sa->w);
2123 uint32_t level_h = isl_align_npot(isl_minify(H0, l), image_align_sa->h);
2124 uint32_t level_d = info->dim == ISL_SURF_DIM_3D ? isl_minify(D0, l) : A0;
2125
2126 uint32_t max_layers_horiz = MIN(level_d, 1u << l);
2127 uint32_t max_layers_vert = isl_align(level_d, 1u << l) / (1u << l);
2128
2129 total_w = MAX(total_w, level_w * max_layers_horiz);
2130 total_h += level_h * max_layers_vert;
2131 }
2132
2133 /* GFX4_3D layouts don't really have an array pitch since each LOD has a
2134 * different number of horizontal and vertical layers. We have to set it
2135 * to something, so at least make it true for LOD0.
2136 */
2137 *array_pitch_el_rows =
2138 isl_align_npot(phys_level0_sa->h, image_align_sa->h) / fmtl->bw;
2139 *phys_total_el = (struct isl_extent4d) {
2140 .w = isl_assert_div(total_w, fmtl->bw),
2141 .h = isl_assert_div(total_h, fmtl->bh),
2142 .d = 1,
2143 .a = 1,
2144 };
2145 }
2146
2147 /**
2148 * A variant of isl_calc_phys_slice0_extent_sa() specific to
2149 * ISL_DIM_LAYOUT_GFX6_STENCIL_HIZ.
2150 */
2151 static void
isl_calc_phys_total_extent_el_gfx6_stencil_hiz(const struct isl_device * dev,const struct isl_surf_init_info * restrict info,const struct isl_tile_info * tile_info,const struct isl_extent3d * image_align_sa,const struct isl_extent4d * phys_level0_sa,uint32_t * array_pitch_el_rows,struct isl_extent4d * phys_total_el)2152 isl_calc_phys_total_extent_el_gfx6_stencil_hiz(
2153 const struct isl_device *dev,
2154 const struct isl_surf_init_info *restrict info,
2155 const struct isl_tile_info *tile_info,
2156 const struct isl_extent3d *image_align_sa,
2157 const struct isl_extent4d *phys_level0_sa,
2158 uint32_t *array_pitch_el_rows,
2159 struct isl_extent4d *phys_total_el)
2160 {
2161 const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
2162
2163 const struct isl_extent2d tile_extent_sa = {
2164 .w = tile_info->logical_extent_el.w * fmtl->bw,
2165 .h = tile_info->logical_extent_el.h * fmtl->bh,
2166 };
2167 /* Tile size is a multiple of image alignment */
2168 assert(tile_extent_sa.w % image_align_sa->w == 0);
2169 assert(tile_extent_sa.h % image_align_sa->h == 0);
2170
2171 const uint32_t W0 = phys_level0_sa->w;
2172 const uint32_t H0 = phys_level0_sa->h;
2173
2174 /* Each image has the same height as LOD0 because the hardware thinks
2175 * everything is LOD0
2176 */
2177 const uint32_t H = isl_align(H0, image_align_sa->h) * phys_level0_sa->a;
2178
2179 uint32_t total_top_w = 0;
2180 uint32_t total_bottom_w = 0;
2181 uint32_t total_h = 0;
2182
2183 for (uint32_t l = 0; l < info->levels; ++l) {
2184 const uint32_t W = isl_minify(W0, l);
2185
2186 const uint32_t w = isl_align(W, tile_extent_sa.w);
2187 const uint32_t h = isl_align(H, tile_extent_sa.h);
2188
2189 if (l == 0) {
2190 total_top_w = w;
2191 total_h = h;
2192 } else if (l == 1) {
2193 total_bottom_w = w;
2194 total_h += h;
2195 } else {
2196 total_bottom_w += w;
2197 }
2198 }
2199
2200 *array_pitch_el_rows =
2201 isl_assert_div(isl_align(H0, image_align_sa->h), fmtl->bh);
2202 *phys_total_el = (struct isl_extent4d) {
2203 .w = isl_assert_div(MAX(total_top_w, total_bottom_w), fmtl->bw),
2204 .h = isl_assert_div(total_h, fmtl->bh),
2205 .d = 1,
2206 .a = 1,
2207 };
2208 }
2209
2210 /**
2211 * A variant of isl_calc_phys_slice0_extent_sa() specific to
2212 * ISL_DIM_LAYOUT_GFX9_1D.
2213 */
2214 static void
isl_calc_phys_total_extent_el_gfx9_1d(const struct isl_device * dev,const struct isl_surf_init_info * restrict info,const struct isl_extent3d * image_align_sa,const struct isl_extent4d * phys_level0_sa,uint32_t * array_pitch_el_rows,struct isl_extent4d * phys_total_el)2215 isl_calc_phys_total_extent_el_gfx9_1d(
2216 const struct isl_device *dev,
2217 const struct isl_surf_init_info *restrict info,
2218 const struct isl_extent3d *image_align_sa,
2219 const struct isl_extent4d *phys_level0_sa,
2220 uint32_t *array_pitch_el_rows,
2221 struct isl_extent4d *phys_total_el)
2222 {
2223 const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
2224
2225 assert(phys_level0_sa->height == 1);
2226 assert(phys_level0_sa->depth == 1);
2227 assert(info->samples == 1);
2228 assert(image_align_sa->w >= fmtl->bw);
2229
2230 uint32_t slice_w = 0;
2231 const uint32_t W0 = phys_level0_sa->w;
2232
2233 for (uint32_t l = 0; l < info->levels; ++l) {
2234 uint32_t W = isl_minify(W0, l);
2235 uint32_t w = isl_align_npot(W, image_align_sa->w);
2236
2237 slice_w += w;
2238 }
2239
2240 *array_pitch_el_rows = 1;
2241 *phys_total_el = (struct isl_extent4d) {
2242 .w = isl_assert_div(slice_w, fmtl->bw),
2243 .h = phys_level0_sa->array_len,
2244 .d = 1,
2245 .a = 1,
2246 };
2247 }
2248
2249 /**
2250 * Calculate the two-dimensional total physical extent of the surface, in
2251 * units of surface elements.
2252 */
2253 static void
isl_calc_phys_total_extent_el(const struct isl_device * dev,const struct isl_surf_init_info * restrict info,const struct isl_tile_info * tile_info,enum isl_dim_layout dim_layout,enum isl_msaa_layout msaa_layout,const struct isl_extent3d * image_align_sa,const struct isl_extent4d * phys_level0_sa,enum isl_array_pitch_span array_pitch_span,uint32_t miptail_start_level,uint32_t * array_pitch_el_rows,struct isl_extent4d * phys_total_el)2254 isl_calc_phys_total_extent_el(const struct isl_device *dev,
2255 const struct isl_surf_init_info *restrict info,
2256 const struct isl_tile_info *tile_info,
2257 enum isl_dim_layout dim_layout,
2258 enum isl_msaa_layout msaa_layout,
2259 const struct isl_extent3d *image_align_sa,
2260 const struct isl_extent4d *phys_level0_sa,
2261 enum isl_array_pitch_span array_pitch_span,
2262 uint32_t miptail_start_level,
2263 uint32_t *array_pitch_el_rows,
2264 struct isl_extent4d *phys_total_el)
2265 {
2266 switch (dim_layout) {
2267 case ISL_DIM_LAYOUT_GFX9_1D:
2268 assert(array_pitch_span == ISL_ARRAY_PITCH_SPAN_COMPACT);
2269 isl_calc_phys_total_extent_el_gfx9_1d(dev, info,
2270 image_align_sa, phys_level0_sa,
2271 array_pitch_el_rows,
2272 phys_total_el);
2273 return;
2274 case ISL_DIM_LAYOUT_GFX4_2D:
2275 isl_calc_phys_total_extent_el_gfx4_2d(dev, info, tile_info, msaa_layout,
2276 image_align_sa, phys_level0_sa,
2277 array_pitch_span,
2278 miptail_start_level,
2279 array_pitch_el_rows,
2280 phys_total_el);
2281 return;
2282 case ISL_DIM_LAYOUT_GFX6_STENCIL_HIZ:
2283 assert(array_pitch_span == ISL_ARRAY_PITCH_SPAN_COMPACT);
2284 isl_calc_phys_total_extent_el_gfx6_stencil_hiz(dev, info, tile_info,
2285 image_align_sa,
2286 phys_level0_sa,
2287 array_pitch_el_rows,
2288 phys_total_el);
2289 return;
2290 case ISL_DIM_LAYOUT_GFX4_3D:
2291 assert(array_pitch_span == ISL_ARRAY_PITCH_SPAN_COMPACT);
2292 isl_calc_phys_total_extent_el_gfx4_3d(dev, info,
2293 image_align_sa, phys_level0_sa,
2294 array_pitch_el_rows,
2295 phys_total_el);
2296 return;
2297 }
2298
2299 unreachable("invalid value for dim_layout");
2300 }
2301
2302 static uint32_t
isl_calc_row_pitch_alignment(const struct isl_device * dev,const struct isl_surf_init_info * surf_info,const struct isl_tile_info * tile_info)2303 isl_calc_row_pitch_alignment(const struct isl_device *dev,
2304 const struct isl_surf_init_info *surf_info,
2305 const struct isl_tile_info *tile_info)
2306 {
2307 if (tile_info->tiling != ISL_TILING_LINEAR) {
2308
2309 /* On gfx12, aligning to 512B may be wanted or needed for CCS_E. */
2310 if (ISL_GFX_VER(dev) == 12 && surf_info->samples == 1 &&
2311 !isl_surf_usage_is_depth_or_stencil(surf_info->usage) &&
2312 _isl_surf_info_supports_ccs(dev, surf_info->format,
2313 surf_info->usage) &&
2314 tile_info->tiling != ISL_TILING_X &&
2315 surf_info->row_pitch_B == 0) {
2316
2317 /* From Bspec 49252, Render Decompression:
2318 *
2319 * "Compressed displayable surfaces must be 16KB aligned and have
2320 * pitches padded to multiple of 4 tiles."
2321 *
2322 * Only consider padding the pitch when the caller has specified no
2323 * pitch. isl_surf_supports_ccs() will confirm that the main surface
2324 * pitch matches CCS expectations.
2325 */
2326 if (isl_surf_usage_is_display(surf_info->usage)) {
2327 assert(tile_info->phys_extent_B.width == 128);
2328 return 512;
2329 }
2330
2331 /* On gfx12.0, CCS fast clears don't seem to cover the correct
2332 * portion of the aux buffer when the pitch is not 512B-aligned. Pad
2333 * the pitch unless Wa_18020603990 applies (slow clear surfaces up
2334 * to 256x256, 32bpp). isl_surf_supports_ccs() won't confirm this
2335 * alignment, so drivers must fall back to slow clears as needed.
2336 */
2337 if (ISL_GFX_VERX10(dev) == 120) {
2338 assert(intel_needs_workaround(dev->info, 18020603990));
2339 if (tile_info->format_bpb > 32 ||
2340 surf_info->width > 256 ||
2341 surf_info->height > 256) {
2342 assert(tile_info->phys_extent_B.width == 128);
2343 return 512;
2344 }
2345 }
2346 }
2347
2348 return tile_info->phys_extent_B.width;
2349 }
2350
2351 /* We only support tiled fragment shading rate buffers. */
2352 assert((surf_info->usage & ISL_SURF_USAGE_CPB_BIT) == 0);
2353
2354 /* From the Broadwel PRM >> Volume 2d: Command Reference: Structures >>
2355 * RENDER_SURFACE_STATE Surface Pitch (p349):
2356 *
2357 * - For linear render target surfaces and surfaces accessed with the
2358 * typed data port messages, the pitch must be a multiple of the
2359 * element size for non-YUV surface formats. Pitch must be
2360 * a multiple of 2 * element size for YUV surface formats.
2361 *
2362 * - [Requirements for SURFTYPE_BUFFER and SURFTYPE_STRBUF, which we
2363 * ignore because isl doesn't do buffers.]
2364 *
2365 * - For other linear surfaces, the pitch can be any multiple of
2366 * bytes.
2367 */
2368 const struct isl_format_layout *fmtl = isl_format_get_layout(surf_info->format);
2369 const uint32_t bs = fmtl->bpb / 8;
2370 uint32_t alignment;
2371
2372 if (surf_info->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) {
2373 if (isl_format_is_yuv(surf_info->format)) {
2374 alignment = 2 * bs;
2375 } else {
2376 alignment = bs;
2377 }
2378 } else {
2379 alignment = 1;
2380 }
2381
2382 /* From the Broadwell PRM >> Volume 2c: Command Reference: Registers >>
2383 * PRI_STRIDE Stride (p1254):
2384 *
2385 * "When using linear memory, this must be at least 64 byte aligned."
2386 *
2387 * However, when displaying on NVIDIA and recent AMD GPUs via PRIME,
2388 * we need a larger pitch of 256 bytes.
2389 *
2390 * If the ISL caller didn't specify a row_pitch_B, then we should assume
2391 * the NVIDIA/AMD requirements. Otherwise, if we have a specified
2392 * row_pitch_B, this is probably because the caller is trying to import a
2393 * buffer. In that case we limit the minimum row pitch to the Intel HW
2394 * requirement.
2395 */
2396 if (surf_info->usage & ISL_SURF_USAGE_DISPLAY_BIT) {
2397 if (surf_info->row_pitch_B == 0)
2398 alignment = isl_align(alignment, 256);
2399 else
2400 alignment = isl_align(alignment, 64);
2401 }
2402
2403 return alignment;
2404 }
2405
2406 static uint32_t
isl_calc_linear_min_row_pitch(const struct isl_device * dev,const struct isl_surf_init_info * info,const struct isl_extent4d * phys_total_el,uint32_t alignment_B)2407 isl_calc_linear_min_row_pitch(const struct isl_device *dev,
2408 const struct isl_surf_init_info *info,
2409 const struct isl_extent4d *phys_total_el,
2410 uint32_t alignment_B)
2411 {
2412 const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
2413 const uint32_t bs = fmtl->bpb / 8;
2414
2415 return isl_align_npot(bs * phys_total_el->w, alignment_B);
2416 }
2417
2418 static uint32_t
isl_calc_tiled_min_row_pitch(const struct isl_device * dev,const struct isl_surf_init_info * surf_info,const struct isl_tile_info * tile_info,const struct isl_extent4d * phys_total_el,uint32_t alignment_B)2419 isl_calc_tiled_min_row_pitch(const struct isl_device *dev,
2420 const struct isl_surf_init_info *surf_info,
2421 const struct isl_tile_info *tile_info,
2422 const struct isl_extent4d *phys_total_el,
2423 uint32_t alignment_B)
2424 {
2425 const struct isl_format_layout *fmtl = isl_format_get_layout(surf_info->format);
2426
2427 assert(fmtl->bpb % tile_info->format_bpb == 0);
2428
2429 const uint32_t tile_el_scale = fmtl->bpb / tile_info->format_bpb;
2430 const uint32_t total_w_tl =
2431 isl_align_div(phys_total_el->w * tile_el_scale,
2432 tile_info->logical_extent_el.width);
2433
2434 /* In some cases the alignment of the pitch might be > to the tile size
2435 * (for example Gfx12 CCS requires 512B alignment while the tile's width
2436 * can be 128B), so align the row pitch to the alignment.
2437 */
2438 assert(alignment_B >= tile_info->phys_extent_B.width);
2439 return isl_align(total_w_tl * tile_info->phys_extent_B.width, alignment_B);
2440 }
2441
2442 static uint32_t
isl_calc_min_row_pitch(const struct isl_device * dev,const struct isl_surf_init_info * surf_info,const struct isl_tile_info * tile_info,const struct isl_extent4d * phys_total_el,uint32_t alignment_B)2443 isl_calc_min_row_pitch(const struct isl_device *dev,
2444 const struct isl_surf_init_info *surf_info,
2445 const struct isl_tile_info *tile_info,
2446 const struct isl_extent4d *phys_total_el,
2447 uint32_t alignment_B)
2448 {
2449 if (tile_info->tiling == ISL_TILING_LINEAR) {
2450 return isl_calc_linear_min_row_pitch(dev, surf_info, phys_total_el,
2451 alignment_B);
2452 } else {
2453 return isl_calc_tiled_min_row_pitch(dev, surf_info, tile_info,
2454 phys_total_el, alignment_B);
2455 }
2456 }
2457
2458 /**
2459 * Is ``pitch`` in the valid range for a hardware bitfield, if the bitfield's
2460 * size is ``bits`` bits?
2461 *
2462 * Hardware pitch fields are offset by 1. For example, if the size of
2463 * RENDER_SURFACE_STATE::SurfacePitch is B bits, then the range of valid
2464 * pitches is [1, 2^b] inclusive. If the surface pitch is N, then
2465 * RENDER_SURFACE_STATE::SurfacePitch must be set to N-1.
2466 */
2467 static bool
pitch_in_range(uint32_t n,uint32_t bits)2468 pitch_in_range(uint32_t n, uint32_t bits)
2469 {
2470 assert(n != 0);
2471 return likely(bits != 0 && 1 <= n && n <= (1 << bits));
2472 }
2473
2474 void PRINTFLIKE(4, 5)
_isl_notify_failure(const struct isl_surf_init_info * surf_info,const char * file,int line,const char * fmt,...)2475 _isl_notify_failure(const struct isl_surf_init_info *surf_info,
2476 const char *file, int line, const char *fmt, ...)
2477 {
2478 if (!INTEL_DEBUG(DEBUG_ISL))
2479 return;
2480
2481 char msg[512];
2482 va_list ap;
2483 va_start(ap, fmt);
2484 int ret = vsnprintf(msg, sizeof(msg), fmt, ap);
2485 assert(ret < sizeof(msg));
2486 va_end(ap);
2487
2488 #define PRINT_USAGE(bit, str) \
2489 (surf_info->usage & ISL_SURF_USAGE_##bit##_BIT) ? ("+"str) : ""
2490 #define PRINT_TILING(bit, str) \
2491 (surf_info->tiling_flags & ISL_TILING_##bit##_BIT) ? ("+"str) : ""
2492
2493 snprintf(msg + ret, sizeof(msg) - ret,
2494 " extent=%ux%ux%u dim=%s msaa=%ux levels=%u rpitch=%u fmt=%s "
2495 "usages=%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s "
2496 "tiling_flags=%s%s%s%s%s%s%s%s%s%s%s%s",
2497 surf_info->width, surf_info->height,
2498 surf_info->dim == ISL_SURF_DIM_3D ?
2499 surf_info->depth : surf_info->array_len,
2500 surf_info->dim == ISL_SURF_DIM_1D ? "1d" :
2501 surf_info->dim == ISL_SURF_DIM_2D ? "2d" : "3d",
2502 surf_info->samples, surf_info->levels,
2503 surf_info->row_pitch_B,
2504 isl_format_get_name(surf_info->format) + strlen("ISL_FORMAT_"),
2505
2506 PRINT_USAGE(RENDER_TARGET, "rt"),
2507 PRINT_USAGE(DEPTH, "depth"),
2508 PRINT_USAGE(STENCIL, "stenc"),
2509 PRINT_USAGE(TEXTURE, "tex"),
2510 PRINT_USAGE(CUBE, "cube"),
2511 PRINT_USAGE(DISABLE_AUX, "noaux"),
2512 PRINT_USAGE(DISPLAY, "disp"),
2513 PRINT_USAGE(HIZ, "hiz"),
2514 PRINT_USAGE(MCS, "mcs"),
2515 PRINT_USAGE(CCS, "ccs"),
2516 PRINT_USAGE(VERTEX_BUFFER, "vb"),
2517 PRINT_USAGE(INDEX_BUFFER, "ib"),
2518 PRINT_USAGE(CONSTANT_BUFFER, "const"),
2519 PRINT_USAGE(STAGING, "stage"),
2520 PRINT_USAGE(SPARSE, "sparse"),
2521 PRINT_USAGE(NO_AUX_TT_ALIGNMENT, "no-aux-align"),
2522
2523 PRINT_TILING(LINEAR, "linear"),
2524 PRINT_TILING(W, "W"),
2525 PRINT_TILING(X, "X"),
2526 PRINT_TILING(Y0, "Y0"),
2527 PRINT_TILING(SKL_Yf, "skl-Yf"),
2528 PRINT_TILING(SKL_Ys, "skl-Ys"),
2529 PRINT_TILING(ICL_Yf, "icl-Yf"),
2530 PRINT_TILING(ICL_Ys, "icl-Ys"),
2531 PRINT_TILING(4, "4"),
2532 PRINT_TILING(64, "64"),
2533 PRINT_TILING(HIZ, "hiz"),
2534 PRINT_TILING(CCS, "ccs"));
2535
2536 #undef PRINT_USAGE
2537 #undef PRINT_TILING
2538
2539 mesa_logd("%s:%i: %s", file, line, msg);
2540 }
2541
2542 static bool
isl_calc_row_pitch(const struct isl_device * dev,const struct isl_surf_init_info * surf_info,const struct isl_tile_info * tile_info,enum isl_dim_layout dim_layout,const struct isl_extent4d * phys_total_el,uint32_t * out_row_pitch_B)2543 isl_calc_row_pitch(const struct isl_device *dev,
2544 const struct isl_surf_init_info *surf_info,
2545 const struct isl_tile_info *tile_info,
2546 enum isl_dim_layout dim_layout,
2547 const struct isl_extent4d *phys_total_el,
2548 uint32_t *out_row_pitch_B)
2549 {
2550 uint32_t alignment_B =
2551 isl_calc_row_pitch_alignment(dev, surf_info, tile_info);
2552
2553 const uint32_t min_row_pitch_B =
2554 isl_calc_min_row_pitch(dev, surf_info, tile_info, phys_total_el,
2555 alignment_B);
2556
2557 if (surf_info->row_pitch_B != 0) {
2558 if (surf_info->row_pitch_B < min_row_pitch_B) {
2559 return notify_failure(surf_info,
2560 "requested row pitch (%uB) less than minimum "
2561 "allowed (%uB)",
2562 surf_info->row_pitch_B, min_row_pitch_B);
2563 }
2564
2565 if (surf_info->row_pitch_B % alignment_B != 0) {
2566 return notify_failure(surf_info,
2567 "requested row pitch (%uB) doesn't satisfy the "
2568 "minimum alignment requirement (%uB)",
2569 surf_info->row_pitch_B, alignment_B);
2570 }
2571 }
2572
2573 const uint32_t row_pitch_B =
2574 surf_info->row_pitch_B != 0 ? surf_info->row_pitch_B : min_row_pitch_B;
2575
2576 const uint32_t row_pitch_tl = row_pitch_B / tile_info->phys_extent_B.width;
2577
2578 if (row_pitch_B == 0)
2579 return notify_failure(surf_info, "calculated row pitch is zero");
2580
2581 if (dim_layout == ISL_DIM_LAYOUT_GFX9_1D) {
2582 /* SurfacePitch is ignored for this layout. */
2583 goto done;
2584 }
2585
2586 if ((surf_info->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT |
2587 ISL_SURF_USAGE_TEXTURE_BIT |
2588 ISL_SURF_USAGE_STORAGE_BIT)) &&
2589 !pitch_in_range(row_pitch_B, RENDER_SURFACE_STATE_SurfacePitch_bits(dev->info))) {
2590 return notify_failure(surf_info,
2591 "row pitch (%uB) not in range of "
2592 "RENDER_SURFACE_STATE::SurfacePitch",
2593 row_pitch_B);
2594 }
2595
2596 if ((surf_info->usage & (ISL_SURF_USAGE_CCS_BIT |
2597 ISL_SURF_USAGE_MCS_BIT)) &&
2598 !pitch_in_range(row_pitch_tl, RENDER_SURFACE_STATE_AuxiliarySurfacePitch_bits(dev->info))) {
2599 return notify_failure(surf_info,
2600 "row_pitch_tl=%u not in range of "
2601 "RENDER_SURFACE_STATE::AuxiliarySurfacePitch",
2602 row_pitch_tl);
2603 }
2604
2605 if ((surf_info->usage & ISL_SURF_USAGE_DEPTH_BIT) &&
2606 !pitch_in_range(row_pitch_B, _3DSTATE_DEPTH_BUFFER_SurfacePitch_bits(dev->info))) {
2607 return notify_failure(surf_info,
2608 "row pitch (%uB) not in range of "
2609 "3DSTATE_DEPTH_BUFFER::SurfacePitch",
2610 row_pitch_B);
2611 }
2612
2613 if ((surf_info->usage & ISL_SURF_USAGE_HIZ_BIT) &&
2614 !pitch_in_range(row_pitch_B, _3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_bits(dev->info))) {
2615 return notify_failure(surf_info,
2616 "row pitch (%uB) not in range of "
2617 "3DSTATE_HIER_DEPTH_BUFFER::SurfacePitch",
2618 row_pitch_B);
2619 }
2620
2621 const uint32_t stencil_pitch_bits = dev->use_separate_stencil ?
2622 _3DSTATE_STENCIL_BUFFER_SurfacePitch_bits(dev->info) :
2623 _3DSTATE_DEPTH_BUFFER_SurfacePitch_bits(dev->info);
2624
2625 if ((surf_info->usage & ISL_SURF_USAGE_STENCIL_BIT) &&
2626 !pitch_in_range(row_pitch_B, stencil_pitch_bits)) {
2627 return notify_failure(surf_info,
2628 "row pitch (%uB) not in range of "
2629 "3DSTATE_STENCIL_BUFFER/3DSTATE_DEPTH_BUFFER::SurfacePitch",
2630 row_pitch_B);
2631 }
2632
2633 if ((surf_info->usage & ISL_SURF_USAGE_CPB_BIT) &&
2634 !pitch_in_range(row_pitch_B, _3DSTATE_CPSIZE_CONTROL_BUFFER_SurfacePitch_bits(dev->info)))
2635 return false;
2636
2637 done:
2638 *out_row_pitch_B = row_pitch_B;
2639 return true;
2640 }
2641
2642 static bool
isl_calc_size(const struct isl_device * dev,const struct isl_surf_init_info * info,const struct isl_tile_info * tile_info,const struct isl_extent4d * phys_total_el,uint32_t array_pitch_el_rows,uint32_t row_pitch_B,uint64_t * out_size_B)2643 isl_calc_size(const struct isl_device *dev,
2644 const struct isl_surf_init_info *info,
2645 const struct isl_tile_info *tile_info,
2646 const struct isl_extent4d *phys_total_el,
2647 uint32_t array_pitch_el_rows,
2648 uint32_t row_pitch_B,
2649 uint64_t *out_size_B)
2650 {
2651 uint64_t size_B;
2652 if (tile_info->tiling == ISL_TILING_LINEAR) {
2653 /* LINEAR tiling has no concept of intra-tile arrays */
2654 assert(phys_total_el->d == 1 && phys_total_el->a == 1);
2655
2656 size_B = (uint64_t) row_pitch_B * phys_total_el->h;
2657
2658 } else {
2659 /* Pitches must make sense with the tiling */
2660 assert(row_pitch_B % tile_info->phys_extent_B.width == 0);
2661
2662 uint32_t array_slices, array_pitch_tl_rows;
2663 if (phys_total_el->d > 1) {
2664 assert(phys_total_el->a == 1);
2665 array_pitch_tl_rows = isl_assert_div(array_pitch_el_rows,
2666 tile_info->logical_extent_el.h);
2667 array_slices = isl_align_div(phys_total_el->d,
2668 tile_info->logical_extent_el.d);
2669 } else if (phys_total_el->a > 1) {
2670 assert(phys_total_el->d == 1);
2671 array_pitch_tl_rows = isl_assert_div(array_pitch_el_rows,
2672 tile_info->logical_extent_el.h);
2673 array_slices = isl_align_div(phys_total_el->a,
2674 tile_info->logical_extent_el.a);
2675 } else {
2676 assert(phys_total_el->d == 1 && phys_total_el->a == 1);
2677 array_pitch_tl_rows = 0;
2678 array_slices = 1;
2679 }
2680
2681 const uint32_t total_h_tl =
2682 (array_slices - 1) * array_pitch_tl_rows +
2683 isl_align_div(phys_total_el->h, tile_info->logical_extent_el.height);
2684
2685 size_B = (uint64_t) total_h_tl * tile_info->phys_extent_B.height *
2686 row_pitch_B;
2687
2688 /* Bspec 57340 (r59562):
2689 *
2690 * When allocating memory, MCS buffer size is extended by 4KB over
2691 * its original calculated size. First 4KB page of the MCS is
2692 * reserved for internal HW usage.
2693 *
2694 * Allocate an extra 4KB page reserved for hardware at the beginning of
2695 * MCS buffer on Xe2. The start address of MCS is the head of the 4KB
2696 * page. Any manipulation on the content of MCS should start after 4KB
2697 * from the start address.
2698 */
2699 if (dev->info->ver >= 20 && info->usage & ISL_SURF_USAGE_MCS_BIT)
2700 size_B += 4096;
2701 }
2702
2703 /* If for some reason we can't support the appropriate tiling format and
2704 * end up falling to linear or some other format, make sure the image size
2705 * and alignment are aligned to the expected block size so we can at least
2706 * do opaque binds.
2707 */
2708 if (info->usage & ISL_SURF_USAGE_SPARSE_BIT)
2709 size_B = isl_align(size_B, 64 * 1024);
2710
2711 /* Pre-gfx9: from the Broadwell PRM Vol 5, Surface Layout:
2712 * "In addition to restrictions on maximum height, width, and depth,
2713 * surfaces are also restricted to a maximum size in bytes. This
2714 * maximum is 2 GB for all products and all surface types."
2715 *
2716 * gfx9-10: from the Skylake PRM Vol 5, Maximum Surface Size in Bytes:
2717 * "In addition to restrictions on maximum height, width, and depth,
2718 * surfaces are also restricted to a maximum size of 2^38 bytes.
2719 * All pixels within the surface must be contained within 2^38 bytes
2720 * of the base address."
2721 *
2722 * gfx11+ platforms raised this limit to 2^44 bytes.
2723 */
2724 uint64_t max_surface_B = 1ull << (ISL_GFX_VER(dev) >= 11 ? 44 :
2725 ISL_GFX_VER(dev) >= 9 ? 38 : 31);
2726 if (size_B > max_surface_B) {
2727 return notify_failure(
2728 info,
2729 "calculated size (%"PRIu64"B) exceeds platform limit of %"PRIu64"B",
2730 size_B, max_surface_B);
2731 }
2732
2733 *out_size_B = size_B;
2734 return true;
2735 }
2736
2737 static uint32_t
isl_calc_base_alignment(const struct isl_device * dev,const struct isl_surf_init_info * info,const struct isl_tile_info * tile_info)2738 isl_calc_base_alignment(const struct isl_device *dev,
2739 const struct isl_surf_init_info *info,
2740 const struct isl_tile_info *tile_info)
2741 {
2742 uint32_t base_alignment_B;
2743 if (tile_info->tiling == ISL_TILING_LINEAR) {
2744 /* From the Broadwell PRM Vol 2d,
2745 * RENDER_SURFACE_STATE::SurfaceBaseAddress:
2746 *
2747 * "The Base Address for linear render target surfaces and surfaces
2748 * accessed with the typed surface read/write data port messages must
2749 * be element-size aligned, for non-YUV surface formats, or a
2750 * multiple of 2 element-sizes for YUV surface formats. Other linear
2751 * surfaces have no alignment requirements (byte alignment is
2752 * sufficient.)"
2753 */
2754 base_alignment_B = MAX(1, info->min_alignment_B);
2755 if (info->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) {
2756 if (isl_format_is_yuv(info->format)) {
2757 base_alignment_B =
2758 MAX(base_alignment_B, tile_info->format_bpb / 4);
2759 } else {
2760 base_alignment_B =
2761 MAX(base_alignment_B, tile_info->format_bpb / 8);
2762 }
2763 }
2764 base_alignment_B = isl_round_up_to_power_of_two(base_alignment_B);
2765
2766 /* From the Skylake PRM Vol 2c, PLANE_STRIDE::Stride:
2767 *
2768 * "For Linear memory, this field specifies the stride in chunks of
2769 * 64 bytes (1 cache line)."
2770 */
2771 if (isl_surf_usage_is_display(info->usage))
2772 base_alignment_B = MAX(base_alignment_B, 64);
2773 } else {
2774 const uint32_t tile_size_B = tile_info->phys_extent_B.width *
2775 tile_info->phys_extent_B.height;
2776 assert(isl_is_pow2(info->min_alignment_B) && isl_is_pow2(tile_size_B));
2777 base_alignment_B = MAX(info->min_alignment_B, tile_size_B);
2778
2779 if (_isl_surf_info_supports_ccs(dev, info->format, info->usage)) {
2780 /* Wa_22015614752:
2781 *
2782 * Due to L3 cache being tagged with (engineID, vaID) and the CCS
2783 * block/cacheline being 256 bytes, 2 engines accessing a 64Kb range
2784 * with compression will generate 2 different CCS cacheline entries
2785 * in L3, this will lead to corruptions. To avoid this, we need to
2786 * ensure 2 images do not share a 256 bytes CCS cacheline. With a
2787 * ratio of compression of 1/256, this is 64Kb alignment (even for
2788 * Tile4...)
2789 *
2790 * ATS-M PRMS, Vol 2a: Command Reference: Instructions,
2791 * XY_CTRL_SURF_COPY_BLT, "Size of Control Surface Copy" field, the
2792 * CCS blocks are 256 bytes :
2793 *
2794 * "This field indicates size of the Control Surface or CCS copy.
2795 * It is expressed in terms of number of 256B block of CCS, where
2796 * each 256B block of CCS corresponds to 64KB of main surface."
2797 */
2798 if (intel_needs_workaround(dev->info, 22015614752) &&
2799 (info->usage & (ISL_SURF_USAGE_MULTI_ENGINE_SEQ_BIT |
2800 ISL_SURF_USAGE_MULTI_ENGINE_PAR_BIT))) {
2801 base_alignment_B = MAX(base_alignment_B,
2802 256 /* cacheline */ * 256 /* AUX ratio */);
2803 }
2804
2805 /* Platforms using an aux map require that images be
2806 * granularity-aligned if they're going to used with CCS. This is
2807 * because the Aux translation table maps main surface addresses to
2808 * aux addresses at a granularity in the main surface. Because we
2809 * don't know for sure in ISL if a surface will use CCS, we have to
2810 * guess based on the DISABLE_AUX usage bit. The one thing we do know
2811 * is that we haven't enable CCS on linear images yet so we can avoid
2812 * the extra alignment there.
2813 */
2814 if (dev->info->has_aux_map &&
2815 !(info->usage & ISL_SURF_USAGE_NO_AUX_TT_ALIGNMENT_BIT)) {
2816 base_alignment_B = MAX(base_alignment_B, dev->info->verx10 >= 125 ?
2817 1024 * 1024 : 64 * 1024);
2818 }
2819 }
2820 }
2821
2822 /* If for some reason we can't support the appropriate tiling format and
2823 * end up falling to linear or some other format, make sure the image size
2824 * and alignment are aligned to the expected block size so we can at least
2825 * do opaque binds.
2826 */
2827 if (info->usage & ISL_SURF_USAGE_SPARSE_BIT)
2828 base_alignment_B = MAX(base_alignment_B, 64 * 1024);
2829
2830 return base_alignment_B;
2831 }
2832
2833 bool
isl_surf_init_s(const struct isl_device * dev,struct isl_surf * surf,const struct isl_surf_init_info * restrict info)2834 isl_surf_init_s(const struct isl_device *dev,
2835 struct isl_surf *surf,
2836 const struct isl_surf_init_info *restrict info)
2837 {
2838 /* Some sanity checks */
2839 assert(!(info->usage & ISL_SURF_USAGE_CPB_BIT) ||
2840 dev->info->has_coarse_pixel_primitive_and_cb);
2841
2842 const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
2843
2844 const struct isl_extent4d logical_level0_px = {
2845 .w = info->width,
2846 .h = info->height,
2847 .d = info->depth,
2848 .a = info->array_len,
2849 };
2850
2851 enum isl_tiling tiling;
2852 if (!isl_surf_choose_tiling(dev, info, &tiling))
2853 return false;
2854
2855 const enum isl_dim_layout dim_layout =
2856 isl_surf_choose_dim_layout(dev, info->dim, tiling, info->usage);
2857
2858 enum isl_msaa_layout msaa_layout;
2859 if (!isl_choose_msaa_layout(dev, info, tiling, &msaa_layout))
2860 return false;
2861
2862 struct isl_tile_info tile_info;
2863 isl_tiling_get_info(tiling, info->dim, msaa_layout, fmtl->bpb,
2864 info->samples, &tile_info);
2865
2866 struct isl_extent3d image_align_el;
2867 isl_choose_image_alignment_el(dev, info, &tile_info, dim_layout,
2868 msaa_layout, &image_align_el);
2869
2870 struct isl_extent3d image_align_sa =
2871 isl_extent3d_el_to_sa(info->format, image_align_el);
2872
2873 struct isl_extent4d phys_level0_sa;
2874 isl_calc_phys_level0_extent_sa(dev, info, dim_layout, tiling, msaa_layout,
2875 &phys_level0_sa);
2876
2877 enum isl_array_pitch_span array_pitch_span =
2878 isl_choose_array_pitch_span(dev, info, dim_layout, &phys_level0_sa);
2879
2880 uint32_t miptail_start_level =
2881 isl_choose_miptail_start_level(dev, info, &tile_info);
2882
2883 uint32_t array_pitch_el_rows;
2884 struct isl_extent4d phys_total_el;
2885 isl_calc_phys_total_extent_el(dev, info, &tile_info,
2886 dim_layout, msaa_layout,
2887 &image_align_sa, &phys_level0_sa,
2888 array_pitch_span, miptail_start_level,
2889 &array_pitch_el_rows,
2890 &phys_total_el);
2891
2892 uint32_t row_pitch_B;
2893 if (!isl_calc_row_pitch(dev, info, &tile_info, dim_layout,
2894 &phys_total_el, &row_pitch_B))
2895 return false;
2896
2897 uint64_t size_B;
2898 if (!isl_calc_size(dev, info, &tile_info, &phys_total_el,
2899 array_pitch_el_rows, row_pitch_B, &size_B))
2900 return false;
2901
2902 const uint32_t base_alignment_B =
2903 isl_calc_base_alignment(dev, info, &tile_info);
2904
2905 *surf = (struct isl_surf) {
2906 .dim = info->dim,
2907 .dim_layout = dim_layout,
2908 .msaa_layout = msaa_layout,
2909 .tiling = tiling,
2910 .format = info->format,
2911
2912 .levels = info->levels,
2913 .samples = info->samples,
2914
2915 .image_alignment_el = image_align_el,
2916 .logical_level0_px = logical_level0_px,
2917 .phys_level0_sa = phys_level0_sa,
2918
2919 .size_B = size_B,
2920 .alignment_B = base_alignment_B,
2921 .row_pitch_B = row_pitch_B,
2922 .array_pitch_el_rows = array_pitch_el_rows,
2923 .array_pitch_span = array_pitch_span,
2924 .miptail_start_level = miptail_start_level,
2925
2926 .usage = info->usage,
2927 };
2928
2929 return true;
2930 }
2931
2932 void
isl_surf_get_tile_info(const struct isl_surf * surf,struct isl_tile_info * tile_info)2933 isl_surf_get_tile_info(const struct isl_surf *surf,
2934 struct isl_tile_info *tile_info)
2935 {
2936 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
2937 isl_tiling_get_info(surf->tiling, surf->dim, surf->msaa_layout, fmtl->bpb,
2938 surf->samples, tile_info);
2939 }
2940
2941 bool
isl_surf_get_hiz_surf(const struct isl_device * dev,const struct isl_surf * surf,struct isl_surf * hiz_surf)2942 isl_surf_get_hiz_surf(const struct isl_device *dev,
2943 const struct isl_surf *surf,
2944 struct isl_surf *hiz_surf)
2945 {
2946 if (INTEL_DEBUG(DEBUG_NO_HIZ))
2947 return false;
2948
2949 if (surf->usage & ISL_SURF_USAGE_DISABLE_AUX_BIT)
2950 return false;
2951
2952 /* HiZ support does not exist prior to Gfx5 */
2953 if (ISL_GFX_VER(dev) < 5)
2954 return false;
2955
2956 if (!isl_surf_usage_is_depth(surf->usage))
2957 return false;
2958
2959 /* From the Sandy Bridge PRM, Vol 2 Part 1,
2960 * 3DSTATE_DEPTH_BUFFER::Hierarchical Depth Buffer Enable,
2961 *
2962 * If this field is enabled, the Surface Format of the depth buffer
2963 * cannot be D32_FLOAT_S8X24_UINT or D24_UNORM_S8_UINT. Use of stencil
2964 * requires the separate stencil buffer.
2965 *
2966 * On SNB+, HiZ can't be used with combined depth-stencil buffers.
2967 */
2968 if (isl_surf_usage_is_stencil(surf->usage))
2969 return false;
2970
2971 /* Multisampled depth is always interleaved */
2972 assert(surf->msaa_layout == ISL_MSAA_LAYOUT_NONE ||
2973 surf->msaa_layout == ISL_MSAA_LAYOUT_INTERLEAVED);
2974
2975 /* From the Broadwell PRM Vol. 7, "Hierarchical Depth Buffer":
2976 *
2977 * "The Surface Type, Height, Width, Depth, Minimum Array Element, Render
2978 * Target View Extent, and Depth Coordinate Offset X/Y of the
2979 * hierarchical depth buffer are inherited from the depth buffer. The
2980 * height and width of the hierarchical depth buffer that must be
2981 * allocated are computed by the following formulas, where HZ is the
2982 * hierarchical depth buffer and Z is the depth buffer. The Z_Height,
2983 * Z_Width, and Z_Depth values given in these formulas are those present
2984 * in 3DSTATE_DEPTH_BUFFER incremented by one.
2985 *
2986 * "The value of Z_Height and Z_Width must each be multiplied by 2 before
2987 * being applied to the table below if Number of Multisamples is set to
2988 * NUMSAMPLES_4. The value of Z_Height must be multiplied by 2 and
2989 * Z_Width must be multiplied by 4 before being applied to the table
2990 * below if Number of Multisamples is set to NUMSAMPLES_8."
2991 *
2992 * In the Sky Lake PRM, the second paragraph is gone. This means that,
2993 * from Sandy Bridge through Broadwell, HiZ compresses samples in the
2994 * primary depth surface. On Sky Lake and onward, HiZ compresses pixels.
2995 *
2996 * There are a number of different ways that this discrepancy could be
2997 * handled. The way we have chosen is to simply make MSAA HiZ have the
2998 * same number of samples as the parent surface pre-Sky Lake and always be
2999 * single-sampled on Sky Lake and above. Since the block sizes of
3000 * compressed formats are given in samples, this neatly handles everything
3001 * without the need for additional HiZ formats with different block sizes
3002 * on SKL+.
3003 */
3004 const unsigned samples = ISL_GFX_VER(dev) >= 9 ? 1 : surf->samples;
3005
3006 const enum isl_format format =
3007 ISL_GFX_VERX10(dev) >= 125 ? ISL_FORMAT_GFX125_HIZ : ISL_FORMAT_HIZ;
3008
3009 return isl_surf_init(dev, hiz_surf,
3010 .dim = surf->dim,
3011 .format = format,
3012 .width = surf->logical_level0_px.width,
3013 .height = surf->logical_level0_px.height,
3014 .depth = surf->logical_level0_px.depth,
3015 .levels = surf->levels,
3016 .array_len = surf->logical_level0_px.array_len,
3017 .samples = samples,
3018 .usage = ISL_SURF_USAGE_HIZ_BIT,
3019 .tiling_flags = ISL_TILING_HIZ_BIT);
3020 }
3021
3022 bool
isl_surf_get_mcs_surf(const struct isl_device * dev,const struct isl_surf * surf,struct isl_surf * mcs_surf)3023 isl_surf_get_mcs_surf(const struct isl_device *dev,
3024 const struct isl_surf *surf,
3025 struct isl_surf *mcs_surf)
3026 {
3027 /* It must be multisampled with an array layout */
3028 if (surf->msaa_layout != ISL_MSAA_LAYOUT_ARRAY)
3029 return false;
3030
3031 /* On Gfx12+ this format is not listed in TGL PRMs, Volume 2b: Command
3032 * Reference: Enumerations, RenderCompressionFormat
3033 */
3034 if (ISL_GFX_VER(dev) >= 12 &&
3035 surf->format == ISL_FORMAT_R9G9B9E5_SHAREDEXP)
3036 return false;
3037
3038 /* The following are true of all multisampled surfaces */
3039 assert(surf->samples > 1);
3040 assert(surf->dim == ISL_SURF_DIM_2D);
3041 assert(surf->levels == 1);
3042 assert(surf->logical_level0_px.depth == 1);
3043 assert(isl_format_supports_multisampling(dev->info, surf->format));
3044
3045 enum isl_format mcs_format;
3046 switch (surf->samples) {
3047 case 2: mcs_format = ISL_FORMAT_MCS_2X; break;
3048 case 4: mcs_format = ISL_FORMAT_MCS_4X; break;
3049 case 8: mcs_format = ISL_FORMAT_MCS_8X; break;
3050 case 16: mcs_format = ISL_FORMAT_MCS_16X; break;
3051 default:
3052 unreachable("Invalid sample count");
3053 }
3054
3055 return isl_surf_init(dev, mcs_surf,
3056 .dim = ISL_SURF_DIM_2D,
3057 .format = mcs_format,
3058 .width = surf->logical_level0_px.width,
3059 .height = surf->logical_level0_px.height,
3060 .depth = 1,
3061 .levels = 1,
3062 .array_len = surf->logical_level0_px.array_len,
3063 .samples = 1, /* MCS surfaces are really single-sampled */
3064 .usage = ISL_SURF_USAGE_MCS_BIT,
3065 .tiling_flags = ISL_TILING_ANY_MASK);
3066 }
3067
3068 bool
_isl_surf_info_supports_ccs(const struct isl_device * dev,enum isl_format format,isl_surf_usage_flags_t usage)3069 _isl_surf_info_supports_ccs(const struct isl_device *dev,
3070 enum isl_format format,
3071 isl_surf_usage_flags_t usage)
3072 {
3073 if (!isl_format_supports_ccs_d(dev->info, format) &&
3074 !isl_format_supports_ccs_e(dev->info, format))
3075 return false;
3076
3077 /* CCS is only for color images on Gfx7-11 */
3078 if (ISL_GFX_VER(dev) <= 11 && isl_surf_usage_is_depth_or_stencil(usage))
3079 return false;
3080
3081 if (usage & ISL_SURF_USAGE_DISABLE_AUX_BIT)
3082 return false;
3083
3084 /* TODO: Disable for now, as we're not sure about the meaning of
3085 * 3DSTATE_CPSIZE_CONTROL_BUFFER::CPCBCompressionEnable
3086 */
3087 if (isl_surf_usage_is_cpb(usage) && dev->info->ver < 20)
3088 return false;
3089
3090 if (INTEL_DEBUG(DEBUG_NO_CCS))
3091 return false;
3092
3093 return true;
3094 }
3095
3096 bool
isl_surf_supports_ccs(const struct isl_device * dev,const struct isl_surf * surf,const struct isl_surf * hiz_or_mcs_surf)3097 isl_surf_supports_ccs(const struct isl_device *dev,
3098 const struct isl_surf *surf,
3099 const struct isl_surf *hiz_or_mcs_surf)
3100 {
3101 if (!_isl_surf_info_supports_ccs(dev, surf->format, surf->usage))
3102 return false;
3103
3104 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
3105 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
3106 *
3107 * - Support is limited to tiled render targets.
3108 *
3109 * From the BSpec (44930) for Gfx12:
3110 *
3111 * Linear CCS is only allowed for Untyped Buffers but only via HDC
3112 * Data-Port messages.
3113 *
3114 * We never use untyped messages on surfaces created by ISL on Gfx9+ so
3115 * this means linear is out on Gfx12+ as well.
3116 */
3117 if (surf->tiling == ISL_TILING_LINEAR)
3118 return false;
3119
3120 /* From the SKL PRMs, Volume 7: MCS Buffer for Render Target(s),
3121 *
3122 * - Note: Lossless Color Compression can only be applied to Surfaces
3123 * which are TileY, TileYs, or TileYf.
3124 *
3125 * From the ACM PRMs, Volume 9: MCS/CCS Buffers for Render Target(s),
3126 *
3127 * - Note: Lossless Color Compression can only be applied to Surfaces
3128 * which are Linear, Tile4, or Tile64. (TileY/TileYF/TileYS on older
3129 * devices)
3130 *
3131 * It is made clear that X-tiling is no longer supported on SKL+.
3132 */
3133 if (ISL_GFX_VER(dev) >= 9 && surf->tiling == ISL_TILING_X)
3134 return false;
3135
3136 /* TODO: add CCS support for Ys/Yf */
3137 if (isl_tiling_is_std_y(surf->tiling))
3138 return false;
3139
3140 /* Wa_22015614752: There are issues with multiple engines accessing
3141 * the same CCS cacheline in parallel. This can happen if this image
3142 * has multiple subresources. Such conflicts can be avoided with
3143 * tilings that set the subresource alignment to 64K and with miptails
3144 * disabled. If we aren't using such a configuration, disable CCS.
3145 */
3146 if (intel_needs_workaround(dev->info, 22015614752) &&
3147 (surf->usage & ISL_SURF_USAGE_MULTI_ENGINE_PAR_BIT) &&
3148 (surf->levels > 1 ||
3149 surf->logical_level0_px.depth > 1 ||
3150 surf->logical_level0_px.array_len > 1)) {
3151 assert(surf->miptail_start_level >= surf->levels);
3152 if (surf->tiling != ISL_TILING_64) {
3153 assert(surf->tiling == ISL_TILING_4);
3154 return false;
3155 }
3156 }
3157
3158 if (ISL_GFX_VER(dev) == 12) {
3159 if (isl_surf_usage_is_stencil(surf->usage)) {
3160 /* HiZ and MCS aren't allowed with stencil */
3161 assert(hiz_or_mcs_surf == NULL || hiz_or_mcs_surf->size_B == 0);
3162
3163 /* Multi-sampled stencil cannot have CCS */
3164 if (surf->samples > 1)
3165 return false;
3166 } else if (isl_surf_usage_is_depth(surf->usage)) {
3167 const struct isl_surf *hiz_surf = hiz_or_mcs_surf;
3168
3169 /* With depth surfaces, HIZ is required for CCS. */
3170 if (hiz_surf == NULL || hiz_surf->size_B == 0)
3171 return false;
3172
3173 assert(hiz_surf->usage & ISL_SURF_USAGE_HIZ_BIT);
3174 assert(hiz_surf->tiling == ISL_TILING_HIZ);
3175 assert(isl_format_is_hiz(hiz_surf->format));
3176 } else if (surf->samples > 1) {
3177 const struct isl_surf *mcs_surf = hiz_or_mcs_surf;
3178
3179 /* With multisampled color, CCS requires MCS */
3180 if (mcs_surf == NULL || mcs_surf->size_B == 0)
3181 return false;
3182
3183 assert(mcs_surf->usage & ISL_SURF_USAGE_MCS_BIT);
3184 assert(isl_format_is_mcs(mcs_surf->format));
3185 } else {
3186 /* Single-sampled color can't have MCS or HiZ */
3187 assert(hiz_or_mcs_surf == NULL || hiz_or_mcs_surf->size_B == 0);
3188
3189 /* From Bspec 49252, Render Decompression:
3190 *
3191 * "Compressed displayable surfaces must be 16KB aligned and have
3192 * pitches padded to multiple of 4 tiles."
3193 *
3194 * The drm_fourcc.h header doesn't require the aligned address for
3195 * compressed dmabufs, but it does require the aligned pitch.
3196 */
3197 if (isl_surf_usage_is_display(surf->usage)) {
3198 assert(surf->tiling == ISL_TILING_4 ||
3199 surf->tiling == ISL_TILING_Y0);
3200 if (surf->row_pitch_B % 512 != 0)
3201 return false;
3202 }
3203
3204 /* From BSpec 44930,
3205 *
3206 * "Compression of 3D Ys surfaces with 64 or 128 bpp is not
3207 * supported in Gen12. Moreover, "Render Target Fast-clear Enable"
3208 * command is not supported for any 3D Ys surfaces. except when
3209 * Surface is a Procdural Texture."
3210 *
3211 * It's not clear where the exception applies, but either way, we
3212 * don't support Procedural Textures.
3213 */
3214 if (surf->dim == ISL_SURF_DIM_3D &&
3215 surf->tiling == ISL_TILING_ICL_Ys &&
3216 isl_format_get_layout(surf->format)->bpb >= 64)
3217 return false;
3218 }
3219 } else if (ISL_GFX_VER(dev) < 12) {
3220 if (surf->samples > 1)
3221 return false;
3222
3223 /* CCS is only for color images on Gfx7-11 */
3224 assert(!isl_surf_usage_is_depth_or_stencil(surf->usage));
3225
3226 /* We're single-sampled color so having HiZ or MCS makes no sense */
3227 assert(hiz_or_mcs_surf == NULL || hiz_or_mcs_surf->size_B == 0);
3228
3229 /* The PRM doesn't say this explicitly, but fast-clears don't appear to
3230 * work for 3D textures until gfx9 where the layout of 3D textures
3231 * changes to match 2D array textures.
3232 */
3233 if (ISL_GFX_VER(dev) <= 8 && surf->dim != ISL_SURF_DIM_2D)
3234 return false;
3235
3236 /* From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652 (Color Clear of
3237 * Non-MultiSampler Render Target Restrictions):
3238 *
3239 * "Support is for non-mip-mapped and non-array surface types only."
3240 *
3241 * This restriction is lifted on gfx8+. Technically, it may be possible
3242 * to create a CCS for an arrayed or mipmapped image and only enable
3243 * CCS_D when rendering to the base slice. However, there is no
3244 * documentation tell us what the hardware would do in that case or what
3245 * it does if you walk off the bases slice. (Does it ignore CCS or does
3246 * it start scribbling over random memory?) We play it safe and just
3247 * follow the docs and don't allow CCS_D for arrayed or mip-mapped
3248 * surfaces.
3249 */
3250 if (ISL_GFX_VER(dev) <= 7 &&
3251 (surf->levels > 1 || surf->logical_level0_px.array_len > 1))
3252 return false;
3253 }
3254
3255 return true;
3256 }
3257
3258 bool
isl_surf_get_ccs_surf(const struct isl_device * dev,const struct isl_surf * surf,struct isl_surf * ccs_surf,uint32_t row_pitch_B)3259 isl_surf_get_ccs_surf(const struct isl_device *dev,
3260 const struct isl_surf *surf,
3261 struct isl_surf *ccs_surf,
3262 uint32_t row_pitch_B)
3263 {
3264 if (!isl_surf_supports_ccs(dev, surf, NULL))
3265 return false;
3266
3267 enum isl_format ccs_format;
3268 if (ISL_GFX_VER(dev) >= 9 && ISL_GFX_VER(dev) <= 11) {
3269 switch (isl_format_get_layout(surf->format)->bpb) {
3270 case 32: ccs_format = ISL_FORMAT_GFX9_CCS_32BPP; break;
3271 case 64: ccs_format = ISL_FORMAT_GFX9_CCS_64BPP; break;
3272 case 128: ccs_format = ISL_FORMAT_GFX9_CCS_128BPP; break;
3273 default: unreachable("Unsupported CCS format");
3274 }
3275 } else if (surf->tiling == ISL_TILING_Y0) {
3276 switch (isl_format_get_layout(surf->format)->bpb) {
3277 case 32: ccs_format = ISL_FORMAT_GFX7_CCS_32BPP_Y; break;
3278 case 64: ccs_format = ISL_FORMAT_GFX7_CCS_64BPP_Y; break;
3279 case 128: ccs_format = ISL_FORMAT_GFX7_CCS_128BPP_Y; break;
3280 default: unreachable("Unsupported CCS format");
3281 }
3282 } else if (surf->tiling == ISL_TILING_X) {
3283 switch (isl_format_get_layout(surf->format)->bpb) {
3284 case 32: ccs_format = ISL_FORMAT_GFX7_CCS_32BPP_X; break;
3285 case 64: ccs_format = ISL_FORMAT_GFX7_CCS_64BPP_X; break;
3286 case 128: ccs_format = ISL_FORMAT_GFX7_CCS_128BPP_X; break;
3287 default: unreachable("Unsupported CCS format");
3288 }
3289 } else {
3290 unreachable("Invalid tiling format");
3291 }
3292
3293 return isl_surf_init(dev, ccs_surf,
3294 .dim = surf->dim,
3295 .format = ccs_format,
3296 .width = surf->logical_level0_px.width,
3297 .height = surf->logical_level0_px.height,
3298 .depth = surf->logical_level0_px.depth,
3299 .levels = surf->levels,
3300 .array_len = surf->logical_level0_px.array_len,
3301 .samples = 1,
3302 .row_pitch_B = row_pitch_B,
3303 .usage = ISL_SURF_USAGE_CCS_BIT,
3304 .tiling_flags = ISL_TILING_CCS_BIT);
3305 }
3306
3307 #define isl_genX_call(dev, func, ...) \
3308 switch (ISL_GFX_VERX10(dev)) { \
3309 case 40: \
3310 isl_gfx4_##func(__VA_ARGS__); \
3311 break; \
3312 case 45: \
3313 /* G45 surface state is the same as gfx5 */ \
3314 case 50: \
3315 isl_gfx5_##func(__VA_ARGS__); \
3316 break; \
3317 case 60: \
3318 isl_gfx6_##func(__VA_ARGS__); \
3319 break; \
3320 case 70: \
3321 isl_gfx7_##func(__VA_ARGS__); \
3322 break; \
3323 case 75: \
3324 isl_gfx75_##func(__VA_ARGS__); \
3325 break; \
3326 case 80: \
3327 isl_gfx8_##func(__VA_ARGS__); \
3328 break; \
3329 case 90: \
3330 isl_gfx9_##func(__VA_ARGS__); \
3331 break; \
3332 case 110: \
3333 isl_gfx11_##func(__VA_ARGS__); \
3334 break; \
3335 case 120: \
3336 isl_gfx12_##func(__VA_ARGS__); \
3337 break; \
3338 case 125: \
3339 isl_gfx125_##func(__VA_ARGS__); \
3340 break; \
3341 case 200: \
3342 isl_gfx20_##func(__VA_ARGS__); \
3343 break; \
3344 case 300: \
3345 isl_gfx30_##func(__VA_ARGS__); \
3346 break; \
3347 default: \
3348 assert(!"Unknown hardware generation"); \
3349 }
3350
3351 /**
3352 * A variant of isl_surf_get_image_offset_sa() specific to
3353 * ISL_DIM_LAYOUT_GFX4_2D.
3354 */
3355 static void
get_image_offset_sa_gfx4_2d(const struct isl_surf * surf,uint32_t level,uint32_t logical_array_layer,uint32_t * x_offset_sa,uint32_t * y_offset_sa,uint32_t * z_offset_sa,uint32_t * array_offset)3356 get_image_offset_sa_gfx4_2d(const struct isl_surf *surf,
3357 uint32_t level, uint32_t logical_array_layer,
3358 uint32_t *x_offset_sa,
3359 uint32_t *y_offset_sa,
3360 uint32_t *z_offset_sa,
3361 uint32_t *array_offset)
3362 {
3363 assert(level < surf->levels);
3364 if (surf->dim == ISL_SURF_DIM_3D)
3365 assert(logical_array_layer < surf->logical_level0_px.depth);
3366 else
3367 assert(logical_array_layer < surf->logical_level0_px.array_len);
3368
3369 const struct isl_extent3d image_align_sa =
3370 isl_surf_get_image_alignment_sa(surf);
3371
3372 const uint32_t W0 = surf->phys_level0_sa.width;
3373 const uint32_t H0 = surf->phys_level0_sa.height;
3374
3375 const uint32_t phys_layer = logical_array_layer *
3376 (surf->msaa_layout == ISL_MSAA_LAYOUT_ARRAY ? surf->samples : 1);
3377
3378 uint32_t x = 0, y;
3379 if (isl_tiling_is_std_y(surf->tiling) ||
3380 isl_tiling_is_64(surf->tiling)) {
3381 y = 0;
3382 if (surf->dim == ISL_SURF_DIM_3D) {
3383 *z_offset_sa = logical_array_layer;
3384 *array_offset = 0;
3385 } else {
3386 *z_offset_sa = 0;
3387 *array_offset = phys_layer;
3388 }
3389 } else {
3390 y = phys_layer * isl_surf_get_array_pitch_sa_rows(surf);
3391 *z_offset_sa = 0;
3392 *array_offset = 0;
3393 }
3394
3395 for (uint32_t l = 0; l < MIN(level, surf->miptail_start_level); ++l) {
3396 if (l == 1) {
3397 uint32_t W = isl_minify(W0, l);
3398 x += isl_align_npot(W, image_align_sa.w);
3399 } else {
3400 uint32_t H = isl_minify(H0, l);
3401 y += isl_align_npot(H, image_align_sa.h);
3402 }
3403 }
3404
3405 *x_offset_sa = x;
3406 *y_offset_sa = y;
3407
3408 if (level >= surf->miptail_start_level) {
3409 const struct isl_format_layout *fmtl =
3410 isl_format_get_layout(surf->format);
3411
3412 uint32_t tail_offset_x_el, tail_offset_y_el, tail_offset_z_el;
3413 isl_get_miptail_level_offset_el(surf->tiling, surf->dim,
3414 fmtl->bpb,
3415 level - surf->miptail_start_level,
3416 &tail_offset_x_el,
3417 &tail_offset_y_el,
3418 &tail_offset_z_el);
3419 *x_offset_sa += tail_offset_x_el * fmtl->bw;
3420 *y_offset_sa += tail_offset_y_el * fmtl->bh;
3421 *z_offset_sa += tail_offset_z_el * fmtl->bd;
3422 }
3423 }
3424
3425 /**
3426 * A variant of isl_surf_get_image_offset_sa() specific to
3427 * ISL_DIM_LAYOUT_GFX4_3D.
3428 */
3429 static void
get_image_offset_sa_gfx4_3d(const struct isl_surf * surf,uint32_t level,uint32_t logical_z_offset_px,uint32_t * x_offset_sa,uint32_t * y_offset_sa)3430 get_image_offset_sa_gfx4_3d(const struct isl_surf *surf,
3431 uint32_t level, uint32_t logical_z_offset_px,
3432 uint32_t *x_offset_sa,
3433 uint32_t *y_offset_sa)
3434 {
3435 assert(level < surf->levels);
3436 if (surf->dim == ISL_SURF_DIM_3D) {
3437 assert(surf->phys_level0_sa.array_len == 1);
3438 assert(logical_z_offset_px < isl_minify(surf->phys_level0_sa.depth, level));
3439 } else {
3440 assert(surf->dim == ISL_SURF_DIM_2D);
3441 assert(surf->usage & ISL_SURF_USAGE_CUBE_BIT);
3442 assert(surf->phys_level0_sa.array_len == 6);
3443 assert(logical_z_offset_px < surf->phys_level0_sa.array_len);
3444 }
3445
3446 const struct isl_extent3d image_align_sa =
3447 isl_surf_get_image_alignment_sa(surf);
3448
3449 const uint32_t W0 = surf->phys_level0_sa.width;
3450 const uint32_t H0 = surf->phys_level0_sa.height;
3451 const uint32_t D0 = surf->phys_level0_sa.depth;
3452 const uint32_t AL = surf->phys_level0_sa.array_len;
3453
3454 uint32_t x = 0;
3455 uint32_t y = 0;
3456
3457 for (uint32_t l = 0; l < level; ++l) {
3458 const uint32_t level_h = isl_align_npot(isl_minify(H0, l), image_align_sa.h);
3459 const uint32_t level_d =
3460 isl_align_npot(surf->dim == ISL_SURF_DIM_3D ? isl_minify(D0, l) : AL,
3461 image_align_sa.d);
3462 const uint32_t max_layers_vert = isl_align(level_d, 1u << l) / (1u << l);
3463
3464 y += level_h * max_layers_vert;
3465 }
3466
3467 const uint32_t level_w = isl_align_npot(isl_minify(W0, level), image_align_sa.w);
3468 const uint32_t level_h = isl_align_npot(isl_minify(H0, level), image_align_sa.h);
3469 const uint32_t level_d =
3470 isl_align_npot(surf->dim == ISL_SURF_DIM_3D ? isl_minify(D0, level) : AL,
3471 image_align_sa.d);
3472
3473 const uint32_t max_layers_horiz = MIN(level_d, 1u << level);
3474
3475 x += level_w * (logical_z_offset_px % max_layers_horiz);
3476 y += level_h * (logical_z_offset_px / max_layers_horiz);
3477
3478 *x_offset_sa = x;
3479 *y_offset_sa = y;
3480 }
3481
3482 static void
get_image_offset_sa_gfx6_stencil_hiz(const struct isl_surf * surf,uint32_t level,uint32_t logical_array_layer,uint32_t * x_offset_sa,uint32_t * y_offset_sa)3483 get_image_offset_sa_gfx6_stencil_hiz(const struct isl_surf *surf,
3484 uint32_t level,
3485 uint32_t logical_array_layer,
3486 uint32_t *x_offset_sa,
3487 uint32_t *y_offset_sa)
3488 {
3489 assert(level < surf->levels);
3490 assert(surf->logical_level0_px.depth == 1);
3491 assert(logical_array_layer < surf->logical_level0_px.array_len);
3492
3493 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
3494
3495 const struct isl_extent3d image_align_sa =
3496 isl_surf_get_image_alignment_sa(surf);
3497
3498 struct isl_tile_info tile_info;
3499 isl_surf_get_tile_info(surf, &tile_info);
3500 const struct isl_extent2d tile_extent_sa = {
3501 .w = tile_info.logical_extent_el.w * fmtl->bw,
3502 .h = tile_info.logical_extent_el.h * fmtl->bh,
3503 };
3504 /* Tile size is a multiple of image alignment */
3505 assert(tile_extent_sa.w % image_align_sa.w == 0);
3506 assert(tile_extent_sa.h % image_align_sa.h == 0);
3507
3508 const uint32_t W0 = surf->phys_level0_sa.w;
3509 const uint32_t H0 = surf->phys_level0_sa.h;
3510
3511 /* Each image has the same height as LOD0 because the hardware thinks
3512 * everything is LOD0
3513 */
3514 const uint32_t H = isl_align(H0, image_align_sa.h);
3515
3516 /* Quick sanity check for consistency */
3517 if (surf->phys_level0_sa.array_len > 1)
3518 assert(surf->array_pitch_el_rows == isl_assert_div(H, fmtl->bh));
3519
3520 uint32_t x = 0, y = 0;
3521 for (uint32_t l = 0; l < level; ++l) {
3522 const uint32_t W = isl_minify(W0, l);
3523
3524 const uint32_t w = isl_align(W, tile_extent_sa.w);
3525 const uint32_t h = isl_align(H * surf->phys_level0_sa.a,
3526 tile_extent_sa.h);
3527
3528 if (l == 0) {
3529 y += h;
3530 } else {
3531 x += w;
3532 }
3533 }
3534
3535 y += H * logical_array_layer;
3536
3537 *x_offset_sa = x;
3538 *y_offset_sa = y;
3539 }
3540
3541 /**
3542 * A variant of isl_surf_get_image_offset_sa() specific to
3543 * ISL_DIM_LAYOUT_GFX9_1D.
3544 */
3545 static void
get_image_offset_sa_gfx9_1d(const struct isl_surf * surf,uint32_t level,uint32_t layer,uint32_t * x_offset_sa,uint32_t * y_offset_sa)3546 get_image_offset_sa_gfx9_1d(const struct isl_surf *surf,
3547 uint32_t level, uint32_t layer,
3548 uint32_t *x_offset_sa,
3549 uint32_t *y_offset_sa)
3550 {
3551 assert(level < surf->levels);
3552 assert(layer < surf->phys_level0_sa.array_len);
3553 assert(surf->phys_level0_sa.height == 1);
3554 assert(surf->phys_level0_sa.depth == 1);
3555 assert(surf->samples == 1);
3556
3557 const uint32_t W0 = surf->phys_level0_sa.width;
3558 const struct isl_extent3d image_align_sa =
3559 isl_surf_get_image_alignment_sa(surf);
3560
3561 uint32_t x = 0;
3562
3563 for (uint32_t l = 0; l < level; ++l) {
3564 uint32_t W = isl_minify(W0, l);
3565 uint32_t w = isl_align_npot(W, image_align_sa.w);
3566
3567 x += w;
3568 }
3569
3570 *x_offset_sa = x;
3571 *y_offset_sa = layer * isl_surf_get_array_pitch_sa_rows(surf);
3572 }
3573
3574 /**
3575 * Calculate the offset, in units of surface samples, to a subimage in the
3576 * surface.
3577 *
3578 * @invariant level < surface levels
3579 * @invariant logical_array_layer < logical array length of surface
3580 * @invariant logical_z_offset_px < logical depth of surface at level
3581 */
3582 void
isl_surf_get_image_offset_sa(const struct isl_surf * surf,uint32_t level,uint32_t logical_array_layer,uint32_t logical_z_offset_px,uint32_t * x_offset_sa,uint32_t * y_offset_sa,uint32_t * z_offset_sa,uint32_t * array_offset)3583 isl_surf_get_image_offset_sa(const struct isl_surf *surf,
3584 uint32_t level,
3585 uint32_t logical_array_layer,
3586 uint32_t logical_z_offset_px,
3587 uint32_t *x_offset_sa,
3588 uint32_t *y_offset_sa,
3589 uint32_t *z_offset_sa,
3590 uint32_t *array_offset)
3591 {
3592 assert(level < surf->levels);
3593 assert(logical_array_layer < surf->logical_level0_px.array_len);
3594 assert(logical_z_offset_px
3595 < isl_minify(surf->logical_level0_px.depth, level));
3596
3597 switch (surf->dim_layout) {
3598 case ISL_DIM_LAYOUT_GFX9_1D:
3599 get_image_offset_sa_gfx9_1d(surf, level, logical_array_layer,
3600 x_offset_sa, y_offset_sa);
3601 *z_offset_sa = 0;
3602 *array_offset = 0;
3603 break;
3604 case ISL_DIM_LAYOUT_GFX4_2D:
3605 get_image_offset_sa_gfx4_2d(surf, level, logical_array_layer
3606 + logical_z_offset_px,
3607 x_offset_sa, y_offset_sa,
3608 z_offset_sa, array_offset);
3609 break;
3610 case ISL_DIM_LAYOUT_GFX4_3D:
3611 get_image_offset_sa_gfx4_3d(surf, level, logical_array_layer +
3612 logical_z_offset_px,
3613 x_offset_sa, y_offset_sa);
3614 *z_offset_sa = 0;
3615 *array_offset = 0;
3616 break;
3617 case ISL_DIM_LAYOUT_GFX6_STENCIL_HIZ:
3618 get_image_offset_sa_gfx6_stencil_hiz(surf, level, logical_array_layer +
3619 logical_z_offset_px,
3620 x_offset_sa, y_offset_sa);
3621 *z_offset_sa = 0;
3622 *array_offset = 0;
3623 break;
3624
3625 default:
3626 unreachable("not reached");
3627 }
3628 }
3629
3630 void
isl_surf_get_image_offset_el(const struct isl_surf * surf,uint32_t level,uint32_t logical_array_layer,uint32_t logical_z_offset_px,uint32_t * x_offset_el,uint32_t * y_offset_el,uint32_t * z_offset_el,uint32_t * array_offset)3631 isl_surf_get_image_offset_el(const struct isl_surf *surf,
3632 uint32_t level,
3633 uint32_t logical_array_layer,
3634 uint32_t logical_z_offset_px,
3635 uint32_t *x_offset_el,
3636 uint32_t *y_offset_el,
3637 uint32_t *z_offset_el,
3638 uint32_t *array_offset)
3639 {
3640 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
3641
3642 assert(level < surf->levels);
3643 assert(logical_array_layer < surf->logical_level0_px.array_len);
3644 assert(logical_z_offset_px
3645 < isl_minify(surf->logical_level0_px.depth, level));
3646
3647 uint32_t x_offset_sa, y_offset_sa, z_offset_sa;
3648 isl_surf_get_image_offset_sa(surf, level,
3649 logical_array_layer,
3650 logical_z_offset_px,
3651 &x_offset_sa,
3652 &y_offset_sa,
3653 &z_offset_sa,
3654 array_offset);
3655
3656 *x_offset_el = x_offset_sa / fmtl->bw;
3657 *y_offset_el = y_offset_sa / fmtl->bh;
3658 *z_offset_el = z_offset_sa / fmtl->bd;
3659 }
3660
3661 void
isl_surf_get_image_offset_B_tile_sa(const struct isl_surf * surf,uint32_t level,uint32_t logical_array_layer,uint32_t logical_z_offset_px,uint64_t * offset_B,uint32_t * x_offset_sa,uint32_t * y_offset_sa)3662 isl_surf_get_image_offset_B_tile_sa(const struct isl_surf *surf,
3663 uint32_t level,
3664 uint32_t logical_array_layer,
3665 uint32_t logical_z_offset_px,
3666 uint64_t *offset_B,
3667 uint32_t *x_offset_sa,
3668 uint32_t *y_offset_sa)
3669 {
3670 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
3671
3672 uint32_t x_offset_el, y_offset_el;
3673 isl_surf_get_image_offset_B_tile_el(surf, level,
3674 logical_array_layer,
3675 logical_z_offset_px,
3676 offset_B,
3677 &x_offset_el,
3678 &y_offset_el);
3679
3680 if (x_offset_sa) {
3681 *x_offset_sa = x_offset_el * fmtl->bw;
3682 } else {
3683 assert(x_offset_el == 0);
3684 }
3685
3686 if (y_offset_sa) {
3687 *y_offset_sa = y_offset_el * fmtl->bh;
3688 } else {
3689 assert(y_offset_el == 0);
3690 }
3691 }
3692
3693 void
isl_surf_get_image_offset_B_tile_el(const struct isl_surf * surf,uint32_t level,uint32_t logical_array_layer,uint32_t logical_z_offset_px,uint64_t * offset_B,uint32_t * x_offset_el,uint32_t * y_offset_el)3694 isl_surf_get_image_offset_B_tile_el(const struct isl_surf *surf,
3695 uint32_t level,
3696 uint32_t logical_array_layer,
3697 uint32_t logical_z_offset_px,
3698 uint64_t *offset_B,
3699 uint32_t *x_offset_el,
3700 uint32_t *y_offset_el)
3701 {
3702 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
3703
3704 uint32_t total_x_offset_el, total_y_offset_el;
3705 uint32_t total_z_offset_el, total_array_offset;
3706 isl_surf_get_image_offset_el(surf, level, logical_array_layer,
3707 logical_z_offset_px,
3708 &total_x_offset_el,
3709 &total_y_offset_el,
3710 &total_z_offset_el,
3711 &total_array_offset);
3712
3713 uint32_t z_offset_el, array_offset;
3714 isl_tiling_get_intratile_offset_el(surf->tiling, surf->dim,
3715 surf->msaa_layout, fmtl->bpb,
3716 surf->samples,
3717 surf->row_pitch_B,
3718 surf->array_pitch_el_rows,
3719 total_x_offset_el,
3720 total_y_offset_el,
3721 total_z_offset_el,
3722 total_array_offset,
3723 offset_B,
3724 x_offset_el,
3725 y_offset_el,
3726 &z_offset_el,
3727 &array_offset);
3728 if (level >= surf->miptail_start_level) {
3729 /* We can do a byte offset to the first level of a miptail but we cannot
3730 * offset into a miptail.
3731 */
3732 assert(level == surf->miptail_start_level);
3733
3734 /* The byte offset will get us to the miptail page. The other offsets
3735 * are to the actual level within the miptail. It is assumed that the
3736 * caller will set up a texture with a miptail and use the hardware to
3737 * handle offseting inside the miptail.
3738 */
3739 *x_offset_el = 0;
3740 *y_offset_el = 0;
3741 } else {
3742 assert(z_offset_el == 0);
3743 assert(array_offset == 0);
3744 }
3745 }
3746
3747 void
isl_surf_get_image_range_B_tile(const struct isl_surf * surf,uint32_t level,uint32_t logical_array_layer,uint32_t logical_z_offset_px,uint64_t * start_tile_B,uint64_t * end_tile_B)3748 isl_surf_get_image_range_B_tile(const struct isl_surf *surf,
3749 uint32_t level,
3750 uint32_t logical_array_layer,
3751 uint32_t logical_z_offset_px,
3752 uint64_t *start_tile_B,
3753 uint64_t *end_tile_B)
3754 {
3755 uint32_t start_x_offset_el, start_y_offset_el;
3756 uint32_t start_z_offset_el, start_array_slice;
3757 isl_surf_get_image_offset_el(surf, level, logical_array_layer,
3758 logical_z_offset_px,
3759 &start_x_offset_el,
3760 &start_y_offset_el,
3761 &start_z_offset_el,
3762 &start_array_slice);
3763
3764 /* Compute the size of the subimage in surface elements */
3765 const uint32_t subimage_w_sa = isl_minify(surf->phys_level0_sa.w, level);
3766 const uint32_t subimage_h_sa = isl_minify(surf->phys_level0_sa.h, level);
3767 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
3768 const uint32_t subimage_w_el = isl_align_div_npot(subimage_w_sa, fmtl->bw);
3769 const uint32_t subimage_h_el = isl_align_div_npot(subimage_h_sa, fmtl->bh);
3770
3771 /* Find the last pixel */
3772 uint32_t end_x_offset_el = start_x_offset_el + subimage_w_el - 1;
3773 uint32_t end_y_offset_el = start_y_offset_el + subimage_h_el - 1;
3774
3775 /* We only consider one Z or array slice */
3776 const uint32_t end_z_offset_el = start_z_offset_el;
3777 const uint32_t end_array_slice = start_array_slice;
3778
3779 UNUSED uint32_t x_offset_el, y_offset_el, z_offset_el, array_slice;
3780 isl_tiling_get_intratile_offset_el(surf->tiling, surf->dim,
3781 surf->msaa_layout, fmtl->bpb,
3782 surf->samples,
3783 surf->row_pitch_B,
3784 surf->array_pitch_el_rows,
3785 start_x_offset_el,
3786 start_y_offset_el,
3787 start_z_offset_el,
3788 start_array_slice,
3789 start_tile_B,
3790 &x_offset_el,
3791 &y_offset_el,
3792 &z_offset_el,
3793 &array_slice);
3794
3795 isl_tiling_get_intratile_offset_el(surf->tiling, surf->dim,
3796 surf->msaa_layout, fmtl->bpb,
3797 surf->samples,
3798 surf->row_pitch_B,
3799 surf->array_pitch_el_rows,
3800 end_x_offset_el,
3801 end_y_offset_el,
3802 end_z_offset_el,
3803 end_array_slice,
3804 end_tile_B,
3805 &x_offset_el,
3806 &y_offset_el,
3807 &z_offset_el,
3808 &array_slice);
3809
3810 struct isl_tile_info tile_info;
3811 isl_surf_get_tile_info(surf, &tile_info);
3812
3813 /* We want the range we return to be exclusive but the tile containing the
3814 * last pixel (what we just calculated) is inclusive. Add one and round up
3815 * to the tile size.
3816 */
3817 *end_tile_B = ALIGN_NPOT(*end_tile_B + 1, tile_info.phys_extent_B.w *
3818 tile_info.phys_extent_B.h);
3819
3820 assert(*end_tile_B <= surf->size_B);
3821 }
3822
3823 void
isl_surf_get_image_surf(const struct isl_device * dev,const struct isl_surf * surf,uint32_t level,uint32_t logical_array_layer,uint32_t logical_z_offset_px,struct isl_surf * image_surf,uint64_t * offset_B,uint32_t * x_offset_sa,uint32_t * y_offset_sa)3824 isl_surf_get_image_surf(const struct isl_device *dev,
3825 const struct isl_surf *surf,
3826 uint32_t level,
3827 uint32_t logical_array_layer,
3828 uint32_t logical_z_offset_px,
3829 struct isl_surf *image_surf,
3830 uint64_t *offset_B,
3831 uint32_t *x_offset_sa,
3832 uint32_t *y_offset_sa)
3833 {
3834 isl_surf_get_image_offset_B_tile_sa(surf,
3835 level,
3836 logical_array_layer,
3837 logical_z_offset_px,
3838 offset_B,
3839 x_offset_sa,
3840 y_offset_sa);
3841
3842 /* Even for cube maps there will be only single face, therefore drop the
3843 * corresponding flag if present.
3844 */
3845 const isl_surf_usage_flags_t usage =
3846 surf->usage & (~ISL_SURF_USAGE_CUBE_BIT);
3847
3848 bool ok UNUSED;
3849 ok = isl_surf_init(dev, image_surf,
3850 .dim = ISL_SURF_DIM_2D,
3851 .format = surf->format,
3852 .width = isl_minify(surf->logical_level0_px.w, level),
3853 .height = isl_minify(surf->logical_level0_px.h, level),
3854 .depth = 1,
3855 .levels = 1,
3856 .array_len = 1,
3857 .samples = surf->samples,
3858 .row_pitch_B = surf->row_pitch_B,
3859 .usage = usage,
3860 .tiling_flags = (1 << surf->tiling));
3861 assert(ok);
3862 }
3863
3864 bool
isl_surf_get_uncompressed_surf(const struct isl_device * dev,const struct isl_surf * _surf,const struct isl_view * _view,struct isl_surf * ucompr_surf,struct isl_view * ucompr_view,uint64_t * offset_B,uint32_t * x_offset_el,uint32_t * y_offset_el)3865 isl_surf_get_uncompressed_surf(const struct isl_device *dev,
3866 const struct isl_surf *_surf,
3867 const struct isl_view *_view,
3868 struct isl_surf *ucompr_surf,
3869 struct isl_view *ucompr_view,
3870 uint64_t *offset_B,
3871 uint32_t *x_offset_el,
3872 uint32_t *y_offset_el)
3873 {
3874 /* Input and output pointers may be the same, save the input contents now. */
3875 const struct isl_surf __surf = *_surf, *surf = &__surf;
3876 const struct isl_view __view = *_view, *view = &__view;
3877 const struct isl_format_layout *fmtl =
3878 isl_format_get_layout(surf->format);
3879 const enum isl_format view_format = view->format;
3880
3881 assert(fmtl->bw > 1 || fmtl->bh > 1 || fmtl->bd > 1);
3882 assert(isl_format_is_compressed(surf->format));
3883 assert(!isl_format_is_compressed(view->format));
3884 assert(isl_format_get_layout(view->format)->bpb == fmtl->bpb);
3885 assert(view->levels == 1);
3886
3887 const uint32_t view_width_px =
3888 isl_minify(surf->logical_level0_px.width, view->base_level);
3889 const uint32_t view_height_px =
3890 isl_minify(surf->logical_level0_px.height, view->base_level);
3891
3892 assert(surf->samples == 1);
3893 const uint32_t view_width_el = isl_align_div_npot(view_width_px, fmtl->bw);
3894 const uint32_t view_height_el = isl_align_div_npot(view_height_px, fmtl->bh);
3895
3896 /* If we ever enable 3D block formats, we'll need to re-think this */
3897 assert(fmtl->bd == 1);
3898
3899 if (isl_tiling_is_std_y(surf->tiling) ||
3900 isl_tiling_is_64(surf->tiling)) {
3901 /* If the requested level is not part of the miptail, we just offset to
3902 * the requested level. Because we're using standard tilings and aren't
3903 * in the miptail, arrays and 3D textures should just work so long as we
3904 * have the right array stride in the end.
3905 *
3906 * If the requested level is in the miptail, we instead offset to the
3907 * base of the miptail. Because offsets into the miptail are fixed by
3908 * the tiling and don't depend on the actual size of the image, we can
3909 * set the level in the view to offset into the miptail regardless of
3910 * the fact minification yields different results for the compressed and
3911 * uncompressed surface.
3912 */
3913 const uint32_t base_level =
3914 MIN(view->base_level, surf->miptail_start_level);
3915
3916 isl_surf_get_image_offset_B_tile_el(surf, base_level, 0, 0,
3917 offset_B, x_offset_el, y_offset_el);
3918 /* Tile64, Ys and Yf should have no intratile X or Y offset */
3919 assert(*x_offset_el == 0 && *y_offset_el == 0);
3920
3921 /* Save off the array pitch */
3922 const uint32_t array_pitch_el_rows = surf->array_pitch_el_rows;
3923
3924 const uint32_t view_depth_px =
3925 isl_minify(surf->logical_level0_px.depth, view->base_level);
3926 const uint32_t view_depth_el =
3927 isl_align_div_npot(view_depth_px, fmtl->bd);
3928
3929 /* We need to compute the size of the uncompressed surface we will
3930 * create. If we're not in the miptail, it is just the view size in
3931 * surface elements. If we are in a miptail, we need a size that will
3932 * minify to the view size in surface elements. This may not be the same
3933 * as the size of base_level, but that's not a problem. Slot offsets are
3934 * fixed in HW (see the tables used in isl_get_miptail_level_offset_el).
3935 */
3936 const uint32_t ucompr_level = view->base_level - base_level;
3937
3938 /* The > 1 check is here to prevent a change in the surface's overall
3939 * dimension (e.g. 2D->3D).
3940 *
3941 * Also having a base_level dimension = 1 doesn´t mean the HW will
3942 * ignore higher mip level. Once the dimension has reached 1, it'll stay
3943 * at 1 in the higher mip levels.
3944 */
3945 struct isl_extent3d ucompr_surf_extent_el = {
3946 .w = view_width_el > 1 ? view_width_el << ucompr_level : 1,
3947 .h = view_height_el > 1 ? view_height_el << ucompr_level : 1,
3948 .d = view_depth_el > 1 ? view_depth_el << ucompr_level : 1,
3949 };
3950
3951 isl_surf_usage_flags_t usage = surf->usage;
3952 /* CCS-enabled surfaces can have different layout requirements than
3953 * surfaces without CCS support. So, for accuracy, disable CCS
3954 * support if the original surface lacked it.
3955 */
3956 if (_isl_surf_info_supports_ccs(dev, surf->format, surf->usage) !=
3957 _isl_surf_info_supports_ccs(dev, view_format, usage)) {
3958 assert(_isl_surf_info_supports_ccs(dev, view_format, usage));
3959 usage |= ISL_SURF_USAGE_DISABLE_AUX_BIT;
3960 }
3961
3962 bool ok UNUSED;
3963 ok = isl_surf_init(dev, ucompr_surf,
3964 .dim = surf->dim,
3965 .format = view->format,
3966 .width = ucompr_surf_extent_el.width,
3967 .height = ucompr_surf_extent_el.height,
3968 .depth = ucompr_surf_extent_el.depth,
3969 .levels = ucompr_level + 1,
3970 .array_len = surf->logical_level0_px.array_len,
3971 .samples = surf->samples,
3972 .min_miptail_start_level =
3973 (int) (view->base_level < surf->miptail_start_level),
3974 .row_pitch_B = surf->row_pitch_B,
3975 .usage = usage,
3976 .tiling_flags = (1u << surf->tiling));
3977 assert(ok);
3978
3979 /* Use the array pitch from the original surface. This way 2D arrays
3980 * and 3D textures should work properly, just with one LOD.
3981 */
3982 assert(ucompr_surf->array_pitch_el_rows <= array_pitch_el_rows);
3983 ucompr_surf->array_pitch_el_rows = array_pitch_el_rows;
3984
3985 /* The newly created image represents only the one miplevel so we
3986 * need to adjust the view accordingly. Because we offset it to
3987 * miplevel but used a Z and array slice of 0, the array range can be
3988 * left alone.
3989 */
3990 *ucompr_view = *view;
3991 ucompr_view->base_level -= base_level;
3992 } else {
3993 if (view->array_len > 1) {
3994 /* The Skylake PRM Vol. 2d, "RENDER_SURFACE_STATE::X Offset" says:
3995 *
3996 * "If Surface Array is enabled, this field must be zero."
3997 *
3998 * The PRMs for other hardware have similar text. This is also tricky
3999 * to handle with things like BLORP's SW offsetting because the
4000 * increased surface size required for the offset may result in an
4001 * image height greater than qpitch.
4002 */
4003 if (view->base_level > 0)
4004 return false;
4005
4006 /* On Haswell and earlier, RENDER_SURFACE_STATE doesn't have a QPitch
4007 * field; it only has "array pitch span" which means the QPitch is
4008 * automatically calculated. Since we're smashing the surface format
4009 * (block formats are subtly different) and the number of miplevels,
4010 * that calculation will get thrown off. This means we can't do
4011 * arrays even at LOD0
4012 *
4013 * On Broadwell, we do have a QPitch field which we can control.
4014 * However, HALIGN and VALIGN are specified in pixels and are
4015 * hard-coded to align to exactly the block size of the compressed
4016 * texture. This means that, when reinterpreted as a non-compressed
4017 * the QPitch may be anything but the HW requires it to be properly
4018 * aligned.
4019 */
4020 if (ISL_GFX_VER(dev) < 9)
4021 return false;
4022
4023 *ucompr_surf = *surf;
4024 ucompr_surf->levels = 1;
4025 ucompr_surf->format = view_format;
4026
4027 /* We're making an uncompressed view here. The image dimensions need
4028 * to be scaled down by the block size.
4029 */
4030 assert(ucompr_surf->logical_level0_px.width == view_width_px);
4031 assert(ucompr_surf->logical_level0_px.height == view_height_px);
4032 ucompr_surf->logical_level0_px.width = view_width_el;
4033 ucompr_surf->logical_level0_px.height = view_height_el;
4034 ucompr_surf->phys_level0_sa = isl_surf_get_phys_level0_el(surf);
4035
4036 /* The surface mostly stays as-is; there is no offset */
4037 *offset_B = 0;
4038 *x_offset_el = 0;
4039 *y_offset_el = 0;
4040
4041 /* The view remains the same */
4042 *ucompr_view = *view;
4043 } else {
4044 /* If only one array slice is requested, directly offset to that
4045 * slice. We could, in theory, still use arrays in some cases but
4046 * BLORP isn't prepared for this and everyone who calls this function
4047 * should be prepared to handle an X/Y offset.
4048 */
4049 isl_surf_get_image_offset_B_tile_el(surf,
4050 view->base_level,
4051 surf->dim == ISL_SURF_DIM_3D ?
4052 0 : view->base_array_layer,
4053 surf->dim == ISL_SURF_DIM_3D ?
4054 view->base_array_layer : 0,
4055 offset_B,
4056 x_offset_el,
4057 y_offset_el);
4058
4059 isl_surf_usage_flags_t usage = surf->usage;
4060
4061 /* Even for cube maps there will be only single face, therefore drop
4062 * the corresponding flag if present.
4063 */
4064 usage &= ~ISL_SURF_USAGE_CUBE_BIT;
4065
4066 /* CCS-enabled surfaces can have different layout requirements than
4067 * surfaces without CCS support. So, for accuracy, disable CCS
4068 * support if the original surface lacked it.
4069 */
4070 if (_isl_surf_info_supports_ccs(dev, surf->format, surf->usage) !=
4071 _isl_surf_info_supports_ccs(dev, view_format, usage)) {
4072 assert(_isl_surf_info_supports_ccs(dev, view_format, usage));
4073 usage |= ISL_SURF_USAGE_DISABLE_AUX_BIT;
4074 }
4075
4076 bool ok UNUSED;
4077 ok = isl_surf_init(dev, ucompr_surf,
4078 .dim = ISL_SURF_DIM_2D,
4079 .format = view_format,
4080 .width = view_width_el,
4081 .height = view_height_el,
4082 .depth = 1,
4083 .levels = 1,
4084 .array_len = 1,
4085 .samples = 1,
4086 .row_pitch_B = surf->row_pitch_B,
4087 .usage = usage,
4088 .tiling_flags = (1 << surf->tiling));
4089 assert(ok);
4090
4091 /* The newly created image represents the one subimage we're
4092 * referencing with this view so it only has one array slice and
4093 * miplevel.
4094 */
4095 *ucompr_view = *view;
4096 ucompr_view->base_array_layer = 0;
4097 ucompr_view->base_level = 0;
4098 }
4099 }
4100
4101 return true;
4102 }
4103
4104 void
isl_tiling_get_intratile_offset_el(enum isl_tiling tiling,enum isl_surf_dim dim,enum isl_msaa_layout msaa_layout,uint32_t bpb,uint32_t samples,uint32_t row_pitch_B,uint32_t array_pitch_el_rows,uint32_t total_x_offset_el,uint32_t total_y_offset_el,uint32_t total_z_offset_el,uint32_t total_array_offset,uint64_t * tile_offset_B,uint32_t * x_offset_el,uint32_t * y_offset_el,uint32_t * z_offset_el,uint32_t * array_offset)4105 isl_tiling_get_intratile_offset_el(enum isl_tiling tiling,
4106 enum isl_surf_dim dim,
4107 enum isl_msaa_layout msaa_layout,
4108 uint32_t bpb,
4109 uint32_t samples,
4110 uint32_t row_pitch_B,
4111 uint32_t array_pitch_el_rows,
4112 uint32_t total_x_offset_el,
4113 uint32_t total_y_offset_el,
4114 uint32_t total_z_offset_el,
4115 uint32_t total_array_offset,
4116 uint64_t *tile_offset_B,
4117 uint32_t *x_offset_el,
4118 uint32_t *y_offset_el,
4119 uint32_t *z_offset_el,
4120 uint32_t *array_offset)
4121 {
4122 if (tiling == ISL_TILING_LINEAR) {
4123 assert(bpb % 8 == 0);
4124 assert(samples == 1);
4125 assert(total_z_offset_el == 0 && total_array_offset == 0);
4126 *tile_offset_B = (uint64_t)total_y_offset_el * row_pitch_B +
4127 (uint64_t)total_x_offset_el * (bpb / 8);
4128 *x_offset_el = 0;
4129 *y_offset_el = 0;
4130 *z_offset_el = 0;
4131 *array_offset = 0;
4132 return;
4133 }
4134
4135 struct isl_tile_info tile_info;
4136 isl_tiling_get_info(tiling, dim, msaa_layout, bpb, samples, &tile_info);
4137
4138 /* Pitches must make sense with the tiling */
4139 assert(row_pitch_B % tile_info.phys_extent_B.width == 0);
4140 if (tile_info.logical_extent_el.d > 1 || tile_info.logical_extent_el.a > 1)
4141 assert(array_pitch_el_rows % tile_info.logical_extent_el.h == 0);
4142
4143 /* For non-power-of-two formats, we need the address to be both tile and
4144 * element-aligned. The easiest way to achieve this is to work with a tile
4145 * that is three times as wide as the regular tile.
4146 *
4147 * The tile info returned by get_tile_info has a logical size that is an
4148 * integer number of tile_info.format_bpb size elements. To scale the
4149 * tile, we scale up the physical width and then treat the logical tile
4150 * size as if it has bpb size elements.
4151 */
4152 const uint32_t tile_el_scale = bpb / tile_info.format_bpb;
4153 tile_info.phys_extent_B.width *= tile_el_scale;
4154
4155 /* Compute the offset into the tile */
4156 *x_offset_el = total_x_offset_el % tile_info.logical_extent_el.w;
4157 *y_offset_el = total_y_offset_el % tile_info.logical_extent_el.h;
4158 *z_offset_el = total_z_offset_el % tile_info.logical_extent_el.d;
4159 *array_offset = total_array_offset % tile_info.logical_extent_el.a;
4160
4161 /* Compute the offset of the tile in units of whole tiles */
4162 uint32_t x_offset_tl = total_x_offset_el / tile_info.logical_extent_el.w;
4163 uint32_t y_offset_tl = total_y_offset_el / tile_info.logical_extent_el.h;
4164 uint32_t z_offset_tl = total_z_offset_el / tile_info.logical_extent_el.d;
4165 uint32_t a_offset_tl = total_array_offset / tile_info.logical_extent_el.a;
4166
4167 /* Compute an array pitch in number of tiles */
4168 uint32_t array_pitch_tl_rows =
4169 array_pitch_el_rows / tile_info.logical_extent_el.h;
4170
4171 /* Add the Z and array offset to the Y offset to get a 2D offset */
4172 y_offset_tl += (z_offset_tl + a_offset_tl) * array_pitch_tl_rows;
4173
4174 *tile_offset_B =
4175 (uint64_t)y_offset_tl * tile_info.phys_extent_B.h * row_pitch_B +
4176 (uint64_t)x_offset_tl * tile_info.phys_extent_B.h * tile_info.phys_extent_B.w;
4177 }
4178
4179 uint32_t
isl_surf_get_depth_format(const struct isl_device * dev,const struct isl_surf * surf)4180 isl_surf_get_depth_format(const struct isl_device *dev,
4181 const struct isl_surf *surf)
4182 {
4183 /* Support for separate stencil buffers began in gfx5. Support for
4184 * interleaved depthstencil buffers ceased in gfx7. The intermediate gens,
4185 * those that supported separate and interleaved stencil, were gfx5 and
4186 * gfx6.
4187 *
4188 * For a list of all available formats, see the Sandybridge PRM >> Volume
4189 * 2 Part 1: 3D/Media - 3D Pipeline >> 3DSTATE_DEPTH_BUFFER >> Surface
4190 * Format (p321).
4191 */
4192
4193 bool has_stencil = surf->usage & ISL_SURF_USAGE_STENCIL_BIT;
4194
4195 assert(surf->usage & ISL_SURF_USAGE_DEPTH_BIT);
4196
4197 if (has_stencil)
4198 assert(ISL_GFX_VER(dev) < 7);
4199
4200 switch (surf->format) {
4201 default:
4202 unreachable("bad isl depth format");
4203 case ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS:
4204 assert(ISL_GFX_VER(dev) < 7);
4205 return 0; /* D32_FLOAT_S8X24_UINT */
4206 case ISL_FORMAT_R32_FLOAT:
4207 assert(!has_stencil);
4208 return 1; /* D32_FLOAT */
4209 case ISL_FORMAT_R24_UNORM_X8_TYPELESS:
4210 if (has_stencil) {
4211 assert(ISL_GFX_VER(dev) < 7);
4212 return 2; /* D24_UNORM_S8_UINT */
4213 } else {
4214 assert(ISL_GFX_VER(dev) >= 5);
4215 return 3; /* D24_UNORM_X8_UINT */
4216 }
4217 case ISL_FORMAT_R16_UNORM:
4218 assert(!has_stencil);
4219 return 5; /* D16_UNORM */
4220 }
4221 }
4222
4223 bool
isl_swizzle_supports_rendering(const struct intel_device_info * devinfo,struct isl_swizzle swizzle)4224 isl_swizzle_supports_rendering(const struct intel_device_info *devinfo,
4225 struct isl_swizzle swizzle)
4226 {
4227 if (devinfo->platform == INTEL_PLATFORM_HSW) {
4228 /* From the Haswell PRM,
4229 * RENDER_SURFACE_STATE::Shader Channel Select Red
4230 *
4231 * "The Shader channel selects also define which shader channels are
4232 * written to which surface channel. If the Shader channel select is
4233 * SCS_ZERO or SCS_ONE then it is not written to the surface. If the
4234 * shader channel select is SCS_RED it is written to the surface red
4235 * channel and so on. If more than one shader channel select is set
4236 * to the same surface channel only the first shader channel in RGBA
4237 * order will be written."
4238 */
4239 return true;
4240 } else if (devinfo->ver <= 7) {
4241 /* Ivy Bridge and early doesn't have any swizzling */
4242 return isl_swizzle_is_identity(swizzle);
4243 } else {
4244 /* From the Sky Lake PRM Vol. 2d,
4245 * RENDER_SURFACE_STATE::Shader Channel Select Red
4246 *
4247 * "For Render Target, Red, Green and Blue Shader Channel Selects
4248 * MUST be such that only valid components can be swapped i.e. only
4249 * change the order of components in the pixel. Any other values for
4250 * these Shader Channel Select fields are not valid for Render
4251 * Targets. This also means that there MUST not be multiple shader
4252 * channels mapped to the same RT channel."
4253 *
4254 * From the Sky Lake PRM Vol. 2d,
4255 * RENDER_SURFACE_STATE::Shader Channel Select Alpha
4256 *
4257 * "For Render Target, this field MUST be programmed to
4258 * value = SCS_ALPHA."
4259 *
4260 * Bspec 57023: RENDER_SURFACE_STATE:: Shader Channel Select Red
4261 *
4262 * "Render Target messages do not support swapping of colors with
4263 * alpha. The Red, Green, or Blue Shader Channel Selects do not
4264 * support SCS_ALPHA. The Shader Channel Select Alpha does not support
4265 * SCS_RED, SCS_GREEN, or SCS_BLUE."
4266 */
4267 return (swizzle.r == ISL_CHANNEL_SELECT_RED ||
4268 swizzle.r == ISL_CHANNEL_SELECT_GREEN ||
4269 swizzle.r == ISL_CHANNEL_SELECT_BLUE) &&
4270 (swizzle.g == ISL_CHANNEL_SELECT_RED ||
4271 swizzle.g == ISL_CHANNEL_SELECT_GREEN ||
4272 swizzle.g == ISL_CHANNEL_SELECT_BLUE) &&
4273 (swizzle.b == ISL_CHANNEL_SELECT_RED ||
4274 swizzle.b == ISL_CHANNEL_SELECT_GREEN ||
4275 swizzle.b == ISL_CHANNEL_SELECT_BLUE) &&
4276 swizzle.r != swizzle.g &&
4277 swizzle.r != swizzle.b &&
4278 swizzle.g != swizzle.b &&
4279 swizzle.a == ISL_CHANNEL_SELECT_ALPHA;
4280 }
4281 }
4282
4283 static enum isl_channel_select
swizzle_select(enum isl_channel_select chan,struct isl_swizzle swizzle)4284 swizzle_select(enum isl_channel_select chan, struct isl_swizzle swizzle)
4285 {
4286 switch (chan) {
4287 case ISL_CHANNEL_SELECT_ZERO:
4288 case ISL_CHANNEL_SELECT_ONE:
4289 return chan;
4290 case ISL_CHANNEL_SELECT_RED:
4291 return swizzle.r;
4292 case ISL_CHANNEL_SELECT_GREEN:
4293 return swizzle.g;
4294 case ISL_CHANNEL_SELECT_BLUE:
4295 return swizzle.b;
4296 case ISL_CHANNEL_SELECT_ALPHA:
4297 return swizzle.a;
4298 default:
4299 unreachable("Invalid swizzle component");
4300 }
4301 }
4302
4303 /**
4304 * Returns the single swizzle that is equivalent to applying the two given
4305 * swizzles in sequence.
4306 */
4307 struct isl_swizzle
isl_swizzle_compose(struct isl_swizzle first,struct isl_swizzle second)4308 isl_swizzle_compose(struct isl_swizzle first, struct isl_swizzle second)
4309 {
4310 return (struct isl_swizzle) {
4311 .r = swizzle_select(first.r, second),
4312 .g = swizzle_select(first.g, second),
4313 .b = swizzle_select(first.b, second),
4314 .a = swizzle_select(first.a, second),
4315 };
4316 }
4317
4318 /**
4319 * Returns a swizzle that is the pseudo-inverse of this swizzle.
4320 */
4321 struct isl_swizzle
isl_swizzle_invert(struct isl_swizzle swizzle)4322 isl_swizzle_invert(struct isl_swizzle swizzle)
4323 {
4324 /* Default to zero for channels which do not show up in the swizzle */
4325 enum isl_channel_select chans[4] = {
4326 ISL_CHANNEL_SELECT_ZERO,
4327 ISL_CHANNEL_SELECT_ZERO,
4328 ISL_CHANNEL_SELECT_ZERO,
4329 ISL_CHANNEL_SELECT_ZERO,
4330 };
4331
4332 /* We go in ABGR order so that, if there are any duplicates, the first one
4333 * is taken if you look at it in RGBA order. This is what Haswell hardware
4334 * does for render target swizzles.
4335 */
4336 if ((unsigned)(swizzle.a - ISL_CHANNEL_SELECT_RED) < 4)
4337 chans[swizzle.a - ISL_CHANNEL_SELECT_RED] = ISL_CHANNEL_SELECT_ALPHA;
4338 if ((unsigned)(swizzle.b - ISL_CHANNEL_SELECT_RED) < 4)
4339 chans[swizzle.b - ISL_CHANNEL_SELECT_RED] = ISL_CHANNEL_SELECT_BLUE;
4340 if ((unsigned)(swizzle.g - ISL_CHANNEL_SELECT_RED) < 4)
4341 chans[swizzle.g - ISL_CHANNEL_SELECT_RED] = ISL_CHANNEL_SELECT_GREEN;
4342 if ((unsigned)(swizzle.r - ISL_CHANNEL_SELECT_RED) < 4)
4343 chans[swizzle.r - ISL_CHANNEL_SELECT_RED] = ISL_CHANNEL_SELECT_RED;
4344
4345 return (struct isl_swizzle) { chans[0], chans[1], chans[2], chans[3] };
4346 }
4347
4348 static uint32_t
isl_color_value_channel(union isl_color_value src,enum isl_channel_select chan,uint32_t one)4349 isl_color_value_channel(union isl_color_value src,
4350 enum isl_channel_select chan,
4351 uint32_t one)
4352 {
4353 if (chan == ISL_CHANNEL_SELECT_ZERO)
4354 return 0;
4355 if (chan == ISL_CHANNEL_SELECT_ONE)
4356 return one;
4357
4358 assert(chan >= ISL_CHANNEL_SELECT_RED);
4359 assert(chan < ISL_CHANNEL_SELECT_RED + 4);
4360
4361 return src.u32[chan - ISL_CHANNEL_SELECT_RED];
4362 }
4363
4364 /** Applies an inverse swizzle to a color value */
4365 union isl_color_value
isl_color_value_swizzle(union isl_color_value src,struct isl_swizzle swizzle,bool is_float)4366 isl_color_value_swizzle(union isl_color_value src,
4367 struct isl_swizzle swizzle,
4368 bool is_float)
4369 {
4370 uint32_t one = is_float ? 0x3f800000 : 1;
4371
4372 return (union isl_color_value) { .u32 = {
4373 isl_color_value_channel(src, swizzle.r, one),
4374 isl_color_value_channel(src, swizzle.g, one),
4375 isl_color_value_channel(src, swizzle.b, one),
4376 isl_color_value_channel(src, swizzle.a, one),
4377 } };
4378 }
4379
4380 /** Applies an inverse swizzle to a color value */
4381 union isl_color_value
isl_color_value_swizzle_inv(union isl_color_value src,struct isl_swizzle swizzle)4382 isl_color_value_swizzle_inv(union isl_color_value src,
4383 struct isl_swizzle swizzle)
4384 {
4385 union isl_color_value dst = { .u32 = { 0, } };
4386
4387 /* We assign colors in ABGR order so that the first one will be taken in
4388 * RGBA precedence order. According to the PRM docs for shader channel
4389 * select, this matches Haswell hardware behavior.
4390 */
4391 if ((unsigned)(swizzle.a - ISL_CHANNEL_SELECT_RED) < 4)
4392 dst.u32[swizzle.a - ISL_CHANNEL_SELECT_RED] = src.u32[3];
4393 if ((unsigned)(swizzle.b - ISL_CHANNEL_SELECT_RED) < 4)
4394 dst.u32[swizzle.b - ISL_CHANNEL_SELECT_RED] = src.u32[2];
4395 if ((unsigned)(swizzle.g - ISL_CHANNEL_SELECT_RED) < 4)
4396 dst.u32[swizzle.g - ISL_CHANNEL_SELECT_RED] = src.u32[1];
4397 if ((unsigned)(swizzle.r - ISL_CHANNEL_SELECT_RED) < 4)
4398 dst.u32[swizzle.r - ISL_CHANNEL_SELECT_RED] = src.u32[0];
4399
4400 return dst;
4401 }
4402
4403 uint8_t
isl_format_get_aux_map_encoding(enum isl_format format)4404 isl_format_get_aux_map_encoding(enum isl_format format)
4405 {
4406 switch(format) {
4407 case ISL_FORMAT_R32G32B32A32_FLOAT: return 0x11;
4408 case ISL_FORMAT_R32G32B32X32_FLOAT: return 0x11;
4409 case ISL_FORMAT_R32G32B32A32_SINT: return 0x12;
4410 case ISL_FORMAT_R32G32B32A32_UINT: return 0x13;
4411 case ISL_FORMAT_R16G16B16A16_UNORM: return 0x14;
4412 case ISL_FORMAT_R16G16B16A16_SNORM: return 0x15;
4413 case ISL_FORMAT_R16G16B16A16_SINT: return 0x16;
4414 case ISL_FORMAT_R16G16B16A16_UINT: return 0x17;
4415 case ISL_FORMAT_R16G16B16A16_FLOAT: return 0x10;
4416 case ISL_FORMAT_R16G16B16X16_FLOAT: return 0x10;
4417 case ISL_FORMAT_R32G32_FLOAT: return 0x11;
4418 case ISL_FORMAT_R32G32_SINT: return 0x12;
4419 case ISL_FORMAT_R32G32_UINT: return 0x13;
4420 case ISL_FORMAT_B8G8R8A8_UNORM: return 0xA;
4421 case ISL_FORMAT_B8G8R8X8_UNORM: return 0xA;
4422 case ISL_FORMAT_B8G8R8A8_UNORM_SRGB: return 0xA;
4423 case ISL_FORMAT_B8G8R8X8_UNORM_SRGB: return 0xA;
4424 case ISL_FORMAT_R10G10B10A2_UNORM: return 0x18;
4425 case ISL_FORMAT_R10G10B10A2_UNORM_SRGB: return 0x18;
4426 case ISL_FORMAT_R10G10B10_FLOAT_A2_UNORM: return 0x19;
4427 case ISL_FORMAT_R10G10B10A2_UINT: return 0x1A;
4428 case ISL_FORMAT_R8G8B8A8_UNORM: return 0xA;
4429 case ISL_FORMAT_R8G8B8A8_UNORM_SRGB: return 0xA;
4430 case ISL_FORMAT_R8G8B8A8_SNORM: return 0x1B;
4431 case ISL_FORMAT_R8G8B8A8_SINT: return 0x1C;
4432 case ISL_FORMAT_R8G8B8A8_UINT: return 0x1D;
4433 case ISL_FORMAT_R16G16_UNORM: return 0x14;
4434 case ISL_FORMAT_R16G16_SNORM: return 0x15;
4435 case ISL_FORMAT_R16G16_SINT: return 0x16;
4436 case ISL_FORMAT_R16G16_UINT: return 0x17;
4437 case ISL_FORMAT_R16G16_FLOAT: return 0x10;
4438 case ISL_FORMAT_B10G10R10A2_UNORM: return 0x18;
4439 case ISL_FORMAT_B10G10R10A2_UNORM_SRGB: return 0x18;
4440 case ISL_FORMAT_R11G11B10_FLOAT: return 0x1E;
4441 case ISL_FORMAT_R32_SINT: return 0x12;
4442 case ISL_FORMAT_R32_UINT: return 0x13;
4443 case ISL_FORMAT_R32_FLOAT: return 0x11;
4444 case ISL_FORMAT_R24_UNORM_X8_TYPELESS: return 0x13;
4445 case ISL_FORMAT_B5G6R5_UNORM: return 0xA;
4446 case ISL_FORMAT_B5G6R5_UNORM_SRGB: return 0xA;
4447 case ISL_FORMAT_B5G5R5A1_UNORM: return 0xA;
4448 case ISL_FORMAT_B5G5R5A1_UNORM_SRGB: return 0xA;
4449 case ISL_FORMAT_B4G4R4A4_UNORM: return 0xA;
4450 case ISL_FORMAT_B4G4R4A4_UNORM_SRGB: return 0xA;
4451 case ISL_FORMAT_R8G8_UNORM: return 0xA;
4452 case ISL_FORMAT_R8G8_SNORM: return 0x1B;
4453 case ISL_FORMAT_R8G8_SINT: return 0x1C;
4454 case ISL_FORMAT_R8G8_UINT: return 0x1D;
4455 case ISL_FORMAT_R16_UNORM: return 0x14;
4456 case ISL_FORMAT_R16_SNORM: return 0x15;
4457 case ISL_FORMAT_R16_SINT: return 0x16;
4458 case ISL_FORMAT_R16_UINT: return 0x17;
4459 case ISL_FORMAT_R16_FLOAT: return 0x10;
4460 case ISL_FORMAT_B5G5R5X1_UNORM: return 0xA;
4461 case ISL_FORMAT_B5G5R5X1_UNORM_SRGB: return 0xA;
4462 case ISL_FORMAT_A1B5G5R5_UNORM: return 0xA;
4463 case ISL_FORMAT_A4B4G4R4_UNORM: return 0xA;
4464 case ISL_FORMAT_R8_UNORM: return 0xA;
4465 case ISL_FORMAT_R8_SNORM: return 0x1B;
4466 case ISL_FORMAT_R8_SINT: return 0x1C;
4467 case ISL_FORMAT_R8_UINT: return 0x1D;
4468 case ISL_FORMAT_A8_UNORM: return 0xA;
4469 case ISL_FORMAT_PLANAR_420_8: return 0xF;
4470 case ISL_FORMAT_PLANAR_420_10: return 0x7;
4471 case ISL_FORMAT_PLANAR_420_12: return 0x8;
4472 case ISL_FORMAT_PLANAR_420_16: return 0x8;
4473 case ISL_FORMAT_YCRCB_NORMAL: return 0x3;
4474 case ISL_FORMAT_YCRCB_SWAPY: return 0xB;
4475 default:
4476 unreachable("Unsupported aux-map format!");
4477 return 0;
4478 }
4479 }
4480
4481 const char *
isl_aux_op_to_name(enum isl_aux_op op)4482 isl_aux_op_to_name(enum isl_aux_op op)
4483 {
4484 static const char *names[] = {
4485 [ISL_AUX_OP_NONE] = "none",
4486 [ISL_AUX_OP_FAST_CLEAR] = "fast-clear",
4487 [ISL_AUX_OP_FULL_RESOLVE] = "full-resolve",
4488 [ISL_AUX_OP_PARTIAL_RESOLVE] = "partial-resolve",
4489 [ISL_AUX_OP_AMBIGUATE] = "ambiguate",
4490 };
4491 assert(op < ARRAY_SIZE(names));
4492 return names[op];
4493 }
4494
4495 const char *
isl_tiling_to_name(enum isl_tiling tiling)4496 isl_tiling_to_name(enum isl_tiling tiling)
4497 {
4498 static const char *names[] = {
4499 [ISL_TILING_LINEAR] = "linear",
4500 [ISL_TILING_W] = "W",
4501 [ISL_TILING_X] = "X",
4502 [ISL_TILING_Y0] = "Y0",
4503 [ISL_TILING_SKL_Yf] = "SKL-Yf",
4504 [ISL_TILING_SKL_Ys] = "SKL-Ys",
4505 [ISL_TILING_ICL_Yf] = "ICL-Yf",
4506 [ISL_TILING_ICL_Ys] = "ICL-Ys",
4507 [ISL_TILING_4] = "4",
4508 [ISL_TILING_64] = "64",
4509 [ISL_TILING_64_XE2] = "64-Xe2",
4510 [ISL_TILING_HIZ] = "hiz",
4511 [ISL_TILING_CCS] = "ccs",
4512 };
4513 assert(tiling < ARRAY_SIZE(names));
4514 return names[tiling];
4515 }
4516
4517 const char *
isl_aux_usage_to_name(enum isl_aux_usage usage)4518 isl_aux_usage_to_name(enum isl_aux_usage usage)
4519 {
4520 static const char *names[] = {
4521 [ISL_AUX_USAGE_NONE] = "none",
4522 [ISL_AUX_USAGE_HIZ] = "hiz",
4523 [ISL_AUX_USAGE_MCS] = "mcs",
4524 [ISL_AUX_USAGE_CCS_D] = "ccs-d",
4525 [ISL_AUX_USAGE_CCS_E] = "ccs-e",
4526 [ISL_AUX_USAGE_FCV_CCS_E] = "fcv-ccs-e",
4527 [ISL_AUX_USAGE_MC] = "mc",
4528 [ISL_AUX_USAGE_HIZ_CCS_WT] = "hiz-ccs-wt",
4529 [ISL_AUX_USAGE_HIZ_CCS] = "hiz-ccs",
4530 [ISL_AUX_USAGE_MCS_CCS] = "mcs-ccs",
4531 [ISL_AUX_USAGE_STC_CCS] = "stc-ccs",
4532 };
4533 assert(usage < ARRAY_SIZE(names));
4534 return names[usage];
4535 }
4536
4537 const char *
isl_aux_state_to_name(enum isl_aux_state state)4538 isl_aux_state_to_name(enum isl_aux_state state)
4539 {
4540 static const char *names[] = {
4541 [ISL_AUX_STATE_CLEAR] = "clear",
4542 [ISL_AUX_STATE_PARTIAL_CLEAR] = "partial_clear",
4543 [ISL_AUX_STATE_COMPRESSED_CLEAR] = "compressed_clear",
4544 [ISL_AUX_STATE_COMPRESSED_NO_CLEAR] = "compressed_no_clear",
4545 [ISL_AUX_STATE_RESOLVED] = "resolved",
4546 [ISL_AUX_STATE_PASS_THROUGH] = "pass-through",
4547 [ISL_AUX_STATE_AUX_INVALID] = "invalid",
4548 };
4549 assert(state < ARRAY_SIZE(names));
4550 return names[state];
4551 }
4552