1 /*
2 * Copyright © 2023 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26
27 #include "util/macros.h"
28
29 #include "anv_private.h"
30
31 #include "genxml/gen_macros.h"
32 #include "genxml/genX_pack.h"
33 #include "common/intel_compute_slm.h"
34 #include "common/intel_genX_state_brw.h"
35
36 static void
genX(emit_simpler_shader_init_fragment)37 genX(emit_simpler_shader_init_fragment)(struct anv_simple_shader *state)
38 {
39 assert(state->cmd_buffer && state->cmd_buffer->state.current_pipeline == _3D);
40
41 struct anv_batch *batch = state->batch;
42 struct anv_device *device = state->device;
43 const struct brw_wm_prog_data *prog_data =
44 brw_wm_prog_data_const(state->kernel->prog_data);
45
46 uint32_t *dw = anv_batch_emitn(batch,
47 1 + 2 * GENX(VERTEX_ELEMENT_STATE_length),
48 GENX(3DSTATE_VERTEX_ELEMENTS));
49 /* You might think there is some shady stuff going here and you would be
50 * right. We're setting up 2 VERTEX_ELEMENT_STATE yet we're only providing
51 * 1 (positions) VERTEX_BUFFER_STATE later.
52 *
53 * Find more about how to set up a 3D pipeline with a fragment shader but
54 * without a vertex shader in blorp_emit_vertex_elements() in
55 * blorp_genX_exec_brw.h.
56 */
57 GENX(VERTEX_ELEMENT_STATE_pack)(
58 batch, dw + 1, &(struct GENX(VERTEX_ELEMENT_STATE)) {
59 .VertexBufferIndex = 1,
60 .Valid = true,
61 .SourceElementFormat = ISL_FORMAT_R32G32B32A32_FLOAT,
62 .SourceElementOffset = 0,
63 .Component0Control = VFCOMP_STORE_SRC,
64 .Component1Control = VFCOMP_STORE_0,
65 .Component2Control = VFCOMP_STORE_0,
66 .Component3Control = VFCOMP_STORE_0,
67 });
68 GENX(VERTEX_ELEMENT_STATE_pack)(
69 batch, dw + 3, &(struct GENX(VERTEX_ELEMENT_STATE)) {
70 .VertexBufferIndex = 0,
71 .Valid = true,
72 .SourceElementFormat = ISL_FORMAT_R32G32B32_FLOAT,
73 .SourceElementOffset = 0,
74 .Component0Control = VFCOMP_STORE_SRC,
75 .Component1Control = VFCOMP_STORE_SRC,
76 .Component2Control = VFCOMP_STORE_SRC,
77 .Component3Control = VFCOMP_STORE_1_FP,
78 });
79
80 anv_batch_emit(batch, GENX(3DSTATE_VF_STATISTICS), vf);
81 anv_batch_emit(batch, GENX(3DSTATE_VF_SGVS), sgvs) {
82 sgvs.InstanceIDEnable = true;
83 sgvs.InstanceIDComponentNumber = COMP_1;
84 sgvs.InstanceIDElementOffset = 0;
85 }
86 #if GFX_VER >= 11
87 anv_batch_emit(batch, GENX(3DSTATE_VF_SGVS_2), sgvs);
88 #endif
89 anv_batch_emit(batch, GENX(3DSTATE_VF_INSTANCING), vfi) {
90 vfi.InstancingEnable = false;
91 vfi.VertexElementIndex = 0;
92 }
93 anv_batch_emit(batch, GENX(3DSTATE_VF_INSTANCING), vfi) {
94 vfi.InstancingEnable = false;
95 vfi.VertexElementIndex = 1;
96 }
97
98 anv_batch_emit(batch, GENX(3DSTATE_VF_TOPOLOGY), topo) {
99 topo.PrimitiveTopologyType = _3DPRIM_RECTLIST;
100 }
101
102 /* Emit URB setup. We tell it that the VS is active because we want it to
103 * allocate space for the VS. Even though one isn't run, we need VUEs to
104 * store the data that VF is going to pass to SOL.
105 */
106 struct intel_urb_config urb_cfg_out = {
107 .size = { DIV_ROUND_UP(32, 64), 1, 1, 1 },
108 };
109
110 genX(emit_l3_config)(batch, device, state->l3_config);
111 state->cmd_buffer->state.current_l3_config = state->l3_config;
112
113 enum intel_urb_deref_block_size deref_block_size;
114 genX(emit_urb_setup)(device, batch, state->l3_config,
115 VK_SHADER_STAGE_VERTEX_BIT | VK_SHADER_STAGE_FRAGMENT_BIT,
116 state->urb_cfg, &urb_cfg_out, &deref_block_size);
117
118 anv_batch_emit(batch, GENX(3DSTATE_PS_BLEND), ps_blend) {
119 ps_blend.HasWriteableRT = true;
120 }
121
122 anv_batch_emit(batch, GENX(3DSTATE_WM_DEPTH_STENCIL), wm);
123
124 #if GFX_VER >= 12
125 anv_batch_emit(batch, GENX(3DSTATE_DEPTH_BOUNDS), db) {
126 db.DepthBoundsTestEnable = false;
127 db.DepthBoundsTestMinValue = 0.0;
128 db.DepthBoundsTestMaxValue = 1.0;
129 }
130 #endif
131
132 anv_batch_emit(batch, GENX(3DSTATE_MULTISAMPLE), ms);
133 anv_batch_emit(batch, GENX(3DSTATE_SAMPLE_MASK), sm) {
134 sm.SampleMask = 0x1;
135 }
136
137 anv_batch_emit(batch, GENX(3DSTATE_VS), vs);
138 anv_batch_emit(batch, GENX(3DSTATE_HS), hs);
139 anv_batch_emit(batch, GENX(3DSTATE_TE), te);
140 anv_batch_emit(batch, GENX(3DSTATE_DS), DS);
141
142 #if GFX_VERx10 >= 125
143 if (device->vk.enabled_extensions.EXT_mesh_shader) {
144 anv_batch_emit(batch, GENX(3DSTATE_MESH_CONTROL), mesh);
145 anv_batch_emit(batch, GENX(3DSTATE_TASK_CONTROL), task);
146 }
147 #endif
148
149 anv_batch_emit(batch, GENX(3DSTATE_STREAMOUT), so);
150
151 anv_batch_emit(batch, GENX(3DSTATE_GS), gs);
152
153 anv_batch_emit(batch, GENX(3DSTATE_CLIP), clip) {
154 clip.PerspectiveDivideDisable = true;
155 }
156
157 anv_batch_emit(batch, GENX(3DSTATE_SF), sf) {
158 #if GFX_VER >= 12
159 sf.DerefBlockSize = deref_block_size;
160 #endif
161 }
162
163 anv_batch_emit(batch, GENX(3DSTATE_RASTER), raster) {
164 raster.CullMode = CULLMODE_NONE;
165 }
166
167 anv_batch_emit(batch, GENX(3DSTATE_SBE), sbe) {
168 sbe.VertexURBEntryReadOffset = 1;
169 sbe.NumberofSFOutputAttributes = prog_data->num_varying_inputs;
170 sbe.VertexURBEntryReadLength = MAX2((prog_data->num_varying_inputs + 1) / 2, 1);
171 sbe.ConstantInterpolationEnable = prog_data->flat_inputs;
172 sbe.ForceVertexURBEntryReadLength = true;
173 sbe.ForceVertexURBEntryReadOffset = true;
174 for (unsigned i = 0; i < 32; i++)
175 sbe.AttributeActiveComponentFormat[i] = ACF_XYZW;
176 }
177
178 anv_batch_emit(batch, GENX(3DSTATE_WM), wm);
179
180 anv_batch_emit(batch, GENX(3DSTATE_PS), ps) {
181 intel_set_ps_dispatch_state(&ps, device->info, prog_data,
182 1 /* rasterization_samples */,
183 0 /* msaa_flags */);
184
185 ps.VectorMaskEnable = prog_data->uses_vmask;
186
187 ps.BindingTableEntryCount = GFX_VER == 9 ? 1 : 0;
188 #if GFX_VER < 20
189 ps.PushConstantEnable = prog_data->base.nr_params > 0 ||
190 prog_data->base.ubo_ranges[0].length;
191 #endif
192
193 ps.DispatchGRFStartRegisterForConstantSetupData0 =
194 brw_wm_prog_data_dispatch_grf_start_reg(prog_data, ps, 0);
195 ps.DispatchGRFStartRegisterForConstantSetupData1 =
196 brw_wm_prog_data_dispatch_grf_start_reg(prog_data, ps, 1);
197 #if GFX_VER < 20
198 ps.DispatchGRFStartRegisterForConstantSetupData2 =
199 brw_wm_prog_data_dispatch_grf_start_reg(prog_data, ps, 2);
200 #endif
201
202 ps.KernelStartPointer0 = state->kernel->kernel.offset +
203 brw_wm_prog_data_prog_offset(prog_data, ps, 0);
204 ps.KernelStartPointer1 = state->kernel->kernel.offset +
205 brw_wm_prog_data_prog_offset(prog_data, ps, 1);
206 #if GFX_VER < 20
207 ps.KernelStartPointer2 = state->kernel->kernel.offset +
208 brw_wm_prog_data_prog_offset(prog_data, ps, 2);
209 #endif
210
211 #if GFX_VER >= 30
212 ps.RegistersPerThread = ptl_register_blocks(prog_data->base.grf_used);
213 #endif
214
215 ps.MaximumNumberofThreadsPerPSD = device->info->max_threads_per_psd - 1;
216 }
217
218 #if INTEL_WA_18038825448_GFX_VER
219 const bool needs_ps_dependency =
220 genX(cmd_buffer_set_coarse_pixel_active)
221 (state->cmd_buffer, ANV_COARSE_PIXEL_STATE_DISABLED);
222 #endif
223
224 anv_batch_emit(batch, GENX(3DSTATE_PS_EXTRA), psx) {
225 psx.PixelShaderValid = true;
226 #if GFX_VER < 20
227 psx.AttributeEnable = prog_data->num_varying_inputs > 0;
228 #endif
229 psx.PixelShaderIsPerSample = prog_data->persample_dispatch;
230 psx.PixelShaderComputedDepthMode = prog_data->computed_depth_mode;
231 psx.PixelShaderComputesStencil = prog_data->computed_stencil;
232
233 #if INTEL_WA_18038825448_GFX_VER
234 psx.EnablePSDependencyOnCPsizeChange = needs_ps_dependency;
235 #endif
236 }
237
238 anv_batch_emit(batch, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC), cc) {
239 struct anv_state cc_state =
240 anv_state_stream_alloc(state->dynamic_state_stream,
241 4 * GENX(CC_VIEWPORT_length), 32);
242 if (cc_state.map == NULL)
243 return;
244
245 struct GENX(CC_VIEWPORT) cc_viewport = {
246 .MinimumDepth = 0.0f,
247 .MaximumDepth = 1.0f,
248 };
249 GENX(CC_VIEWPORT_pack)(NULL, cc_state.map, &cc_viewport);
250 cc.CCViewportPointer = cc_state.offset;
251 }
252
253 #if GFX_VER >= 12
254 /* Disable Primitive Replication. */
255 anv_batch_emit(batch, GENX(3DSTATE_PRIMITIVE_REPLICATION), pr);
256 #endif
257
258 anv_batch_emit(batch, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS), alloc);
259 anv_batch_emit(batch, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_HS), alloc);
260 anv_batch_emit(batch, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_DS), alloc);
261 anv_batch_emit(batch, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_GS), alloc);
262 anv_batch_emit(batch, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS), alloc) {
263 alloc.ConstantBufferOffset = 0;
264 alloc.ConstantBufferSize = device->info->max_constant_urb_size_kb;
265 }
266
267 #if GFX_VERx10 == 125
268 /* DG2: Wa_22011440098
269 * MTL: Wa_18022330953
270 *
271 * In 3D mode, after programming push constant alloc command immediately
272 * program push constant command(ZERO length) without any commit between
273 * them.
274 *
275 * Note that Wa_16011448509 isn't needed here as all address bits are zero.
276 */
277 anv_batch_emit(batch, GENX(3DSTATE_CONSTANT_ALL), c) {
278 /* Update empty push constants for all stages (bitmask = 11111b) */
279 c.ShaderUpdateEnable = 0x1f;
280 c.MOCS = anv_mocs(device, NULL, 0);
281 }
282 #endif
283
284 #if GFX_VER == 9
285 /* Allocate a binding table for Gfx9 for 2 reason :
286 *
287 * 1. we need a to emit a 3DSTATE_BINDING_TABLE_POINTERS_PS to make the
288 * HW apply the preceeding 3DSTATE_CONSTANT_PS
289 *
290 * 2. Emitting an empty 3DSTATE_BINDING_TABLE_POINTERS_PS would cause RT
291 * writes (even though they're empty) to disturb later writes
292 * (probably due to RT cache)
293 *
294 * Our binding table only has one entry to the null surface.
295 */
296 uint32_t bt_offset;
297 state->bt_state =
298 anv_cmd_buffer_alloc_binding_table(state->cmd_buffer, 1, &bt_offset);
299 if (state->bt_state.map == NULL) {
300 VkResult result = anv_cmd_buffer_new_binding_table_block(state->cmd_buffer);
301 if (result != VK_SUCCESS)
302 return;
303
304 /* Re-emit state base addresses so we get the new surface state base
305 * address before we start emitting binding tables etc.
306 */
307 genX(cmd_buffer_emit_bt_pool_base_address)(state->cmd_buffer);
308
309 state->bt_state =
310 anv_cmd_buffer_alloc_binding_table(state->cmd_buffer, 1, &bt_offset);
311 assert(state->bt_state.map != NULL);
312 }
313
314 uint32_t *bt_map = state->bt_state.map;
315 bt_map[0] = anv_bindless_state_for_binding_table(
316 device,
317 device->null_surface_state).offset + bt_offset;
318
319 state->cmd_buffer->state.descriptors_dirty |= VK_SHADER_STAGE_FRAGMENT_BIT;
320 #endif
321
322 #if INTEL_WA_14018283232_GFX_VER
323 genX(cmd_buffer_ensure_wa_14018283232)(state->cmd_buffer, false);
324 #endif
325
326 /* Flag all the instructions emitted by the memcpy. */
327 struct anv_gfx_dynamic_state *hw_state =
328 &state->cmd_buffer->state.gfx.dyn_state;
329
330 BITSET_SET(hw_state->dirty, ANV_GFX_STATE_URB);
331 BITSET_SET(hw_state->dirty, ANV_GFX_STATE_VF_STATISTICS);
332 BITSET_SET(hw_state->dirty, ANV_GFX_STATE_VF);
333 BITSET_SET(hw_state->dirty, ANV_GFX_STATE_VF_TOPOLOGY);
334 BITSET_SET(hw_state->dirty, ANV_GFX_STATE_VERTEX_INPUT);
335 BITSET_SET(hw_state->dirty, ANV_GFX_STATE_VF_SGVS);
336 #if GFX_VER >= 11
337 BITSET_SET(hw_state->dirty, ANV_GFX_STATE_VF_SGVS_2);
338 #endif
339 #if GFX_VER >= 12
340 BITSET_SET(hw_state->dirty, ANV_GFX_STATE_PRIMITIVE_REPLICATION);
341 #endif
342 BITSET_SET(hw_state->dirty, ANV_GFX_STATE_STREAMOUT);
343 BITSET_SET(hw_state->dirty, ANV_GFX_STATE_VIEWPORT_CC);
344 BITSET_SET(hw_state->dirty, ANV_GFX_STATE_CLIP);
345 BITSET_SET(hw_state->dirty, ANV_GFX_STATE_RASTER);
346 BITSET_SET(hw_state->dirty, ANV_GFX_STATE_SAMPLE_MASK);
347 BITSET_SET(hw_state->dirty, ANV_GFX_STATE_MULTISAMPLE);
348 BITSET_SET(hw_state->dirty, ANV_GFX_STATE_DEPTH_BOUNDS);
349 BITSET_SET(hw_state->dirty, ANV_GFX_STATE_WM);
350 BITSET_SET(hw_state->dirty, ANV_GFX_STATE_WM_DEPTH_STENCIL);
351 BITSET_SET(hw_state->dirty, ANV_GFX_STATE_SF);
352 BITSET_SET(hw_state->dirty, ANV_GFX_STATE_SBE);
353 BITSET_SET(hw_state->dirty, ANV_GFX_STATE_VS);
354 BITSET_SET(hw_state->dirty, ANV_GFX_STATE_HS);
355 BITSET_SET(hw_state->dirty, ANV_GFX_STATE_DS);
356 BITSET_SET(hw_state->dirty, ANV_GFX_STATE_TE);
357 BITSET_SET(hw_state->dirty, ANV_GFX_STATE_GS);
358 BITSET_SET(hw_state->dirty, ANV_GFX_STATE_PS);
359 BITSET_SET(hw_state->dirty, ANV_GFX_STATE_PS_EXTRA);
360 BITSET_SET(hw_state->dirty, ANV_GFX_STATE_PS_BLEND);
361 if (device->vk.enabled_extensions.EXT_mesh_shader) {
362 BITSET_SET(hw_state->dirty, ANV_GFX_STATE_MESH_CONTROL);
363 BITSET_SET(hw_state->dirty, ANV_GFX_STATE_TASK_CONTROL);
364 }
365
366 /* Update urb config after simple shader. */
367 memcpy(&state->cmd_buffer->state.gfx.urb_cfg, &urb_cfg_out,
368 sizeof(struct intel_urb_config));
369
370 state->cmd_buffer->state.gfx.vb_dirty = BITFIELD_BIT(0);
371 state->cmd_buffer->state.gfx.dirty |= ~(ANV_CMD_DIRTY_INDEX_BUFFER |
372 ANV_CMD_DIRTY_XFB_ENABLE |
373 ANV_CMD_DIRTY_OCCLUSION_QUERY_ACTIVE |
374 ANV_CMD_DIRTY_RESTART_INDEX);
375 state->cmd_buffer->state.push_constants_dirty |= VK_SHADER_STAGE_FRAGMENT_BIT;
376 state->cmd_buffer->state.gfx.push_constant_stages = VK_SHADER_STAGE_FRAGMENT_BIT;
377 }
378
379 static void
genX(emit_simpler_shader_init_compute)380 genX(emit_simpler_shader_init_compute)(struct anv_simple_shader *state)
381 {
382 assert(state->cmd_buffer == NULL ||
383 state->cmd_buffer->state.current_pipeline == GPGPU);
384
385 #if GFX_VERx10 >= 125
386 struct anv_shader_bin *cs_bin = state->kernel;
387 const struct brw_cs_prog_data *prog_data =
388 (const struct brw_cs_prog_data *) cs_bin->prog_data;
389 /* Currently our simple shaders are simple enough that they never spill. */
390 assert(prog_data->base.total_scratch == 0);
391 if (state->cmd_buffer != NULL) {
392 genX(cmd_buffer_ensure_cfe_state)(state->cmd_buffer, 0);
393 } else {
394 anv_batch_emit(state->batch, GENX(CFE_STATE), cfe) {
395 cfe.MaximumNumberofThreads =
396 state->device->info->max_cs_threads *
397 state->device->info->subslice_total;
398 }
399 }
400 #endif
401
402 if (state->cmd_buffer) {
403 state->cmd_buffer->state.push_constants_dirty |= VK_SHADER_STAGE_COMPUTE_BIT;
404 state->cmd_buffer->state.compute.pipeline_dirty = true;
405 }
406 }
407
408 /** Initialize a simple shader emission */
409 void
genX(emit_simple_shader_init)410 genX(emit_simple_shader_init)(struct anv_simple_shader *state)
411 {
412 assert(state->kernel->stage == MESA_SHADER_FRAGMENT ||
413 state->kernel->stage == MESA_SHADER_COMPUTE);
414
415 if (state->kernel->stage == MESA_SHADER_FRAGMENT)
416 genX(emit_simpler_shader_init_fragment)(state);
417 else
418 genX(emit_simpler_shader_init_compute)(state);
419 }
420
421 /** Allocate push constant data for a simple shader */
422 struct anv_state
genX(simple_shader_alloc_push)423 genX(simple_shader_alloc_push)(struct anv_simple_shader *state, uint32_t size)
424 {
425 struct anv_state s;
426
427 if (state->kernel->stage == MESA_SHADER_FRAGMENT) {
428 s = anv_state_stream_alloc(state->dynamic_state_stream,
429 size, ANV_UBO_ALIGNMENT);
430 } else {
431 #if GFX_VERx10 >= 125
432 s = anv_state_stream_alloc(state->general_state_stream, align(size, 64), 64);
433 #else
434 s = anv_state_stream_alloc(state->dynamic_state_stream, size, 64);
435 #endif
436 }
437
438 if (s.map == NULL)
439 anv_batch_set_error(state->batch, VK_ERROR_OUT_OF_DEVICE_MEMORY);
440
441 return s;
442 }
443
444 /** Get the address of allocated push constant data by
445 * genX(simple_shader_alloc_push)
446 */
447 struct anv_address
genX(simple_shader_push_state_address)448 genX(simple_shader_push_state_address)(struct anv_simple_shader *state,
449 struct anv_state push_state)
450 {
451 if (state->kernel->stage == MESA_SHADER_FRAGMENT) {
452 return anv_state_pool_state_address(
453 &state->device->dynamic_state_pool, push_state);
454 } else {
455 #if GFX_VERx10 >= 125
456 return anv_state_pool_state_address(
457 &state->device->general_state_pool, push_state);
458 #else
459 return anv_state_pool_state_address(
460 &state->device->dynamic_state_pool, push_state);
461 #endif
462 }
463 }
464
465 /** Emit a simple shader dispatch */
466 void
genX(emit_simple_shader_dispatch)467 genX(emit_simple_shader_dispatch)(struct anv_simple_shader *state,
468 uint32_t num_threads,
469 struct anv_state push_state)
470 {
471 struct anv_device *device = state->device;
472 struct anv_batch *batch = state->batch;
473 struct anv_address push_addr =
474 anv_state_pool_state_address(&device->dynamic_state_pool, push_state);
475
476 if (state->kernel->stage == MESA_SHADER_FRAGMENT) {
477 /* At the moment we require a command buffer associated with this
478 * emission as we need to allocate binding tables on Gfx9.
479 */
480 assert(state->cmd_buffer != NULL);
481
482 struct anv_state vs_data_state =
483 anv_state_stream_alloc(state->dynamic_state_stream,
484 9 * sizeof(uint32_t), 32);
485 if (vs_data_state.map == NULL)
486 return;
487
488 float x0 = 0.0f, x1 = MIN2(num_threads, 8192);
489 float y0 = 0.0f, y1 = DIV_ROUND_UP(num_threads, 8192);
490 float z = 0.0f;
491
492 float *vertices = vs_data_state.map;
493 vertices[0] = x1; vertices[1] = y1; vertices[2] = z; /* v0 */
494 vertices[3] = x0; vertices[4] = y1; vertices[5] = z; /* v1 */
495 vertices[6] = x0; vertices[7] = y0; vertices[8] = z; /* v2 */
496
497 uint32_t *dw = anv_batch_emitn(batch,
498 1 + GENX(VERTEX_BUFFER_STATE_length),
499 GENX(3DSTATE_VERTEX_BUFFERS));
500 GENX(VERTEX_BUFFER_STATE_pack)(batch, dw + 1,
501 &(struct GENX(VERTEX_BUFFER_STATE)) {
502 .VertexBufferIndex = 0,
503 .AddressModifyEnable = true,
504 .BufferStartingAddress = (struct anv_address) {
505 .bo = device->dynamic_state_pool.block_pool.bo,
506 .offset = vs_data_state.offset,
507 },
508 .BufferPitch = 3 * sizeof(float),
509 .BufferSize = 9 * sizeof(float),
510 .MOCS = anv_mocs(device, NULL, 0),
511 #if GFX_VER >= 12
512 .L3BypassDisable = true,
513 #endif
514 });
515
516 #if GFX_VERx10 > 120
517 dw =
518 anv_batch_emitn(batch,
519 GENX(3DSTATE_CONSTANT_ALL_length) +
520 GENX(3DSTATE_CONSTANT_ALL_DATA_length),
521 GENX(3DSTATE_CONSTANT_ALL),
522 .ShaderUpdateEnable = BITFIELD_BIT(MESA_SHADER_FRAGMENT),
523 .PointerBufferMask = 0x1,
524 .MOCS = anv_mocs(device, NULL, 0));
525
526 GENX(3DSTATE_CONSTANT_ALL_DATA_pack)(
527 batch, dw + GENX(3DSTATE_CONSTANT_ALL_length),
528 &(struct GENX(3DSTATE_CONSTANT_ALL_DATA)) {
529 .PointerToConstantBuffer = push_addr,
530 .ConstantBufferReadLength = DIV_ROUND_UP(push_state.alloc_size, 32),
531 });
532 #else
533 /* The Skylake PRM contains the following restriction:
534 *
535 * "The driver must ensure The following case does not occur
536 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
537 * buffer 3 read length equal to zero committed followed by a
538 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
539 * zero committed."
540 *
541 * To avoid this, we program the highest slot.
542 */
543 anv_batch_emit(batch, GENX(3DSTATE_CONSTANT_PS), c) {
544 c.MOCS = anv_mocs(device, NULL, 0);
545 c.ConstantBody.ReadLength[3] = DIV_ROUND_UP(push_state.alloc_size, 32);
546 c.ConstantBody.Buffer[3] = push_addr;
547 }
548 #endif
549
550 #if GFX_VER == 9
551 /* Why are the push constants not flushed without a binding table
552 * update??
553 */
554 anv_batch_emit(batch, GENX(3DSTATE_BINDING_TABLE_POINTERS_PS), btp) {
555 btp.PointertoPSBindingTable = state->bt_state.offset;
556 }
557 #endif
558
559 genX(emit_breakpoint)(batch, device, true);
560 anv_batch_emit(batch, GENX(3DPRIMITIVE), prim) {
561 prim.VertexAccessType = SEQUENTIAL;
562 prim.PrimitiveTopologyType = _3DPRIM_RECTLIST;
563 prim.VertexCountPerInstance = 3;
564 prim.InstanceCount = 1;
565 }
566 genX(batch_emit_post_3dprimitive_was)(batch, device, _3DPRIM_RECTLIST, 3);
567 genX(emit_breakpoint)(batch, device, false);
568 } else {
569 const struct intel_device_info *devinfo = device->info;
570 const struct brw_cs_prog_data *prog_data =
571 (const struct brw_cs_prog_data *) state->kernel->prog_data;
572 const struct intel_cs_dispatch_info dispatch =
573 brw_cs_get_dispatch_info(devinfo, prog_data, NULL);
574
575 #if GFX_VERx10 >= 125
576 struct GENX(COMPUTE_WALKER_BODY) body = {
577 .SIMDSize = dispatch.simd_size / 16,
578 .MessageSIMD = dispatch.simd_size / 16,
579 .IndirectDataStartAddress = push_state.offset,
580 .IndirectDataLength = push_state.alloc_size,
581 .LocalXMaximum = prog_data->local_size[0] - 1,
582 .LocalYMaximum = prog_data->local_size[1] - 1,
583 .LocalZMaximum = prog_data->local_size[2] - 1,
584 .ThreadGroupIDXDimension = DIV_ROUND_UP(num_threads,
585 dispatch.simd_size),
586 .ThreadGroupIDYDimension = 1,
587 .ThreadGroupIDZDimension = 1,
588 .ExecutionMask = dispatch.right_mask,
589 .PostSync.MOCS = anv_mocs(device, NULL, 0),
590
591 #if GFX_VERx10 >= 125
592 .GenerateLocalID = prog_data->generate_local_id != 0,
593 .EmitLocal = prog_data->generate_local_id,
594 .WalkOrder = prog_data->walk_order,
595 .TileLayout = prog_data->walk_order == INTEL_WALK_ORDER_YXZ ?
596 TileY32bpe : Linear,
597 #endif
598
599 .InterfaceDescriptor = (struct GENX(INTERFACE_DESCRIPTOR_DATA)) {
600 .KernelStartPointer = state->kernel->kernel.offset +
601 brw_cs_prog_data_prog_offset(prog_data,
602 dispatch.simd_size),
603 .SamplerStatePointer = 0,
604 .BindingTablePointer = 0,
605 .BindingTableEntryCount = 0,
606 .NumberofThreadsinGPGPUThreadGroup = dispatch.threads,
607 .SharedLocalMemorySize = intel_compute_slm_encode_size(GFX_VER,
608 prog_data->base.total_shared),
609 .NumberOfBarriers = prog_data->uses_barrier,
610 #if GFX_VER >= 30
611 .RegistersPerThread = ptl_register_blocks(prog_data->base.grf_used),
612 #endif
613 },
614 };
615
616 anv_batch_emit(batch, GENX(COMPUTE_WALKER), cw) {
617 cw.body = body;
618 }
619 #else
620 const uint32_t vfe_curbe_allocation =
621 ALIGN(prog_data->push.per_thread.regs * dispatch.threads +
622 prog_data->push.cross_thread.regs, 2);
623
624 /* From the Sky Lake PRM Vol 2a, MEDIA_VFE_STATE:
625 *
626 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
627 * the only bits that are changed are scoreboard related: Scoreboard
628 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
629 * these scoreboard related states, a MEDIA_STATE_FLUSH is
630 * sufficient."
631 */
632 enum anv_pipe_bits emitted_bits = 0;
633 genX(emit_apply_pipe_flushes)(batch, device, GPGPU, ANV_PIPE_CS_STALL_BIT,
634 &emitted_bits);
635
636 /* If we have a command buffer allocated with the emission, update the
637 * pending bits.
638 */
639 if (state->cmd_buffer)
640 anv_cmd_buffer_update_pending_query_bits(state->cmd_buffer, emitted_bits);
641
642 anv_batch_emit(batch, GENX(MEDIA_VFE_STATE), vfe) {
643 vfe.StackSize = 0;
644 vfe.MaximumNumberofThreads =
645 devinfo->max_cs_threads * devinfo->subslice_total - 1;
646 vfe.NumberofURBEntries = 2;
647 #if GFX_VER < 11
648 vfe.ResetGatewayTimer = true;
649 #endif
650 vfe.URBEntryAllocationSize = 2;
651 vfe.CURBEAllocationSize = vfe_curbe_allocation;
652
653 if (prog_data->base.total_scratch) {
654 /* Broadwell's Per Thread Scratch Space is in the range [0, 11]
655 * where 0 = 1k, 1 = 2k, 2 = 4k, ..., 11 = 2M.
656 */
657 vfe.PerThreadScratchSpace =
658 ffs(prog_data->base.total_scratch) - 11;
659 vfe.ScratchSpaceBasePointer =
660 (struct anv_address) {
661 .bo = anv_scratch_pool_alloc(device,
662 &device->scratch_pool,
663 MESA_SHADER_COMPUTE,
664 prog_data->base.total_scratch),
665 .offset = 0,
666 };
667 }
668 }
669 struct anv_state iface_desc_state =
670 anv_state_stream_alloc(state->dynamic_state_stream,
671 GENX(INTERFACE_DESCRIPTOR_DATA_length) * 4, 64);
672 if (iface_desc_state.map == NULL)
673 return;
674
675 struct GENX(INTERFACE_DESCRIPTOR_DATA) iface_desc = {
676 .KernelStartPointer = state->kernel->kernel.offset +
677 brw_cs_prog_data_prog_offset(prog_data,
678 dispatch.simd_size),
679
680 .SamplerCount = 0,
681 .BindingTableEntryCount = 0,
682 .BarrierEnable = prog_data->uses_barrier,
683 .SharedLocalMemorySize = intel_compute_slm_encode_size(GFX_VER,
684 prog_data->base.total_shared),
685
686 .ConstantURBEntryReadOffset = 0,
687 .ConstantURBEntryReadLength = prog_data->push.per_thread.regs,
688 .CrossThreadConstantDataReadLength = prog_data->push.cross_thread.regs,
689 #if GFX_VER >= 12
690 /* TODO: Check if we are missing workarounds and enable mid-thread
691 * preemption.
692 *
693 * We still have issues with mid-thread preemption (it was already
694 * disabled by the kernel on gfx11, due to missing workarounds). It's
695 * possible that we are just missing some workarounds, and could
696 * enable it later, but for now let's disable it to fix a GPU in
697 * compute in Car Chase (and possibly more).
698 */
699 .ThreadPreemptionDisable = true,
700 #endif
701 .NumberofThreadsinGPGPUThreadGroup = dispatch.threads,
702 #if GFX_VER >= 30
703 .RegistersPerThread = ptl_register_blocks(prog_data->base.grf_used),
704 #endif
705 };
706 GENX(INTERFACE_DESCRIPTOR_DATA_pack)(batch, iface_desc_state.map, &iface_desc);
707 anv_batch_emit(batch, GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD), mid) {
708 mid.InterfaceDescriptorTotalLength = iface_desc_state.alloc_size;
709 mid.InterfaceDescriptorDataStartAddress = iface_desc_state.offset;
710 }
711 anv_batch_emit(batch, GENX(MEDIA_CURBE_LOAD), curbe) {
712 curbe.CURBEDataStartAddress = push_state.offset;
713 curbe.CURBETotalDataLength = push_state.alloc_size;
714 }
715 anv_batch_emit(batch, GENX(GPGPU_WALKER), ggw) {
716 ggw.SIMDSize = dispatch.simd_size / 16;
717 ggw.ThreadDepthCounterMaximum = 0;
718 ggw.ThreadHeightCounterMaximum = 0;
719 ggw.ThreadWidthCounterMaximum = dispatch.threads - 1;
720 ggw.ThreadGroupIDXDimension = DIV_ROUND_UP(num_threads,
721 dispatch.simd_size);
722 ggw.ThreadGroupIDYDimension = 1;
723 ggw.ThreadGroupIDZDimension = 1;
724 ggw.RightExecutionMask = dispatch.right_mask;
725 ggw.BottomExecutionMask = 0xffffffff;
726 }
727 anv_batch_emit(batch, GENX(MEDIA_STATE_FLUSH), msf);
728 #endif
729 }
730 }
731
732 void
genX(emit_simple_shader_end)733 genX(emit_simple_shader_end)(struct anv_simple_shader *state)
734 {
735 anv_batch_emit(state->batch, GENX(MI_BATCH_BUFFER_END), end);
736
737 if ((state->batch->next - state->batch->start) & 4)
738 anv_batch_emit(state->batch, GENX(MI_NOOP), noop);
739 }
740