1 /******************************************************************************* 2 Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. 3 4 Permission is hereby granted, free of charge, to any person obtaining a 5 copy of this software and associated documentation files (the "Software"), 6 to deal in the Software without restriction, including without limitation 7 the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 and/or sell copies of the Software, and to permit persons to whom the 9 Software is furnished to do so, subject to the following conditions: 10 11 The above copyright notice and this permission notice shall be included in 12 all copies or substantial portions of the Software. 13 14 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 19 FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 20 DEALINGS IN THE SOFTWARE. 21 22 *******************************************************************************/ 23 24 #include "nvtypes.h" 25 26 #ifndef _cl85b5_h_ 27 #define _cl85b5_h_ 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 #define GT212_DMA_COPY (0x000085B5) 34 35 #define NV85B5_NOP (0x00000100) 36 #define NV85B5_NOP_PARAMETER 31:0 37 #define NV85B5_PM_TRIGGER (0x00000140) 38 #define NV85B5_PM_TRIGGER_V 31:0 39 #define NV85B5_SET_CTX_DMA(b) (0x00000180 + (b)*0x00000004) 40 #define NV85B5_SET_CTX_DMA_HANDLE 31:0 41 #define NV85B5_SET_APPLICATION_ID (0x00000200) 42 #define NV85B5_SET_APPLICATION_ID_ID 31:0 43 #define NV85B5_SET_APPLICATION_ID_ID_NORMAL (0x00000001) 44 #define NV85B5_SET_WATCHDOG_TIMER (0x00000204) 45 #define NV85B5_SET_WATCHDOG_TIMER_TIMER 31:0 46 #define NV85B5_SET_SEMAPHORE_A (0x00000240) 47 #define NV85B5_SET_SEMAPHORE_A_UPPER 7:0 48 #define NV85B5_SET_SEMAPHORE_A_CTX_DMA 31:28 49 #define NV85B5_SET_SEMAPHORE_B (0x00000244) 50 #define NV85B5_SET_SEMAPHORE_B_LOWER 31:0 51 #define NV85B5_SET_SEMAPHORE_PAYLOAD (0x00000248) 52 #define NV85B5_SET_SEMAPHORE_PAYLOAD_PAYLOAD 31:0 53 #define NV85B5_LAUNCH_DMA (0x00000300) 54 #define NV85B5_LAUNCH_DMA_DATA_TRANSFER_TYPE 1:0 55 #define NV85B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE (0x00000000) 56 #define NV85B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED (0x00000001) 57 #define NV85B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED (0x00000002) 58 #define NV85B5_LAUNCH_DMA_FLUSH_ENABLE 2:2 59 #define NV85B5_LAUNCH_DMA_FLUSH_ENABLE_FALSE (0x00000000) 60 #define NV85B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE (0x00000001) 61 #define NV85B5_LAUNCH_DMA_SEMAPHORE_TYPE 4:3 62 #define NV85B5_LAUNCH_DMA_SEMAPHORE_TYPE_NONE (0x00000000) 63 #define NV85B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE (0x00000001) 64 #define NV85B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_FOUR_WORD_SEMAPHORE (0x00000002) 65 #define NV85B5_LAUNCH_DMA_INTERRUPT_TYPE 6:5 66 #define NV85B5_LAUNCH_DMA_INTERRUPT_TYPE_NONE (0x00000000) 67 #define NV85B5_LAUNCH_DMA_INTERRUPT_TYPE_BLOCKING (0x00000001) 68 #define NV85B5_LAUNCH_DMA_INTERRUPT_TYPE_NON_BLOCKING (0x00000002) 69 #define NV85B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT 7:7 70 #define NV85B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) 71 #define NV85B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH (0x00000001) 72 #define NV85B5_LAUNCH_DMA_DST_MEMORY_LAYOUT 8:8 73 #define NV85B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) 74 #define NV85B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH (0x00000001) 75 #define NV85B5_LAUNCH_DMA_MULTI_LINE_ENABLE 9:9 76 #define NV85B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE (0x00000000) 77 #define NV85B5_LAUNCH_DMA_MULTI_LINE_ENABLE_TRUE (0x00000001) 78 #define NV85B5_LAUNCH_DMA_REMAP_ENABLE 10:10 79 #define NV85B5_LAUNCH_DMA_REMAP_ENABLE_FALSE (0x00000000) 80 #define NV85B5_LAUNCH_DMA_REMAP_ENABLE_TRUE (0x00000001) 81 #define NV85B5_OFFSET_IN_UPPER (0x00000400) 82 #define NV85B5_OFFSET_IN_UPPER_UPPER 7:0 83 #define NV85B5_OFFSET_IN_UPPER_CTX_DMA 31:28 84 #define NV85B5_OFFSET_IN_LOWER (0x00000404) 85 #define NV85B5_OFFSET_IN_LOWER_VALUE 31:0 86 #define NV85B5_OFFSET_OUT_UPPER (0x00000408) 87 #define NV85B5_OFFSET_OUT_UPPER_UPPER 7:0 88 #define NV85B5_OFFSET_OUT_UPPER_CTX_DMA 31:28 89 #define NV85B5_OFFSET_OUT_LOWER (0x0000040C) 90 #define NV85B5_OFFSET_OUT_LOWER_VALUE 31:0 91 #define NV85B5_PITCH_IN (0x00000410) 92 #define NV85B5_PITCH_IN_VALUE 31:0 93 #define NV85B5_PITCH_OUT (0x00000414) 94 #define NV85B5_PITCH_OUT_VALUE 31:0 95 #define NV85B5_LINE_LENGTH_IN (0x00000418) 96 #define NV85B5_LINE_LENGTH_IN_VALUE 31:0 97 #define NV85B5_LINE_COUNT (0x0000041C) 98 #define NV85B5_LINE_COUNT_VALUE 31:0 99 #define NV85B5_SET_REMAP_CONST_A (0x00000700) 100 #define NV85B5_SET_REMAP_CONST_A_V 31:0 101 #define NV85B5_SET_REMAP_CONST_B (0x00000704) 102 #define NV85B5_SET_REMAP_CONST_B_V 31:0 103 #define NV85B5_SET_REMAP_COMPONENTS (0x00000708) 104 #define NV85B5_SET_REMAP_COMPONENTS_DST_X 2:0 105 #define NV85B5_SET_REMAP_COMPONENTS_DST_X_SRC_X (0x00000000) 106 #define NV85B5_SET_REMAP_COMPONENTS_DST_X_SRC_Y (0x00000001) 107 #define NV85B5_SET_REMAP_COMPONENTS_DST_X_SRC_Z (0x00000002) 108 #define NV85B5_SET_REMAP_COMPONENTS_DST_X_SRC_W (0x00000003) 109 #define NV85B5_SET_REMAP_COMPONENTS_DST_X_CONST_A (0x00000004) 110 #define NV85B5_SET_REMAP_COMPONENTS_DST_X_CONST_B (0x00000005) 111 #define NV85B5_SET_REMAP_COMPONENTS_DST_X_NO_WRITE (0x00000006) 112 #define NV85B5_SET_REMAP_COMPONENTS_DST_Y 6:4 113 #define NV85B5_SET_REMAP_COMPONENTS_DST_Y_SRC_X (0x00000000) 114 #define NV85B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Y (0x00000001) 115 #define NV85B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Z (0x00000002) 116 #define NV85B5_SET_REMAP_COMPONENTS_DST_Y_SRC_W (0x00000003) 117 #define NV85B5_SET_REMAP_COMPONENTS_DST_Y_CONST_A (0x00000004) 118 #define NV85B5_SET_REMAP_COMPONENTS_DST_Y_CONST_B (0x00000005) 119 #define NV85B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE (0x00000006) 120 #define NV85B5_SET_REMAP_COMPONENTS_DST_Z 10:8 121 #define NV85B5_SET_REMAP_COMPONENTS_DST_Z_SRC_X (0x00000000) 122 #define NV85B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Y (0x00000001) 123 #define NV85B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Z (0x00000002) 124 #define NV85B5_SET_REMAP_COMPONENTS_DST_Z_SRC_W (0x00000003) 125 #define NV85B5_SET_REMAP_COMPONENTS_DST_Z_CONST_A (0x00000004) 126 #define NV85B5_SET_REMAP_COMPONENTS_DST_Z_CONST_B (0x00000005) 127 #define NV85B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE (0x00000006) 128 #define NV85B5_SET_REMAP_COMPONENTS_DST_W 14:12 129 #define NV85B5_SET_REMAP_COMPONENTS_DST_W_SRC_X (0x00000000) 130 #define NV85B5_SET_REMAP_COMPONENTS_DST_W_SRC_Y (0x00000001) 131 #define NV85B5_SET_REMAP_COMPONENTS_DST_W_SRC_Z (0x00000002) 132 #define NV85B5_SET_REMAP_COMPONENTS_DST_W_SRC_W (0x00000003) 133 #define NV85B5_SET_REMAP_COMPONENTS_DST_W_CONST_A (0x00000004) 134 #define NV85B5_SET_REMAP_COMPONENTS_DST_W_CONST_B (0x00000005) 135 #define NV85B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE (0x00000006) 136 #define NV85B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE 17:16 137 #define NV85B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE (0x00000000) 138 #define NV85B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_TWO (0x00000001) 139 #define NV85B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_THREE (0x00000002) 140 #define NV85B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_FOUR (0x00000003) 141 #define NV85B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS 21:20 142 #define NV85B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_ONE (0x00000000) 143 #define NV85B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_TWO (0x00000001) 144 #define NV85B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_THREE (0x00000002) 145 #define NV85B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_FOUR (0x00000003) 146 #define NV85B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS 25:24 147 #define NV85B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE (0x00000000) 148 #define NV85B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO (0x00000001) 149 #define NV85B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE (0x00000002) 150 #define NV85B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR (0x00000003) 151 #define NV85B5_SET_DST_BLOCK_SIZE (0x0000070C) 152 #define NV85B5_SET_DST_BLOCK_SIZE_WIDTH 3:0 153 #define NV85B5_SET_DST_BLOCK_SIZE_WIDTH_QUARTER_GOB (0x0000000E) 154 #define NV85B5_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) 155 #define NV85B5_SET_DST_BLOCK_SIZE_HEIGHT 7:4 156 #define NV85B5_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) 157 #define NV85B5_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) 158 #define NV85B5_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) 159 #define NV85B5_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) 160 #define NV85B5_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) 161 #define NV85B5_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) 162 #define NV85B5_SET_DST_BLOCK_SIZE_DEPTH 11:8 163 #define NV85B5_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) 164 #define NV85B5_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) 165 #define NV85B5_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) 166 #define NV85B5_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) 167 #define NV85B5_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) 168 #define NV85B5_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) 169 #define NV85B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT 15:12 170 #define NV85B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_TESLA_4 (0x00000000) 171 #define NV85B5_SET_DST_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) 172 #define NV85B5_SET_DST_WIDTH (0x00000710) 173 #define NV85B5_SET_DST_WIDTH_V 31:0 174 #define NV85B5_SET_DST_HEIGHT (0x00000714) 175 #define NV85B5_SET_DST_HEIGHT_V 31:0 176 #define NV85B5_SET_DST_DEPTH (0x00000718) 177 #define NV85B5_SET_DST_DEPTH_V 31:0 178 #define NV85B5_SET_DST_LAYER (0x0000071C) 179 #define NV85B5_SET_DST_LAYER_V 31:0 180 #define NV85B5_SET_DST_ORIGIN (0x00000720) 181 #define NV85B5_SET_DST_ORIGIN_X 15:0 182 #define NV85B5_SET_DST_ORIGIN_Y 31:16 183 #define NV85B5_SET_SRC_BLOCK_SIZE (0x00000728) 184 #define NV85B5_SET_SRC_BLOCK_SIZE_WIDTH 3:0 185 #define NV85B5_SET_SRC_BLOCK_SIZE_WIDTH_QUARTER_GOB (0x0000000E) 186 #define NV85B5_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB (0x00000000) 187 #define NV85B5_SET_SRC_BLOCK_SIZE_HEIGHT 7:4 188 #define NV85B5_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB (0x00000000) 189 #define NV85B5_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS (0x00000001) 190 #define NV85B5_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS (0x00000002) 191 #define NV85B5_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS (0x00000003) 192 #define NV85B5_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS (0x00000004) 193 #define NV85B5_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS (0x00000005) 194 #define NV85B5_SET_SRC_BLOCK_SIZE_DEPTH 11:8 195 #define NV85B5_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB (0x00000000) 196 #define NV85B5_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS (0x00000001) 197 #define NV85B5_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS (0x00000002) 198 #define NV85B5_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS (0x00000003) 199 #define NV85B5_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS (0x00000004) 200 #define NV85B5_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS (0x00000005) 201 #define NV85B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT 15:12 202 #define NV85B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_TESLA_4 (0x00000000) 203 #define NV85B5_SET_SRC_BLOCK_SIZE_GOB_HEIGHT_GOB_HEIGHT_FERMI_8 (0x00000001) 204 #define NV85B5_SET_SRC_WIDTH (0x0000072C) 205 #define NV85B5_SET_SRC_WIDTH_V 31:0 206 #define NV85B5_SET_SRC_HEIGHT (0x00000730) 207 #define NV85B5_SET_SRC_HEIGHT_V 31:0 208 #define NV85B5_SET_SRC_DEPTH (0x00000734) 209 #define NV85B5_SET_SRC_DEPTH_V 31:0 210 #define NV85B5_SET_SRC_LAYER (0x00000738) 211 #define NV85B5_SET_SRC_LAYER_V 31:0 212 #define NV85B5_SET_SRC_ORIGIN (0x0000073C) 213 #define NV85B5_SET_SRC_ORIGIN_X 15:0 214 #define NV85B5_SET_SRC_ORIGIN_Y 31:16 215 #define NV85B5_PM_TRIGGER_END (0x00001114) 216 #define NV85B5_PM_TRIGGER_END_V 31:0 217 218 #ifdef __cplusplus 219 }; /* extern "C" */ 220 #endif 221 #endif // _cl85b5_h 222 223