1 /******************************************************************************* 2 Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. 3 4 Permission is hereby granted, free of charge, to any person obtaining a 5 copy of this software and associated documentation files (the "Software"), 6 to deal in the Software without restriction, including without limitation 7 the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 and/or sell copies of the Software, and to permit persons to whom the 9 Software is furnished to do so, subject to the following conditions: 10 11 The above copyright notice and this permission notice shall be included in 12 all copies or substantial portions of the Software. 13 14 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 19 FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 20 DEALINGS IN THE SOFTWARE. 21 22 *******************************************************************************/ 23 #ifndef _clc06f_h_ 24 #define _clc06f_h_ 25 26 #ifdef __cplusplus 27 extern "C" { 28 #endif 29 30 #include "nvtypes.h" 31 32 /* class PASCAL_CHANNEL_GPFIFO */ 33 /* 34 * Documentation for PASCAL_CHANNEL_GPFIFO can be found in dev_pbdma.ref, 35 * chapter "User Control Registers". It is documented as device NV_UDMA. 36 * The GPFIFO format itself is also documented in dev_pbdma.ref, 37 * NV_PPBDMA_GP_ENTRY_*. The pushbuffer format is documented in dev_ram.ref, 38 * chapter "FIFO DMA RAM", NV_FIFO_DMA_*. 39 * 40 * Note there is no .mfs file for this class. 41 */ 42 #define PASCAL_CHANNEL_GPFIFO_A (0x0000C06F) 43 44 #define NVC06F_TYPEDEF PASCAL_CHANNELChannelGPFifoA 45 46 /* dma flow control data structure */ 47 typedef volatile struct Nvc06fControl_struct { 48 NvU32 Ignored00[0x010]; /* 0000-003f*/ 49 NvU32 Put; /* put offset, read/write 0040-0043*/ 50 NvU32 Get; /* get offset, read only 0044-0047*/ 51 NvU32 Reference; /* reference value, read only 0048-004b*/ 52 NvU32 PutHi; /* high order put offset bits 004c-004f*/ 53 NvU32 Ignored01[0x002]; /* 0050-0057*/ 54 NvU32 TopLevelGet; /* top level get offset, read only 0058-005b*/ 55 NvU32 TopLevelGetHi; /* high order top level get bits 005c-005f*/ 56 NvU32 GetHi; /* high order get offset bits 0060-0063*/ 57 NvU32 Ignored02[0x007]; /* 0064-007f*/ 58 NvU32 Ignored03; /* used to be engine yield 0080-0083*/ 59 NvU32 Ignored04[0x001]; /* 0084-0087*/ 60 NvU32 GPGet; /* GP FIFO get offset, read only 0088-008b*/ 61 NvU32 GPPut; /* GP FIFO put offset 008c-008f*/ 62 NvU32 Ignored05[0x5c]; 63 } Nvc06fControl, PascalAControlGPFifo; 64 65 /* fields and values */ 66 #define NVC06F_NUMBER_OF_SUBCHANNELS (8) 67 #define NVC06F_SET_OBJECT (0x00000000) 68 #define NVC06F_SET_OBJECT_NVCLASS 15:0 69 #define NVC06F_SET_OBJECT_ENGINE 20:16 70 #define NVC06F_SET_OBJECT_ENGINE_SW 0x0000001f 71 #define NVC06F_ILLEGAL (0x00000004) 72 #define NVC06F_ILLEGAL_HANDLE 31:0 73 #define NVC06F_NOP (0x00000008) 74 #define NVC06F_NOP_HANDLE 31:0 75 #define NVC06F_SEMAPHOREA (0x00000010) 76 #define NVC06F_SEMAPHOREA_OFFSET_UPPER 7:0 77 #define NVC06F_SEMAPHOREB (0x00000014) 78 #define NVC06F_SEMAPHOREB_OFFSET_LOWER 31:2 79 #define NVC06F_SEMAPHOREC (0x00000018) 80 #define NVC06F_SEMAPHOREC_PAYLOAD 31:0 81 #define NVC06F_SEMAPHORED (0x0000001C) 82 #define NVC06F_SEMAPHORED_OPERATION 4:0 83 #define NVC06F_SEMAPHORED_OPERATION_ACQUIRE 0x00000001 84 #define NVC06F_SEMAPHORED_OPERATION_RELEASE 0x00000002 85 #define NVC06F_SEMAPHORED_OPERATION_ACQ_GEQ 0x00000004 86 #define NVC06F_SEMAPHORED_OPERATION_ACQ_AND 0x00000008 87 #define NVC06F_SEMAPHORED_OPERATION_REDUCTION 0x00000010 88 #define NVC06F_SEMAPHORED_ACQUIRE_SWITCH 12:12 89 #define NVC06F_SEMAPHORED_ACQUIRE_SWITCH_DISABLED 0x00000000 90 #define NVC06F_SEMAPHORED_ACQUIRE_SWITCH_ENABLED 0x00000001 91 #define NVC06F_SEMAPHORED_RELEASE_WFI 20:20 92 #define NVC06F_SEMAPHORED_RELEASE_WFI_EN 0x00000000 93 #define NVC06F_SEMAPHORED_RELEASE_WFI_DIS 0x00000001 94 #define NVC06F_SEMAPHORED_RELEASE_SIZE 24:24 95 #define NVC06F_SEMAPHORED_RELEASE_SIZE_16BYTE 0x00000000 96 #define NVC06F_SEMAPHORED_RELEASE_SIZE_4BYTE 0x00000001 97 #define NVC06F_SEMAPHORED_REDUCTION 30:27 98 #define NVC06F_SEMAPHORED_REDUCTION_MIN 0x00000000 99 #define NVC06F_SEMAPHORED_REDUCTION_MAX 0x00000001 100 #define NVC06F_SEMAPHORED_REDUCTION_XOR 0x00000002 101 #define NVC06F_SEMAPHORED_REDUCTION_AND 0x00000003 102 #define NVC06F_SEMAPHORED_REDUCTION_OR 0x00000004 103 #define NVC06F_SEMAPHORED_REDUCTION_ADD 0x00000005 104 #define NVC06F_SEMAPHORED_REDUCTION_INC 0x00000006 105 #define NVC06F_SEMAPHORED_REDUCTION_DEC 0x00000007 106 #define NVC06F_SEMAPHORED_FORMAT 31:31 107 #define NVC06F_SEMAPHORED_FORMAT_SIGNED 0x00000000 108 #define NVC06F_SEMAPHORED_FORMAT_UNSIGNED 0x00000001 109 #define NVC06F_NON_STALL_INTERRUPT (0x00000020) 110 #define NVC06F_NON_STALL_INTERRUPT_HANDLE 31:0 111 #define NVC06F_FB_FLUSH (0x00000024) // Deprecated - use MEMBAR TYPE SYS_MEMBAR 112 #define NVC06F_FB_FLUSH_HANDLE 31:0 113 // NOTE - MEM_OP_A and MEM_OP_B have been replaced in gp100 with methods for 114 // specifying the page address for a targeted TLB invalidate and the uTLB for 115 // a targeted REPLAY_CANCEL for UVM. 116 // The previous MEM_OP_A/B functionality is in MEM_OP_C/D, with slightly 117 // rearranged fields. 118 #define NVC06F_MEM_OP_A (0x00000028) 119 #define NVC06F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_CLIENT_UNIT_ID 5:0 // only relevant for REPLAY_CANCEL_TARGETED 120 #define NVC06F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_GPC_ID 10:6 // only relevant for REPLAY_CANCEL_TARGETED 121 #define NVC06F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR 11:11 122 #define NVC06F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_EN 0x00000001 123 #define NVC06F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_DIS 0x00000000 124 #define NVC06F_MEM_OP_A_TLB_INVALIDATE_TARGET_ADDR_LO 31:12 125 #define NVC06F_MEM_OP_B (0x0000002c) 126 #define NVC06F_MEM_OP_B_TLB_INVALIDATE_TARGET_ADDR_HI 31:0 127 #define NVC06F_MEM_OP_C (0x00000030) 128 #define NVC06F_MEM_OP_C_MEMBAR_TYPE 2:0 129 #define NVC06F_MEM_OP_C_MEMBAR_TYPE_SYS_MEMBAR 0x00000000 130 #define NVC06F_MEM_OP_C_MEMBAR_TYPE_MEMBAR 0x00000001 131 #define NVC06F_MEM_OP_C_TLB_INVALIDATE_PDB 0:0 132 #define NVC06F_MEM_OP_C_TLB_INVALIDATE_PDB_ONE 0x00000000 133 #define NVC06F_MEM_OP_C_TLB_INVALIDATE_PDB_ALL 0x00000001 // Probably nonsensical for MMU_TLB_INVALIDATE_TARGETED 134 #define NVC06F_MEM_OP_C_TLB_INVALIDATE_GPC 1:1 135 #define NVC06F_MEM_OP_C_TLB_INVALIDATE_GPC_ENABLE 0x00000000 136 #define NVC06F_MEM_OP_C_TLB_INVALIDATE_GPC_DISABLE 0x00000001 137 #define NVC06F_MEM_OP_C_TLB_INVALIDATE_REPLAY 4:2 // only relevant if GPC ENABLE 138 #define NVC06F_MEM_OP_C_TLB_INVALIDATE_REPLAY_NONE 0x00000000 139 #define NVC06F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START 0x00000001 140 #define NVC06F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START_ACK_ALL 0x00000002 141 #define NVC06F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_TARGETED 0x00000003 142 #define NVC06F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_GLOBAL 0x00000004 143 #define NVC06F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE 6:5 // only relevant if GPC ENABLE 144 #define NVC06F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_NONE 0x00000000 145 #define NVC06F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_GLOBALLY 0x00000001 146 #define NVC06F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_INTRANODE 0x00000002 147 #define NVC06F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL 9:7 // Invalidate affects this level and all below 148 #define NVC06F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_ALL 0x00000000 // Invalidate tlb caches at all levels of the page table 149 #define NVC06F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_PTE_ONLY 0x00000001 150 #define NVC06F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE0 0x00000002 151 #define NVC06F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE1 0x00000003 152 #define NVC06F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE2 0x00000004 153 #define NVC06F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE3 0x00000005 154 #define NVC06F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE4 0x00000006 155 #define NVC06F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE5 0x00000007 156 #define NVC06F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE 11:10 // only relevant if PDB_ONE 157 #define NVC06F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_VID_MEM 0x00000000 158 #define NVC06F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_COHERENT 0x00000002 159 #define NVC06F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_NONCOHERENT 0x00000003 160 #define NVC06F_MEM_OP_C_TLB_INVALIDATE_PDB_ADDR_LO 31:12 // only relevant if PDB_ONE 161 // MEM_OP_D MUST be preceded by MEM_OPs A-C. 162 #define NVC06F_MEM_OP_D (0x00000034) 163 #define NVC06F_MEM_OP_D_TLB_INVALIDATE_PDB_ADDR_HI 26:0 // only relevant if PDB_ONE 164 #define NVC06F_MEM_OP_D_OPERATION 31:27 165 #define NVC06F_MEM_OP_D_OPERATION_MEMBAR 0x00000005 166 #define NVC06F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE 0x00000009 167 #define NVC06F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE_TARGETED 0x0000000a 168 #define NVC06F_MEM_OP_D_OPERATION_L2_PEERMEM_INVALIDATE 0x0000000d 169 #define NVC06F_MEM_OP_D_OPERATION_L2_SYSMEM_INVALIDATE 0x0000000e 170 // CLEAN_LINES is an alias for Tegra/GPU IP usage 171 #define NVC06F_MEM_OP_D_OPERATION_L2_INVALIDATE_CLEAN_LINES 0x0000000e 172 // This B alias is confusing but it was missed as part of the update. Left here 173 // for compatibility. 174 #define NVC06F_MEM_OP_B_OPERATION_L2_INVALIDATE_CLEAN_LINES 0x0000000e 175 #define NVC06F_MEM_OP_D_OPERATION_L2_CLEAN_COMPTAGS 0x0000000f 176 #define NVC06F_MEM_OP_D_OPERATION_L2_FLUSH_DIRTY 0x00000010 177 #define NVC06F_MEM_OP_D_OPERATION_L2_WAIT_FOR_SYS_PENDING_READS 0x00000015 178 #define NVC06F_SET_REFERENCE (0x00000050) 179 #define NVC06F_SET_REFERENCE_COUNT 31:0 180 // Syncpoint methods are only available on Tegra parts. Attempting to use 181 // them on discrete GPUs will result in Host raising NV_PPBDMA_INTR_0_METHOD. 182 #define NVC06F_SYNCPOINTA (0x00000070) 183 #define NVC06F_SYNCPOINTA_PAYLOAD 31:0 184 #define NVC06F_SYNCPOINTB (0x00000074) 185 #define NVC06F_SYNCPOINTB_OPERATION 0:0 186 #define NVC06F_SYNCPOINTB_OPERATION_WAIT 0x00000000 187 #define NVC06F_SYNCPOINTB_OPERATION_INCR 0x00000001 188 #define NVC06F_SYNCPOINTB_WAIT_SWITCH 4:4 189 #define NVC06F_SYNCPOINTB_WAIT_SWITCH_DIS 0x00000000 190 #define NVC06F_SYNCPOINTB_WAIT_SWITCH_EN 0x00000001 191 #define NVC06F_SYNCPOINTB_SYNCPT_INDEX 19:8 192 #define NVC06F_WFI (0x00000078) 193 #define NVC06F_WFI_SCOPE 0:0 194 #define NVC06F_WFI_SCOPE_CURRENT_SCG_TYPE 0x00000000 195 #define NVC06F_WFI_SCOPE_ALL 0x00000001 196 #define NVC06F_CRC_CHECK (0x0000007c) 197 #define NVC06F_CRC_CHECK_VALUE 31:0 198 #define NVC06F_YIELD (0x00000080) 199 #define NVC06F_YIELD_OP 1:0 200 #define NVC06F_YIELD_OP_NOP 0x00000000 201 #define NVC06F_YIELD_OP_PBDMA_TIMESLICE 0x00000001 202 #define NVC06F_YIELD_OP_RUNLIST_TIMESLICE 0x00000002 203 #define NVC06F_YIELD_OP_TSG 0x00000003 204 205 206 /* GPFIFO entry format */ 207 #define NVC06F_GP_ENTRY__SIZE 8 208 #define NVC06F_GP_ENTRY0_FETCH 0:0 209 #define NVC06F_GP_ENTRY0_FETCH_UNCONDITIONAL 0x00000000 210 #define NVC06F_GP_ENTRY0_FETCH_CONDITIONAL 0x00000001 211 #define NVC06F_GP_ENTRY0_GET 31:2 212 #define NVC06F_GP_ENTRY0_OPERAND 31:0 213 #define NVC06F_GP_ENTRY1_GET_HI 7:0 214 #define NVC06F_GP_ENTRY1_PRIV 8:8 215 #define NVC06F_GP_ENTRY1_PRIV_USER 0x00000000 216 #define NVC06F_GP_ENTRY1_PRIV_KERNEL 0x00000001 217 #define NVC06F_GP_ENTRY1_LEVEL 9:9 218 #define NVC06F_GP_ENTRY1_LEVEL_MAIN 0x00000000 219 #define NVC06F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001 220 #define NVC06F_GP_ENTRY1_LENGTH 30:10 221 #define NVC06F_GP_ENTRY1_SYNC 31:31 222 #define NVC06F_GP_ENTRY1_SYNC_PROCEED 0x00000000 223 #define NVC06F_GP_ENTRY1_SYNC_WAIT 0x00000001 224 #define NVC06F_GP_ENTRY1_OPCODE 7:0 225 #define NVC06F_GP_ENTRY1_OPCODE_NOP 0x00000000 226 #define NVC06F_GP_ENTRY1_OPCODE_ILLEGAL 0x00000001 227 #define NVC06F_GP_ENTRY1_OPCODE_GP_CRC 0x00000002 228 #define NVC06F_GP_ENTRY1_OPCODE_PB_CRC 0x00000003 229 230 /* dma method formats */ 231 #define NVC06F_DMA_METHOD_ADDRESS_OLD 12:2 232 #define NVC06F_DMA_METHOD_ADDRESS 11:0 233 #define NVC06F_DMA_SUBDEVICE_MASK 15:4 234 #define NVC06F_DMA_METHOD_SUBCHANNEL 15:13 235 #define NVC06F_DMA_TERT_OP 17:16 236 #define NVC06F_DMA_TERT_OP_GRP0_INC_METHOD (0x00000000) 237 #define NVC06F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK (0x00000001) 238 #define NVC06F_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK (0x00000002) 239 #define NVC06F_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK (0x00000003) 240 #define NVC06F_DMA_TERT_OP_GRP2_NON_INC_METHOD (0x00000000) 241 #define NVC06F_DMA_METHOD_COUNT_OLD 28:18 242 #define NVC06F_DMA_METHOD_COUNT 28:16 243 #define NVC06F_DMA_IMMD_DATA 28:16 244 #define NVC06F_DMA_SEC_OP 31:29 245 #define NVC06F_DMA_SEC_OP_GRP0_USE_TERT (0x00000000) 246 #define NVC06F_DMA_SEC_OP_INC_METHOD (0x00000001) 247 #define NVC06F_DMA_SEC_OP_GRP2_USE_TERT (0x00000002) 248 #define NVC06F_DMA_SEC_OP_NON_INC_METHOD (0x00000003) 249 #define NVC06F_DMA_SEC_OP_IMMD_DATA_METHOD (0x00000004) 250 #define NVC06F_DMA_SEC_OP_ONE_INC (0x00000005) 251 #define NVC06F_DMA_SEC_OP_RESERVED6 (0x00000006) 252 #define NVC06F_DMA_SEC_OP_END_PB_SEGMENT (0x00000007) 253 /* dma incrementing method format */ 254 #define NVC06F_DMA_INCR_ADDRESS 11:0 255 #define NVC06F_DMA_INCR_SUBCHANNEL 15:13 256 #define NVC06F_DMA_INCR_COUNT 28:16 257 #define NVC06F_DMA_INCR_OPCODE 31:29 258 #define NVC06F_DMA_INCR_OPCODE_VALUE (0x00000001) 259 #define NVC06F_DMA_INCR_DATA 31:0 260 /* dma non-incrementing method format */ 261 #define NVC06F_DMA_NONINCR_ADDRESS 11:0 262 #define NVC06F_DMA_NONINCR_SUBCHANNEL 15:13 263 #define NVC06F_DMA_NONINCR_COUNT 28:16 264 #define NVC06F_DMA_NONINCR_OPCODE 31:29 265 #define NVC06F_DMA_NONINCR_OPCODE_VALUE (0x00000003) 266 #define NVC06F_DMA_NONINCR_DATA 31:0 267 /* dma increment-once method format */ 268 #define NVC06F_DMA_ONEINCR_ADDRESS 11:0 269 #define NVC06F_DMA_ONEINCR_SUBCHANNEL 15:13 270 #define NVC06F_DMA_ONEINCR_COUNT 28:16 271 #define NVC06F_DMA_ONEINCR_OPCODE 31:29 272 #define NVC06F_DMA_ONEINCR_OPCODE_VALUE (0x00000005) 273 #define NVC06F_DMA_ONEINCR_DATA 31:0 274 /* dma no-operation format */ 275 #define NVC06F_DMA_NOP (0x00000000) 276 /* dma immediate-data format */ 277 #define NVC06F_DMA_IMMD_ADDRESS 11:0 278 #define NVC06F_DMA_IMMD_SUBCHANNEL 15:13 279 #define NVC06F_DMA_IMMD_DATA 28:16 280 #define NVC06F_DMA_IMMD_OPCODE 31:29 281 #define NVC06F_DMA_IMMD_OPCODE_VALUE (0x00000004) 282 /* dma set sub-device mask format */ 283 #define NVC06F_DMA_SET_SUBDEVICE_MASK_VALUE 15:4 284 #define NVC06F_DMA_SET_SUBDEVICE_MASK_OPCODE 31:16 285 #define NVC06F_DMA_SET_SUBDEVICE_MASK_OPCODE_VALUE (0x00000001) 286 /* dma store sub-device mask format */ 287 #define NVC06F_DMA_STORE_SUBDEVICE_MASK_VALUE 15:4 288 #define NVC06F_DMA_STORE_SUBDEVICE_MASK_OPCODE 31:16 289 #define NVC06F_DMA_STORE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000002) 290 /* dma use sub-device mask format */ 291 #define NVC06F_DMA_USE_SUBDEVICE_MASK_OPCODE 31:16 292 #define NVC06F_DMA_USE_SUBDEVICE_MASK_OPCODE_VALUE (0x00000003) 293 /* dma end-segment format */ 294 #define NVC06F_DMA_ENDSEG_OPCODE 31:29 295 #define NVC06F_DMA_ENDSEG_OPCODE_VALUE (0x00000007) 296 /* dma legacy incrementing/non-incrementing formats */ 297 #define NVC06F_DMA_ADDRESS 12:2 298 #define NVC06F_DMA_SUBCH 15:13 299 #define NVC06F_DMA_OPCODE3 17:16 300 #define NVC06F_DMA_OPCODE3_NONE (0x00000000) 301 #define NVC06F_DMA_COUNT 28:18 302 #define NVC06F_DMA_OPCODE 31:29 303 #define NVC06F_DMA_OPCODE_METHOD (0x00000000) 304 #define NVC06F_DMA_OPCODE_NONINC_METHOD (0x00000002) 305 #define NVC06F_DMA_DATA 31:0 306 307 #ifdef __cplusplus 308 }; /* extern "C" */ 309 #endif 310 311 #endif /* _clc06f_h_ */ 312