1 /******************************************************************************* 2 Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. 3 4 Permission is hereby granted, free of charge, to any person obtaining a 5 copy of this software and associated documentation files (the "Software"), 6 to deal in the Software without restriction, including without limitation 7 the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 and/or sell copies of the Software, and to permit persons to whom the 9 Software is furnished to do so, subject to the following conditions: 10 11 The above copyright notice and this permission notice shall be included in 12 all copies or substantial portions of the Software. 13 14 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 19 FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 20 DEALINGS IN THE SOFTWARE. 21 22 *******************************************************************************/ 23 24 /* AUTO GENERATED FILE -- DO NOT EDIT */ 25 26 #ifndef __CLC7C0QMD_H__ 27 #define __CLC7C0QMD_H__ 28 29 /* 30 ** Queue Meta Data, Version 02_03 31 */ 32 33 // The below C preprocessor definitions describe "multi-word" structures, where 34 // fields may have bit numbers beyond 32. For example, MW(127:96) means 35 // the field is in bits 0-31 of word number 3 of the structure. The "MW(X:Y)" 36 // syntax is to distinguish from similar "X:Y" single-word definitions: the 37 // macros historically used for single-word definitions would fail with 38 // multi-word definitions. 39 // 40 // See nvmisc.h:DRF_VAL_MW() in the source code of the kernel 41 // interface layer of nvidia.ko for an example of how to manipulate 42 // these MW(X:Y) definitions. 43 44 #define NVC7C0_QMDV02_03_OUTER_PUT MW(30:0) 45 #define NVC7C0_QMDV02_03_OUTER_OVERFLOW MW(31:31) 46 #define NVC7C0_QMDV02_03_OUTER_GET MW(62:32) 47 #define NVC7C0_QMDV02_03_OUTER_STICKY_OVERFLOW MW(63:63) 48 #define NVC7C0_QMDV02_03_INNER_GET MW(94:64) 49 #define NVC7C0_QMDV02_03_INNER_OVERFLOW MW(95:95) 50 #define NVC7C0_QMDV02_03_INNER_PUT MW(126:96) 51 #define NVC7C0_QMDV02_03_INNER_STICKY_OVERFLOW MW(127:127) 52 #define NVC7C0_QMDV02_03_QMD_GROUP_ID MW(133:128) 53 #define NVC7C0_QMDV02_03_SM_GLOBAL_CACHING_ENABLE MW(134:134) 54 #define NVC7C0_QMDV02_03_RUN_CTA_IN_ONE_SM_PARTITION MW(135:135) 55 #define NVC7C0_QMDV02_03_RUN_CTA_IN_ONE_SM_PARTITION_FALSE 0x00000000 56 #define NVC7C0_QMDV02_03_RUN_CTA_IN_ONE_SM_PARTITION_TRUE 0x00000001 57 #define NVC7C0_QMDV02_03_IS_QUEUE MW(136:136) 58 #define NVC7C0_QMDV02_03_IS_QUEUE_FALSE 0x00000000 59 #define NVC7C0_QMDV02_03_IS_QUEUE_TRUE 0x00000001 60 #define NVC7C0_QMDV02_03_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(137:137) 61 #define NVC7C0_QMDV02_03_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 62 #define NVC7C0_QMDV02_03_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 63 #define NVC7C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE0 MW(138:138) 64 #define NVC7C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 65 #define NVC7C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 66 #define NVC7C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE1 MW(139:139) 67 #define NVC7C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 68 #define NVC7C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 69 #define NVC7C0_QMDV02_03_REQUIRE_SCHEDULING_PCAS MW(140:140) 70 #define NVC7C0_QMDV02_03_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 71 #define NVC7C0_QMDV02_03_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 72 #define NVC7C0_QMDV02_03_DEPENDENT_QMD_SCHEDULE_ENABLE MW(141:141) 73 #define NVC7C0_QMDV02_03_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE 0x00000000 74 #define NVC7C0_QMDV02_03_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE 0x00000001 75 #define NVC7C0_QMDV02_03_DEPENDENT_QMD_TYPE MW(142:142) 76 #define NVC7C0_QMDV02_03_DEPENDENT_QMD_TYPE_QUEUE 0x00000000 77 #define NVC7C0_QMDV02_03_DEPENDENT_QMD_TYPE_GRID 0x00000001 78 #define NVC7C0_QMDV02_03_DEPENDENT_QMD_FIELD_COPY MW(143:143) 79 #define NVC7C0_QMDV02_03_DEPENDENT_QMD_FIELD_COPY_FALSE 0x00000000 80 #define NVC7C0_QMDV02_03_DEPENDENT_QMD_FIELD_COPY_TRUE 0x00000001 81 #define NVC7C0_QMDV02_03_QMD_RESERVED_B MW(159:144) 82 #define NVC7C0_QMDV02_03_CIRCULAR_QUEUE_SIZE MW(184:160) 83 #define NVC7C0_QMDV02_03_QMD_RESERVED_C MW(185:185) 84 #define NVC7C0_QMDV02_03_INVALIDATE_TEXTURE_HEADER_CACHE MW(186:186) 85 #define NVC7C0_QMDV02_03_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 86 #define NVC7C0_QMDV02_03_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 87 #define NVC7C0_QMDV02_03_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(187:187) 88 #define NVC7C0_QMDV02_03_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 89 #define NVC7C0_QMDV02_03_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 90 #define NVC7C0_QMDV02_03_INVALIDATE_TEXTURE_DATA_CACHE MW(188:188) 91 #define NVC7C0_QMDV02_03_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 92 #define NVC7C0_QMDV02_03_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 93 #define NVC7C0_QMDV02_03_INVALIDATE_SHADER_DATA_CACHE MW(189:189) 94 #define NVC7C0_QMDV02_03_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 95 #define NVC7C0_QMDV02_03_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 96 #define NVC7C0_QMDV02_03_INVALIDATE_INSTRUCTION_CACHE MW(190:190) 97 #define NVC7C0_QMDV02_03_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 98 #define NVC7C0_QMDV02_03_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 99 #define NVC7C0_QMDV02_03_INVALIDATE_SHADER_CONSTANT_CACHE MW(191:191) 100 #define NVC7C0_QMDV02_03_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 101 #define NVC7C0_QMDV02_03_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 102 #define NVC7C0_QMDV02_03_CTA_RASTER_WIDTH_RESUME MW(223:192) 103 #define NVC7C0_QMDV02_03_CTA_RASTER_HEIGHT_RESUME MW(239:224) 104 #define NVC7C0_QMDV02_03_CTA_RASTER_DEPTH_RESUME MW(255:240) 105 #define NVC7C0_QMDV02_03_PROGRAM_PREFETCH_ADDR_LOWER_SHIFTED MW(287:256) 106 #define NVC7C0_QMDV02_03_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) 107 #define NVC7C0_QMDV02_03_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) 108 #define NVC7C0_QMDV02_03_QMD_RESERVED_D MW(335:328) 109 #define NVC7C0_QMDV02_03_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) 110 #define NVC7C0_QMDV02_03_CWD_REFERENCE_COUNT_ID MW(357:352) 111 #define NVC7C0_QMDV02_03_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) 112 #define NVC7C0_QMDV02_03_RELEASE_MEMBAR_TYPE MW(366:366) 113 #define NVC7C0_QMDV02_03_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 114 #define NVC7C0_QMDV02_03_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 115 #define NVC7C0_QMDV02_03_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) 116 #define NVC7C0_QMDV02_03_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 117 #define NVC7C0_QMDV02_03_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 118 #define NVC7C0_QMDV02_03_CWD_MEMBAR_TYPE MW(369:368) 119 #define NVC7C0_QMDV02_03_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 120 #define NVC7C0_QMDV02_03_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 121 #define NVC7C0_QMDV02_03_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 122 #define NVC7C0_QMDV02_03_SEQUENTIALLY_RUN_CTAS MW(370:370) 123 #define NVC7C0_QMDV02_03_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 124 #define NVC7C0_QMDV02_03_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 125 #define NVC7C0_QMDV02_03_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) 126 #define NVC7C0_QMDV02_03_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 127 #define NVC7C0_QMDV02_03_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 128 #define NVC7C0_QMDV02_03_API_VISIBLE_CALL_LIMIT MW(378:378) 129 #define NVC7C0_QMDV02_03_API_VISIBLE_CALL_LIMIT__32 0x00000000 130 #define NVC7C0_QMDV02_03_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 131 #define NVC7C0_QMDV02_03_SAMPLER_INDEX MW(382:382) 132 #define NVC7C0_QMDV02_03_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 133 #define NVC7C0_QMDV02_03_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 134 #define NVC7C0_QMDV02_03_CTA_RASTER_WIDTH MW(415:384) 135 #define NVC7C0_QMDV02_03_CTA_RASTER_HEIGHT MW(431:416) 136 #define NVC7C0_QMDV02_03_QMD_RESERVED13A MW(447:432) 137 #define NVC7C0_QMDV02_03_CTA_RASTER_DEPTH MW(463:448) 138 #define NVC7C0_QMDV02_03_QMD_RESERVED14A MW(479:464) 139 #define NVC7C0_QMDV02_03_DEPENDENT_QMD_POINTER MW(511:480) 140 #define NVC7C0_QMDV02_03_COALESCE_WAITING_PERIOD MW(529:522) 141 #define NVC7C0_QMDV02_03_QUEUE_ENTRIES_PER_CTA_LOG2 MW(534:530) 142 #define NVC7C0_QMDV02_03_SHARED_MEMORY_SIZE MW(561:544) 143 #define NVC7C0_QMDV02_03_MIN_SM_CONFIG_SHARED_MEM_SIZE MW(568:562) 144 #define NVC7C0_QMDV02_03_MAX_SM_CONFIG_SHARED_MEM_SIZE MW(575:569) 145 #define NVC7C0_QMDV02_03_QMD_VERSION MW(579:576) 146 #define NVC7C0_QMDV02_03_QMD_MAJOR_VERSION MW(583:580) 147 #define NVC7C0_QMDV02_03_QMD_RESERVED_H MW(591:584) 148 #define NVC7C0_QMDV02_03_CTA_THREAD_DIMENSION0 MW(607:592) 149 #define NVC7C0_QMDV02_03_CTA_THREAD_DIMENSION1 MW(623:608) 150 #define NVC7C0_QMDV02_03_CTA_THREAD_DIMENSION2 MW(639:624) 151 #define NVC7C0_QMDV02_03_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) 152 #define NVC7C0_QMDV02_03_CONSTANT_BUFFER_VALID_FALSE 0x00000000 153 #define NVC7C0_QMDV02_03_CONSTANT_BUFFER_VALID_TRUE 0x00000001 154 #define NVC7C0_QMDV02_03_REGISTER_COUNT_V MW(656:648) 155 #define NVC7C0_QMDV02_03_TARGET_SM_CONFIG_SHARED_MEM_SIZE MW(663:657) 156 #define NVC7C0_QMDV02_03_FREE_CTA_SLOTS_EMPTY_SM MW(671:664) 157 #define NVC7C0_QMDV02_03_SM_DISABLE_MASK_LOWER MW(703:672) 158 #define NVC7C0_QMDV02_03_SM_DISABLE_MASK_UPPER MW(735:704) 159 #define NVC7C0_QMDV02_03_RELEASE0_ADDRESS_LOWER MW(767:736) 160 #define NVC7C0_QMDV02_03_RELEASE0_ADDRESS_UPPER MW(775:768) 161 #define NVC7C0_QMDV02_03_QMD_RESERVED_J MW(783:776) 162 #define NVC7C0_QMDV02_03_RELEASE0_REDUCTION_OP MW(790:788) 163 #define NVC7C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 164 #define NVC7C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 165 #define NVC7C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 166 #define NVC7C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 167 #define NVC7C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 168 #define NVC7C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 169 #define NVC7C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 170 #define NVC7C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 171 #define NVC7C0_QMDV02_03_QMD_RESERVED_K MW(791:791) 172 #define NVC7C0_QMDV02_03_RELEASE0_REDUCTION_FORMAT MW(793:792) 173 #define NVC7C0_QMDV02_03_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 174 #define NVC7C0_QMDV02_03_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 175 #define NVC7C0_QMDV02_03_RELEASE0_REDUCTION_ENABLE MW(794:794) 176 #define NVC7C0_QMDV02_03_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 177 #define NVC7C0_QMDV02_03_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 178 #define NVC7C0_QMDV02_03_RELEASE0_STRUCTURE_SIZE MW(799:799) 179 #define NVC7C0_QMDV02_03_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 180 #define NVC7C0_QMDV02_03_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 181 #define NVC7C0_QMDV02_03_RELEASE0_PAYLOAD MW(831:800) 182 #define NVC7C0_QMDV02_03_RELEASE1_ADDRESS_LOWER MW(863:832) 183 #define NVC7C0_QMDV02_03_RELEASE1_ADDRESS_UPPER MW(871:864) 184 #define NVC7C0_QMDV02_03_QMD_RESERVED_L MW(879:872) 185 #define NVC7C0_QMDV02_03_RELEASE1_REDUCTION_OP MW(886:884) 186 #define NVC7C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 187 #define NVC7C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 188 #define NVC7C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 189 #define NVC7C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 190 #define NVC7C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 191 #define NVC7C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 192 #define NVC7C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 193 #define NVC7C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 194 #define NVC7C0_QMDV02_03_QMD_RESERVED_M MW(887:887) 195 #define NVC7C0_QMDV02_03_RELEASE1_REDUCTION_FORMAT MW(889:888) 196 #define NVC7C0_QMDV02_03_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 197 #define NVC7C0_QMDV02_03_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 198 #define NVC7C0_QMDV02_03_RELEASE1_REDUCTION_ENABLE MW(890:890) 199 #define NVC7C0_QMDV02_03_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 200 #define NVC7C0_QMDV02_03_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 201 #define NVC7C0_QMDV02_03_RELEASE1_STRUCTURE_SIZE MW(895:895) 202 #define NVC7C0_QMDV02_03_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 203 #define NVC7C0_QMDV02_03_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 204 #define NVC7C0_QMDV02_03_RELEASE1_PAYLOAD MW(927:896) 205 #define NVC7C0_QMDV02_03_SHADER_LOCAL_MEMORY_LOW_SIZE MW(951:928) 206 #define NVC7C0_QMDV02_03_QMD_RESERVED_N MW(954:952) 207 #define NVC7C0_QMDV02_03_BARRIER_COUNT MW(959:955) 208 #define NVC7C0_QMDV02_03_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(983:960) 209 #define NVC7C0_QMDV02_03_REGISTER_COUNT MW(991:984) 210 #define NVC7C0_QMDV02_03_PROGRAM_PREFETCH_ADDR_UPPER_SHIFTED MW(1000:992) 211 #define NVC7C0_QMDV02_03_PROGRAM_PREFETCH_SIZE MW(1009:1001) 212 #define NVC7C0_QMDV02_03_QMD_RESERVED_A MW(1015:1010) 213 #define NVC7C0_QMDV02_03_SASS_VERSION MW(1023:1016) 214 #define NVC7C0_QMDV02_03_CONSTANT_BUFFER_ADDR_LOWER(i) MW((1055+(i)*64):(1024+(i)*64)) 215 #define NVC7C0_QMDV02_03_CONSTANT_BUFFER_ADDR_UPPER(i) MW((1072+(i)*64):(1056+(i)*64)) 216 #define NVC7C0_QMDV02_03_CONSTANT_BUFFER_PREFETCH_POST(i) MW((1073+(i)*64):(1073+(i)*64)) 217 #define NVC7C0_QMDV02_03_CONSTANT_BUFFER_PREFETCH_POST_FALSE 0x00000000 218 #define NVC7C0_QMDV02_03_CONSTANT_BUFFER_PREFETCH_POST_TRUE 0x00000001 219 #define NVC7C0_QMDV02_03_CONSTANT_BUFFER_INVALIDATE(i) MW((1074+(i)*64):(1074+(i)*64)) 220 #define NVC7C0_QMDV02_03_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 221 #define NVC7C0_QMDV02_03_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 222 #define NVC7C0_QMDV02_03_CONSTANT_BUFFER_SIZE_SHIFTED4(i) MW((1087+(i)*64):(1075+(i)*64)) 223 #define NVC7C0_QMDV02_03_PROGRAM_ADDRESS_LOWER MW(1567:1536) 224 #define NVC7C0_QMDV02_03_PROGRAM_ADDRESS_UPPER MW(1584:1568) 225 #define NVC7C0_QMDV02_03_QMD_RESERVED_S MW(1599:1585) 226 #define NVC7C0_QMDV02_03_HW_ONLY_INNER_GET MW(1630:1600) 227 #define NVC7C0_QMDV02_03_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1631:1631) 228 #define NVC7C0_QMDV02_03_HW_ONLY_INNER_PUT MW(1662:1632) 229 #define NVC7C0_QMDV02_03_HW_ONLY_SCG_TYPE MW(1663:1663) 230 #define NVC7C0_QMDV02_03_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1693:1664) 231 #define NVC7C0_QMDV02_03_QMD_RESERVED_Q MW(1694:1694) 232 #define NVC7C0_QMDV02_03_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1695:1695) 233 #define NVC7C0_QMDV02_03_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 234 #define NVC7C0_QMDV02_03_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 235 #define NVC7C0_QMDV02_03_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1727:1696) 236 #define NVC7C0_QMDV02_03_QMD_SPARE_G MW(1759:1728) 237 #define NVC7C0_QMDV02_03_QMD_SPARE_H MW(1791:1760) 238 #define NVC7C0_QMDV02_03_QMD_SPARE_I MW(1823:1792) 239 #define NVC7C0_QMDV02_03_QMD_SPARE_J MW(1855:1824) 240 #define NVC7C0_QMDV02_03_QMD_SPARE_K MW(1887:1856) 241 #define NVC7C0_QMDV02_03_QMD_SPARE_L MW(1919:1888) 242 #define NVC7C0_QMDV02_03_QMD_SPARE_M MW(1951:1920) 243 #define NVC7C0_QMDV02_03_QMD_SPARE_N MW(1983:1952) 244 #define NVC7C0_QMDV02_03_DEBUG_ID_UPPER MW(2015:1984) 245 #define NVC7C0_QMDV02_03_DEBUG_ID_LOWER MW(2047:2016) 246 247 248 /* 249 ** Queue Meta Data, Version 02_04 250 */ 251 252 #define NVC7C0_QMDV02_04_OUTER_PUT MW(30:0) 253 #define NVC7C0_QMDV02_04_OUTER_OVERFLOW MW(31:31) 254 #define NVC7C0_QMDV02_04_OUTER_GET MW(62:32) 255 #define NVC7C0_QMDV02_04_OUTER_STICKY_OVERFLOW MW(63:63) 256 #define NVC7C0_QMDV02_04_INNER_GET MW(94:64) 257 #define NVC7C0_QMDV02_04_INNER_OVERFLOW MW(95:95) 258 #define NVC7C0_QMDV02_04_INNER_PUT MW(126:96) 259 #define NVC7C0_QMDV02_04_INNER_STICKY_OVERFLOW MW(127:127) 260 #define NVC7C0_QMDV02_04_QMD_GROUP_ID MW(133:128) 261 #define NVC7C0_QMDV02_04_SM_GLOBAL_CACHING_ENABLE MW(134:134) 262 #define NVC7C0_QMDV02_04_RUN_CTA_IN_ONE_SM_PARTITION MW(135:135) 263 #define NVC7C0_QMDV02_04_RUN_CTA_IN_ONE_SM_PARTITION_FALSE 0x00000000 264 #define NVC7C0_QMDV02_04_RUN_CTA_IN_ONE_SM_PARTITION_TRUE 0x00000001 265 #define NVC7C0_QMDV02_04_IS_QUEUE MW(136:136) 266 #define NVC7C0_QMDV02_04_IS_QUEUE_FALSE 0x00000000 267 #define NVC7C0_QMDV02_04_IS_QUEUE_TRUE 0x00000001 268 #define NVC7C0_QMDV02_04_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(137:137) 269 #define NVC7C0_QMDV02_04_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 270 #define NVC7C0_QMDV02_04_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 271 #define NVC7C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE0 MW(138:138) 272 #define NVC7C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 273 #define NVC7C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 274 #define NVC7C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE1 MW(139:139) 275 #define NVC7C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 276 #define NVC7C0_QMDV02_04_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 277 #define NVC7C0_QMDV02_04_REQUIRE_SCHEDULING_PCAS MW(140:140) 278 #define NVC7C0_QMDV02_04_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 279 #define NVC7C0_QMDV02_04_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 280 #define NVC7C0_QMDV02_04_DEPENDENT_QMD0_ENABLE MW(141:141) 281 #define NVC7C0_QMDV02_04_DEPENDENT_QMD0_ENABLE_FALSE 0x00000000 282 #define NVC7C0_QMDV02_04_DEPENDENT_QMD0_ENABLE_TRUE 0x00000001 283 #define NVC7C0_QMDV02_04_DEPENDENT_QMD0_ACTION MW(144:142) 284 #define NVC7C0_QMDV02_04_DEPENDENT_QMD0_ACTION_QMD_INCREMENT_PUT 0x00000000 285 #define NVC7C0_QMDV02_04_DEPENDENT_QMD0_ACTION_QMD_SCHEDULE 0x00000001 286 #define NVC7C0_QMDV02_04_DEPENDENT_QMD0_ACTION_QMD_INVALIDATE_COPY_SCHEDULE 0x00000003 287 #define NVC7C0_QMDV02_04_DEPENDENT_QMD0_ACTION_QMD_DECREMENT_DEPENDENCE 0x00000004 288 #define NVC7C0_QMDV02_04_DEPENDENT_QMD0_PREFETCH MW(145:145) 289 #define NVC7C0_QMDV02_04_DEPENDENT_QMD0_PREFETCH_FALSE 0x00000000 290 #define NVC7C0_QMDV02_04_DEPENDENT_QMD0_PREFETCH_TRUE 0x00000001 291 #define NVC7C0_QMDV02_04_DEPENDENT_QMD1_ENABLE MW(146:146) 292 #define NVC7C0_QMDV02_04_DEPENDENT_QMD1_ENABLE_FALSE 0x00000000 293 #define NVC7C0_QMDV02_04_DEPENDENT_QMD1_ENABLE_TRUE 0x00000001 294 #define NVC7C0_QMDV02_04_DEPENDENT_QMD1_ACTION MW(149:147) 295 #define NVC7C0_QMDV02_04_DEPENDENT_QMD1_ACTION_QMD_INCREMENT_PUT 0x00000000 296 #define NVC7C0_QMDV02_04_DEPENDENT_QMD1_ACTION_QMD_SCHEDULE 0x00000001 297 #define NVC7C0_QMDV02_04_DEPENDENT_QMD1_ACTION_QMD_INVALIDATE_COPY_SCHEDULE 0x00000003 298 #define NVC7C0_QMDV02_04_DEPENDENT_QMD1_ACTION_QMD_DECREMENT_DEPENDENCE 0x00000004 299 #define NVC7C0_QMDV02_04_DEPENDENT_QMD1_PREFETCH MW(150:150) 300 #define NVC7C0_QMDV02_04_DEPENDENT_QMD1_PREFETCH_FALSE 0x00000000 301 #define NVC7C0_QMDV02_04_DEPENDENT_QMD1_PREFETCH_TRUE 0x00000001 302 #define NVC7C0_QMDV02_04_DEPENDENCE_COUNTER MW(157:151) 303 #define NVC7C0_QMDV02_04_SELF_COPY_ON_COMPLETION MW(158:158) 304 #define NVC7C0_QMDV02_04_SELF_COPY_ON_COMPLETION_FALSE 0x00000000 305 #define NVC7C0_QMDV02_04_SELF_COPY_ON_COMPLETION_TRUE 0x00000001 306 #define NVC7C0_QMDV02_04_QMD_RESERVED_B MW(159:159) 307 #define NVC7C0_QMDV02_04_CIRCULAR_QUEUE_SIZE MW(184:160) 308 #define NVC7C0_QMDV02_04_DEMOTE_L2_EVICT_LAST MW(185:185) 309 #define NVC7C0_QMDV02_04_INVALIDATE_TEXTURE_HEADER_CACHE MW(186:186) 310 #define NVC7C0_QMDV02_04_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 311 #define NVC7C0_QMDV02_04_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 312 #define NVC7C0_QMDV02_04_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(187:187) 313 #define NVC7C0_QMDV02_04_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 314 #define NVC7C0_QMDV02_04_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 315 #define NVC7C0_QMDV02_04_INVALIDATE_TEXTURE_DATA_CACHE MW(188:188) 316 #define NVC7C0_QMDV02_04_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 317 #define NVC7C0_QMDV02_04_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 318 #define NVC7C0_QMDV02_04_INVALIDATE_SHADER_DATA_CACHE MW(189:189) 319 #define NVC7C0_QMDV02_04_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 320 #define NVC7C0_QMDV02_04_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 321 #define NVC7C0_QMDV02_04_INVALIDATE_INSTRUCTION_CACHE MW(190:190) 322 #define NVC7C0_QMDV02_04_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 323 #define NVC7C0_QMDV02_04_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 324 #define NVC7C0_QMDV02_04_INVALIDATE_SHADER_CONSTANT_CACHE MW(191:191) 325 #define NVC7C0_QMDV02_04_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 326 #define NVC7C0_QMDV02_04_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 327 #define NVC7C0_QMDV02_04_CTA_RASTER_WIDTH_RESUME MW(223:192) 328 #define NVC7C0_QMDV02_04_CTA_RASTER_HEIGHT_RESUME MW(239:224) 329 #define NVC7C0_QMDV02_04_CTA_RASTER_DEPTH_RESUME MW(255:240) 330 #define NVC7C0_QMDV02_04_PROGRAM_PREFETCH_ADDR_LOWER_SHIFTED MW(287:256) 331 #define NVC7C0_QMDV02_04_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) 332 #define NVC7C0_QMDV02_04_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) 333 #define NVC7C0_QMDV02_04_QMD_RESERVED_D MW(335:328) 334 #define NVC7C0_QMDV02_04_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) 335 #define NVC7C0_QMDV02_04_CWD_REFERENCE_COUNT_ID MW(357:352) 336 #define NVC7C0_QMDV02_04_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) 337 #define NVC7C0_QMDV02_04_RELEASE_MEMBAR_TYPE MW(366:366) 338 #define NVC7C0_QMDV02_04_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 339 #define NVC7C0_QMDV02_04_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 340 #define NVC7C0_QMDV02_04_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) 341 #define NVC7C0_QMDV02_04_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 342 #define NVC7C0_QMDV02_04_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 343 #define NVC7C0_QMDV02_04_CWD_MEMBAR_TYPE MW(369:368) 344 #define NVC7C0_QMDV02_04_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 345 #define NVC7C0_QMDV02_04_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 346 #define NVC7C0_QMDV02_04_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 347 #define NVC7C0_QMDV02_04_SEQUENTIALLY_RUN_CTAS MW(370:370) 348 #define NVC7C0_QMDV02_04_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 349 #define NVC7C0_QMDV02_04_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 350 #define NVC7C0_QMDV02_04_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) 351 #define NVC7C0_QMDV02_04_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 352 #define NVC7C0_QMDV02_04_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 353 #define NVC7C0_QMDV02_04_API_VISIBLE_CALL_LIMIT MW(378:378) 354 #define NVC7C0_QMDV02_04_API_VISIBLE_CALL_LIMIT__32 0x00000000 355 #define NVC7C0_QMDV02_04_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 356 #define NVC7C0_QMDV02_04_SAMPLER_INDEX MW(382:382) 357 #define NVC7C0_QMDV02_04_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 358 #define NVC7C0_QMDV02_04_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 359 #define NVC7C0_QMDV02_04_DISABLE_AUTO_INVALIDATE MW(383:383) 360 #define NVC7C0_QMDV02_04_DISABLE_AUTO_INVALIDATE_FALSE 0x00000000 361 #define NVC7C0_QMDV02_04_DISABLE_AUTO_INVALIDATE_TRUE 0x00000001 362 #define NVC7C0_QMDV02_04_CTA_RASTER_WIDTH MW(415:384) 363 #define NVC7C0_QMDV02_04_CTA_RASTER_HEIGHT MW(431:416) 364 #define NVC7C0_QMDV02_04_QMD_RESERVED13A MW(447:432) 365 #define NVC7C0_QMDV02_04_CTA_RASTER_DEPTH MW(463:448) 366 #define NVC7C0_QMDV02_04_QMD_RESERVED14A MW(479:464) 367 #define NVC7C0_QMDV02_04_DEPENDENT_QMD0_POINTER MW(511:480) 368 #define NVC7C0_QMDV02_04_COALESCE_WAITING_PERIOD MW(529:522) 369 #define NVC7C0_QMDV02_04_QUEUE_ENTRIES_PER_CTA_LOG2 MW(534:530) 370 #define NVC7C0_QMDV02_04_SHARED_MEMORY_SIZE MW(561:544) 371 #define NVC7C0_QMDV02_04_MIN_SM_CONFIG_SHARED_MEM_SIZE MW(568:562) 372 #define NVC7C0_QMDV02_04_MAX_SM_CONFIG_SHARED_MEM_SIZE MW(575:569) 373 #define NVC7C0_QMDV02_04_QMD_VERSION MW(579:576) 374 #define NVC7C0_QMDV02_04_QMD_MAJOR_VERSION MW(583:580) 375 #define NVC7C0_QMDV02_04_QMD_RESERVED_H MW(591:584) 376 #define NVC7C0_QMDV02_04_CTA_THREAD_DIMENSION0 MW(607:592) 377 #define NVC7C0_QMDV02_04_CTA_THREAD_DIMENSION1 MW(623:608) 378 #define NVC7C0_QMDV02_04_CTA_THREAD_DIMENSION2 MW(639:624) 379 #define NVC7C0_QMDV02_04_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) 380 #define NVC7C0_QMDV02_04_CONSTANT_BUFFER_VALID_FALSE 0x00000000 381 #define NVC7C0_QMDV02_04_CONSTANT_BUFFER_VALID_TRUE 0x00000001 382 #define NVC7C0_QMDV02_04_REGISTER_COUNT_V MW(656:648) 383 #define NVC7C0_QMDV02_04_TARGET_SM_CONFIG_SHARED_MEM_SIZE MW(663:657) 384 #define NVC7C0_QMDV02_04_FREE_CTA_SLOTS_EMPTY_SM MW(671:664) 385 #define NVC7C0_QMDV02_04_SM_DISABLE_MASK_LOWER MW(703:672) 386 #define NVC7C0_QMDV02_04_SM_DISABLE_MASK_UPPER MW(735:704) 387 #define NVC7C0_QMDV02_04_RELEASE0_ADDRESS_LOWER MW(767:736) 388 #define NVC7C0_QMDV02_04_RELEASE0_ADDRESS_UPPER MW(775:768) 389 #define NVC7C0_QMDV02_04_QMD_RESERVED_J MW(783:776) 390 #define NVC7C0_QMDV02_04_RELEASE0_REDUCTION_OP MW(790:788) 391 #define NVC7C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 392 #define NVC7C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 393 #define NVC7C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 394 #define NVC7C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 395 #define NVC7C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 396 #define NVC7C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 397 #define NVC7C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 398 #define NVC7C0_QMDV02_04_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 399 #define NVC7C0_QMDV02_04_QMD_RESERVED_K MW(791:791) 400 #define NVC7C0_QMDV02_04_RELEASE0_REDUCTION_FORMAT MW(793:792) 401 #define NVC7C0_QMDV02_04_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 402 #define NVC7C0_QMDV02_04_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 403 #define NVC7C0_QMDV02_04_RELEASE0_REDUCTION_ENABLE MW(794:794) 404 #define NVC7C0_QMDV02_04_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 405 #define NVC7C0_QMDV02_04_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 406 #define NVC7C0_QMDV02_04_RELEASE0_STRUCTURE_SIZE MW(799:799) 407 #define NVC7C0_QMDV02_04_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 408 #define NVC7C0_QMDV02_04_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 409 #define NVC7C0_QMDV02_04_RELEASE0_PAYLOAD MW(831:800) 410 #define NVC7C0_QMDV02_04_RELEASE1_ADDRESS_LOWER MW(863:832) 411 #define NVC7C0_QMDV02_04_RELEASE1_ADDRESS_UPPER MW(871:864) 412 #define NVC7C0_QMDV02_04_QMD_RESERVED_L MW(879:872) 413 #define NVC7C0_QMDV02_04_RELEASE1_REDUCTION_OP MW(886:884) 414 #define NVC7C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 415 #define NVC7C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 416 #define NVC7C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 417 #define NVC7C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 418 #define NVC7C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 419 #define NVC7C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 420 #define NVC7C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 421 #define NVC7C0_QMDV02_04_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 422 #define NVC7C0_QMDV02_04_QMD_RESERVED_M MW(887:887) 423 #define NVC7C0_QMDV02_04_RELEASE1_REDUCTION_FORMAT MW(889:888) 424 #define NVC7C0_QMDV02_04_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 425 #define NVC7C0_QMDV02_04_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 426 #define NVC7C0_QMDV02_04_RELEASE1_REDUCTION_ENABLE MW(890:890) 427 #define NVC7C0_QMDV02_04_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 428 #define NVC7C0_QMDV02_04_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 429 #define NVC7C0_QMDV02_04_RELEASE1_STRUCTURE_SIZE MW(895:895) 430 #define NVC7C0_QMDV02_04_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 431 #define NVC7C0_QMDV02_04_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 432 #define NVC7C0_QMDV02_04_RELEASE1_PAYLOAD MW(927:896) 433 #define NVC7C0_QMDV02_04_SHADER_LOCAL_MEMORY_LOW_SIZE MW(951:928) 434 #define NVC7C0_QMDV02_04_QMD_RESERVED_N MW(954:952) 435 #define NVC7C0_QMDV02_04_BARRIER_COUNT MW(959:955) 436 #define NVC7C0_QMDV02_04_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(983:960) 437 #define NVC7C0_QMDV02_04_QMD_RESERVED_G MW(991:984) 438 #define NVC7C0_QMDV02_04_PROGRAM_PREFETCH_ADDR_UPPER_SHIFTED MW(1000:992) 439 #define NVC7C0_QMDV02_04_PROGRAM_PREFETCH_SIZE MW(1009:1001) 440 #define NVC7C0_QMDV02_04_PROGRAM_PREFETCH_TYPE MW(1011:1010) 441 #define NVC7C0_QMDV02_04_PROGRAM_PREFETCH_TYPE_PREFETCH_LAUNCH 0x00000000 442 #define NVC7C0_QMDV02_04_PROGRAM_PREFETCH_TYPE_PREFTECH_POST 0x00000001 443 #define NVC7C0_QMDV02_04_QMD_RESERVED_A MW(1015:1012) 444 #define NVC7C0_QMDV02_04_SASS_VERSION MW(1023:1016) 445 #define NVC7C0_QMDV02_04_CONSTANT_BUFFER_ADDR_LOWER(i) MW((1055+(i)*64):(1024+(i)*64)) 446 #define NVC7C0_QMDV02_04_CONSTANT_BUFFER_ADDR_UPPER(i) MW((1072+(i)*64):(1056+(i)*64)) 447 #define NVC7C0_QMDV02_04_CONSTANT_BUFFER_PREFETCH_POST(i) MW((1073+(i)*64):(1073+(i)*64)) 448 #define NVC7C0_QMDV02_04_CONSTANT_BUFFER_PREFETCH_POST_FALSE 0x00000000 449 #define NVC7C0_QMDV02_04_CONSTANT_BUFFER_PREFETCH_POST_TRUE 0x00000001 450 #define NVC7C0_QMDV02_04_CONSTANT_BUFFER_INVALIDATE(i) MW((1074+(i)*64):(1074+(i)*64)) 451 #define NVC7C0_QMDV02_04_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 452 #define NVC7C0_QMDV02_04_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 453 #define NVC7C0_QMDV02_04_CONSTANT_BUFFER_SIZE_SHIFTED4(i) MW((1087+(i)*64):(1075+(i)*64)) 454 #define NVC7C0_QMDV02_04_PROGRAM_ADDRESS_LOWER MW(1567:1536) 455 #define NVC7C0_QMDV02_04_PROGRAM_ADDRESS_UPPER MW(1584:1568) 456 #define NVC7C0_QMDV02_04_QMD_RESERVED_S MW(1599:1585) 457 #define NVC7C0_QMDV02_04_HW_ONLY_INNER_GET MW(1630:1600) 458 #define NVC7C0_QMDV02_04_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1631:1631) 459 #define NVC7C0_QMDV02_04_HW_ONLY_INNER_PUT MW(1662:1632) 460 #define NVC7C0_QMDV02_04_HW_ONLY_SCG_TYPE MW(1663:1663) 461 #define NVC7C0_QMDV02_04_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1693:1664) 462 #define NVC7C0_QMDV02_04_QMD_RESERVED_Q MW(1694:1694) 463 #define NVC7C0_QMDV02_04_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1695:1695) 464 #define NVC7C0_QMDV02_04_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 465 #define NVC7C0_QMDV02_04_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 466 #define NVC7C0_QMDV02_04_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1727:1696) 467 #define NVC7C0_QMDV02_04_HW_ONLY_DEPENDENCE_COUNTER MW(1734:1728) 468 #define NVC7C0_QMDV02_04_QMD_RESERVED_I MW(1759:1735) 469 #define NVC7C0_QMDV02_04_QMD_SPARE_H MW(1791:1760) 470 #define NVC7C0_QMDV02_04_QMD_SPARE_I MW(1823:1792) 471 #define NVC7C0_QMDV02_04_QMD_SPARE_J MW(1855:1824) 472 #define NVC7C0_QMDV02_04_QMD_SPARE_K MW(1887:1856) 473 #define NVC7C0_QMDV02_04_QMD_SPARE_L MW(1919:1888) 474 #define NVC7C0_QMDV02_04_QMD_SPARE_M MW(1951:1920) 475 #define NVC7C0_QMDV02_04_QMD_SPARE_N MW(1983:1952) 476 #define NVC7C0_QMDV02_04_DEBUG_ID_UPPER MW(2015:1984) 477 #define NVC7C0_QMDV02_04_DEBUG_ID_LOWER MW(2047:2016) 478 479 480 /* 481 ** Queue Meta Data, Version 03_00 482 */ 483 484 #define NVC7C0_QMDV03_00_OUTER_PUT MW(30:0) 485 #define NVC7C0_QMDV03_00_OUTER_OVERFLOW MW(31:31) 486 #define NVC7C0_QMDV03_00_OUTER_GET MW(62:32) 487 #define NVC7C0_QMDV03_00_OUTER_STICKY_OVERFLOW MW(63:63) 488 #define NVC7C0_QMDV03_00_INNER_GET MW(94:64) 489 #define NVC7C0_QMDV03_00_INNER_OVERFLOW MW(95:95) 490 #define NVC7C0_QMDV03_00_INNER_PUT MW(126:96) 491 #define NVC7C0_QMDV03_00_INNER_STICKY_OVERFLOW MW(127:127) 492 #define NVC7C0_QMDV03_00_QMD_GROUP_ID MW(133:128) 493 #define NVC7C0_QMDV03_00_SM_GLOBAL_CACHING_ENABLE MW(134:134) 494 #define NVC7C0_QMDV03_00_RUN_CTA_IN_ONE_SM_PARTITION MW(135:135) 495 #define NVC7C0_QMDV03_00_RUN_CTA_IN_ONE_SM_PARTITION_FALSE 0x00000000 496 #define NVC7C0_QMDV03_00_RUN_CTA_IN_ONE_SM_PARTITION_TRUE 0x00000001 497 #define NVC7C0_QMDV03_00_IS_QUEUE MW(136:136) 498 #define NVC7C0_QMDV03_00_IS_QUEUE_FALSE 0x00000000 499 #define NVC7C0_QMDV03_00_IS_QUEUE_TRUE 0x00000001 500 #define NVC7C0_QMDV03_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(137:137) 501 #define NVC7C0_QMDV03_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 502 #define NVC7C0_QMDV03_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 503 #define NVC7C0_QMDV03_00_QMD_RESERVED04A MW(139:138) 504 #define NVC7C0_QMDV03_00_REQUIRE_SCHEDULING_PCAS MW(140:140) 505 #define NVC7C0_QMDV03_00_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 506 #define NVC7C0_QMDV03_00_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 507 #define NVC7C0_QMDV03_00_QMD_RESERVED04B MW(141:141) 508 #define NVC7C0_QMDV03_00_DEPENDENCE_COUNTER MW(157:142) 509 #define NVC7C0_QMDV03_00_SELF_COPY_ON_COMPLETION MW(158:158) 510 #define NVC7C0_QMDV03_00_SELF_COPY_ON_COMPLETION_FALSE 0x00000000 511 #define NVC7C0_QMDV03_00_SELF_COPY_ON_COMPLETION_TRUE 0x00000001 512 #define NVC7C0_QMDV03_00_QMD_RESERVED04C MW(159:159) 513 #define NVC7C0_QMDV03_00_CIRCULAR_QUEUE_SIZE MW(184:160) 514 #define NVC7C0_QMDV03_00_DEMOTE_L2_EVICT_LAST MW(185:185) 515 #define NVC7C0_QMDV03_00_INVALIDATE_TEXTURE_HEADER_CACHE MW(186:186) 516 #define NVC7C0_QMDV03_00_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 517 #define NVC7C0_QMDV03_00_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 518 #define NVC7C0_QMDV03_00_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(187:187) 519 #define NVC7C0_QMDV03_00_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 520 #define NVC7C0_QMDV03_00_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 521 #define NVC7C0_QMDV03_00_INVALIDATE_TEXTURE_DATA_CACHE MW(188:188) 522 #define NVC7C0_QMDV03_00_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 523 #define NVC7C0_QMDV03_00_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 524 #define NVC7C0_QMDV03_00_INVALIDATE_SHADER_DATA_CACHE MW(189:189) 525 #define NVC7C0_QMDV03_00_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 526 #define NVC7C0_QMDV03_00_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 527 #define NVC7C0_QMDV03_00_INVALIDATE_INSTRUCTION_CACHE MW(190:190) 528 #define NVC7C0_QMDV03_00_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 529 #define NVC7C0_QMDV03_00_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 530 #define NVC7C0_QMDV03_00_INVALIDATE_SHADER_CONSTANT_CACHE MW(191:191) 531 #define NVC7C0_QMDV03_00_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 532 #define NVC7C0_QMDV03_00_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 533 #define NVC7C0_QMDV03_00_CTA_RASTER_WIDTH_RESUME MW(223:192) 534 #define NVC7C0_QMDV03_00_CTA_RASTER_HEIGHT_RESUME MW(239:224) 535 #define NVC7C0_QMDV03_00_CTA_RASTER_DEPTH_RESUME MW(255:240) 536 #define NVC7C0_QMDV03_00_PROGRAM_PREFETCH_ADDR_LOWER_SHIFTED MW(287:256) 537 #define NVC7C0_QMDV03_00_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) 538 #define NVC7C0_QMDV03_00_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) 539 #define NVC7C0_QMDV03_00_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) 540 #define NVC7C0_QMDV03_00_CWD_REFERENCE_COUNT_ID MW(357:352) 541 #define NVC7C0_QMDV03_00_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) 542 #define NVC7C0_QMDV03_00_QMD_RESERVED11A MW(366:366) 543 #define NVC7C0_QMDV03_00_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) 544 #define NVC7C0_QMDV03_00_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 545 #define NVC7C0_QMDV03_00_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 546 #define NVC7C0_QMDV03_00_CWD_MEMBAR_TYPE MW(369:368) 547 #define NVC7C0_QMDV03_00_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 548 #define NVC7C0_QMDV03_00_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 549 #define NVC7C0_QMDV03_00_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 550 #define NVC7C0_QMDV03_00_SEQUENTIALLY_RUN_CTAS MW(370:370) 551 #define NVC7C0_QMDV03_00_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 552 #define NVC7C0_QMDV03_00_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 553 #define NVC7C0_QMDV03_00_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) 554 #define NVC7C0_QMDV03_00_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 555 #define NVC7C0_QMDV03_00_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 556 #define NVC7C0_QMDV03_00_QMD_RESERVED11B MW(377:372) 557 #define NVC7C0_QMDV03_00_API_VISIBLE_CALL_LIMIT MW(378:378) 558 #define NVC7C0_QMDV03_00_API_VISIBLE_CALL_LIMIT__32 0x00000000 559 #define NVC7C0_QMDV03_00_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 560 #define NVC7C0_QMDV03_00_QMD_RESERVED11C MW(381:379) 561 #define NVC7C0_QMDV03_00_SAMPLER_INDEX MW(382:382) 562 #define NVC7C0_QMDV03_00_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 563 #define NVC7C0_QMDV03_00_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 564 #define NVC7C0_QMDV03_00_DISABLE_AUTO_INVALIDATE MW(383:383) 565 #define NVC7C0_QMDV03_00_DISABLE_AUTO_INVALIDATE_FALSE 0x00000000 566 #define NVC7C0_QMDV03_00_DISABLE_AUTO_INVALIDATE_TRUE 0x00000001 567 #define NVC7C0_QMDV03_00_CTA_RASTER_WIDTH MW(415:384) 568 #define NVC7C0_QMDV03_00_CTA_RASTER_HEIGHT MW(431:416) 569 #define NVC7C0_QMDV03_00_CTA_RASTER_DEPTH MW(463:448) 570 #define NVC7C0_QMDV03_00_DEPENDENT_QMD0_POINTER MW(511:480) 571 #define NVC7C0_QMDV03_00_DEPENDENT_QMD0_ENABLE MW(512:512) 572 #define NVC7C0_QMDV03_00_DEPENDENT_QMD0_ENABLE_FALSE 0x00000000 573 #define NVC7C0_QMDV03_00_DEPENDENT_QMD0_ENABLE_TRUE 0x00000001 574 #define NVC7C0_QMDV03_00_DEPENDENT_QMD0_ACTION MW(515:513) 575 #define NVC7C0_QMDV03_00_DEPENDENT_QMD0_ACTION_QMD_INCREMENT_PUT 0x00000000 576 #define NVC7C0_QMDV03_00_DEPENDENT_QMD0_ACTION_QMD_SCHEDULE 0x00000001 577 #define NVC7C0_QMDV03_00_DEPENDENT_QMD0_ACTION_QMD_INVALIDATE_COPY_SCHEDULE 0x00000003 578 #define NVC7C0_QMDV03_00_DEPENDENT_QMD0_ACTION_QMD_DECREMENT_DEPENDENCE 0x00000004 579 #define NVC7C0_QMDV03_00_DEPENDENT_QMD0_PREFETCH MW(516:516) 580 #define NVC7C0_QMDV03_00_DEPENDENT_QMD0_PREFETCH_FALSE 0x00000000 581 #define NVC7C0_QMDV03_00_DEPENDENT_QMD0_PREFETCH_TRUE 0x00000001 582 #define NVC7C0_QMDV03_00_DEPENDENT_QMD1_ENABLE MW(517:517) 583 #define NVC7C0_QMDV03_00_DEPENDENT_QMD1_ENABLE_FALSE 0x00000000 584 #define NVC7C0_QMDV03_00_DEPENDENT_QMD1_ENABLE_TRUE 0x00000001 585 #define NVC7C0_QMDV03_00_DEPENDENT_QMD1_ACTION MW(520:518) 586 #define NVC7C0_QMDV03_00_DEPENDENT_QMD1_ACTION_QMD_INCREMENT_PUT 0x00000000 587 #define NVC7C0_QMDV03_00_DEPENDENT_QMD1_ACTION_QMD_SCHEDULE 0x00000001 588 #define NVC7C0_QMDV03_00_DEPENDENT_QMD1_ACTION_QMD_INVALIDATE_COPY_SCHEDULE 0x00000003 589 #define NVC7C0_QMDV03_00_DEPENDENT_QMD1_ACTION_QMD_DECREMENT_DEPENDENCE 0x00000004 590 #define NVC7C0_QMDV03_00_DEPENDENT_QMD1_PREFETCH MW(521:521) 591 #define NVC7C0_QMDV03_00_DEPENDENT_QMD1_PREFETCH_FALSE 0x00000000 592 #define NVC7C0_QMDV03_00_DEPENDENT_QMD1_PREFETCH_TRUE 0x00000001 593 #define NVC7C0_QMDV03_00_COALESCE_WAITING_PERIOD MW(529:522) 594 #define NVC7C0_QMDV03_00_QUEUE_ENTRIES_PER_CTA_LOG2 MW(534:530) 595 #define NVC7C0_QMDV03_00_OCCUPANCY_THRESHOLD_SHARED_MEM MW(542:535) 596 #define NVC7C0_QMDV03_00_CTA_LAUNCH_QUEUE MW(543:543) 597 #define NVC7C0_QMDV03_00_SHARED_MEMORY_SIZE MW(561:544) 598 #define NVC7C0_QMDV03_00_MIN_SM_CONFIG_SHARED_MEM_SIZE MW(567:562) 599 #define NVC7C0_QMDV03_00_QMD_RESERVED17A MW(568:568) 600 #define NVC7C0_QMDV03_00_MAX_SM_CONFIG_SHARED_MEM_SIZE MW(574:569) 601 #define NVC7C0_QMDV03_00_QMD_RESERVED17B MW(575:575) 602 #define NVC7C0_QMDV03_00_QMD_VERSION MW(579:576) 603 #define NVC7C0_QMDV03_00_QMD_MAJOR_VERSION MW(583:580) 604 #define NVC7C0_QMDV03_00_OCCUPANCY_MAX_SHARED_MEM MW(591:584) 605 #define NVC7C0_QMDV03_00_CTA_THREAD_DIMENSION0 MW(607:592) 606 #define NVC7C0_QMDV03_00_CTA_THREAD_DIMENSION1 MW(623:608) 607 #define NVC7C0_QMDV03_00_CTA_THREAD_DIMENSION2 MW(639:624) 608 #define NVC7C0_QMDV03_00_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) 609 #define NVC7C0_QMDV03_00_CONSTANT_BUFFER_VALID_FALSE 0x00000000 610 #define NVC7C0_QMDV03_00_CONSTANT_BUFFER_VALID_TRUE 0x00000001 611 #define NVC7C0_QMDV03_00_REGISTER_COUNT_V MW(656:648) 612 #define NVC7C0_QMDV03_00_TARGET_SM_CONFIG_SHARED_MEM_SIZE MW(662:657) 613 #define NVC7C0_QMDV03_00_SHARED_ALLOCATION_ENABLE MW(663:663) 614 #define NVC7C0_QMDV03_00_SHARED_ALLOCATION_ENABLE_FALSE 0x00000000 615 #define NVC7C0_QMDV03_00_SHARED_ALLOCATION_ENABLE_TRUE 0x00000001 616 #define NVC7C0_QMDV03_00_FREE_CTA_SLOTS_EMPTY_SM MW(671:664) 617 #define NVC7C0_QMDV03_00_SM_DISABLE_MASK_LOWER MW(703:672) 618 #define NVC7C0_QMDV03_00_SM_DISABLE_MASK_UPPER MW(735:704) 619 #define NVC7C0_QMDV03_00_SHADER_LOCAL_MEMORY_LOW_SIZE MW(759:736) 620 #define NVC7C0_QMDV03_00_BARRIER_COUNT MW(767:763) 621 #define NVC7C0_QMDV03_00_RELEASE0_ADDRESS_LOWER MW(799:768) 622 #define NVC7C0_QMDV03_00_RELEASE0_ADDRESS_UPPER MW(807:800) 623 #define NVC7C0_QMDV03_00_SEMAPHORE_RESERVED25A MW(818:808) 624 #define NVC7C0_QMDV03_00_RELEASE0_MEMBAR_TYPE MW(819:819) 625 #define NVC7C0_QMDV03_00_RELEASE0_MEMBAR_TYPE_FE_NONE 0x00000000 626 #define NVC7C0_QMDV03_00_RELEASE0_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 627 #define NVC7C0_QMDV03_00_RELEASE0_REDUCTION_OP MW(822:820) 628 #define NVC7C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 629 #define NVC7C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 630 #define NVC7C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 631 #define NVC7C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 632 #define NVC7C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 633 #define NVC7C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 634 #define NVC7C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 635 #define NVC7C0_QMDV03_00_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 636 #define NVC7C0_QMDV03_00_RELEASE0_ENABLE MW(823:823) 637 #define NVC7C0_QMDV03_00_RELEASE0_ENABLE_FALSE 0x00000000 638 #define NVC7C0_QMDV03_00_RELEASE0_ENABLE_TRUE 0x00000001 639 #define NVC7C0_QMDV03_00_RELEASE0_REDUCTION_FORMAT MW(825:824) 640 #define NVC7C0_QMDV03_00_RELEASE0_REDUCTION_FORMAT_UNSIGNED 0x00000000 641 #define NVC7C0_QMDV03_00_RELEASE0_REDUCTION_FORMAT_SIGNED 0x00000001 642 #define NVC7C0_QMDV03_00_RELEASE0_REDUCTION_ENABLE MW(826:826) 643 #define NVC7C0_QMDV03_00_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 644 #define NVC7C0_QMDV03_00_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 645 #define NVC7C0_QMDV03_00_RELEASE0_TRAP_TYPE MW(828:827) 646 #define NVC7C0_QMDV03_00_RELEASE0_TRAP_TYPE_TRAP_NONE 0x00000000 647 #define NVC7C0_QMDV03_00_RELEASE0_TRAP_TYPE_TRAP_UNCONDITIONAL 0x00000001 648 #define NVC7C0_QMDV03_00_RELEASE0_TRAP_TYPE_TRAP_CONDITIONAL 0x00000002 649 #define NVC7C0_QMDV03_00_RELEASE0_TRAP_TYPE_TRAP_CONDITIONAL_EXT 0x00000003 650 #define NVC7C0_QMDV03_00_RELEASE0_PAYLOAD64B MW(829:829) 651 #define NVC7C0_QMDV03_00_RELEASE0_PAYLOAD64B_FALSE 0x00000000 652 #define NVC7C0_QMDV03_00_RELEASE0_PAYLOAD64B_TRUE 0x00000001 653 #define NVC7C0_QMDV03_00_RELEASE0_STRUCTURE_SIZE MW(831:830) 654 #define NVC7C0_QMDV03_00_RELEASE0_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS 0x00000000 655 #define NVC7C0_QMDV03_00_RELEASE0_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD 0x00000001 656 #define NVC7C0_QMDV03_00_RELEASE0_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS 0x00000002 657 #define NVC7C0_QMDV03_00_RELEASE0_PAYLOAD_LOWER MW(863:832) 658 #define NVC7C0_QMDV03_00_RELEASE0_PAYLOAD_UPPER MW(895:864) 659 #define NVC7C0_QMDV03_00_RELEASE1_ADDRESS_LOWER MW(927:896) 660 #define NVC7C0_QMDV03_00_RELEASE1_ADDRESS_UPPER MW(935:928) 661 #define NVC7C0_QMDV03_00_SEMAPHORE_RESERVED29A MW(946:936) 662 #define NVC7C0_QMDV03_00_RELEASE1_MEMBAR_TYPE MW(947:947) 663 #define NVC7C0_QMDV03_00_RELEASE1_MEMBAR_TYPE_FE_NONE 0x00000000 664 #define NVC7C0_QMDV03_00_RELEASE1_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 665 #define NVC7C0_QMDV03_00_RELEASE1_REDUCTION_OP MW(950:948) 666 #define NVC7C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 667 #define NVC7C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 668 #define NVC7C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 669 #define NVC7C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 670 #define NVC7C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 671 #define NVC7C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 672 #define NVC7C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 673 #define NVC7C0_QMDV03_00_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 674 #define NVC7C0_QMDV03_00_RELEASE1_ENABLE MW(951:951) 675 #define NVC7C0_QMDV03_00_RELEASE1_ENABLE_FALSE 0x00000000 676 #define NVC7C0_QMDV03_00_RELEASE1_ENABLE_TRUE 0x00000001 677 #define NVC7C0_QMDV03_00_RELEASE1_REDUCTION_FORMAT MW(953:952) 678 #define NVC7C0_QMDV03_00_RELEASE1_REDUCTION_FORMAT_UNSIGNED 0x00000000 679 #define NVC7C0_QMDV03_00_RELEASE1_REDUCTION_FORMAT_SIGNED 0x00000001 680 #define NVC7C0_QMDV03_00_RELEASE1_REDUCTION_ENABLE MW(954:954) 681 #define NVC7C0_QMDV03_00_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 682 #define NVC7C0_QMDV03_00_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 683 #define NVC7C0_QMDV03_00_RELEASE1_TRAP_TYPE MW(956:955) 684 #define NVC7C0_QMDV03_00_RELEASE1_TRAP_TYPE_TRAP_NONE 0x00000000 685 #define NVC7C0_QMDV03_00_RELEASE1_TRAP_TYPE_TRAP_UNCONDITIONAL 0x00000001 686 #define NVC7C0_QMDV03_00_RELEASE1_TRAP_TYPE_TRAP_CONDITIONAL 0x00000002 687 #define NVC7C0_QMDV03_00_RELEASE1_TRAP_TYPE_TRAP_CONDITIONAL_EXT 0x00000003 688 #define NVC7C0_QMDV03_00_RELEASE1_PAYLOAD64B MW(957:957) 689 #define NVC7C0_QMDV03_00_RELEASE1_PAYLOAD64B_FALSE 0x00000000 690 #define NVC7C0_QMDV03_00_RELEASE1_PAYLOAD64B_TRUE 0x00000001 691 #define NVC7C0_QMDV03_00_RELEASE1_STRUCTURE_SIZE MW(959:958) 692 #define NVC7C0_QMDV03_00_RELEASE1_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS 0x00000000 693 #define NVC7C0_QMDV03_00_RELEASE1_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD 0x00000001 694 #define NVC7C0_QMDV03_00_RELEASE1_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS 0x00000002 695 #define NVC7C0_QMDV03_00_RELEASE1_PAYLOAD_LOWER MW(991:960) 696 #define NVC7C0_QMDV03_00_RELEASE1_PAYLOAD_UPPER MW(1023:992) 697 #define NVC7C0_QMDV03_00_CONSTANT_BUFFER_ADDR_LOWER(i) MW((1055+(i)*64):(1024+(i)*64)) 698 #define NVC7C0_QMDV03_00_CONSTANT_BUFFER_ADDR_UPPER(i) MW((1072+(i)*64):(1056+(i)*64)) 699 #define NVC7C0_QMDV03_00_CONSTANT_BUFFER_PREFETCH_POST(i) MW((1073+(i)*64):(1073+(i)*64)) 700 #define NVC7C0_QMDV03_00_CONSTANT_BUFFER_PREFETCH_POST_FALSE 0x00000000 701 #define NVC7C0_QMDV03_00_CONSTANT_BUFFER_PREFETCH_POST_TRUE 0x00000001 702 #define NVC7C0_QMDV03_00_CONSTANT_BUFFER_INVALIDATE(i) MW((1074+(i)*64):(1074+(i)*64)) 703 #define NVC7C0_QMDV03_00_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 704 #define NVC7C0_QMDV03_00_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 705 #define NVC7C0_QMDV03_00_CONSTANT_BUFFER_SIZE_SHIFTED4(i) MW((1087+(i)*64):(1075+(i)*64)) 706 #define NVC7C0_QMDV03_00_PROGRAM_ADDRESS_LOWER MW(1567:1536) 707 #define NVC7C0_QMDV03_00_PROGRAM_ADDRESS_UPPER MW(1584:1568) 708 #define NVC7C0_QMDV03_00_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1623:1600) 709 #define NVC7C0_QMDV03_00_PROGRAM_PREFETCH_ADDR_UPPER_SHIFTED MW(1640:1632) 710 #define NVC7C0_QMDV03_00_PROGRAM_PREFETCH_SIZE MW(1649:1641) 711 #define NVC7C0_QMDV03_00_PROGRAM_PREFETCH_TYPE MW(1651:1650) 712 #define NVC7C0_QMDV03_00_PROGRAM_PREFETCH_TYPE_PREFETCH_LAUNCH 0x00000000 713 #define NVC7C0_QMDV03_00_PROGRAM_PREFETCH_TYPE_PREFTECH_POST 0x00000001 714 #define NVC7C0_QMDV03_00_SASS_VERSION MW(1663:1656) 715 #define NVC7C0_QMDV03_00_RELEASE2_ADDRESS_LOWER MW(1695:1664) 716 #define NVC7C0_QMDV03_00_RELEASE2_ADDRESS_UPPER MW(1703:1696) 717 #define NVC7C0_QMDV03_00_SEMAPHORE_RESERVED53A MW(1714:1704) 718 #define NVC7C0_QMDV03_00_RELEASE2_MEMBAR_TYPE MW(1715:1715) 719 #define NVC7C0_QMDV03_00_RELEASE2_MEMBAR_TYPE_FE_NONE 0x00000000 720 #define NVC7C0_QMDV03_00_RELEASE2_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 721 #define NVC7C0_QMDV03_00_RELEASE2_REDUCTION_OP MW(1718:1716) 722 #define NVC7C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_ADD 0x00000000 723 #define NVC7C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_MIN 0x00000001 724 #define NVC7C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_MAX 0x00000002 725 #define NVC7C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_INC 0x00000003 726 #define NVC7C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_DEC 0x00000004 727 #define NVC7C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_AND 0x00000005 728 #define NVC7C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_OR 0x00000006 729 #define NVC7C0_QMDV03_00_RELEASE2_REDUCTION_OP_RED_XOR 0x00000007 730 #define NVC7C0_QMDV03_00_RELEASE2_ENABLE MW(1719:1719) 731 #define NVC7C0_QMDV03_00_RELEASE2_ENABLE_FALSE 0x00000000 732 #define NVC7C0_QMDV03_00_RELEASE2_ENABLE_TRUE 0x00000001 733 #define NVC7C0_QMDV03_00_RELEASE2_REDUCTION_FORMAT MW(1721:1720) 734 #define NVC7C0_QMDV03_00_RELEASE2_REDUCTION_FORMAT_UNSIGNED 0x00000000 735 #define NVC7C0_QMDV03_00_RELEASE2_REDUCTION_FORMAT_SIGNED 0x00000001 736 #define NVC7C0_QMDV03_00_RELEASE2_REDUCTION_ENABLE MW(1722:1722) 737 #define NVC7C0_QMDV03_00_RELEASE2_REDUCTION_ENABLE_FALSE 0x00000000 738 #define NVC7C0_QMDV03_00_RELEASE2_REDUCTION_ENABLE_TRUE 0x00000001 739 #define NVC7C0_QMDV03_00_RELEASE2_TRAP_TYPE MW(1724:1723) 740 #define NVC7C0_QMDV03_00_RELEASE2_TRAP_TYPE_TRAP_NONE 0x00000000 741 #define NVC7C0_QMDV03_00_RELEASE2_TRAP_TYPE_TRAP_UNCONDITIONAL 0x00000001 742 #define NVC7C0_QMDV03_00_RELEASE2_TRAP_TYPE_TRAP_CONDITIONAL 0x00000002 743 #define NVC7C0_QMDV03_00_RELEASE2_TRAP_TYPE_TRAP_CONDITIONAL_EXT 0x00000003 744 #define NVC7C0_QMDV03_00_RELEASE2_PAYLOAD64B MW(1725:1725) 745 #define NVC7C0_QMDV03_00_RELEASE2_PAYLOAD64B_FALSE 0x00000000 746 #define NVC7C0_QMDV03_00_RELEASE2_PAYLOAD64B_TRUE 0x00000001 747 #define NVC7C0_QMDV03_00_RELEASE2_STRUCTURE_SIZE MW(1727:1726) 748 #define NVC7C0_QMDV03_00_RELEASE2_STRUCTURE_SIZE_SEMAPHORE_FOUR_WORDS 0x00000000 749 #define NVC7C0_QMDV03_00_RELEASE2_STRUCTURE_SIZE_SEMAPHORE_ONE_WORD 0x00000001 750 #define NVC7C0_QMDV03_00_RELEASE2_STRUCTURE_SIZE_SEMAPHORE_TWO_WORDS 0x00000002 751 #define NVC7C0_QMDV03_00_RELEASE2_PAYLOAD_LOWER MW(1759:1728) 752 #define NVC7C0_QMDV03_00_RELEASE2_PAYLOAD_UPPER MW(1791:1760) 753 #define NVC7C0_QMDV03_00_OCCUPANCY_THRESHOLD_WARP MW(1799:1792) 754 #define NVC7C0_QMDV03_00_OCCUPANCY_MAX_WARP MW(1807:1800) 755 #define NVC7C0_QMDV03_00_OCCUPANCY_THRESHOLD_REGISTER MW(1815:1808) 756 #define NVC7C0_QMDV03_00_OCCUPANCY_MAX_REGISTER MW(1823:1816) 757 #define NVC7C0_QMDV03_00_HW_ONLY_INNER_GET MW(1854:1824) 758 #define NVC7C0_QMDV03_00_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1855:1855) 759 #define NVC7C0_QMDV03_00_HW_ONLY_INNER_PUT MW(1886:1856) 760 #define NVC7C0_QMDV03_00_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1917:1888) 761 #define NVC7C0_QMDV03_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1919:1919) 762 #define NVC7C0_QMDV03_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 763 #define NVC7C0_QMDV03_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 764 #define NVC7C0_QMDV03_00_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1951:1920) 765 #define NVC7C0_QMDV03_00_HW_ONLY_DEPENDENCE_COUNTER MW(1967:1952) 766 #define NVC7C0_QMDV03_00_DEBUG_ID_UPPER MW(2015:1984) 767 #define NVC7C0_QMDV03_00_DEBUG_ID_LOWER MW(2047:2016) 768 769 770 771 #endif // #ifndef __CLC7C0QMD_H__ 772