1 /*
2 * Copyright (C) 2021 Collabora, Ltd.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include "compiler/nir/nir_builder.h"
25 #include "pan_ir.h"
26
27 /* Sample positions are supplied in a packed 8:8 fixed-point vec2 format in GPU
28 * memory indexed by the sample. We lower in NIR to take advantage of possible
29 * ALU optimizations at the end. This is convenient for Bifrost, since the
30 * sample positions are passed in this format and it saves the driver from any
31 * system value handling. For Midgard, it's a bit suboptimal (fp16 positions
32 * could be supplied directly), but this lets us unify the implementation, and
33 * it's a pretty trivial difference */
34
35 static bool
pan_lower_sample_pos_impl(struct nir_builder * b,nir_intrinsic_instr * intr,UNUSED void * data)36 pan_lower_sample_pos_impl(struct nir_builder *b, nir_intrinsic_instr *intr,
37 UNUSED void *data)
38 {
39 if (intr->intrinsic != nir_intrinsic_load_sample_pos &&
40 intr->intrinsic != nir_intrinsic_load_sample_pos_or_center)
41 return false;
42
43 b->cursor = nir_before_instr(&intr->instr);
44
45 if (!b->shader->info.fs.uses_sample_shading) {
46 assert(intr->intrinsic == nir_intrinsic_load_sample_pos_or_center);
47
48 /* When sample shading is disabled, lower to a constant (0.5,0.5).
49 *
50 * In Vulkan, sample shading state is always known statically. In
51 * OpenGL, it's possible to enable sample shading dynamically. The only
52 * thing that currently emits load_sample_pos_or_center is
53 * nir_lower_wpos_center, which is only used for Vulkan, so this is
54 * okay.
55 *
56 * In the case where multisample is disabled but sample shading is
57 * enabled , we would skip this branch and load (0.5,0.5) from index 0
58 * in the sample pos table.
59 *
60 * In theory we should get r61[13:23]=32 on Bifrost when sample shading
61 * is disabled, and can load (0.5,0.5) from sample_positions[32] with
62 * the same code we use for loading normal sample positions. This would
63 * allow dynamic sample shading state, but would require passing the raw
64 * sample ID register through to NIR. */
65 nir_def_replace(&intr->def, nir_imm_vec2(b, 0.5, 0.5));
66
67 return true;
68 }
69
70 /* Elements are 4 bytes */
71 nir_def *addr =
72 nir_iadd(b, nir_load_sample_positions_pan(b),
73 nir_u2u64(b, nir_imul_imm(b, nir_load_sample_id(b), 4)));
74
75 /* Decode 8:8 fixed-point */
76 nir_def *raw = nir_load_global(b, addr, 2, 2, 16);
77 nir_def *decoded = nir_fmul_imm(b, nir_i2f16(b, raw), 1.0 / 256.0);
78
79 /* Make NIR validator happy */
80 if (decoded->bit_size != intr->def.bit_size)
81 decoded = nir_f2fN(b, decoded, intr->def.bit_size);
82
83 nir_def_rewrite_uses(&intr->def, decoded);
84 return true;
85 }
86
87 bool
pan_lower_sample_pos(nir_shader * shader)88 pan_lower_sample_pos(nir_shader *shader)
89 {
90 if (shader->info.stage != MESA_SHADER_FRAGMENT)
91 return false;
92
93 return nir_shader_intrinsics_pass(
94 shader, pan_lower_sample_pos_impl,
95 nir_metadata_control_flow, NULL);
96 }
97