1 use super::{InlineAsmArch, InlineAsmType};
2 use crate::spec::{RelocModel, Target};
3 use rustc_data_structures::fx::FxIndexSet;
4 use rustc_macros::HashStable_Generic;
5 use rustc_span::{sym, Symbol};
6 use std::fmt;
7
8 def_reg_class! {
9 RiscV RiscVInlineAsmRegClass {
10 reg,
11 freg,
12 vreg,
13 }
14 }
15
16 impl RiscVInlineAsmRegClass {
valid_modifiers(self, _arch: super::InlineAsmArch) -> &'static [char]17 pub fn valid_modifiers(self, _arch: super::InlineAsmArch) -> &'static [char] {
18 &[]
19 }
20
suggest_class(self, _arch: InlineAsmArch, _ty: InlineAsmType) -> Option<Self>21 pub fn suggest_class(self, _arch: InlineAsmArch, _ty: InlineAsmType) -> Option<Self> {
22 None
23 }
24
suggest_modifier( self, _arch: InlineAsmArch, _ty: InlineAsmType, ) -> Option<(char, &'static str)>25 pub fn suggest_modifier(
26 self,
27 _arch: InlineAsmArch,
28 _ty: InlineAsmType,
29 ) -> Option<(char, &'static str)> {
30 None
31 }
32
default_modifier(self, _arch: InlineAsmArch) -> Option<(char, &'static str)>33 pub fn default_modifier(self, _arch: InlineAsmArch) -> Option<(char, &'static str)> {
34 None
35 }
36
supported_types( self, arch: InlineAsmArch, ) -> &'static [(InlineAsmType, Option<Symbol>)]37 pub fn supported_types(
38 self,
39 arch: InlineAsmArch,
40 ) -> &'static [(InlineAsmType, Option<Symbol>)] {
41 match self {
42 Self::reg => {
43 if arch == InlineAsmArch::RiscV64 {
44 types! { _: I8, I16, I32, I64, F32, F64; }
45 } else {
46 types! { _: I8, I16, I32, F32; }
47 }
48 }
49 Self::freg => types! { f: F32; d: F64; },
50 Self::vreg => &[],
51 }
52 }
53 }
54
not_e( _arch: InlineAsmArch, _reloc_model: RelocModel, target_features: &FxIndexSet<Symbol>, _target: &Target, _is_clobber: bool, ) -> Result<(), &'static str>55 fn not_e(
56 _arch: InlineAsmArch,
57 _reloc_model: RelocModel,
58 target_features: &FxIndexSet<Symbol>,
59 _target: &Target,
60 _is_clobber: bool,
61 ) -> Result<(), &'static str> {
62 if target_features.contains(&sym::e) {
63 Err("register can't be used with the `e` target feature")
64 } else {
65 Ok(())
66 }
67 }
68
69 def_regs! {
70 RiscV RiscVInlineAsmReg RiscVInlineAsmRegClass {
71 x1: reg = ["x1", "ra"],
72 x5: reg = ["x5", "t0"],
73 x6: reg = ["x6", "t1"],
74 x7: reg = ["x7", "t2"],
75 x10: reg = ["x10", "a0"],
76 x11: reg = ["x11", "a1"],
77 x12: reg = ["x12", "a2"],
78 x13: reg = ["x13", "a3"],
79 x14: reg = ["x14", "a4"],
80 x15: reg = ["x15", "a5"],
81 x16: reg = ["x16", "a6"] % not_e,
82 x17: reg = ["x17", "a7"] % not_e,
83 x18: reg = ["x18", "s2"] % not_e,
84 x19: reg = ["x19", "s3"] % not_e,
85 x20: reg = ["x20", "s4"] % not_e,
86 x21: reg = ["x21", "s5"] % not_e,
87 x22: reg = ["x22", "s6"] % not_e,
88 x23: reg = ["x23", "s7"] % not_e,
89 x24: reg = ["x24", "s8"] % not_e,
90 x25: reg = ["x25", "s9"] % not_e,
91 x26: reg = ["x26", "s10"] % not_e,
92 x27: reg = ["x27", "s11"] % not_e,
93 x28: reg = ["x28", "t3"] % not_e,
94 x29: reg = ["x29", "t4"] % not_e,
95 x30: reg = ["x30", "t5"] % not_e,
96 x31: reg = ["x31", "t6"] % not_e,
97 f0: freg = ["f0", "ft0"],
98 f1: freg = ["f1", "ft1"],
99 f2: freg = ["f2", "ft2"],
100 f3: freg = ["f3", "ft3"],
101 f4: freg = ["f4", "ft4"],
102 f5: freg = ["f5", "ft5"],
103 f6: freg = ["f6", "ft6"],
104 f7: freg = ["f7", "ft7"],
105 f8: freg = ["f8", "fs0"],
106 f9: freg = ["f9", "fs1"],
107 f10: freg = ["f10", "fa0"],
108 f11: freg = ["f11", "fa1"],
109 f12: freg = ["f12", "fa2"],
110 f13: freg = ["f13", "fa3"],
111 f14: freg = ["f14", "fa4"],
112 f15: freg = ["f15", "fa5"],
113 f16: freg = ["f16", "fa6"],
114 f17: freg = ["f17", "fa7"],
115 f18: freg = ["f18", "fs2"],
116 f19: freg = ["f19", "fs3"],
117 f20: freg = ["f20", "fs4"],
118 f21: freg = ["f21", "fs5"],
119 f22: freg = ["f22", "fs6"],
120 f23: freg = ["f23", "fs7"],
121 f24: freg = ["f24", "fs8"],
122 f25: freg = ["f25", "fs9"],
123 f26: freg = ["f26", "fs10"],
124 f27: freg = ["f27", "fs11"],
125 f28: freg = ["f28", "ft8"],
126 f29: freg = ["f29", "ft9"],
127 f30: freg = ["f30", "ft10"],
128 f31: freg = ["f31", "ft11"],
129 v0: vreg = ["v0"],
130 v1: vreg = ["v1"],
131 v2: vreg = ["v2"],
132 v3: vreg = ["v3"],
133 v4: vreg = ["v4"],
134 v5: vreg = ["v5"],
135 v6: vreg = ["v6"],
136 v7: vreg = ["v7"],
137 v8: vreg = ["v8"],
138 v9: vreg = ["v9"],
139 v10: vreg = ["v10"],
140 v11: vreg = ["v11"],
141 v12: vreg = ["v12"],
142 v13: vreg = ["v13"],
143 v14: vreg = ["v14"],
144 v15: vreg = ["v15"],
145 v16: vreg = ["v16"],
146 v17: vreg = ["v17"],
147 v18: vreg = ["v18"],
148 v19: vreg = ["v19"],
149 v20: vreg = ["v20"],
150 v21: vreg = ["v21"],
151 v22: vreg = ["v22"],
152 v23: vreg = ["v23"],
153 v24: vreg = ["v24"],
154 v25: vreg = ["v25"],
155 v26: vreg = ["v26"],
156 v27: vreg = ["v27"],
157 v28: vreg = ["v28"],
158 v29: vreg = ["v29"],
159 v30: vreg = ["v30"],
160 v31: vreg = ["v31"],
161 #error = ["x9", "s1"] =>
162 "s1 is used internally by LLVM and cannot be used as an operand for inline asm",
163 #error = ["x8", "s0", "fp"] =>
164 "the frame pointer cannot be used as an operand for inline asm",
165 #error = ["x2", "sp"] =>
166 "the stack pointer cannot be used as an operand for inline asm",
167 #error = ["x3", "gp"] =>
168 "the global pointer cannot be used as an operand for inline asm",
169 #error = ["x4", "tp"] =>
170 "the thread pointer cannot be used as an operand for inline asm" ,
171 #error = ["x0", "zero"] =>
172 "the zero register cannot be used as an operand for inline asm",
173 }
174 }
175
176 impl RiscVInlineAsmReg {
emit( self, out: &mut dyn fmt::Write, _arch: InlineAsmArch, _modifier: Option<char>, ) -> fmt::Result177 pub fn emit(
178 self,
179 out: &mut dyn fmt::Write,
180 _arch: InlineAsmArch,
181 _modifier: Option<char>,
182 ) -> fmt::Result {
183 out.write_str(self.name())
184 }
185 }
186