Lines Matching refs:dst
1458 FRegister dst = destination.AsFpuRegister<FRegister>(); in MoveLocation() local
1461 __ Mtc1(src_low, dst); in MoveLocation()
1462 __ MoveToFpuHigh(src_high, dst); in MoveLocation()
1528 Register dst = destination.AsRegister<Register>(); in MoveConstant() local
1529 __ LoadConst32(dst, value); in MoveConstant()
1574 Register dst = destination.AsRegister<Register>(); in MoveConstant() local
1575 __ LoadConst32(dst, value); in MoveConstant()
2170 Register dst = locations->Out().AsRegister<Register>(); in HandleBinaryOp() local
2185 __ Andi(dst, lhs, rhs_imm); in HandleBinaryOp()
2187 __ And(dst, lhs, rhs_reg); in HandleBinaryOp()
2190 __ Ori(dst, lhs, rhs_imm); in HandleBinaryOp()
2192 __ Or(dst, lhs, rhs_reg); in HandleBinaryOp()
2195 __ Xori(dst, lhs, rhs_imm); in HandleBinaryOp()
2197 __ Xor(dst, lhs, rhs_reg); in HandleBinaryOp()
2205 __ Addiu(dst, lhs, rhs_imm); in HandleBinaryOp()
2213 __ Aui(dst, lhs, rhs_imm_high); in HandleBinaryOp()
2215 __ Addiu(dst, dst, rhs_imm_low); in HandleBinaryOp()
2219 __ Addu(dst, lhs, rhs_reg); in HandleBinaryOp()
2222 __ Subu(dst, lhs, rhs_reg); in HandleBinaryOp()
2371 FRegister dst = locations->Out().AsFpuRegister<FRegister>(); in HandleBinaryOp() local
2376 __ AddS(dst, lhs, rhs); in HandleBinaryOp()
2378 __ AddD(dst, lhs, rhs); in HandleBinaryOp()
2383 __ SubS(dst, lhs, rhs); in HandleBinaryOp()
2385 __ SubD(dst, lhs, rhs); in HandleBinaryOp()
2436 Register dst = locations->Out().AsRegister<Register>(); in HandleShift() local
2440 if (dst != lhs) { in HandleShift()
2441 __ Move(dst, lhs); in HandleShift()
2444 __ Sll(dst, lhs, shift_value); in HandleShift()
2446 __ Sra(dst, lhs, shift_value); in HandleShift()
2448 __ Srl(dst, lhs, shift_value); in HandleShift()
2451 __ Rotr(dst, lhs, shift_value); in HandleShift()
2454 __ Srl(dst, lhs, shift_value); in HandleShift()
2455 __ Or(dst, dst, TMP); in HandleShift()
2460 __ Sllv(dst, lhs, rhs_reg); in HandleShift()
2462 __ Srav(dst, lhs, rhs_reg); in HandleShift()
2464 __ Srlv(dst, lhs, rhs_reg); in HandleShift()
2467 __ Rotrv(dst, lhs, rhs_reg); in HandleShift()
2476 __ Srlv(dst, lhs, rhs_reg); in HandleShift()
2477 __ Or(dst, dst, TMP); in HandleShift()
4263 FRegister dst = locations->Out().AsFpuRegister<FRegister>(); in VisitDiv() local
4267 __ DivS(dst, lhs, rhs); in VisitDiv()
4269 __ DivD(dst, lhs, rhs); in VisitDiv()
4406 Register dst = locations->Out().AsRegister<Register>(); in GenerateIntCompare() local
4424 __ Sltiu(dst, lhs, 1); in GenerateIntCompare()
4426 __ Sltu(dst, ZERO, lhs); in GenerateIntCompare()
4429 __ Addiu(dst, lhs, -rhs_imm); in GenerateIntCompare()
4431 __ Sltiu(dst, dst, 1); in GenerateIntCompare()
4433 __ Sltu(dst, ZERO, dst); in GenerateIntCompare()
4438 __ Xori(dst, lhs, rhs_imm); in GenerateIntCompare()
4444 __ Xor(dst, lhs, rhs_reg); in GenerateIntCompare()
4447 __ Sltiu(dst, dst, 1); in GenerateIntCompare()
4449 __ Sltu(dst, ZERO, dst); in GenerateIntCompare()
4457 __ Slti(dst, lhs, rhs_imm); in GenerateIntCompare()
4463 __ Slt(dst, lhs, rhs_reg); in GenerateIntCompare()
4468 __ Xori(dst, dst, 1); in GenerateIntCompare()
4476 __ Slti(dst, lhs, rhs_imm + 1); in GenerateIntCompare()
4480 __ Xori(dst, dst, 1); in GenerateIntCompare()
4487 __ Slt(dst, rhs_reg, lhs); in GenerateIntCompare()
4491 __ Xori(dst, dst, 1); in GenerateIntCompare()
4503 __ Sltiu(dst, lhs, rhs_imm); in GenerateIntCompare()
4509 __ Sltu(dst, lhs, rhs_reg); in GenerateIntCompare()
4514 __ Xori(dst, dst, 1); in GenerateIntCompare()
4528 __ Sltiu(dst, lhs, rhs_imm + 1); in GenerateIntCompare()
4532 __ Xori(dst, dst, 1); in GenerateIntCompare()
4539 __ Sltu(dst, rhs_reg, lhs); in GenerateIntCompare()
4543 __ Xori(dst, dst, 1); in GenerateIntCompare()
4552 Register dst) { in MaterializeIntCompare() argument
4568 __ Addiu(dst, lhs, -rhs_imm); in MaterializeIntCompare()
4570 __ Xori(dst, lhs, rhs_imm); in MaterializeIntCompare()
4576 __ Xor(dst, lhs, rhs_reg); in MaterializeIntCompare()
4583 __ Slti(dst, lhs, rhs_imm); in MaterializeIntCompare()
4589 __ Slt(dst, lhs, rhs_reg); in MaterializeIntCompare()
4597 __ Slti(dst, lhs, rhs_imm + 1); in MaterializeIntCompare()
4604 __ Slt(dst, rhs_reg, lhs); in MaterializeIntCompare()
4615 __ Sltiu(dst, lhs, rhs_imm); in MaterializeIntCompare()
4621 __ Sltu(dst, lhs, rhs_reg); in MaterializeIntCompare()
4635 __ Sltiu(dst, lhs, rhs_imm + 1); in MaterializeIntCompare()
4642 __ Sltu(dst, rhs_reg, lhs); in MaterializeIntCompare()
4827 Register dst = locations->Out().AsRegister<Register>(); in GenerateLongCompare() local
4849 __ Or(dst, lhs_high, lhs_low); in GenerateLongCompare()
4850 __ Sltiu(dst, dst, 1); in GenerateLongCompare()
4854 __ Or(dst, lhs_high, lhs_low); in GenerateLongCompare()
4855 __ Sltu(dst, ZERO, dst); in GenerateLongCompare()
4858 __ Slt(dst, lhs_high, ZERO); in GenerateLongCompare()
4861 __ Slt(dst, lhs_high, ZERO); in GenerateLongCompare()
4862 __ Xori(dst, dst, 1); in GenerateLongCompare()
4867 __ Sltu(dst, AT, TMP); in GenerateLongCompare()
4868 __ Xori(dst, dst, 1); in GenerateLongCompare()
4873 __ Sltu(dst, AT, TMP); in GenerateLongCompare()
4876 __ Andi(dst, dst, 0); in GenerateLongCompare()
4879 __ Ori(dst, ZERO, 1); in GenerateLongCompare()
4890 __ Or(dst, TMP, AT); in GenerateLongCompare()
4891 __ Sltiu(dst, dst, 1); in GenerateLongCompare()
4898 __ Or(dst, TMP, AT); in GenerateLongCompare()
4899 __ Sltu(dst, ZERO, dst); in GenerateLongCompare()
4903 if (dst == lhs_low) { in GenerateLongCompare()
4905 __ Sltu(dst, lhs_low, TMP); in GenerateLongCompare()
4910 if (dst != lhs_low) { in GenerateLongCompare()
4911 __ LoadConst32(dst, imm_low); in GenerateLongCompare()
4912 __ Sltu(dst, lhs_low, dst); in GenerateLongCompare()
4914 __ Slt(dst, TMP, dst); in GenerateLongCompare()
4915 __ Or(dst, dst, AT); in GenerateLongCompare()
4917 __ Xori(dst, dst, 1); in GenerateLongCompare()
4922 if (dst == lhs_low) { in GenerateLongCompare()
4924 __ Sltu(dst, TMP, lhs_low); in GenerateLongCompare()
4929 if (dst != lhs_low) { in GenerateLongCompare()
4930 __ LoadConst32(dst, imm_low); in GenerateLongCompare()
4931 __ Sltu(dst, dst, lhs_low); in GenerateLongCompare()
4933 __ Slt(dst, TMP, dst); in GenerateLongCompare()
4934 __ Or(dst, dst, AT); in GenerateLongCompare()
4936 __ Xori(dst, dst, 1); in GenerateLongCompare()
4941 if (dst == lhs_low) { in GenerateLongCompare()
4943 __ Sltu(dst, lhs_low, TMP); in GenerateLongCompare()
4948 if (dst != lhs_low) { in GenerateLongCompare()
4949 __ LoadConst32(dst, imm_low); in GenerateLongCompare()
4950 __ Sltu(dst, lhs_low, dst); in GenerateLongCompare()
4952 __ Slt(dst, TMP, dst); in GenerateLongCompare()
4953 __ Or(dst, dst, AT); in GenerateLongCompare()
4955 __ Xori(dst, dst, 1); in GenerateLongCompare()
4960 if (dst == lhs_low) { in GenerateLongCompare()
4962 __ Sltu(dst, TMP, lhs_low); in GenerateLongCompare()
4967 if (dst != lhs_low) { in GenerateLongCompare()
4968 __ LoadConst32(dst, imm_low); in GenerateLongCompare()
4969 __ Sltu(dst, dst, lhs_low); in GenerateLongCompare()
4971 __ Slt(dst, TMP, dst); in GenerateLongCompare()
4972 __ Or(dst, dst, AT); in GenerateLongCompare()
4974 __ Xori(dst, dst, 1); in GenerateLongCompare()
4983 __ Or(dst, TMP, AT); in GenerateLongCompare()
4984 __ Sltiu(dst, dst, 1); in GenerateLongCompare()
4989 __ Or(dst, TMP, AT); in GenerateLongCompare()
4990 __ Sltu(dst, ZERO, dst); in GenerateLongCompare()
4998 __ Or(dst, AT, TMP); in GenerateLongCompare()
5000 __ Xori(dst, dst, 1); in GenerateLongCompare()
5009 __ Or(dst, AT, TMP); in GenerateLongCompare()
5011 __ Xori(dst, dst, 1); in GenerateLongCompare()
5020 __ Or(dst, AT, TMP); in GenerateLongCompare()
5022 __ Xori(dst, dst, 1); in GenerateLongCompare()
5031 __ Or(dst, AT, TMP); in GenerateLongCompare()
5033 __ Xori(dst, dst, 1); in GenerateLongCompare()
5257 Register dst = locations->Out().AsRegister<Register>(); in GenerateFpCompare() local
5266 __ Mfc1(dst, FTMP); in GenerateFpCompare()
5267 __ Andi(dst, dst, 1); in GenerateFpCompare()
5271 __ Mfc1(dst, FTMP); in GenerateFpCompare()
5272 __ Addiu(dst, dst, 1); in GenerateFpCompare()
5280 __ Mfc1(dst, FTMP); in GenerateFpCompare()
5281 __ Andi(dst, dst, 1); in GenerateFpCompare()
5289 __ Mfc1(dst, FTMP); in GenerateFpCompare()
5290 __ Andi(dst, dst, 1); in GenerateFpCompare()
5298 __ Mfc1(dst, FTMP); in GenerateFpCompare()
5299 __ Andi(dst, dst, 1); in GenerateFpCompare()
5307 __ Mfc1(dst, FTMP); in GenerateFpCompare()
5308 __ Andi(dst, dst, 1); in GenerateFpCompare()
5318 __ LoadConst32(dst, 1); in GenerateFpCompare()
5319 __ Movf(dst, ZERO, 0); in GenerateFpCompare()
5323 __ LoadConst32(dst, 1); in GenerateFpCompare()
5324 __ Movt(dst, ZERO, 0); in GenerateFpCompare()
5332 __ LoadConst32(dst, 1); in GenerateFpCompare()
5333 __ Movf(dst, ZERO, 0); in GenerateFpCompare()
5341 __ LoadConst32(dst, 1); in GenerateFpCompare()
5342 __ Movf(dst, ZERO, 0); in GenerateFpCompare()
5350 __ LoadConst32(dst, 1); in GenerateFpCompare()
5351 __ Movf(dst, ZERO, 0); in GenerateFpCompare()
5359 __ LoadConst32(dst, 1); in GenerateFpCompare()
5360 __ Movf(dst, ZERO, 0); in GenerateFpCompare()
5373 __ Mfc1(dst, FTMP); in GenerateFpCompare()
5374 __ Andi(dst, dst, 1); in GenerateFpCompare()
5378 __ Mfc1(dst, FTMP); in GenerateFpCompare()
5379 __ Addiu(dst, dst, 1); in GenerateFpCompare()
5387 __ Mfc1(dst, FTMP); in GenerateFpCompare()
5388 __ Andi(dst, dst, 1); in GenerateFpCompare()
5396 __ Mfc1(dst, FTMP); in GenerateFpCompare()
5397 __ Andi(dst, dst, 1); in GenerateFpCompare()
5405 __ Mfc1(dst, FTMP); in GenerateFpCompare()
5406 __ Andi(dst, dst, 1); in GenerateFpCompare()
5414 __ Mfc1(dst, FTMP); in GenerateFpCompare()
5415 __ Andi(dst, dst, 1); in GenerateFpCompare()
5425 __ LoadConst32(dst, 1); in GenerateFpCompare()
5426 __ Movf(dst, ZERO, 0); in GenerateFpCompare()
5430 __ LoadConst32(dst, 1); in GenerateFpCompare()
5431 __ Movt(dst, ZERO, 0); in GenerateFpCompare()
5439 __ LoadConst32(dst, 1); in GenerateFpCompare()
5440 __ Movf(dst, ZERO, 0); in GenerateFpCompare()
5448 __ LoadConst32(dst, 1); in GenerateFpCompare()
5449 __ Movf(dst, ZERO, 0); in GenerateFpCompare()
5457 __ LoadConst32(dst, 1); in GenerateFpCompare()
5458 __ Movf(dst, ZERO, 0); in GenerateFpCompare()
5466 __ LoadConst32(dst, 1); in GenerateFpCompare()
5467 __ Movf(dst, ZERO, 0); in GenerateFpCompare()
5573 FRegister dst) { in MaterializeFpCompareR6() argument
5580 __ CmpEqS(dst, lhs, rhs); in MaterializeFpCompareR6()
5583 __ CmpEqS(dst, lhs, rhs); in MaterializeFpCompareR6()
5587 __ CmpLtS(dst, lhs, rhs); in MaterializeFpCompareR6()
5589 __ CmpUltS(dst, lhs, rhs); in MaterializeFpCompareR6()
5594 __ CmpLeS(dst, lhs, rhs); in MaterializeFpCompareR6()
5596 __ CmpUleS(dst, lhs, rhs); in MaterializeFpCompareR6()
5601 __ CmpUltS(dst, rhs, lhs); in MaterializeFpCompareR6()
5603 __ CmpLtS(dst, rhs, lhs); in MaterializeFpCompareR6()
5608 __ CmpUleS(dst, rhs, lhs); in MaterializeFpCompareR6()
5610 __ CmpLeS(dst, rhs, lhs); in MaterializeFpCompareR6()
5621 __ CmpEqD(dst, lhs, rhs); in MaterializeFpCompareR6()
5624 __ CmpEqD(dst, lhs, rhs); in MaterializeFpCompareR6()
5628 __ CmpLtD(dst, lhs, rhs); in MaterializeFpCompareR6()
5630 __ CmpUltD(dst, lhs, rhs); in MaterializeFpCompareR6()
5635 __ CmpLeD(dst, lhs, rhs); in MaterializeFpCompareR6()
5637 __ CmpUleD(dst, lhs, rhs); in MaterializeFpCompareR6()
5642 __ CmpUltD(dst, rhs, lhs); in MaterializeFpCompareR6()
5644 __ CmpLtD(dst, rhs, lhs); in MaterializeFpCompareR6()
5649 __ CmpUleD(dst, rhs, lhs); in MaterializeFpCompareR6()
5651 __ CmpLeD(dst, rhs, lhs); in MaterializeFpCompareR6()
6215 Location dst = locations->Out(); in GenConditionalMoveR2() local
6249 DCHECK(dst.Equals(locations->InAt(0))); in GenConditionalMoveR2()
6264 __ Movz(dst.AsRegister<Register>(), src_reg, cond_reg); in GenConditionalMoveR2()
6266 __ Movn(dst.AsRegister<Register>(), src_reg, cond_reg); in GenConditionalMoveR2()
6271 __ Movz(dst.AsRegisterPairLow<Register>(), src_reg, cond_reg); in GenConditionalMoveR2()
6272 __ Movz(dst.AsRegisterPairHigh<Register>(), src_reg_high, cond_reg); in GenConditionalMoveR2()
6274 __ Movn(dst.AsRegisterPairLow<Register>(), src_reg, cond_reg); in GenConditionalMoveR2()
6275 __ Movn(dst.AsRegisterPairHigh<Register>(), src_reg_high, cond_reg); in GenConditionalMoveR2()
6280 __ MovzS(dst.AsFpuRegister<FRegister>(), src.AsFpuRegister<FRegister>(), cond_reg); in GenConditionalMoveR2()
6282 __ MovnS(dst.AsFpuRegister<FRegister>(), src.AsFpuRegister<FRegister>(), cond_reg); in GenConditionalMoveR2()
6287 __ MovzD(dst.AsFpuRegister<FRegister>(), src.AsFpuRegister<FRegister>(), cond_reg); in GenConditionalMoveR2()
6289 __ MovnD(dst.AsFpuRegister<FRegister>(), src.AsFpuRegister<FRegister>(), cond_reg); in GenConditionalMoveR2()
6302 __ Movf(dst.AsRegister<Register>(), src_reg, cond_cc); in GenConditionalMoveR2()
6304 __ Movt(dst.AsRegister<Register>(), src_reg, cond_cc); in GenConditionalMoveR2()
6309 __ Movf(dst.AsRegisterPairLow<Register>(), src_reg, cond_cc); in GenConditionalMoveR2()
6310 __ Movf(dst.AsRegisterPairHigh<Register>(), src_reg_high, cond_cc); in GenConditionalMoveR2()
6312 __ Movt(dst.AsRegisterPairLow<Register>(), src_reg, cond_cc); in GenConditionalMoveR2()
6313 __ Movt(dst.AsRegisterPairHigh<Register>(), src_reg_high, cond_cc); in GenConditionalMoveR2()
6318 __ MovfS(dst.AsFpuRegister<FRegister>(), src.AsFpuRegister<FRegister>(), cond_cc); in GenConditionalMoveR2()
6320 __ MovtS(dst.AsFpuRegister<FRegister>(), src.AsFpuRegister<FRegister>(), cond_cc); in GenConditionalMoveR2()
6325 __ MovfD(dst.AsFpuRegister<FRegister>(), src.AsFpuRegister<FRegister>(), cond_cc); in GenConditionalMoveR2()
6327 __ MovtD(dst.AsFpuRegister<FRegister>(), src.AsFpuRegister<FRegister>(), cond_cc); in GenConditionalMoveR2()
6337 Location dst = locations->Out(); in GenConditionalMoveR6() local
6384 __ Selnez(dst.AsRegister<Register>(), false_src.AsRegister<Register>(), cond_reg); in GenConditionalMoveR6()
6386 __ Seleqz(dst.AsRegister<Register>(), false_src.AsRegister<Register>(), cond_reg); in GenConditionalMoveR6()
6390 __ Seleqz(dst.AsRegister<Register>(), true_src.AsRegister<Register>(), cond_reg); in GenConditionalMoveR6()
6392 __ Selnez(dst.AsRegister<Register>(), true_src.AsRegister<Register>(), cond_reg); in GenConditionalMoveR6()
6403 __ Or(dst.AsRegister<Register>(), AT, TMP); in GenConditionalMoveR6()
6410 Register dst_lo = dst.AsRegisterPairLow<Register>(); in GenConditionalMoveR6()
6411 Register dst_hi = dst.AsRegisterPairHigh<Register>(); in GenConditionalMoveR6()
6442 FRegister dst_reg = dst.AsFpuRegister<FRegister>(); in GenConditionalMoveR6()
6477 FRegister dst_reg = dst.AsFpuRegister<FRegister>(); in GenConditionalMoveR6()
6714 Register dst; in HandleFieldGet() local
6717 dst = dst_loc.AsRegisterPairLow<Register>(); in HandleFieldGet()
6720 dst = dst_loc.AsRegister<Register>(); in HandleFieldGet()
6722 __ LoadFromOffset(load_type, dst, obj, offset, null_checker); in HandleFieldGet()
6725 FRegister dst = dst_loc.AsFpuRegister<FRegister>(); in HandleFieldGet() local
6727 __ LoadSFromOffset(dst, obj, offset, null_checker); in HandleFieldGet()
6729 __ LoadDFromOffset(dst, obj, offset, null_checker); in HandleFieldGet()
8570 Register dst = locations->Out().AsRegister<Register>(); in VisitMul() local
8575 __ MulR6(dst, lhs, rhs); in VisitMul()
8577 __ MulR2(dst, lhs, rhs); in VisitMul()
8620 FRegister dst = locations->Out().AsFpuRegister<FRegister>(); in VisitMul() local
8624 __ MulS(dst, lhs, rhs); in VisitMul()
8626 __ MulD(dst, lhs, rhs); in VisitMul()
8662 Register dst = locations->Out().AsRegister<Register>(); in VisitNeg() local
8664 __ Subu(dst, ZERO, src); in VisitNeg()
8680 FRegister dst = locations->Out().AsFpuRegister<FRegister>(); in VisitNeg() local
8683 __ NegS(dst, src); in VisitNeg()
8685 __ NegD(dst, src); in VisitNeg()
8736 Register dst = locations->Out().AsRegister<Register>(); in VisitNot() local
8738 __ Nor(dst, src, ZERO); in VisitNot()
9709 Register dst = locations->Out().AsRegister<Register>(); in VisitTypeConversion() local
9716 __ Andi(dst, src, 0xFF); in VisitTypeConversion()
9720 __ Seb(dst, src); in VisitTypeConversion()
9722 __ Sll(dst, src, 24); in VisitTypeConversion()
9723 __ Sra(dst, dst, 24); in VisitTypeConversion()
9727 __ Andi(dst, src, 0xFFFF); in VisitTypeConversion()
9731 __ Seh(dst, src); in VisitTypeConversion()
9733 __ Sll(dst, src, 16); in VisitTypeConversion()
9734 __ Sra(dst, dst, 16); in VisitTypeConversion()
9738 if (dst != src) { in VisitTypeConversion()
9739 __ Move(dst, src); in VisitTypeConversion()
9754 FRegister dst = locations->Out().AsFpuRegister<FRegister>(); in VisitTypeConversion() local
9758 __ Cvtsl(dst, FTMP); in VisitTypeConversion()
9760 __ Cvtdl(dst, FTMP); in VisitTypeConversion()
9774 FRegister dst = locations->Out().AsFpuRegister<FRegister>(); in VisitTypeConversion() local
9777 __ Cvtsw(dst, FTMP); in VisitTypeConversion()
9779 __ Cvtdw(dst, FTMP); in VisitTypeConversion()
9828 Register dst = locations->Out().AsRegister<Register>(); in VisitTypeConversion() local
9856 __ LoadConst32(dst, std::numeric_limits<int32_t>::min()); in VisitTypeConversion()
9857 __ Movf(dst, ZERO, 0); in VisitTypeConversion()
9869 __ Mfc1(dst, FTMP); in VisitTypeConversion()
9877 FRegister dst = locations->Out().AsFpuRegister<FRegister>(); in VisitTypeConversion() local
9880 __ Cvtsd(dst, src); in VisitTypeConversion()
9882 __ Cvtds(dst, src); in VisitTypeConversion()