Lines Matching refs:DDR

22 DATA 0xFFD01400 0x43000c30	# DDR Configuration register
25 # bit24: 1= enable exit self refresh mode on DDR access
30 DATA 0xFFD01404 0x37543000	# DDR Controller Control Low
41 DATA 0xFFD01408 0x22125451	# DDR Timing (Low) (active cycles value +1)
52 DATA 0xFFD0140C 0x00000a33	#  DDR Timing (High)
59 DATA 0xFFD01410 0x000000cc	#  DDR Address Control
74 DATA 0xFFD01414 0x00000000	#  DDR Open Pages Control
78 DATA 0xFFD01418 0x00000000	#  DDR Operation
79 # bit3-0:   0x0, DDR cmd
82 DATA 0xFFD0141C 0x00000C52	#  DDR Mode
92 DATA 0xFFD01420 0x00000040	#  DDR Extended Mode
93 # bit0:    0,  DDR DLL enabled
94 # bit1:    0,  DDR drive strenght normal
95 # bit2:    0,  DDR ODT control lsd (disabled)
97 # bit6:    1,  DDR ODT control msb, (disabled)
101 # bit12:   0, DDR output buffer enabled
104 DATA 0xFFD01424 0x0000F17F	#  DDR Controller Control High
109 # bit8  :  1  , add writepath sample stage, must be 1 for DDR freq >= 300MHz
133 DATA 0xFFD01494 0x00030000	#  DDR ODT Control (Low)
134 DATA 0xFFD01498 0x00000000	#  DDR ODT Control (High)
140 DATA 0xFFD01480 0x00000001	# DDR Initialization Control
141 #bit0=1, enable DDR init upon this register write