| /art/compiler/utils/mips/ |
| D | assembler_mips_test.cc | 870 TEST_F(AssemblerMIPSTest, Addiu32) { in TEST_F() argument
871 __ Addiu32(mips::A1, mips::A2, -0x8000); in TEST_F() local
872 __ Addiu32(mips::A1, mips::A2, +0); in TEST_F() local
873 __ Addiu32(mips::A1, mips::A2, +0x7FFF); in TEST_F() local
874 __ Addiu32(mips::A1, mips::A2, -0x10000); in TEST_F() local
875 __ Addiu32(mips::A1, mips::A2, -0x8001); in TEST_F() local
876 __ Addiu32(mips::A1, mips::A2, +0x8000); in TEST_F() local
877 __ Addiu32(mips::A1, mips::A2, +0xFFFE); in TEST_F() local
878 __ Addiu32(mips::A1, mips::A2, -0x10001); in TEST_F() local
879 __ Addiu32(mips::A1, mips::A2, +0xFFFF); in TEST_F() local
[all …]
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| D | assembler_mips.cc | 2878 void MipsAssembler::Addiu32(Register rt, Register rs, int32_t value, Register temp) { in Addiu32() function in art::mips::MipsAssembler
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| /art/compiler/optimizing/ |
| D | intrinsics_mips.cc | 2483 __ Addiu32(AT, AT, -pos_const, TMP); in CheckPosition() local
2569 __ Addiu32(src_base, src, data_offset + char_size * src_pos_const, TMP); in VisitSystemArrayCopyChar() local
2571 __ Addiu32(src_base, src, data_offset, TMP); in VisitSystemArrayCopyChar() local
2577 __ Addiu32(dest_base, dest, data_offset + char_size * dest_pos_const, TMP); in VisitSystemArrayCopyChar() local
2579 __ Addiu32(dest_base, dest, data_offset, TMP); in VisitSystemArrayCopyChar() local
2636 __ Addiu32(out, in, -info.low); in VisitIntegerValueOf() local
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| D | intrinsics_mips64.cc | 1863 __ Addiu32(AT, AT, -pos_const); in CheckPosition() local
2302 __ Addiu32(out, in, -info.low); in VisitIntegerValueOf() local
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| D | code_generator_mips.cc | 870 __ Addiu32(index_reg, index_reg, offset_); in EmitNativeCode() local
6659 __ Addiu32(locations->GetTemp(0).AsRegister<Register>(), obj, offset); in HandleFieldGet() local
6818 __ Addiu32(locations->GetTemp(0).AsRegister<Register>(), obj, offset); in HandleFieldSet() local
7136 __ Addiu32(root_reg, obj, offset); in GenerateGcRootFieldLoad() local
10018 __ Addiu32(temp_reg, value_reg, -lower_bound); in GenPackedSwitchWithCompares() local
10062 __ Addiu32(TMP, value_reg, -lower_bound); in GenTableBasedPackedSwitch() local
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| D | code_generator_mips64.cc | 817 __ Addiu32(index_reg, index_reg, offset_); in EmitNativeCode() local
7509 __ Addiu32(temp_reg, value_reg, -lower_bound); in GenPackedSwitchWithCompares() local
7552 __ Addiu32(TMP, value_reg, -lower_bound); in GenTableBasedPackedSwitch() local
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| /art/compiler/utils/mips64/ |
| D | assembler_mips64_test.cc | 2541 TEST_F(AssemblerMIPS64Test, Addiu32) { in TEST_F() argument
2542 __ Addiu32(mips64::A1, mips64::A2, -0x8000); in TEST_F() local
2543 __ Addiu32(mips64::A1, mips64::A2, +0); in TEST_F() local
2544 __ Addiu32(mips64::A1, mips64::A2, +0x7FFF); in TEST_F() local
2545 __ Addiu32(mips64::A1, mips64::A2, -0x8001); in TEST_F() local
2546 __ Addiu32(mips64::A1, mips64::A2, +0x8000); in TEST_F() local
2547 __ Addiu32(mips64::A1, mips64::A2, -0x10000); in TEST_F() local
2548 __ Addiu32(mips64::A1, mips64::A2, +0x10000); in TEST_F() local
2549 __ Addiu32(mips64::A1, mips64::A2, +0x12345678); in TEST_F() local
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| D | assembler_mips64.cc | 2325 void Mips64Assembler::Addiu32(GpuRegister rt, GpuRegister rs, int32_t value) { in Addiu32() function in art::mips64::Mips64Assembler
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