| /art/compiler/optimizing/ |
| D | intrinsics_mips.cc | 290 __ And(TMP, out, AT); in GenReverse() local
293 __ And(out, out, AT); in GenReverse() local
301 __ And(TMP, out, AT); in GenReverse() local
304 __ And(out, out, AT); in GenReverse() local
307 __ And(TMP, out, AT); in GenReverse() local
310 __ And(out, out, AT); in GenReverse() local
313 __ And(TMP, out, AT); in GenReverse() local
316 __ And(out, out, AT); in GenReverse() local
349 __ And(out_hi, TMP, AT); in GenReverse() local
352 __ And(TMP, TMP, AT); in GenReverse() local
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| D | intrinsics_mips64.cc | 436 __ And(TMP, TMP, AT); in GenBitCount() local
439 __ And(out, TMP, AT); in GenBitCount() local
441 __ And(TMP, TMP, AT); in GenBitCount() local
446 __ And(out, out, AT); in GenBitCount() local
453 __ And(TMP, TMP, AT); in GenBitCount() local
456 __ And(out, TMP, AT); in GenBitCount() local
458 __ And(TMP, TMP, AT); in GenBitCount() local
463 __ And(out, out, AT); in GenBitCount() local
1998 __ And(out, AT, in); in GenHighestOneBit() local
2032 __ And(out, TMP, in); in GenLowestOneBit() local
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| D | code_generator_arm_vixl.cc | 1079 __ And(out, first, second); in GenerateDataProcInstruction() local
4446 __ And(temp1, temp1, temp2); in GenerateMinMaxFloat() local
4716 __ And(shift_right, RegisterFrom(rhs), 0x1F); in HandleLongRotate() local
4846 __ And(out_reg, second_reg, kMaxIntShiftDistance); in HandleShift() local
4882 __ And(o_l, second_reg, kMaxLongShiftDistance); in HandleShift() local
4901 __ And(o_h, second_reg, kMaxLongShiftDistance); in HandleShift() local
4920 __ And(o_h, second_reg, kMaxLongShiftDistance); in HandleShift() local
8114 __ And(out, first, value); in GenerateAndConst() local
8232 __ And(out_reg, first_reg, second_reg); in HandleBitwiseOperation() local
8248 __ And(out_low, first_low, second_low); in HandleBitwiseOperation() local
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| D | intrinsics_arm_vixl.cc | 1368 __ And(temp2, temp2, temp3); in GenerateStringCompareToLoop() local
1369 __ And(out, out, temp3); in GenerateStringCompareToLoop() local
2732 __ And(out_reg_hi, out_reg_hi, in_reg_hi); in GenLowestOneBit() local
2756 __ And(out, temp, in); in GenLowestOneBit() local
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| D | code_generator_arm64.cc | 1981 __ And(dst, lhs, rhs); in HandleBinaryOp() local
2183 __ And(out, left, right_operand); in VisitDataProcWithShifterOp() local
5194 __ And(out, dividend, 1); in GenerateIntRemForPower2Denom() local
5201 __ And(out, dividend, abs_imm - 1); in GenerateIntRemForPower2Denom() local
5202 __ And(temp, temp, abs_imm - 1); in GenerateIntRemForPower2Denom() local
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| D | code_generator_vector_arm64.cc | 773 __ And(dst.V16B(), lhs.V16B(), rhs.V16B()); // lanes do not matter in VisitVecAnd() local
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| D | code_generator_mips.cc | 2187 __ And(dst, lhs, rhs_reg); in HandleBinaryOp() local
2239 __ And(dst_low, lhs_low, rhs_low); in HandleBinaryOp() local
2240 __ And(dst_high, lhs_high, rhs_high); in HandleBinaryOp() local
2317 __ And(dst_low, lhs_low, TMP); in HandleBinaryOp() local
2327 __ And(dst_high, lhs_high, TMP); in HandleBinaryOp() local
4018 __ And(TMP, in_high, TMP); in DivRemByPowerOfTwo() local
9256 __ And(TMP, TMP, AT); in GenerateMinMaxFP() local
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| D | intrinsics_arm64.cc | 505 __ And(dst, temp, src); in GenLowestOneBit() local
1555 __ And(temp1, temp, Operand(1)); // Extract compression flag. in VisitStringEquals() local
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| D | code_generator_mips64.cc | 2022 __ And(dst, lhs, rhs_reg); in HandleBinaryOp() local
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| /art/test/953-invoke-polymorphic-compiler/src/ |
| D | Main.java | 182 private static boolean And(boolean lhs, boolean rhs) { in And() method in Main
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| /art/compiler/utils/mips/ |
| D | assembler_mips_test.cc | 410 TEST_F(AssemblerMIPSTest, And) { in TEST_F() argument
2324 __ And(mips::T0, mips::T1, mips::T2); in TEST_F() local
2470 __ And(mips::T0, mips::T1, mips::T2); in TEST_F() local
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| D | assembler_mips.cc | 557 void MipsAssembler::And(Register rd, Register rs, Register rt) { in And() function in art::mips::MipsAssembler
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| /art/compiler/utils/mips64/ |
| D | assembler_mips64_test.cc | 1191 TEST_F(AssemblerMIPS64Test, And) { in TEST_F() argument
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| D | assembler_mips64.cc | 375 void Mips64Assembler::And(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in And() function in art::mips64::Mips64Assembler
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