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Searched defs:CONFIG_SYS_DDR_TIMING_2 (Results 1 – 25 of 30) sorted by relevance

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/external/u-boot/include/configs/km/
Dkm8321-common.h107 #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ macro
Dkm8309-common.h143 #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ macro
/external/u-boot/include/configs/
Dkm8360.h130 #define CONFIG_SYS_DDR_TIMING_2 (\ macro
DMPC8349EMDS.h108 #define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8 macro
121 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ macro
DMPC8540ADS.h88 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ macro
Dsocrates.h89 #define CONFIG_SYS_DDR_TIMING_2 0x14904CC8 macro
DMPC8560ADS.h87 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ macro
Dve8313.h84 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ macro
Dmpc8308_p1m.h162 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ macro
DMPC8308RDB.h160 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ macro
DMPC8323ERDB.h108 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ macro
DMPC832XEMDS.h118 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ macro
Dids8313.h131 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) |\ macro
Dp1_twr.h106 #define CONFIG_SYS_DDR_TIMING_2 0x0fa880de macro
Dsbc8349.h98 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ macro
DMPC837XEMDS.h158 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ macro
DMPC8315ERDB.h133 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ macro
Dhrcon.h149 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ macro
DMPC8313ERDB.h147 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ macro
DMPC8349ITX.h183 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */ macro
DMPC837XERDB.h172 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ macro
DUCP1020.h182 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF macro
Dsbc8641d.h128 #define CONFIG_SYS_DDR_TIMING_2 0x002040c7 macro
Dstrider.h149 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ macro
DMPC8569MDS.h95 #define CONFIG_SYS_DDR_TIMING_2 0x002888D0 macro

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