1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2004, 2011 Freescale Semiconductor. 4 * (C) Copyright 2002,2003 Motorola,Inc. 5 * Xianghua Xiao <X.Xiao@motorola.com> 6 */ 7 8 /* 9 * mpc8540ads board configuration file 10 * 11 * Please refer to doc/README.mpc85xx for more info. 12 * 13 * Make sure you change the MAC address and other network params first, 14 * search for CONFIG_SERVERIP, etc in this file. 15 */ 16 17 #ifndef __CONFIG_H 18 #define __CONFIG_H 19 20 /* 21 * default CCARBAR is at 0xff700000 22 * assume U-Boot is less than 0.5MB 23 */ 24 25 #ifndef CONFIG_HAS_FEC 26 #define CONFIG_HAS_FEC 1 /* 8540 has FEC */ 27 #endif 28 29 #define CONFIG_PCI_INDIRECT_BRIDGE 30 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 31 #define CONFIG_ENV_OVERWRITE 32 33 /* 34 * sysclk for MPC85xx 35 * 36 * Two valid values are: 37 * 33000000 38 * 66000000 39 * 40 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz 41 * is likely the desired value here, so that is now the default. 42 * The board, however, can run at 66MHz. In any event, this value 43 * must match the settings of some switches. Details can be found 44 * in the README.mpc85xxads. 45 * 46 * XXX -- Can't we run at 66 MHz, anyway? PCI should drop to 47 * 33MHz to accommodate, based on a PCI pin. 48 * Note that PCI-X won't work at 33MHz. 49 */ 50 51 #ifndef CONFIG_SYS_CLK_FREQ 52 #define CONFIG_SYS_CLK_FREQ 33000000 53 #endif 54 55 /* 56 * These can be toggled for performance analysis, otherwise use default. 57 */ 58 #define CONFIG_L2_CACHE /* toggle L2 cache */ 59 #define CONFIG_BTB /* toggle branch predition */ 60 61 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ 62 #define CONFIG_SYS_MEMTEST_END 0x00400000 63 64 #define CONFIG_SYS_CCSRBAR 0xe0000000 65 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 66 67 /* DDR Setup */ 68 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 69 #define CONFIG_DDR_SPD 70 #undef CONFIG_FSL_DDR_INTERACTIVE 71 72 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 73 74 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 75 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 76 77 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 78 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 79 80 /* I2C addresses of SPD EEPROMs */ 81 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 82 83 /* These are used when DDR doesn't use SPD. */ 84 #define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */ 85 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ 86 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002 87 #define CONFIG_SYS_DDR_TIMING_1 0x37344321 88 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ 89 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ 90 #define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ 91 #define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ 92 93 /* 94 * SDRAM on the Local Bus 95 */ 96 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 97 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 98 99 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 100 #define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */ 101 102 #define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */ 103 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 104 #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ 105 #undef CONFIG_SYS_FLASH_CHECKSUM 106 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 107 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 108 109 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 110 111 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 112 #define CONFIG_SYS_RAMBOOT 113 #else 114 #undef CONFIG_SYS_RAMBOOT 115 #endif 116 117 #define CONFIG_FLASH_CFI_DRIVER 118 #define CONFIG_SYS_FLASH_CFI 119 #define CONFIG_SYS_FLASH_EMPTY_INFO 120 121 #undef CONFIG_CLOCKS_IN_MHZ 122 123 /* 124 * Local Bus Definitions 125 */ 126 127 /* 128 * Base Register 2 and Option Register 2 configure SDRAM. 129 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 130 * 131 * For BR2, need: 132 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 133 * port-size = 32-bits = BR2[19:20] = 11 134 * no parity checking = BR2[21:22] = 00 135 * SDRAM for MSEL = BR2[24:26] = 011 136 * Valid = BR[31] = 1 137 * 138 * 0 4 8 12 16 20 24 28 139 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 140 * 141 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 142 * FIXME: the top 17 bits of BR2. 143 */ 144 145 #define CONFIG_SYS_BR2_PRELIM 0xf0001861 146 147 /* 148 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 149 * 150 * For OR2, need: 151 * 64MB mask for AM, OR2[0:7] = 1111 1100 152 * XAM, OR2[17:18] = 11 153 * 9 columns OR2[19-21] = 010 154 * 13 rows OR2[23-25] = 100 155 * EAD set for extra time OR[31] = 1 156 * 157 * 0 4 8 12 16 20 24 28 158 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 159 */ 160 161 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 162 163 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 164 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 165 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 166 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ 167 168 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \ 169 | LSDMR_RFCR5 \ 170 | LSDMR_PRETOACT3 \ 171 | LSDMR_ACTTORW3 \ 172 | LSDMR_BL8 \ 173 | LSDMR_WRC2 \ 174 | LSDMR_CL3 \ 175 | LSDMR_RFEN \ 176 ) 177 178 /* 179 * SDRAM Controller configuration sequence. 180 */ 181 #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) 182 #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 183 #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 184 #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) 185 #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) 186 187 /* 188 * 32KB, 8-bit wide for ADS config reg 189 */ 190 #define CONFIG_SYS_BR4_PRELIM 0xf8000801 191 #define CONFIG_SYS_OR4_PRELIM 0xffffe1f1 192 #define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000) 193 194 #define CONFIG_SYS_INIT_RAM_LOCK 1 195 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 196 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 197 198 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 199 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 200 201 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 202 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 203 204 /* Serial Port */ 205 #define CONFIG_SYS_NS16550_SERIAL 206 #define CONFIG_SYS_NS16550_REG_SIZE 1 207 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 208 209 #define CONFIG_SYS_BAUDRATE_TABLE \ 210 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 211 212 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 213 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 214 215 /* 216 * I2C 217 */ 218 #define CONFIG_SYS_I2C 219 #define CONFIG_SYS_I2C_FSL 220 #define CONFIG_SYS_FSL_I2C_SPEED 400000 221 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 222 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 223 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 224 225 /* RapidIO MMU */ 226 #define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */ 227 #define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */ 228 #define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000 229 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ 230 231 /* 232 * General PCI 233 * Memory space is mapped 1-1, but I/O space must start from 0. 234 */ 235 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 236 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 237 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 238 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 239 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 240 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 241 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 242 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ 243 244 #if defined(CONFIG_PCI) 245 #undef CONFIG_EEPRO100 246 #undef CONFIG_TULIP 247 248 #if !defined(CONFIG_PCI_PNP) 249 #define PCI_ENET0_IOADDR 0xe0000000 250 #define PCI_ENET0_MEMADDR 0xe0000000 251 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 252 #endif 253 254 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 255 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 256 257 #endif /* CONFIG_PCI */ 258 259 #if defined(CONFIG_TSEC_ENET) 260 261 #define CONFIG_MII 1 /* MII PHY management */ 262 #define CONFIG_TSEC1 1 263 #define CONFIG_TSEC1_NAME "TSEC0" 264 #define CONFIG_TSEC2 1 265 #define CONFIG_TSEC2_NAME "TSEC1" 266 #define TSEC1_PHY_ADDR 0 267 #define TSEC2_PHY_ADDR 1 268 #define TSEC1_PHYIDX 0 269 #define TSEC2_PHYIDX 0 270 #define TSEC1_FLAGS TSEC_GIGABIT 271 #define TSEC2_FLAGS TSEC_GIGABIT 272 273 #if CONFIG_HAS_FEC 274 #define CONFIG_MPC85XX_FEC 1 275 #define CONFIG_MPC85XX_FEC_NAME "FEC" 276 #define FEC_PHY_ADDR 3 277 #define FEC_PHYIDX 0 278 #define FEC_FLAGS 0 279 #endif 280 281 /* Options are: TSEC[0-1], FEC */ 282 #define CONFIG_ETHPRIME "TSEC0" 283 284 #endif /* CONFIG_TSEC_ENET */ 285 286 /* 287 * Environment 288 */ 289 #ifndef CONFIG_SYS_RAMBOOT 290 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 291 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 292 #define CONFIG_ENV_SIZE 0x2000 293 #else 294 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 295 #define CONFIG_ENV_SIZE 0x2000 296 #endif 297 298 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 299 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 300 301 /* 302 * BOOTP options 303 */ 304 #define CONFIG_BOOTP_BOOTFILESIZE 305 306 /* 307 * Command line configuration. 308 */ 309 310 #undef CONFIG_WATCHDOG /* watchdog disabled */ 311 312 /* 313 * Miscellaneous configurable options 314 */ 315 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 316 317 /* 318 * For booting Linux, the board info and command line data 319 * have to be in the first 64 MB of memory, since this is 320 * the maximum mapped by the Linux kernel during initialization. 321 */ 322 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 323 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 324 325 #if defined(CONFIG_CMD_KGDB) 326 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 327 #endif 328 329 /* 330 * Environment Configuration 331 */ 332 333 /* The mac addresses for all ethernet interface */ 334 #if defined(CONFIG_TSEC_ENET) 335 #define CONFIG_HAS_ETH0 336 #define CONFIG_HAS_ETH1 337 #define CONFIG_HAS_ETH2 338 #endif 339 340 #define CONFIG_IPADDR 192.168.1.253 341 342 #define CONFIG_HOSTNAME "unknown" 343 #define CONFIG_ROOTPATH "/nfsroot" 344 #define CONFIG_BOOTFILE "your.uImage" 345 346 #define CONFIG_SERVERIP 192.168.1.1 347 #define CONFIG_GATEWAYIP 192.168.1.1 348 #define CONFIG_NETMASK 255.255.255.0 349 350 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ 351 352 #define CONFIG_EXTRA_ENV_SETTINGS \ 353 "netdev=eth0\0" \ 354 "consoledev=ttyS0\0" \ 355 "ramdiskaddr=1000000\0" \ 356 "ramdiskfile=your.ramdisk.u-boot\0" \ 357 "fdtaddr=400000\0" \ 358 "fdtfile=your.fdt.dtb\0" 359 360 #define CONFIG_NFSBOOTCOMMAND \ 361 "setenv bootargs root=/dev/nfs rw " \ 362 "nfsroot=$serverip:$rootpath " \ 363 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 364 "console=$consoledev,$baudrate $othbootargs;" \ 365 "tftp $loadaddr $bootfile;" \ 366 "tftp $fdtaddr $fdtfile;" \ 367 "bootm $loadaddr - $fdtaddr" 368 369 #define CONFIG_RAMBOOTCOMMAND \ 370 "setenv bootargs root=/dev/ram rw " \ 371 "console=$consoledev,$baudrate $othbootargs;" \ 372 "tftp $ramdiskaddr $ramdiskfile;" \ 373 "tftp $loadaddr $bootfile;" \ 374 "tftp $fdtaddr $fdtfile;" \ 375 "bootm $loadaddr $ramdiskaddr $fdtaddr" 376 377 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 378 379 #endif /* __CONFIG_H */ 380