/external/vixl/examples/aarch64/ |
D | neon-matrix-multiply.cc | 51 __ Fmul(v_out, v4.V4S(), v_in, 0); // e.g. (v0.V4S(), v4.V4S(), v8.S(), 0). in GenerateMultiplyColumn() local
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/external/vixl/test/aarch64/ |
D | test-assembler-aarch64.cc | 10865 __ Fmul(s0, s17, s18); in TEST() local 10866 __ Fmul(s1, s18, s19); in TEST() local 10867 __ Fmul(s2, s14, s14); in TEST() local 10868 __ Fmul(s3, s15, s20); in TEST() local 10869 __ Fmul(s4, s16, s20); in TEST() local 10870 __ Fmul(s5, s15, s19); in TEST() local 10871 __ Fmul(s6, s19, s16); in TEST() local 10873 __ Fmul(d7, d30, d31); in TEST() local 10874 __ Fmul(d8, d29, d31); in TEST() local 10875 __ Fmul(d9, d26, d26); in TEST() local [all …]
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/external/v8/src/compiler/arm64/ |
D | code-generator-arm64.cc | 1313 __ Fmul(i.OutputFloat32Register(), i.InputFloat32Register(0), in AssembleArchInstruction() local 1348 __ Fmul(i.OutputDoubleRegister(), i.InputDoubleRegister(0), in AssembleArchInstruction() local
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/external/v8/src/arm64/ |
D | macro-assembler-arm64-inl.h | 695 void TurboAssembler::Fmul(const VRegister& fd, const VRegister& fn, in Fmul() function
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/external/v8/src/builtins/arm64/ |
D | builtins-arm64.cc | 3059 __ Fmul(scratch1_double, scratch1_double, scratch1_double); in Generate_MathPowInternal() local 3065 __ Fmul(result_double, result_double, scratch1_double); in Generate_MathPowInternal() local
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/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
D | LegalizeDAG.cpp | 2592 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt); in ExpandLegalINT_TO_FP() local
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/external/llvm/lib/CodeGen/SelectionDAG/ |
D | LegalizeDAG.cpp | 2411 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt); in ExpandLegalINT_TO_FP() local
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
D | LegalizeDAG.cpp | 2445 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt); in ExpandLegalINT_TO_FP() local
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/external/vixl/src/aarch64/ |
D | macro-assembler-aarch64.h | 1544 void Fmul(const VRegister& vd, const VRegister& vn, const VRegister& vm) { in Fmul() function
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