| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | LiveRegMatrix.cpp | 81 LiveInterval &VRegInterval, unsigned PhysReg, in foreachUnit()
104 void LiveRegMatrix::assign(LiveInterval &VirtReg, unsigned PhysReg) { in assign()
122 unsigned PhysReg = VRM->getPhys(VirtReg.reg); in unassign() local
147 unsigned PhysReg) { in checkRegMaskInterference()
165 unsigned PhysReg) { in checkRegUnitInterference()
186 LiveRegMatrix::checkInterference(LiveInterval &VirtReg, unsigned PhysReg) { in checkInterference()
210 unsigned PhysReg) { in checkInterference()
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| D | RegAllocFast.cpp | 87 MCPhysReg PhysReg = 0; ///< Currently held here. member
140 void markRegUsedInInstr(MCPhysReg PhysReg) { in markRegUsedInInstr()
377 unsigned PhysReg = MO.getReg(); in usePhysReg() local
441 MCPhysReg PhysReg, RegState NewState) { in definePhysReg()
528 void RegAllocFast::assignVirtToPhysReg(LiveReg &LR, MCPhysReg PhysReg) { in assignVirtToPhysReg()
537 RegAllocFast::assignVirtToPhysReg(unsigned VirtReg, MCPhysReg PhysReg) { in assignVirtToPhysReg()
569 for (MCPhysReg PhysReg : AO) { in allocVirtReg() local
581 for (MCPhysReg PhysReg : AO) { in allocVirtReg() local
700 MCPhysReg PhysReg) { in setPhysReg()
774 MCPhysReg PhysReg = LRI->PhysReg; in handleThroughOperands() local
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| D | RegAllocGreedy.cpp | 324 void addEviction(unsigned PhysReg, unsigned Evictor, unsigned Evictee) { in addEviction()
358 unsigned PhysReg; member
528 unsigned PhysReg; member
763 unsigned PhysReg; in tryAssign() local
807 unsigned PhysReg; in canReassign() local
868 bool RAGreedy::canEvictInterference(LiveInterval &VirtReg, unsigned PhysReg, in canEvictInterference()
958 unsigned PhysReg, SlotIndex Start, in canEvictInterferenceInRange()
1020 for (auto PhysReg : Order.getOrder()) { in getCheapestEvicteeWeight() local
1036 void RAGreedy::evictInterference(LiveInterval &VirtReg, unsigned PhysReg, in evictInterference()
1132 while (unsigned PhysReg = Order.next(OrderLimit)) { in tryEvict() local
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| D | RegisterClassInfo.cpp | 111 unsigned PhysReg = RawOrder[i]; in compute() local
133 unsigned PhysReg = CSRAlias[i]; in compute() local
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| D | ReachingDefAnalysis.cpp | 173 int ReachingDefAnalysis::getReachingDef(MachineInstr *MI, int PhysReg) { in getReachingDef()
192 int ReachingDefAnalysis::getClearance(MachineInstr *MI, MCPhysReg PhysReg) { in getClearance()
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| D | AllocationOrder.h | 91 bool isHint(unsigned PhysReg) const { return is_contained(Hints, PhysReg); } in isHint()
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| D | RegAllocBasic.cpp | 205 bool RABasic::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg, in spillInterferences()
264 while (unsigned PhysReg = Order.next()) { in selectOrSplit() local
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| D | InterferenceCache.h | 48 unsigned PhysReg = 0; variable
213 void setPhysReg(InterferenceCache &Cache, unsigned PhysReg) { in setPhysReg()
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| /external/llvm/lib/CodeGen/ |
| D | LiveRegMatrix.cpp | 75 unsigned PhysReg, Callable Func) { in foreachUnit()
97 void LiveRegMatrix::assign(LiveInterval &VirtReg, unsigned PhysReg) { in assign()
115 unsigned PhysReg = VRM->getPhys(VirtReg.reg); in unassign() local
140 unsigned PhysReg) { in checkRegMaskInterference()
158 unsigned PhysReg) { in checkRegUnitInterference()
179 LiveRegMatrix::checkInterference(LiveInterval &VirtReg, unsigned PhysReg) { in checkInterference()
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| D | RegAllocFast.cpp | 72 unsigned PhysReg; // Currently held here. member
123 void markRegUsedInInstr(unsigned PhysReg) { in markRegUsedInInstr()
349 unsigned PhysReg = MO.getReg(); in usePhysReg() local
416 void RAFast::definePhysReg(MachineInstr &MI, unsigned PhysReg, in definePhysReg()
507 void RAFast::assignVirtToPhysReg(LiveReg &LR, unsigned PhysReg) { in assignVirtToPhysReg()
516 RAFast::assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg) { in assignVirtToPhysReg()
556 unsigned PhysReg = *I; in allocVirtReg() local
685 bool RAFast::setPhysReg(MachineInstr *MI, unsigned OpNum, unsigned PhysReg) { in setPhysReg()
759 unsigned PhysReg = LRI->PhysReg; in handleThroughOperands() local
782 unsigned PhysReg = LRI->PhysReg; in handleThroughOperands() local
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| D | RegAllocGreedy.cpp | 263 unsigned PhysReg; member
411 unsigned PhysReg; member
622 unsigned PhysReg; in tryAssign() local
664 unsigned PhysReg; in canReassign() local
725 bool RAGreedy::canEvictInterference(LiveInterval &VirtReg, unsigned PhysReg, in canEvictInterference()
807 void RAGreedy::evictInterference(LiveInterval &VirtReg, unsigned PhysReg, in evictInterference()
894 while (unsigned PhysReg = Order.next(OrderLimit)) { in tryEvict() local
1390 while (unsigned PhysReg = Order.next()) { in calculateRegionSplitCost() local
1647 void RAGreedy::calcGapWeights(unsigned PhysReg, in calcGapWeights()
1810 while (unsigned PhysReg = Order.next()) { in tryLocalSplit() local
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| D | RegisterClassInfo.cpp | 99 unsigned PhysReg = RawOrder[i]; in compute() local
121 unsigned PhysReg = CSRAlias[i]; in compute() local
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| D | RegAllocBasic.cpp | 166 bool RABasic::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg, in spillInterferences()
227 while (unsigned PhysReg = Order.next()) { in selectOrSplit() local
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| D | AllocationOrder.h | 82 bool isHint(unsigned PhysReg) const { in isHint()
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| D | InterferenceCache.h | 42 unsigned PhysReg; variable
202 void setPhysReg(InterferenceCache &Cache, unsigned PhysReg) { in setPhysReg()
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| /external/swiftshader/third_party/llvm-7.0/llvm/tools/llvm-exegesis/lib/ |
| D | RegisterAliasing.cpp | 17 for (const size_t PhysReg : SourceBits.set_bits()) { in getAliasedBits() local
36 for (llvm::MCPhysReg PhysReg : RegClass) in RegisterAliasingTracker() local
43 const llvm::MCRegisterInfo &RegInfo, const llvm::MCPhysReg PhysReg) in RegisterAliasingTracker()
52 for (const size_t PhysReg : SourceBits.set_bits()) { in FillOriginAndAliasedBits() local
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | RegAllocBasic.cpp | 189 for (unsigned PhysReg = 0; PhysReg < PhysReg2LiveUnion.numRegs(); ++PhysReg) { in verify() local
205 unsigned PhysReg = VRM->getPhys(reg); in verify() local
276 void RegAllocBase::assign(LiveInterval &VirtReg, unsigned PhysReg) { in assign()
286 void RegAllocBase::unassign(LiveInterval &VirtReg, unsigned PhysReg) { in unassign()
368 unsigned PhysReg) { in checkPhysRegInterference()
377 void RegAllocBase::spillReg(LiveInterval& VirtReg, unsigned PhysReg, in spillReg()
406 RegAllocBase::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg, in spillInterferences()
437 for (unsigned PhysReg = 0; PhysReg < PhysReg2LiveUnion.numRegs(); ++PhysReg) { in addMBBLiveIns() local
492 unsigned PhysReg = *I; in selectOrSplit() local
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| D | RegisterClassInfo.h | 103 unsigned getLastCalleeSavedAlias(unsigned PhysReg) const { in getLastCalleeSavedAlias()
115 bool isReserved(unsigned PhysReg) const { in isReserved()
125 bool isAllocatable(unsigned PhysReg) const { in isAllocatable()
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| D | RegAllocGreedy.cpp | 184 unsigned PhysReg; member
359 if (unsigned PhysReg = VRM->getPhys(VirtReg)) { in LRE_CanEraseVirtReg() local
369 unsigned PhysReg = VRM->getPhys(VirtReg); in LRE_WillShrinkVirtReg() local
448 unsigned PhysReg; in tryAssign() local
521 bool RAGreedy::canEvictInterference(LiveInterval &VirtReg, unsigned PhysReg, in canEvictInterference()
582 void RAGreedy::evictInterference(LiveInterval &VirtReg, unsigned PhysReg, in evictInterference()
631 while (unsigned PhysReg = Order.next()) { in tryEvict() local
1106 while (unsigned PhysReg = Order.next()) { in tryRegionSplit() local
1267 void RAGreedy::calcGapWeights(unsigned PhysReg, in calcGapWeights()
1373 while (unsigned PhysReg = Order.next()) { in tryLocalSplit() local
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| D | RegAllocFast.cpp | 74 unsigned PhysReg; // Currently held here. member
325 unsigned PhysReg = MO.getReg(); in usePhysReg() local
383 void RAFast::definePhysReg(MachineInstr *MI, unsigned PhysReg, in definePhysReg()
470 void RAFast::assignVirtToPhysReg(LiveRegEntry &LRE, unsigned PhysReg) { in assignVirtToPhysReg()
507 unsigned PhysReg = *I; in allocVirtReg() local
627 bool RAFast::setPhysReg(MachineInstr *MI, unsigned OpNum, unsigned PhysReg) { in setPhysReg()
697 unsigned PhysReg = LRI->second.PhysReg; in handleThroughOperands() local
710 unsigned PhysReg = LRI->second.PhysReg; in handleThroughOperands() local
935 unsigned PhysReg = LRI->second.PhysReg; in AllocateBasicBlock() local
991 unsigned PhysReg = LRI->second.PhysReg; in AllocateBasicBlock() local
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| D | VirtRegRewriter.cpp | 288 unsigned PhysReg, in ComputeReloadLoc()
406 void markClobbered(unsigned PhysReg) { in markClobbered()
437 unsigned GetRegForReload(unsigned VirtReg, unsigned PhysReg, MachineInstr *MI, in GetRegForReload()
723 void AvailableSpills::disallowClobberPhysRegOnly(unsigned PhysReg) { in disallowClobberPhysRegOnly()
740 void AvailableSpills::disallowClobberPhysReg(unsigned PhysReg) { in disallowClobberPhysReg()
748 void AvailableSpills::ClobberPhysRegOnly(unsigned PhysReg) { in ClobberPhysRegOnly()
769 void AvailableSpills::ClobberPhysReg(unsigned PhysReg) { in ClobberPhysReg()
866 unsigned PhysReg, in GetRegForReload()
980 static bool FoldsStackSlotModRef(MachineInstr &MI, int SS, unsigned PhysReg, in FoldsStackSlotModRef()
1076 void AssignPhysToVirtReg(MachineInstr *MI, unsigned VirtReg, unsigned PhysReg, in AssignPhysToVirtReg()
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| D | AllocationOrder.h | 68 bool isHint(unsigned PhysReg) const { return PhysReg == Hint; } in isHint()
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| D | InterferenceCache.h | 40 unsigned PhysReg; variable
169 void setPhysReg(InterferenceCache &Cache, unsigned PhysReg) { in setPhysReg()
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| D | RegisterClassInfo.cpp | 86 unsigned PhysReg = RawOrder[i]; in compute() local
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| D | RegAllocBase.h | 113 LiveIntervalUnion::Query &query(LiveInterval &VirtReg, unsigned PhysReg) { in query()
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