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1 //===-- RegisterClassInfo.cpp - Dynamic Register Class Info ---------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the RegisterClassInfo class which provides dynamic
11 // information about target register classes. Callee saved and reserved
12 // registers depends on calling conventions and other dynamic information, so
13 // some things cannot be determined statically.
14 //
15 //===----------------------------------------------------------------------===//
16 
17 #define DEBUG_TYPE "regalloc"
18 #include "RegisterClassInfo.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/Target/TargetMachine.h"
21 
22 #include "llvm/Support/Debug.h"
23 #include "llvm/Support/raw_ostream.h"
24 
25 using namespace llvm;
26 
RegisterClassInfo()27 RegisterClassInfo::RegisterClassInfo() : Tag(0), MF(0), TRI(0), CalleeSaved(0)
28 {}
29 
runOnMachineFunction(const MachineFunction & mf)30 void RegisterClassInfo::runOnMachineFunction(const MachineFunction &mf) {
31   bool Update = false;
32   MF = &mf;
33 
34   // Allocate new array the first time we see a new target.
35   if (MF->getTarget().getRegisterInfo() != TRI) {
36     TRI = MF->getTarget().getRegisterInfo();
37     RegClass.reset(new RCInfo[TRI->getNumRegClasses()]);
38     Update = true;
39   }
40 
41   // Does this MF have different CSRs?
42   const unsigned *CSR = TRI->getCalleeSavedRegs(MF);
43   if (Update || CSR != CalleeSaved) {
44     // Build a CSRNum map. Every CSR alias gets an entry pointing to the last
45     // overlapping CSR.
46     CSRNum.clear();
47     CSRNum.resize(TRI->getNumRegs(), 0);
48     for (unsigned N = 0; unsigned Reg = CSR[N]; ++N)
49       for (const unsigned *AS = TRI->getOverlaps(Reg);
50            unsigned Alias = *AS; ++AS)
51         CSRNum[Alias] = N + 1; // 0 means no CSR, 1 means CalleeSaved[0], ...
52     Update = true;
53   }
54   CalleeSaved = CSR;
55 
56   // Different reserved registers?
57   BitVector RR = TRI->getReservedRegs(*MF);
58   if (RR != Reserved)
59     Update = true;
60   Reserved = RR;
61 
62   // Invalidate cached information from previous function.
63   if (Update)
64     ++Tag;
65 }
66 
67 /// compute - Compute the preferred allocation order for RC with reserved
68 /// registers filtered out. Volatile registers come first followed by CSR
69 /// aliases ordered according to the CSR order specified by the target.
compute(const TargetRegisterClass * RC) const70 void RegisterClassInfo::compute(const TargetRegisterClass *RC) const {
71   RCInfo &RCI = RegClass[RC->getID()];
72 
73   // Raw register count, including all reserved regs.
74   unsigned NumRegs = RC->getNumRegs();
75 
76   if (!RCI.Order)
77     RCI.Order.reset(new unsigned[NumRegs]);
78 
79   unsigned N = 0;
80   SmallVector<unsigned, 16> CSRAlias;
81 
82   // FIXME: Once targets reserve registers instead of removing them from the
83   // allocation order, we can simply use begin/end here.
84   ArrayRef<unsigned> RawOrder = RC->getRawAllocationOrder(*MF);
85   for (unsigned i = 0; i != RawOrder.size(); ++i) {
86     unsigned PhysReg = RawOrder[i];
87     // Remove reserved registers from the allocation order.
88     if (Reserved.test(PhysReg))
89       continue;
90     if (CSRNum[PhysReg])
91       // PhysReg aliases a CSR, save it for later.
92       CSRAlias.push_back(PhysReg);
93     else
94       RCI.Order[N++] = PhysReg;
95   }
96   RCI.NumRegs = N + CSRAlias.size();
97   assert (RCI.NumRegs <= NumRegs && "Allocation order larger than regclass");
98 
99   // CSR aliases go after the volatile registers, preserve the target's order.
100   std::copy(CSRAlias.begin(), CSRAlias.end(), &RCI.Order[N]);
101 
102   // Check if RC is a proper sub-class.
103   if (const TargetRegisterClass *Super = TRI->getLargestLegalSuperClass(RC))
104     if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs)
105       RCI.ProperSubClass = true;
106 
107   DEBUG({
108     dbgs() << "AllocationOrder(" << RC->getName() << ") = [";
109     for (unsigned I = 0; I != RCI.NumRegs; ++I)
110       dbgs() << ' ' << PrintReg(RCI.Order[I], TRI);
111     dbgs() << (RCI.ProperSubClass ? " ] (sub-class)\n" : " ]\n");
112   });
113 
114   // RCI is now up-to-date.
115   RCI.Tag = Tag;
116 }
117 
118