| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | RegisterScavenging.h | 141 void setUsed(BitVector &Regs) { in setUsed()
144 void setUnused(BitVector &Regs) { in setUnused()
|
| D | CallingConvLower.h | 232 unsigned getFirstUnallocated(const unsigned *Regs, unsigned NumRegs) const { in getFirstUnallocated()
259 unsigned AllocateReg(const unsigned *Regs, unsigned NumRegs) { in AllocateReg()
271 unsigned AllocateReg(const unsigned *Regs, const unsigned *ShadowRegs, in AllocateReg()
|
| /external/syzkaller/vendor/golang.org/x/sys/unix/ |
| D | zptracemipsle_linux.go | 12 Regs [32]uint64 member
33 Regs [32]uint64 member
|
| D | zptracemips_linux.go | 12 Regs [32]uint64 member
33 Regs [32]uint64 member
|
| D | zptracearm_linux.go | 27 Regs [31]uint64 member
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/Disassembler/ |
| D | SystemZDisassembler.cpp | 84 const unsigned *Regs, unsigned Size) { in decodeRegisterClass()
293 const unsigned *Regs) { in decodeBDAddr12Operand()
303 const unsigned *Regs) { in decodeBDAddr20Operand()
313 const unsigned *Regs) { in decodeBDXAddr12Operand()
325 const unsigned *Regs) { in decodeBDXAddr20Operand()
337 const unsigned *Regs) { in decodeBDLAddr12Len4Operand()
349 const unsigned *Regs) { in decodeBDLAddr12Len8Operand()
361 const unsigned *Regs) { in decodeBDRAddr12Operand()
373 const unsigned *Regs) { in decodeBDVAddr12Operand()
|
| /external/capstone/arch/SystemZ/ |
| D | SystemZDisassembler.c | 37 static DecodeStatus decodeRegisterClass(MCInst *Inst, uint64_t RegNo, const unsigned *Regs) in decodeRegisterClass()
186 const unsigned *Regs) in decodeBDAddr12Operand()
199 const unsigned *Regs) in decodeBDAddr20Operand()
211 const unsigned *Regs) in decodeBDXAddr12Operand()
226 const unsigned *Regs) in decodeBDXAddr20Operand()
241 const unsigned *Regs) in decodeBDLAddr12Len8Operand()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/tools/llvm-mca/ |
| D | HWEventListener.h | 73 HWInstructionDispatchedEvent(const InstRef &IR, llvm::ArrayRef<unsigned> Regs) in HWInstructionDispatchedEvent()
83 HWInstructionRetiredEvent(const InstRef &IR, llvm::ArrayRef<unsigned> Regs) in HWInstructionRetiredEvent()
|
| /external/llvm/lib/Target/SystemZ/Disassembler/ |
| D | SystemZDisassembler.cpp | 78 const unsigned *Regs, unsigned Size) { in decodeRegisterClass()
269 const unsigned *Regs) { in decodeBDAddr12Operand()
279 const unsigned *Regs) { in decodeBDAddr20Operand()
289 const unsigned *Regs) { in decodeBDXAddr12Operand()
301 const unsigned *Regs) { in decodeBDXAddr20Operand()
313 const unsigned *Regs) { in decodeBDLAddr12Len8Operand()
325 const unsigned *Regs) { in decodeBDVAddr12Operand()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86CallLowering.cpp | 205 [&](ArrayRef<unsigned> Regs) { in lowerReturn()
346 [&](ArrayRef<unsigned> Regs) { in lowerFormalArguments()
406 [&](ArrayRef<unsigned> Regs) { in lowerCall()
452 [&](ArrayRef<unsigned> Regs) { in lowerCall()
|
| /external/llvm/include/llvm/CodeGen/ |
| D | CallingConvLower.h | 332 unsigned getFirstUnallocated(ArrayRef<MCPhysReg> Regs) const { in getFirstUnallocated()
359 unsigned AllocateReg(ArrayRef<MCPhysReg> Regs) { in AllocateReg()
373 unsigned AllocateRegBlock(ArrayRef<MCPhysReg> Regs, unsigned RegsRequired) { in AllocateRegBlock()
400 unsigned AllocateReg(ArrayRef<MCPhysReg> Regs, const MCPhysReg *ShadowRegs) { in AllocateReg()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | CallingConvLower.h | 343 unsigned getFirstUnallocated(ArrayRef<MCPhysReg> Regs) const { in getFirstUnallocated()
370 unsigned AllocateReg(ArrayRef<MCPhysReg> Regs) { in AllocateReg()
384 unsigned AllocateRegBlock(ArrayRef<MCPhysReg> Regs, unsigned RegsRequired) { in AllocateRegBlock()
411 unsigned AllocateReg(ArrayRef<MCPhysReg> Regs, const MCPhysReg *ShadowRegs) { in AllocateReg()
|
| /external/llvm/utils/TableGen/ |
| D | RegisterInfoEmitter.cpp | 200 const CodeGenRegister::Vec &Regs = RC.getMembers(); in EmitRegUnitPressure() local
338 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { in EmitRegMappingTables()
461 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { in EmitRegMapping()
822 const auto &Regs = RegBank.getRegisters(); in runMCDesc() local
1361 const auto &Regs = RegBank.getRegisters(); in runTargetDesc() local
1459 const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet); in runTargetDesc() local
|
| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyRegisterInfo.cpp | 127 static const unsigned Regs[2][2] = { in getFrameRegister() local
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SIFixWWMLiveness.cpp | 118 void SIFixWWMLiveness::addDefs(const MachineInstr &MI, SparseBitVector<> &Regs) in addDefs()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/ |
| D | RegisterInfoEmitter.cpp | 205 const CodeGenRegister::Vec &Regs = RC.getMembers(); in EmitRegUnitPressure() local
344 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { in EmitRegMappingTables()
467 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { in EmitRegMapping()
831 const auto &Regs = RegBank.getRegisters(); in runMCDesc() local
1403 const auto &Regs = RegBank.getRegisters(); in runTargetDesc() local
1503 const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet); in runTargetDesc() local
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyRegisterInfo.cpp | 133 static const unsigned Regs[2][2] = { in getFrameRegister() local
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/GlobalISel/ |
| D | IRTranslator.cpp | 147 auto *Regs = VMap.getVRegs(Val); in allocateVRegs() local
432 ArrayRef<unsigned> Regs = getOrCreateVRegs(LI); in translateLoad() local
559 auto &Regs = *VMap.getVRegs(U); in translateBitCast() local
939 ArrayRef<unsigned> Regs = getOrCreateVRegs(V); in packRegs() local
958 ArrayRef<unsigned> Regs = getOrCreateVRegs(V); in unpackRegs() local
1247 auto &Regs = *VMap.getVRegs(U); in translateInsertElement() local
1271 auto &Regs = *VMap.getVRegs(U); in translateExtractElement() local
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | RDFRegisters.cpp | 325 auto AliasedRegs = [this] (uint32_t Unit, BitVector &Regs) { in makeRegRef()
335 BitVector Regs(PRI.getTRI().getNumRegs()); in makeRegRef() local
|
| /external/swiftshader/third_party/LLVM/utils/TableGen/ |
| D | RegisterInfoEmitter.cpp | 99 const std::vector<CodeGenRegister*> &Regs, in EmitRegMapping()
262 const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters(); in runMCDesc() local
677 const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters(); in runTargetDesc() local
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 972 SDValue AArch64DAGToDAGISel::createDTuple(ArrayRef<SDValue> Regs) { in createDTuple()
981 SDValue AArch64DAGToDAGISel::createQTuple(ArrayRef<SDValue> Regs) { in createQTuple()
990 SDValue AArch64DAGToDAGISel::createTuple(ArrayRef<SDValue> Regs, in createTuple()
1028 SmallVector<SDValue, 4> Regs(N->op_begin() + Vec0Off, in SelectTable() local
1194 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs); in SelectStore() local
1212 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs); in SelectPostStore() local
1266 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs); in SelectLoadLane() local
1305 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs); in SelectPostLoadLane() local
1360 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs); in SelectStoreLane() local
1390 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs); in SelectPostStoreLane() local
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 1029 SDValue AArch64DAGToDAGISel::createDTuple(ArrayRef<SDValue> Regs) { in createDTuple()
1038 SDValue AArch64DAGToDAGISel::createQTuple(ArrayRef<SDValue> Regs) { in createQTuple()
1047 SDValue AArch64DAGToDAGISel::createTuple(ArrayRef<SDValue> Regs, in createTuple()
1085 SmallVector<SDValue, 4> Regs(N->op_begin() + Vec0Off, in SelectTable() local
1257 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs); in SelectStore() local
1280 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs); in SelectPostStore() local
1334 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs); in SelectLoadLane() local
1373 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs); in SelectPostLoadLane() local
1428 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs); in SelectStoreLane() local
1458 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs); in SelectPostStoreLane() local
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMCallLowering.cpp | 255 SmallVector<unsigned, 4> Regs; in lowerReturnVal() local
543 SmallVector<unsigned, 8> Regs; in lowerCall() local
|
| /external/llvm/lib/CodeGen/AsmPrinter/ |
| D | DbgValueHistoryCalculator.cpp | 153 BitVector &Regs) { in collectChangingRegs()
|
| /external/llvm/lib/CodeGen/ |
| D | MachineCopyPropagation.cpp | 86 static void removeRegsFromMap(Reg2MIMap &Map, const RegList &Regs, in removeRegsFromMap()
|