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Searched defs:Rs (Results 1 – 25 of 46) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/Disassembler/
DMipsDisassembler.cpp634 InsnType Rs = fieldFromInstruction(insn, 16, 5); in DecodeDAHIDATIMMR6() local
648 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeDAHIDATI() local
673 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeAddiGroupBranch() local
703 InsnType Rs = fieldFromInstruction(insn, 16, 5); in DecodePOP35GroupBranchMMR6() local
746 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeDaddiGroupBranch() local
776 InsnType Rs = fieldFromInstruction(insn, 16, 5); in DecodePOP37GroupBranchMMR6() local
817 InsnType Rs = fieldFromInstruction(insn, 16, 5); in DecodePOP65GroupBranchMMR6() local
856 InsnType Rs = fieldFromInstruction(insn, 16, 5); in DecodePOP75GroupBranchMMR6() local
898 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeBlezlGroupBranch() local
943 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeBgtzlGroupBranch() local
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/external/swiftshader/third_party/subzero/src/
DIceAssemblerMIPS32.cpp209 const IValueT Rs = encodeGPRegister(OpRs, "Rs", InsnName); in emitRsRt() local
222 const IValueT Rs = encodeGPRegister(OpRs, "Rs", InsnName); in emitRtRsImm16() local
237 const IValueT Rs = encodeGPRegister(OpRs, "Rs", InsnName); in emitRtRsImm16Rel() local
259 const IValueT Rs = encodeGPRegister(OpRs, "Rs", InsnName); in emitFtRsImm16() local
285 const IValueT Rs = encodeGPRegister(OpRs, "Rs", InsnName); in emitRdRsRt() local
528 const IValueT Rs = encodeGPRegister(OpRs, "Rs", "clz"); in clz() local
656 const IValueT Rs = encodeGPRegister(OpRs, "Rs", "jalr"); in jalr() local
820 const IValueT Rs = encodeGPRegister(OpRs, "Rs", "pseudo-move"); in move() local
837 const IValueT Rs = encodeGPRegister(OpRs, "Rs", "movf"); in movf() local
872 const IValueT Rs = encodeGPRegister(OpRs, "Rs", "movt"); in movt() local
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DIceAssemblerARM32.cpp344 IValueT Rs) { in encodeShiftRotateReg()
393 IValueT Rs; in encodeOperand() local
1128 IValueT Rn, IValueT Rm, IValueT Rs, in emitMulOp()
1717 IValueT Rs = encodeGPRegister(OpSrc1, "Rs", InstName); in emitShift() local
/external/llvm/lib/Target/Mips/Disassembler/
DMipsDisassembler.cpp602 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeAddiGroupBranch() local
632 InsnType Rs = fieldFromInstruction(insn, 16, 5); in DecodePOP35GroupBranchMMR6() local
672 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeDaddiGroupBranch() local
702 InsnType Rs = fieldFromInstruction(insn, 16, 5); in DecodePOP37GroupBranchMMR6() local
743 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeBlezlGroupBranch() local
788 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeBgtzlGroupBranch() local
830 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeBgtzGroupBranch() local
879 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeBlezGroupBranch() local
2287 InsnType Rs = fieldFromInstruction(insn, 16, 5); in DecodeBgtzGroupBranchMMR6() local
2333 InsnType Rs = fieldFromInstruction(insn, 16, 5); in DecodeBlezGroupBranchMMR6() local
/external/capstone/arch/Mips/
DMipsDisassembler.c536 uint32_t Rs = fieldFromInstruction(insn, 21, 5); in DecodeAddiGroupBranch_4() local
572 uint32_t Rs = fieldFromInstruction(insn, 21, 5); in DecodeDaddiGroupBranch_4() local
609 uint32_t Rs = fieldFromInstruction(insn, 21, 5); in DecodeBlezlGroupBranch_4() local
651 uint32_t Rs = fieldFromInstruction(insn, 21, 5); in DecodeBgtzlGroupBranch_4() local
689 uint32_t Rs = fieldFromInstruction(insn, 21, 5); in DecodeBgtzGroupBranch_4() local
735 uint32_t Rs = fieldFromInstruction(insn, 21, 5); in DecodeBlezGroupBranch_4() local
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/AsmParser/
DHexagonAsmParser.cpp1620 MCOperand &Rs = Inst.getOperand(2); in processInstruction() local
1640 MCOperand &Rs = Inst.getOperand(2); in processInstruction() local
1660 MCOperand &Rs = Inst.getOperand(2); in processInstruction() local
1683 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
1716 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
1726 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
1768 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
1785 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
1914 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/
DRISCVMergeBaseOffset.cpp139 unsigned Rs = TailAdd.getOperand(1).getReg(); in matchLargeOffset() local
/external/llvm/lib/Target/Hexagon/AsmParser/
DHexagonAsmParser.cpp1844 MCOperand &Rs = Inst.getOperand(2); in processInstruction() local
1863 MCOperand &Rs = Inst.getOperand(2); in processInstruction() local
1882 MCOperand &Rs = Inst.getOperand(2); in processInstruction() local
1904 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
1943 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
1953 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
1995 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
2014 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
2151 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonSplitDouble.cpp148 const USet &Rs = I.second; in isInduction() local
376 unsigned Rs = MI->getOperand(1).getReg(); in profit() local
478 USet &Rs) { in collectIndRegsForLoop()
585 USet Rs; in collectIndRegs() local
DHexagonConstExtenders.cpp292 Register Rs; member
445 HCE::Register Rs; member
1500 Register Rs = ExtI.second.Rs; // Only one reg allowed now. in calculatePlacement() local
1770 Register Rs = MI.getOperand(IsSub ? 3 : 2); in replaceInstrExpr() local
DHexagonAsmPrinter.cpp417 MCOperand &Rs = Inst.getOperand(1); in HexagonProcessInstruction() local
DHexagonBitTracker.cpp291 uint16_t BW, bool Odd) -> BT::RegisterCell { in evaluate()
DHexagonBitSimplify.cpp1887 const BitTracker::RegisterCell &RC, BitTracker::RegisterRef &Rs, in matchPackhl()
2017 BitTracker::RegisterRef Rs, Rt; in genPackhl() local
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCCompound.cpp202 MCOperand Rs, Rt; in getCompoundInsn() local
/external/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCCompound.cpp207 MCOperand Rs, Rt; in getCompoundInsn() local
/external/llvm/lib/Target/Hexagon/
DHexagonSplitDouble.cpp122 const USet &Rs = I.second; in isInduction() local
431 USet &Rs) { in collectIndRegsForLoop()
537 USet Rs; in collectIndRegs() local
DHexagonAsmPrinter.cpp365 MCOperand &Rs = Inst.getOperand(1); in HexagonProcessInstruction() local
DHexagonBitTracker.cpp225 uint16_t BW, bool Odd) -> BT::RegisterCell { in evaluate()
DHexagonBitSimplify.cpp1782 const BitTracker::RegisterCell &RC, BitTracker::RegisterRef &Rs, in matchPackhl()
1914 BitTracker::RegisterRef Rs, Rt; in genPackhl() local
/external/eigen/Eigen/src/UmfPackSupport/
DUmfPackSupport.h109 … int P[], int Q[], double Dx[], int *do_recip, double Rs[], void *Numeric) in umfpack_get_numeric()
115 … int P[], int Q[], std::complex<double> Dx[], int *do_recip, double Rs[], void *Numeric) in umfpack_get_numeric()
/external/mesa3d/src/mesa/swrast/
Ds_blend.c480 const GLfloat Rs = rgba[i][RCOMP]; in blend_general_float() local
/external/vixl/src/aarch64/
Dassembler-aarch64.h3565 static Instr Rs(CPURegister rs) { in Rs() function
/external/capstone/arch/AArch64/
DAArch64Disassembler.c1196 unsigned Rs = fieldFromInstruction(insn, 16, 5); in DecodeExclusiveLdStInstruction() local
/external/llvm/lib/Target/AArch64/Disassembler/
DAArch64Disassembler.cpp1087 unsigned Rs = fieldFromInstruction(insn, 16, 5); in DecodeExclusiveLdStInstruction() local
/external/v8/src/arm64/
Dassembler-arm64.h2913 static Instr Rs(CPURegister rs) { in Rs() function

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