| /art/compiler/optimizing/ |
| D | code_generator_mips.cc | 2255 __ Sltu(TMP, dst_low, (dst_low == rhs_low) ? lhs_low : rhs_low); in HandleBinaryOp() local
2261 __ Sltu(TMP, lhs_low, rhs_low); in HandleBinaryOp() local
2349 __ Sltu(AT, dst_low, TMP); in HandleBinaryOp() local
3704 __ Sltu(TMP, lhs_low, rhs_low); in VisitCompare() local
3705 __ Sltu(AT, rhs_low, lhs_low); // Inverted: is actually gt. in VisitCompare() local
3877 __ Sltu(AT, ZERO, out_low); in DivRemOneOrMinusOne() local
3960 __ Sltu(TMP, AT, in_low); in DivRemByPowerOfTwo() local
3973 __ Sltu(AT, ZERO, out_low); in DivRemByPowerOfTwo() local
3980 __ Sltu(AT, AT, in_low); in DivRemByPowerOfTwo() local
3985 __ Sltu(AT, ZERO, out_low); in DivRemByPowerOfTwo() local
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| D | code_generator_mips64.cc | 3763 __ Sltu(dst, ZERO, lhs); in GenerateIntLongCompare() local
3774 __ Sltu(dst, ZERO, dst); in GenerateIntLongCompare() local
3790 __ Sltu(dst, ZERO, dst); in GenerateIntLongCompare() local
3850 __ Sltu(dst, lhs, rhs_reg); in GenerateIntLongCompare() local
3880 __ Sltu(dst, rhs_reg, lhs); in GenerateIntLongCompare() local
3972 __ Sltu(dst, lhs, rhs_reg); in MaterializeIntLongCompare() local
3993 __ Sltu(dst, rhs_reg, lhs); in MaterializeIntLongCompare() local
4740 __ Sltu(TMP, ZERO, cond_reg); in GenConditionalMove() local
4775 __ Sltu(TMP, ZERO, cond_reg); in GenConditionalMove() local
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| D | intrinsics_mips.cc | 1827 __ Sltu(out, ZERO, out); in GenIsInfinite() local
2642 __ Sltu(AT, out, AT); in VisitIntegerValueOf() local
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| D | intrinsics_mips64.cc | 1669 __ Sltu(out, ZERO, out); in GenIsInfinite() local
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| /art/compiler/utils/mips/ |
| D | assembler_mips_test.cc | 604 TEST_F(AssemblerMIPSTest, Sltu) { in TEST_F() argument
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| D | assembler_mips.cc | 856 void MipsAssembler::Sltu(Register rd, Register rs, Register rt) { in Sltu() function in art::mips::MipsAssembler
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| /art/compiler/utils/mips64/ |
| D | assembler_mips64_test.cc | 1297 TEST_F(AssemblerMIPS64Test, Sltu) { in TEST_F() argument
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| D | assembler_mips64.cc | 676 void Mips64Assembler::Sltu(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Sltu() function in art::mips64::Mips64Assembler
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