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Searched defs:VirtReg (Results 1 – 25 of 49) sorted by relevance

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/external/llvm/lib/CodeGen/
DLiveRegMatrix.cpp97 void LiveRegMatrix::assign(LiveInterval &VirtReg, unsigned PhysReg) { in assign()
114 void LiveRegMatrix::unassign(LiveInterval &VirtReg) { in unassign()
139 bool LiveRegMatrix::checkRegMaskInterference(LiveInterval &VirtReg, in checkRegMaskInterference()
157 bool LiveRegMatrix::checkRegUnitInterference(LiveInterval &VirtReg, in checkRegUnitInterference()
171 LiveIntervalUnion::Query &LiveRegMatrix::query(LiveInterval &VirtReg, in query()
179 LiveRegMatrix::checkInterference(LiveInterval &VirtReg, unsigned PhysReg) { in checkInterference()
DRegAllocFast.cpp71 unsigned VirtReg; // Virtual register number. member
184 LiveRegMap::iterator findLiveVirtReg(unsigned VirtReg) { in findLiveVirtReg()
205 int RAFast::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) { in getStackSpaceFor()
260 void RAFast::killVirtReg(unsigned VirtReg) { in killVirtReg()
270 void RAFast::spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg) { in spillVirtReg()
419 switch (unsigned VirtReg = PhysRegState[PhysReg]) { in definePhysReg() local
435 switch (unsigned VirtReg = PhysRegState[Alias]) { in definePhysReg() local
462 switch (unsigned VirtReg = PhysRegState[PhysReg]) { in calcSpillCost() local
483 switch (unsigned VirtReg = PhysRegState[Alias]) { in calcSpillCost() local
516 RAFast::assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg) { in assignVirtToPhysReg()
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DRegAllocGreedy.cpp216 void setStage(const LiveInterval &VirtReg, LiveRangeStage Stage) { in setStage()
494 bool RAGreedy::LRE_CanEraseVirtReg(unsigned VirtReg) { in LRE_CanEraseVirtReg()
506 void RAGreedy::LRE_WillShrinkVirtReg(unsigned VirtReg) { in LRE_WillShrinkVirtReg()
618 unsigned RAGreedy::tryAssign(LiveInterval &VirtReg, in tryAssign()
662 unsigned RAGreedy::canReassign(LiveInterval &VirtReg, unsigned PrevReg) { in canReassign()
725 bool RAGreedy::canEvictInterference(LiveInterval &VirtReg, unsigned PhysReg, in canEvictInterference()
807 void RAGreedy::evictInterference(LiveInterval &VirtReg, unsigned PhysReg, in evictInterference()
858 unsigned RAGreedy::tryEvict(LiveInterval &VirtReg, in tryEvict()
1353 unsigned RAGreedy::tryRegionSplit(LiveInterval &VirtReg, AllocationOrder &Order, in tryRegionSplit()
1383 unsigned RAGreedy::calculateRegionSplitCost(LiveInterval &VirtReg, in calculateRegionSplitCost()
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DLiveIntervalUnion.cpp29 void LiveIntervalUnion::unify(LiveInterval &VirtReg, const LiveRange &Range) { in unify()
56 void LiveIntervalUnion::extract(LiveInterval &VirtReg, const LiveRange &Range) { in extract()
DVirtRegMap.cpp82 bool VirtRegMap::hasPreferredPhys(unsigned VirtReg) { in hasPreferredPhys()
91 bool VirtRegMap::hasKnownPreference(unsigned VirtReg) { in hasKnownPreference()
291 unsigned VirtReg = TargetRegisterInfo::index2VirtReg(Idx); in addMBBLiveIns() local
398 unsigned VirtReg = MO.getReg(); in rewrite() local
DAllocationOrder.cpp30 AllocationOrder::AllocationOrder(unsigned VirtReg, in AllocationOrder()
DRegAllocBasic.cpp166 bool RABasic::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg, in spillInterferences()
220 unsigned RABasic::selectOrSplit(LiveInterval &VirtReg, in selectOrSplit()
DRegAllocBase.cpp85 while (LiveInterval *VirtReg = dequeue()) { in allocatePhysRegs() local
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DLiveRegMatrix.cpp104 void LiveRegMatrix::assign(LiveInterval &VirtReg, unsigned PhysReg) { in assign()
121 void LiveRegMatrix::unassign(LiveInterval &VirtReg) { in unassign()
146 bool LiveRegMatrix::checkRegMaskInterference(LiveInterval &VirtReg, in checkRegMaskInterference()
164 bool LiveRegMatrix::checkRegUnitInterference(LiveInterval &VirtReg, in checkRegUnitInterference()
186 LiveRegMatrix::checkInterference(LiveInterval &VirtReg, unsigned PhysReg) { in checkInterference()
DRegAllocFast.cpp86 unsigned VirtReg; ///< Virtual register number. member
201 LiveRegMap::iterator findLiveVirtReg(unsigned VirtReg) { in findLiveVirtReg()
231 int RegAllocFast::getStackSpaceFor(unsigned VirtReg, in getStackSpaceFor()
295 void RegAllocFast::killVirtReg(unsigned VirtReg) { in killVirtReg()
306 unsigned VirtReg) { in spillVirtReg()
443 switch (unsigned VirtReg = PhysRegState[PhysReg]) { in definePhysReg() local
459 switch (unsigned VirtReg = PhysRegState[Alias]) { in definePhysReg() local
485 switch (unsigned VirtReg = PhysRegState[PhysReg]) { in calcSpillCost() local
506 switch (unsigned VirtReg = PhysRegState[Alias]) { in calcSpillCost() local
537 RegAllocFast::assignVirtToPhysReg(unsigned VirtReg, MCPhysReg PhysReg) { in assignVirtToPhysReg()
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DRegAllocGreedy.cpp260 void setStage(const LiveInterval &VirtReg, LiveRangeStage Stage) { in setStage()
633 bool RAGreedy::LRE_CanEraseVirtReg(unsigned VirtReg) { in LRE_CanEraseVirtReg()
648 void RAGreedy::LRE_WillShrinkVirtReg(unsigned VirtReg) { in LRE_WillShrinkVirtReg()
759 unsigned RAGreedy::tryAssign(LiveInterval &VirtReg, in tryAssign()
805 unsigned RAGreedy::canReassign(LiveInterval &VirtReg, unsigned PrevReg) { in canReassign()
868 bool RAGreedy::canEvictInterference(LiveInterval &VirtReg, unsigned PhysReg, in canEvictInterference()
957 bool RAGreedy::canEvictInterferenceInRange(LiveInterval &VirtReg, in canEvictInterferenceInRange()
1011 LiveInterval &VirtReg, in getCheapestEvicteeWeight()
1036 void RAGreedy::evictInterference(LiveInterval &VirtReg, unsigned PhysReg, in evictInterference()
1094 unsigned RAGreedy::tryEvict(LiveInterval &VirtReg, in tryEvict()
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DRegAllocBasic.cpp160 void RABasic::LRE_WillShrinkVirtReg(unsigned VirtReg) { in LRE_WillShrinkVirtReg()
205 bool RABasic::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg, in spillInterferences()
257 unsigned RABasic::selectOrSplit(LiveInterval &VirtReg, in selectOrSplit()
DLiveIntervalUnion.cpp30 void LiveIntervalUnion::unify(LiveInterval &VirtReg, const LiveRange &Range) { in unify()
57 void LiveIntervalUnion::extract(LiveInterval &VirtReg, const LiveRange &Range) { in extract()
DAllocationOrder.cpp30 AllocationOrder::AllocationOrder(unsigned VirtReg, in AllocationOrder()
DVirtRegMap.cpp103 bool VirtRegMap::hasPreferredPhys(unsigned VirtReg) { in hasPreferredPhys()
112 bool VirtRegMap::hasKnownPreference(unsigned VirtReg) { in hasKnownPreference()
316 unsigned VirtReg = TargetRegisterInfo::index2VirtReg(Idx); in addMBBLiveIns() local
519 unsigned VirtReg = MO.getReg(); in rewrite() local
DRegAllocBase.cpp89 while (LiveInterval *VirtReg = dequeue()) { in allocatePhysRegs() local
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DRegAllocBasic.cpp268 LiveInterval &VirtReg = *I->second; in seedLiveRegs() local
276 void RegAllocBase::assign(LiveInterval &VirtReg, unsigned PhysReg) { in assign()
286 void RegAllocBase::unassign(LiveInterval &VirtReg, unsigned PhysReg) { in unassign()
301 while (LiveInterval *VirtReg = dequeue()) { in allocatePhysRegs() local
367 unsigned RegAllocBase::checkPhysRegInterference(LiveInterval &VirtReg, in checkPhysRegInterference()
377 void RegAllocBase::spillReg(LiveInterval& VirtReg, unsigned PhysReg, in spillReg()
406 RegAllocBase::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg, in spillInterferences()
482 unsigned RABasic::selectOrSplit(LiveInterval &VirtReg, in selectOrSplit()
DRegAllocFast.cpp176 int RAFast::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) { in getStackSpaceFor()
235 void RAFast::killVirtReg(unsigned VirtReg) { in killVirtReg()
245 void RAFast::spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg) { in spillVirtReg()
386 switch (unsigned VirtReg = PhysRegState[PhysReg]) { in definePhysReg() local
402 switch (unsigned VirtReg = PhysRegState[Alias]) { in definePhysReg() local
429 switch (unsigned VirtReg = PhysRegState[PhysReg]) { in calcSpillCost() local
449 switch (unsigned VirtReg = PhysRegState[Alias]) { in calcSpillCost() local
480 const unsigned VirtReg = LRE.first; in allocVirtReg() local
542 unsigned VirtReg, unsigned Hint) { in defineVirtReg()
576 unsigned VirtReg, unsigned Hint) { in reloadVirtReg()
DLiveIntervalUnion.cpp28 void LiveIntervalUnion::unify(LiveInterval &VirtReg) { in unify()
55 void LiveIntervalUnion::extract(LiveInterval &VirtReg) { in extract()
DRegAllocGreedy.cpp142 void setStage(const LiveInterval &VirtReg, LiveRangeStage Stage) { in setStage()
358 bool RAGreedy::LRE_CanEraseVirtReg(unsigned VirtReg) { in LRE_CanEraseVirtReg()
368 void RAGreedy::LRE_WillShrinkVirtReg(unsigned VirtReg) { in LRE_WillShrinkVirtReg()
444 unsigned RAGreedy::tryAssign(LiveInterval &VirtReg, in tryAssign()
521 bool RAGreedy::canEvictInterference(LiveInterval &VirtReg, unsigned PhysReg, in canEvictInterference()
582 void RAGreedy::evictInterference(LiveInterval &VirtReg, unsigned PhysReg, in evictInterference()
613 unsigned RAGreedy::tryEvict(LiveInterval &VirtReg, in tryEvict()
1085 unsigned RAGreedy::tryRegionSplit(LiveInterval &VirtReg, AllocationOrder &Order, in tryRegionSplit()
1218 unsigned RAGreedy::tryBlockSplit(LiveInterval &VirtReg, AllocationOrder &Order, in tryBlockSplit()
1320 unsigned RAGreedy::tryLocalSplit(LiveInterval &VirtReg, AllocationOrder &Order, in tryLocalSplit()
[all …]
DAllocationOrder.cpp25 AllocationOrder::AllocationOrder(unsigned VirtReg, in AllocationOrder()
DVirtRegMap.cpp183 void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *OldMI, in virtFolded()
197 void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *MI, ModRef MRInfo) { in virtFolded()
281 unsigned VirtReg = MO.getReg(); in rewrite() local
DVirtRegRewriter.cpp369 unsigned VirtReg; member
396 unsigned VirtReg) { in addReuse()
437 unsigned GetRegForReload(unsigned VirtReg, unsigned PhysReg, MachineInstr *MI, in GetRegForReload()
692 unsigned VirtReg = MO.getReg(); in ReMaterialize() local
990 unsigned VirtReg = I->second.first; in FoldsStackSlotModRef() local
1076 void AssignPhysToVirtReg(MachineInstr *MI, unsigned VirtReg, unsigned PhysReg, in AssignPhysToVirtReg()
1275 OptimizeByUnfold2(unsigned VirtReg, int SS, in OptimizeByUnfold2()
1427 unsigned VirtReg = MO.getReg(); in OptimizeByUnfold() local
1519 unsigned VirtReg, unsigned SrcReg, int SS, in CommuteToFoldReload()
1789 unsigned VirtReg = RestoreRegs[e-i-1]; // Reverse order. in InsertRestores() local
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DVirtRegMap.h212 bool hasPreferredPhys(unsigned VirtReg) { in hasPreferredPhys()
230 unsigned getOriginal(unsigned VirtReg) const { in getOriginal()
449 void setIsImplicitlyDefined(unsigned VirtReg) { in setIsImplicitlyDefined()
454 bool isImplicitlyDefined(unsigned VirtReg) const { in isImplicitlyDefined()
/external/llvm/include/llvm/CodeGen/
DLiveIntervalUnion.h88 void unify(LiveInterval &VirtReg) { in unify()
94 void extract(LiveInterval &VirtReg) { in extract()
113 LiveInterval *VirtReg; variable

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