1 /*
2 * Copyright © 2015-2016 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "brw_compiler.h"
25 #include "brw_shader.h"
26 #include "brw_eu.h"
27 #include "common/gen_debug.h"
28 #include "compiler/nir/nir.h"
29 #include "main/errors.h"
30 #include "util/debug.h"
31
32 #define COMMON_OPTIONS \
33 .lower_sub = true, \
34 .lower_fdiv = true, \
35 .lower_scmp = true, \
36 .lower_fmod32 = true, \
37 .lower_fmod64 = false, \
38 .lower_bitfield_extract = true, \
39 .lower_bitfield_insert = true, \
40 .lower_uadd_carry = true, \
41 .lower_usub_borrow = true, \
42 .lower_fdiv = true, \
43 .lower_flrp64 = true, \
44 .native_integers = true, \
45 .use_interpolated_input_intrinsics = true, \
46 .vertex_id_zero_based = true
47
48 static const struct nir_shader_compiler_options scalar_nir_options = {
49 COMMON_OPTIONS,
50 .lower_pack_half_2x16 = true,
51 .lower_pack_snorm_2x16 = true,
52 .lower_pack_snorm_4x8 = true,
53 .lower_pack_unorm_2x16 = true,
54 .lower_pack_unorm_4x8 = true,
55 .lower_unpack_half_2x16 = true,
56 .lower_unpack_snorm_2x16 = true,
57 .lower_unpack_snorm_4x8 = true,
58 .lower_unpack_unorm_2x16 = true,
59 .lower_unpack_unorm_4x8 = true,
60 .max_unroll_iterations = 32,
61 };
62
63 static const struct nir_shader_compiler_options vector_nir_options = {
64 COMMON_OPTIONS,
65
66 /* In the vec4 backend, our dpN instruction replicates its result to all the
67 * components of a vec4. We would like NIR to give us replicated fdot
68 * instructions because it can optimize better for us.
69 */
70 .fdot_replicates = true,
71
72 /* Prior to Gen6, there are no three source operations for SIMD4x2. */
73 .lower_flrp32 = true,
74
75 .lower_pack_snorm_2x16 = true,
76 .lower_pack_unorm_2x16 = true,
77 .lower_unpack_snorm_2x16 = true,
78 .lower_unpack_unorm_2x16 = true,
79 .lower_extract_byte = true,
80 .lower_extract_word = true,
81 .max_unroll_iterations = 32,
82 };
83
84 static const struct nir_shader_compiler_options vector_nir_options_gen6 = {
85 COMMON_OPTIONS,
86
87 /* In the vec4 backend, our dpN instruction replicates its result to all the
88 * components of a vec4. We would like NIR to give us replicated fdot
89 * instructions because it can optimize better for us.
90 */
91 .fdot_replicates = true,
92
93 .lower_pack_snorm_2x16 = true,
94 .lower_pack_unorm_2x16 = true,
95 .lower_unpack_snorm_2x16 = true,
96 .lower_unpack_unorm_2x16 = true,
97 .lower_extract_byte = true,
98 .lower_extract_word = true,
99 .max_unroll_iterations = 32,
100 };
101
102 struct brw_compiler *
brw_compiler_create(void * mem_ctx,const struct gen_device_info * devinfo)103 brw_compiler_create(void *mem_ctx, const struct gen_device_info *devinfo)
104 {
105 struct brw_compiler *compiler = rzalloc(mem_ctx, struct brw_compiler);
106
107 compiler->devinfo = devinfo;
108
109 brw_fs_alloc_reg_sets(compiler);
110 brw_vec4_alloc_reg_set(compiler);
111 brw_init_compaction_tables(devinfo);
112
113 compiler->precise_trig = env_var_as_boolean("INTEL_PRECISE_TRIG", false);
114
115 if (devinfo->gen >= 10) {
116 /* We don't support vec4 mode on Cannonlake. */
117 for (int i = MESA_SHADER_VERTEX; i < MESA_SHADER_STAGES; i++)
118 compiler->scalar_stage[i] = true;
119 } else {
120 compiler->scalar_stage[MESA_SHADER_VERTEX] =
121 devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_VS", true);
122 compiler->scalar_stage[MESA_SHADER_TESS_CTRL] =
123 devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_TCS", true);
124 compiler->scalar_stage[MESA_SHADER_TESS_EVAL] =
125 devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_TES", true);
126 compiler->scalar_stage[MESA_SHADER_GEOMETRY] =
127 devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_GS", true);
128 compiler->scalar_stage[MESA_SHADER_FRAGMENT] = true;
129 compiler->scalar_stage[MESA_SHADER_COMPUTE] = true;
130 }
131
132 /* We want the GLSL compiler to emit code that uses condition codes */
133 for (int i = 0; i < MESA_SHADER_STAGES; i++) {
134 compiler->glsl_compiler_options[i].MaxUnrollIterations = 0;
135 compiler->glsl_compiler_options[i].MaxIfDepth =
136 devinfo->gen < 6 ? 16 : UINT_MAX;
137
138 compiler->glsl_compiler_options[i].EmitNoIndirectInput = true;
139 compiler->glsl_compiler_options[i].EmitNoIndirectUniform = false;
140
141 bool is_scalar = compiler->scalar_stage[i];
142
143 compiler->glsl_compiler_options[i].EmitNoIndirectOutput = is_scalar;
144 compiler->glsl_compiler_options[i].EmitNoIndirectTemp = is_scalar;
145 compiler->glsl_compiler_options[i].OptimizeForAOS = !is_scalar;
146
147 if (is_scalar) {
148 compiler->glsl_compiler_options[i].NirOptions = &scalar_nir_options;
149 } else {
150 compiler->glsl_compiler_options[i].NirOptions =
151 devinfo->gen < 6 ? &vector_nir_options : &vector_nir_options_gen6;
152 }
153
154 compiler->glsl_compiler_options[i].LowerBufferInterfaceBlocks = true;
155 compiler->glsl_compiler_options[i].ClampBlockIndicesToArrayBounds = true;
156 }
157
158 compiler->glsl_compiler_options[MESA_SHADER_TESS_CTRL].EmitNoIndirectInput = false;
159 compiler->glsl_compiler_options[MESA_SHADER_TESS_EVAL].EmitNoIndirectInput = false;
160 compiler->glsl_compiler_options[MESA_SHADER_TESS_CTRL].EmitNoIndirectOutput = false;
161
162 if (compiler->scalar_stage[MESA_SHADER_GEOMETRY])
163 compiler->glsl_compiler_options[MESA_SHADER_GEOMETRY].EmitNoIndirectInput = false;
164
165 return compiler;
166 }
167
168 unsigned
brw_prog_data_size(gl_shader_stage stage)169 brw_prog_data_size(gl_shader_stage stage)
170 {
171 STATIC_ASSERT(MESA_SHADER_VERTEX == 0);
172 STATIC_ASSERT(MESA_SHADER_TESS_CTRL == 1);
173 STATIC_ASSERT(MESA_SHADER_TESS_EVAL == 2);
174 STATIC_ASSERT(MESA_SHADER_GEOMETRY == 3);
175 STATIC_ASSERT(MESA_SHADER_FRAGMENT == 4);
176 STATIC_ASSERT(MESA_SHADER_COMPUTE == 5);
177 static const size_t stage_sizes[] = {
178 sizeof(struct brw_vs_prog_data),
179 sizeof(struct brw_tcs_prog_data),
180 sizeof(struct brw_tes_prog_data),
181 sizeof(struct brw_gs_prog_data),
182 sizeof(struct brw_wm_prog_data),
183 sizeof(struct brw_cs_prog_data),
184 };
185 assert((int)stage >= 0 && stage < ARRAY_SIZE(stage_sizes));
186 return stage_sizes[stage];
187 }
188
189 unsigned
brw_prog_key_size(gl_shader_stage stage)190 brw_prog_key_size(gl_shader_stage stage)
191 {
192 static const size_t stage_sizes[] = {
193 sizeof(struct brw_vs_prog_key),
194 sizeof(struct brw_tcs_prog_key),
195 sizeof(struct brw_tes_prog_key),
196 sizeof(struct brw_gs_prog_key),
197 sizeof(struct brw_wm_prog_key),
198 sizeof(struct brw_cs_prog_key),
199 };
200 assert((int)stage >= 0 && stage < ARRAY_SIZE(stage_sizes));
201 return stage_sizes[stage];
202 }
203