| /external/gemmlowp/meta/generators/ |
| D | qnt_Nx8_neon.py | 26 def BuildName(lanes, leftovers, aligned): argument
35 def LoadAndDuplicateOffsets(emitter, registers, lanes, offsets): argument
86 def GenerateQuantize(emitter, registers, lanes, lane_temps, argument
108 def GenerateLoadQuantizeStore(emitter, registers, lanes, multiplicative_offset, argument
140 def GenerateLoadLeftovers(emitter, registers, leftovers, lanes): argument
193 def GenerateStoreLeftovers(emitter, registers, leftovers, lane_temps, lanes): argument
246 def GenerateLeftoverLoadQuantizeStore(emitter, registers, leftovers, lanes, argument
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| D | zip_Nx8_neon.py | 64 def GenerateClearAggregators(emitter, lanes): argument
69 def GenerateLoadAggregateStore(emitter, lanes, output_address, alignment): argument
88 def GenerateLeftoverLoadAggregateStore(emitter, leftovers, lanes, argument
167 def GenerateAggregatorReduction(emitter, registers, lanes, output_address, argument
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| D | mul_1x8_Mx8_neon.py | 197 def BuildName(result_type, lhs_add, rhs_add, lanes): argument
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| /external/u-boot/drivers/video/ |
| D | anx9804.h | 21 static inline void anx9804_init(unsigned int i2c_bus, u8 lanes, u8 data_rate, in anx9804_init()
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| D | anx9804.c | 28 void anx9804_init(unsigned int i2c_bus, u8 lanes, u8 data_rate, int bpp) in anx9804_init()
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| /external/u-boot/arch/arm/cpu/armv8/fsl-layerscape/ |
| D | ls1043a_serdes.c | 12 u8 lanes[SRDS_MAX_LANES]; member
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| D | ls1012a_serdes.c | 12 u8 lanes[SRDS_MAX_LANES]; member
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| D | ls2080a_serdes.c | 11 u8 lanes[SRDS_MAX_LANES]; member
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| D | ls1046a_serdes.c | 12 u8 lanes[SRDS_MAX_LANES]; member
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| D | ls1088a_serdes.c | 11 u8 lanes[SRDS_MAX_LANES]; member
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| /external/u-boot/arch/powerpc/cpu/mpc85xx/ |
| D | t2080_serdes.c | 15 u8 lanes[SRDS_MAX_LANES]; member
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| D | c29x_serdes.c | 18 u8 lanes[SRDS1_MAX_LANES]; member
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| D | b4860_serdes.c | 14 u8 lanes[SRDS_MAX_LANES]; member
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| D | t4240_serdes.c | 14 u8 lanes[SRDS_MAX_LANES]; member
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| D | fsl_corenet_serdes.c | 63 } lanes[SRDS_MAX_LANES] = { variable
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| /external/tensorflow/tensorflow/core/profiler/lib/ |
| D | profiler_session.cc | 48 std::vector<uint64> lanes; in AssignLanes() local
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| /external/tensorflow/tensorflow/core/profiler/internal/ |
| D | tfprof_timeline.h | 69 std::vector<std::map<int64, int64>> lanes; variable
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| /external/u-boot/arch/arm/mach-tegra/ |
| D | xusb-padctl-common.h | 63 const struct tegra_xusb_padctl_lane *lanes; member
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| /external/u-boot/drivers/pci/ |
| D | pci_tegra.c | 380 static int tegra_pcie_get_xbar_config(ofnode node, u32 lanes, in tegra_pcie_get_xbar_config()
454 static int tegra_pcie_parse_port_info(ofnode node, uint *index, uint *lanes) in tegra_pcie_parse_port_info()
487 u32 lanes = 0; in tegra_pcie_parse_dt() local
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| /external/u-boot/drivers/video/bridge/ |
| D | anx6345.c | 270 u8 chipid, colordepth, lanes, data_rate, c; in anx6345_enable() local
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| /external/skia/src/compute/hs/gen/ |
| D | gen.h | 61 uint32_t lanes; member
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| /external/skqp/src/compute/hs/gen/ |
| D | gen.h | 61 uint32_t lanes; member
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| /external/vixl/src/aarch64/ |
| D | operands-aarch64.h | 411 VIXL_DEPRECATED("GetLanes", int lanes() const) { return GetLanes(); } in lanes() function
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| /external/u-boot/drivers/ddr/fsl/ |
| D | ctrl_regs.c | 2663 u32 sdram_cfg, i, tmp, lanes, ddr_type; in erratum_a009942_check_cpo() local
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| /external/v8/src/mips/ |
| D | simulator-mips.cc | 6396 #define BZ_DF(witdh, lanes) \ in DecodeTypeImmediate() argument
6426 #define BNZ_DF(witdh, lanes) \ in DecodeTypeImmediate() argument
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