1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2012 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <asm/fsl_serdes.h>
8 #include <asm/processor.h>
9 #include <asm/io.h>
10 #include "fsl_corenet2_serdes.h"
11
12 struct serdes_config {
13 u8 protocol;
14 u8 lanes[SRDS_MAX_LANES];
15 };
16
17 #ifdef CONFIG_ARCH_B4860
18 static struct serdes_config serdes1_cfg_tbl[] = {
19 /* SerDes 1 */
20 {0x01, {AURORA, AURORA, CPRI6, CPRI5,
21 CPRI4, CPRI3, CPRI2, CPRI1} },
22 {0x02, {AURORA, AURORA, CPRI6, CPRI5,
23 CPRI4, CPRI3, CPRI2, CPRI1} },
24 {0x04, {AURORA, AURORA, CPRI6, CPRI5,
25 CPRI4, CPRI3, CPRI2, CPRI1} },
26 {0x05, {AURORA, AURORA, CPRI6, CPRI5,
27 CPRI4, CPRI3, CPRI2, CPRI1} },
28 {0x06, {AURORA, AURORA, CPRI6, CPRI5,
29 CPRI4, CPRI3, CPRI2, CPRI1} },
30 {0x07, {AURORA, AURORA, CPRI6, CPRI5,
31 CPRI4, CPRI3, CPRI2, CPRI1} },
32 {0x08, {AURORA, AURORA, CPRI6, CPRI5,
33 CPRI4, CPRI3, CPRI2, CPRI1} },
34 {0x09, {AURORA, AURORA, CPRI6, CPRI5,
35 CPRI4, CPRI3, CPRI2, CPRI1} },
36 {0x0A, {AURORA, AURORA, CPRI6, CPRI5,
37 CPRI4, CPRI3, CPRI2, CPRI1} },
38 {0x0B, {AURORA, AURORA, CPRI6, CPRI5,
39 CPRI4, CPRI3, CPRI2, CPRI1} },
40 {0x0C, {AURORA, AURORA, CPRI6, CPRI5,
41 CPRI4, CPRI3, CPRI2, CPRI1} },
42 {0x0D, {CPRI8, CPRI7, CPRI6, CPRI5,
43 CPRI4, CPRI3, CPRI2, CPRI1}},
44 {0x0E, {CPRI8, CPRI7, CPRI6, CPRI5,
45 CPRI4, CPRI3, CPRI2, CPRI1}},
46 {0x12, {CPRI8, CPRI7, CPRI6, CPRI5,
47 CPRI4, CPRI3, CPRI2, CPRI1}},
48 {0x29, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
49 CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1} },
50 {0x2a, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
51 CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
52 {0x2C, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
53 CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
54 {0x2D, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
55 CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
56 {0x2E, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
57 CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
58 {0x2F, {AURORA, AURORA,
59 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
60 CPRI4, CPRI3, CPRI2, CPRI1} },
61 {0x30, {AURORA, AURORA,
62 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
63 CPRI4, CPRI3, CPRI2, CPRI1}},
64 {0x32, {AURORA, AURORA,
65 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
66 CPRI4, CPRI3, CPRI2, CPRI1}},
67 {0x33, {AURORA, AURORA,
68 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
69 CPRI4, CPRI3, CPRI2, CPRI1}},
70 {0x34, {AURORA, AURORA,
71 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
72 CPRI4, CPRI3, CPRI2, CPRI1}},
73 {0x39, {AURORA, AURORA, CPRI6, CPRI5,
74 CPRI4, CPRI3, CPRI2, CPRI1} },
75 {0x3A, {AURORA, AURORA, CPRI6, CPRI5,
76 CPRI4, CPRI3, CPRI2, CPRI1} },
77 {0x3C, {AURORA, AURORA, CPRI6, CPRI5,
78 CPRI4, CPRI3, CPRI2, CPRI1} },
79 {0x3D, {AURORA, AURORA, CPRI6, CPRI5,
80 CPRI4, CPRI3, CPRI2, CPRI1} },
81 {0x3E, {CPRI8, CPRI7, CPRI6, CPRI5,
82 CPRI4, CPRI3, CPRI2, CPRI1}},
83 {0x5C, {AURORA, AURORA,
84 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
85 CPRI4, CPRI3, CPRI2, CPRI1} },
86 {0x5D, {AURORA, AURORA,
87 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
88 CPRI4, CPRI3, CPRI2, CPRI1} },
89 {}
90 };
91 static struct serdes_config serdes2_cfg_tbl[] = {
92 /* SerDes 2 */
93 {0x17, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
94 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
95 AURORA, AURORA, SRIO1, SRIO1} },
96 {0x18, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
97 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
98 AURORA, AURORA, SRIO1, SRIO1}},
99 {0x1D, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
100 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
101 AURORA, AURORA, SRIO1, SRIO1}},
102 {0x2A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
103 SRIO2, SRIO2,
104 AURORA, AURORA, SRIO1, SRIO1} },
105 {0x2B, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
106 SRIO2, SRIO2,
107 AURORA, AURORA, SRIO1, SRIO1}},
108 {0x30, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
109 SRIO2, SRIO2,
110 AURORA, AURORA,
111 SRIO1, SRIO1}},
112 {0x48, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
113 SGMII_FM1_DTSEC3, AURORA,
114 SRIO1, SRIO1, SRIO1, SRIO1} },
115 {0x49, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
116 SGMII_FM1_DTSEC3, AURORA,
117 SRIO1, SRIO1, SRIO1, SRIO1}},
118 {0x4A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
119 SGMII_FM1_DTSEC3, AURORA,
120 SRIO1, SRIO1, SRIO1, SRIO1}},
121 {0x4C, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
122 SGMII_FM1_DTSEC3, AURORA,
123 SRIO1, SRIO1, SRIO1, SRIO1}},
124 {0x4E, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
125 SGMII_FM1_DTSEC3, AURORA,
126 SRIO1, SRIO1, SRIO1, SRIO1}},
127 {0x79, {SRIO2, SRIO2, SRIO2, SRIO2,
128 SRIO1, SRIO1, SRIO1, SRIO1} },
129 {0x7A, {SRIO2, SRIO2, SRIO2, SRIO2,
130 SRIO1, SRIO1, SRIO1, SRIO1}},
131 {0x83, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
132 SRIO2, SRIO2, AURORA, AURORA,
133 XFI_FM1_MAC9, XFI_FM1_MAC10} },
134 {0x84, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
135 SRIO2, SRIO2, AURORA, AURORA,
136 XFI_FM1_MAC9, XFI_FM1_MAC10}},
137 {0x85, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
138 SRIO2, SRIO2, AURORA, AURORA,
139 XFI_FM1_MAC9, XFI_FM1_MAC10}},
140 {0x86, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
141 SRIO2, SRIO2,
142 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
143 XFI_FM1_MAC9, XFI_FM1_MAC10} },
144 {0x87, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
145 SRIO2, SRIO2,
146 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
147 XFI_FM1_MAC9, XFI_FM1_MAC10}},
148 {0x8C, {SRIO2, SRIO2, SRIO2, SRIO2,
149 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
150 XFI_FM1_MAC9, XFI_FM1_MAC10} },
151 {0x8D, {SRIO2, SRIO2, SRIO2, SRIO2,
152 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
153 XFI_FM1_MAC9, XFI_FM1_MAC10}},
154 {0x93, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
155 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
156 XAUI_FM1_MAC10, XAUI_FM1_MAC10,
157 XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
158 {0x9E, {PCIE1, PCIE1, PCIE1, PCIE1,
159 XAUI_FM1_MAC10, XAUI_FM1_MAC10,
160 XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
161 {0x9A, {PCIE1, PCIE1,
162 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
163 XAUI_FM1_MAC10, XAUI_FM1_MAC10,
164 XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
165 {0xB1, {PCIE1, PCIE1, PCIE1, PCIE1,
166 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
167 XFI_FM1_MAC9, XFI_FM1_MAC10} },
168 {0xB2, {PCIE1, PCIE1, PCIE1, PCIE1,
169 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
170 XFI_FM1_MAC9, XFI_FM1_MAC10}},
171 {0xC3, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
172 XAUI_FM1_MAC9, XAUI_FM1_MAC9,
173 SRIO1, SRIO1, SRIO1, SRIO1}},
174 {0x98, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
175 XAUI_FM1_MAC9, XAUI_FM1_MAC9,
176 XAUI_FM1_MAC10, XAUI_FM1_MAC10,
177 XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
178 {}
179 };
180 #endif
181
182 #ifdef CONFIG_ARCH_B4420
183 static struct serdes_config serdes1_cfg_tbl[] = {
184 {0x0D, {NONE, NONE, CPRI6, CPRI5,
185 CPRI4, CPRI3, NONE, NONE} },
186 {0x0E, {NONE, NONE, CPRI8, CPRI5,
187 CPRI4, CPRI3, NONE, NONE} },
188 {0x0F, {NONE, NONE, CPRI6, CPRI5,
189 CPRI4, CPRI3, NONE, NONE} },
190 {0x17, {NONE, NONE,
191 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
192 NONE, NONE, NONE, NONE} },
193 {0x18, {NONE, NONE,
194 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
195 NONE, NONE, NONE, NONE} },
196 {0x1B, {NONE, NONE,
197 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
198 NONE, NONE, NONE, NONE} },
199 {0x1D, {NONE, NONE, AURORA, AURORA,
200 NONE, NONE, NONE, NONE} },
201 {0x1E, {NONE, NONE, AURORA, AURORA,
202 NONE, NONE, NONE, NONE} },
203 {0x21, {NONE, NONE, AURORA, AURORA,
204 NONE, NONE, NONE, NONE} },
205 {0x3E, {NONE, NONE, CPRI6, CPRI5,
206 CPRI4, CPRI3, NONE, NONE} },
207 {}
208 };
209 static struct serdes_config serdes2_cfg_tbl[] = {
210 {0x48, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
211 SGMII_FM1_DTSEC3, AURORA,
212 NONE, NONE, NONE, NONE} },
213 {0x49, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
214 SGMII_FM1_DTSEC3, AURORA,
215 NONE, NONE, NONE, NONE} },
216 {0x4A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
217 SGMII_FM1_DTSEC3, AURORA,
218 NONE, NONE, NONE, NONE} },
219 {0x6E, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
220 AURORA, AURORA, NONE, NONE, NONE, NONE} },
221 {0x6F, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
222 AURORA, AURORA, NONE, NONE, NONE, NONE} },
223 {0x70, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
224 AURORA, AURORA, NONE, NONE, NONE, NONE} },
225 {0x99, {PCIE1, PCIE1,
226 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
227 NONE, NONE, NONE, NONE} },
228 {0x9A, {PCIE1, PCIE1,
229 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
230 NONE, NONE, NONE, NONE} },
231 {0x9D, {PCIE1, PCIE1, PCIE1, PCIE1,
232 NONE, NONE, NONE, NONE} },
233 {0x9E, {PCIE1, PCIE1, PCIE1, PCIE1,
234 NONE, NONE, NONE, NONE} },
235 {}
236 };
237 #endif
238
239 static struct serdes_config *serdes_cfg_tbl[] = {
240 serdes1_cfg_tbl,
241 serdes2_cfg_tbl,
242 };
243
serdes_get_prtcl(int serdes,int cfg,int lane)244 enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
245 {
246 struct serdes_config *ptr;
247
248 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
249 return 0;
250
251 ptr = serdes_cfg_tbl[serdes];
252 while (ptr->protocol) {
253 if (ptr->protocol == cfg)
254 return ptr->lanes[lane];
255 ptr++;
256 }
257
258 return 0;
259 }
260
is_serdes_prtcl_valid(int serdes,u32 prtcl)261 int is_serdes_prtcl_valid(int serdes, u32 prtcl)
262 {
263 int i;
264 struct serdes_config *ptr;
265
266 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
267 return 0;
268
269 ptr = serdes_cfg_tbl[serdes];
270 while (ptr->protocol) {
271 if (ptr->protocol == prtcl)
272 break;
273 ptr++;
274 }
275
276 if (!ptr->protocol)
277 return 0;
278
279 for (i = 0; i < SRDS_MAX_LANES; i++) {
280 if (ptr->lanes[i] != NONE)
281 return 1;
282 }
283
284 return 0;
285 }
286