| /art/compiler/jni/quick/ |
| D | jni_compiler.cc | 351 ManagedRegister out_reg = main_jni_conv->CurrentParamRegister(); in ArtJniCompileMethodInternal() local
398 ManagedRegister out_reg = main_jni_conv->CurrentParamRegister(); in ArtJniCompileMethodInternal() local
473 ManagedRegister out_reg = main_jni_conv->CurrentParamRegister(); in ArtJniCompileMethodInternal() local
593 ManagedRegister out_reg = end_jni_conv->CurrentParamRegister(); in ArtJniCompileMethodInternal() local
605 ManagedRegister out_reg = end_jni_conv->CurrentParamRegister(); in ArtJniCompileMethodInternal() local
693 ManagedRegister out_reg = jni_conv->CurrentParamRegister(); in CopyParameter() local
717 ManagedRegister out_reg = jni_conv->CurrentParamRegister(); in CopyParameter() local
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| /art/tools/dexanalyze/ |
| D | dexanalyze_bytecode.cc | 266 uint32_t out_reg = inst->VRegA_22c(); in ProcessCodeItem() local
296 uint32_t out_reg = is_jumbo ? inst->VRegA_31c() : inst->VRegA_21c(); in ProcessCodeItem() local
324 uint32_t out_reg = inst->VRegA_21c(); in ProcessCodeItem() local
440 uint32_t out_reg = inst->VRegA_22c(); in ProcessCodeItem() local
454 uint32_t out_reg = inst->VRegA_22c(); in ProcessCodeItem() local
469 uint32_t out_reg = inst->VRegA_21c(); in ProcessCodeItem() local
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| /art/compiler/utils/x86/ |
| D | jni_macro_assembler_x86.cc | 427 X86ManagedRegister out_reg = mout_reg.AsX86(); in CreateHandleScopeEntry() local
468 X86ManagedRegister out_reg = mout_reg.AsX86(); in LoadReferenceFromHandleScope() local
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| /art/compiler/utils/x86_64/ |
| D | jni_macro_assembler_x86_64.cc | 478 X86_64ManagedRegister out_reg = mout_reg.AsX86_64(); in CreateHandleScopeEntry() local
525 X86_64ManagedRegister out_reg = mout_reg.AsX86_64(); in LoadReferenceFromHandleScope() local
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| /art/compiler/utils/arm64/ |
| D | jni_macro_assembler_arm64.cc | 561 Arm64ManagedRegister out_reg = m_out_reg.AsArm64(); in CreateHandleScopeEntry() local
608 Arm64ManagedRegister out_reg = m_out_reg.AsArm64(); in LoadReferenceFromHandleScope() local
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| /art/compiler/utils/arm/ |
| D | jni_macro_assembler_arm_vixl.cc | 486 vixl::aarch32::Register out_reg = AsVIXLRegister(mout_reg.AsArm()); in CreateHandleScopeEntry() local
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| /art/compiler/optimizing/ |
| D | code_generator_arm_vixl.cc | 4264 vixl32::Register out_reg = OutputRegister(rem); in VisitRem() local
4572 vixl32::Register out_reg = RegisterFrom(locations->Out()); in VisitAbs() local
4841 vixl32::Register out_reg = OutputRegister(op); in HandleShift() local
7978 vixl32::Register out_reg = RegisterFrom(out); in VisitBitwiseNegatedRight() local
8196 vixl32::Register out_reg = OutputRegister(instruction); in HandleBitwiseOperation() local
8230 vixl32::Register out_reg = OutputRegister(instruction); in HandleBitwiseOperation() local
8267 vixl32::Register out_reg = RegisterFrom(out); in GenerateReferenceLoadOneRegister() local
8301 vixl32::Register out_reg = RegisterFrom(out); in GenerateReferenceLoadTwoRegisters() local
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| D | code_generator_arm64.cc | 5314 Register out_reg = OutputRegister(abs); in VisitAbs() local
5322 FPRegister out_reg = OutputFPRegister(abs); in VisitAbs() local
5706 Register out_reg = RegisterFrom(out, type); in GenerateReferenceLoadOneRegister() local
5746 Register out_reg = RegisterFrom(out, type); in GenerateReferenceLoadTwoRegisters() local
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| D | code_generator_x86_64.cc | 6949 CpuRegister out_reg = out.AsRegister<CpuRegister>(); in GenerateReferenceLoadOneRegister() local
6982 CpuRegister out_reg = out.AsRegister<CpuRegister>(); in GenerateReferenceLoadTwoRegisters() local
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| D | code_generator_mips64.cc | 5090 GpuRegister out_reg = out.AsRegister<GpuRegister>(); in GenerateReferenceLoadOneRegister() local
5130 GpuRegister out_reg = out.AsRegister<GpuRegister>(); in GenerateReferenceLoadTwoRegisters() local
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| D | intrinsics_arm64.cc | 596 Register out_reg = is_double ? XRegisterFrom(l->Out()) : WRegisterFrom(l->Out()); in GenMathRound() local
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| D | code_generator_x86.cc | 7645 Register out_reg = out.AsRegister<Register>(); in GenerateReferenceLoadOneRegister() local
7678 Register out_reg = out.AsRegister<Register>(); in GenerateReferenceLoadTwoRegisters() local
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| D | intrinsics_arm_vixl.cc | 467 vixl32::Register out_reg = OutputRegister(invoke); in VisitMathRoundFloat() local
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| D | code_generator_mips.cc | 6918 Register out_reg = out.AsRegister<Register>(); in GenerateReferenceLoadOneRegister() local
6958 Register out_reg = out.AsRegister<Register>(); in GenerateReferenceLoadTwoRegisters() local
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| /art/oatdump/ |
| D | oatdump.cc | 1457 for (size_t out_reg = 0; out_reg < num_outs; out_reg++) { in DumpVregLocations() local
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| /art/compiler/utils/mips64/ |
| D | assembler_mips64.cc | 3956 Mips64ManagedRegister out_reg = mout_reg.AsMips64(); in CreateHandleScopeEntry() local
4006 Mips64ManagedRegister out_reg = mout_reg.AsMips64(); in LoadReferenceFromHandleScope() local
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| /art/compiler/utils/mips/ |
| D | assembler_mips.cc | 5121 MipsManagedRegister out_reg = mout_reg.AsMips(); in CreateHandleScopeEntry() local
5170 MipsManagedRegister out_reg = mout_reg.AsMips(); in LoadReferenceFromHandleScope() local
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