| /external/u-boot/drivers/video/exynos/ |
| D | exynos_dp_lowlevel.c | 22 unsigned int reg; in exynos_dp_enable_video_input() local
39 unsigned int reg; in exynos_dp_enable_video_bist() local
55 unsigned int reg; in exynos_dp_enable_video_mute() local
70 unsigned int reg; in exynos_dp_init_analog_param() local
173 unsigned int reg; in exynos_dp_enable_sw_func() local
189 unsigned int reg; in exynos_dp_set_analog_power_down() local
242 unsigned int reg; in exynos_dp_get_pll_lock_status() local
255 unsigned int reg; in exynos_dp_set_pll_power() local
270 unsigned int reg; in exynos_dp_init_analog_func() local
319 unsigned int reg; in exynos_dp_init_hpd() local
[all …]
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| D | exynos_mipi_dsi_lowlevel.c | 20 unsigned int reg; in exynos_mipi_dsi_func_reset() local
34 unsigned int reg = 0; in exynos_mipi_dsi_sw_reset() local
51 unsigned int reg = readl(&mipi_dsim->intsrc); in exynos_mipi_dsi_sw_release() local
63 unsigned int reg = readl(&mipi_dsim->intmsk); in exynos_mipi_dsi_set_interrupt_mask() local
76 unsigned int reg; in exynos_mipi_dsi_init_fifo_pointer() local
104 unsigned int reg; in exynos_mipi_dsi_set_main_disp_resol() local
123 unsigned int reg; in exynos_mipi_dsi_set_main_disp_vporch() local
141 unsigned int reg; in exynos_mipi_dsi_set_main_disp_hporch() local
156 unsigned int reg; in exynos_mipi_dsi_set_main_disp_sync_area() local
172 unsigned int reg; in exynos_mipi_dsi_set_sub_disp_resol() local
[all …]
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| /external/mesa3d/src/amd/vulkan/ |
| D | radv_cs.h | 42 static inline void radeon_set_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned nu… in radeon_set_config_reg_seq()
51 static inline void radeon_set_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) in radeon_set_config_reg()
57 static inline void radeon_set_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned n… in radeon_set_context_reg_seq()
66 static inline void radeon_set_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) in radeon_set_context_reg()
74 unsigned reg, unsigned idx, in radeon_set_context_reg_idx()
84 static inline void radeon_set_sh_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) in radeon_set_sh_reg_seq()
93 static inline void radeon_set_sh_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) in radeon_set_sh_reg()
99 static inline void radeon_set_uconfig_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned n… in radeon_set_uconfig_reg_seq()
108 static inline void radeon_set_uconfig_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) in radeon_set_uconfig_reg()
115 unsigned reg, unsigned idx, in radeon_set_uconfig_reg_idx()
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| /external/u-boot/arch/x86/cpu/quark/ |
| D | msg_port.c | 11 void msg_port_setup(int op, int port, int reg) in msg_port_setup()
18 u32 msg_port_read(u8 port, u32 reg) in msg_port_read()
30 void msg_port_write(u8 port, u32 reg, u32 value) in msg_port_write()
38 u32 msg_port_alt_read(u8 port, u32 reg) in msg_port_alt_read()
50 void msg_port_alt_write(u8 port, u32 reg, u32 value) in msg_port_alt_write()
58 u32 msg_port_io_read(u8 port, u32 reg) in msg_port_io_read()
70 void msg_port_io_write(u8 port, u32 reg, u32 value) in msg_port_io_write()
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| /external/virglrenderer/src/gallium/auxiliary/tgsi/ |
| D | tgsi_sanity.c | 66 scan_register_key(const scan_register *reg) in scan_register_key()
76 fill_scan_register1d(scan_register *reg, in fill_scan_register1d()
86 fill_scan_register2d(scan_register *reg, in fill_scan_register2d()
96 scan_register_dst(scan_register *reg, in scan_register_dst()
114 scan_register_src(scan_register *reg, in scan_register_src()
134 scan_register *reg = MALLOC(sizeof(scan_register)); in create_scan_register_src() local
143 scan_register *reg = MALLOC(sizeof(scan_register)); in create_scan_register_dst() local
202 const scan_register *reg) in is_register_declared()
219 scan_register *reg = (scan_register *)cso_hash_iter_data(iter); in is_any_register_declared() local
231 scan_register *reg) in is_register_used()
[all …]
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| D | tgsi_util.c | 53 const struct tgsi_src_register *reg, in tgsi_util_get_src_register_swizzle()
74 const struct tgsi_full_src_register *reg, in tgsi_util_get_full_src_register_swizzle()
84 struct tgsi_src_register *reg, in tgsi_util_set_src_register_swizzle()
108 const struct tgsi_full_src_register *reg, in tgsi_util_get_full_src_register_sign_mode()
137 struct tgsi_full_src_register *reg, in tgsi_util_set_full_src_register_sign_mode()
356 tgsi_util_get_src_from_ind(const struct tgsi_ind_register *reg) in tgsi_util_get_src_from_ind()
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| /external/mesa3d/src/gallium/auxiliary/tgsi/ |
| D | tgsi_sanity.c | 67 scan_register_key(const scan_register *reg) in scan_register_key()
77 fill_scan_register1d(scan_register *reg, in fill_scan_register1d()
87 fill_scan_register2d(scan_register *reg, in fill_scan_register2d()
97 scan_register_dst(scan_register *reg, in scan_register_dst()
115 scan_register_src(scan_register *reg, in scan_register_src()
135 scan_register *reg = MALLOC(sizeof(scan_register)); in create_scan_register_src() local
144 scan_register *reg = MALLOC(sizeof(scan_register)); in create_scan_register_dst() local
203 const scan_register *reg) in is_register_declared()
220 scan_register *reg = (scan_register *)cso_hash_iter_data(iter); in is_any_register_declared() local
232 scan_register *reg) in is_register_used()
[all …]
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| /external/u-boot/arch/x86/include/asm/arch-quark/ |
| D | msg_port.h | 108 #define msg_port_generic_clrsetbits(type, port, reg, clr, set) \ argument
113 #define msg_port_clrbits(port, reg, clr) \ argument
115 #define msg_port_setbits(port, reg, set) \ argument
117 #define msg_port_clrsetbits(port, reg, clr, set) \ argument
120 #define msg_port_alt_clrbits(port, reg, clr) \ argument
122 #define msg_port_alt_setbits(port, reg, set) \ argument
124 #define msg_port_alt_clrsetbits(port, reg, clr, set) \ argument
127 #define msg_port_io_clrbits(port, reg, clr) \ argument
129 #define msg_port_io_setbits(port, reg, set) \ argument
131 #define msg_port_io_clrsetbits(port, reg, clr, set) \ argument
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| /external/google-breakpad/src/common/ |
| D | dwarf_cfi_to_module.cc | 178 unsigned reg = i; in RegisterName() local
192 void DwarfCFIToModule::Record(Module::Address address, int reg, in Record()
212 bool DwarfCFIToModule::UndefinedRule(uint64 address, int reg) { in UndefinedRule()
218 bool DwarfCFIToModule::SameValueRule(uint64 address, int reg) { in SameValueRule()
225 bool DwarfCFIToModule::OffsetRule(uint64 address, int reg, in OffsetRule()
233 bool DwarfCFIToModule::ValOffsetRule(uint64 address, int reg, in ValOffsetRule()
241 bool DwarfCFIToModule::RegisterRule(uint64 address, int reg, in RegisterRule()
249 bool DwarfCFIToModule::ExpressionRule(uint64 address, int reg, in ExpressionRule()
256 bool DwarfCFIToModule::ValExpressionRule(uint64 address, int reg, in ValExpressionRule()
269 void DwarfCFIToModule::Reporter::UnnamedRegister(size_t offset, int reg) { in UnnamedRegister()
[all …]
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| /external/mesa3d/src/mesa/drivers/dri/radeon/ |
| D | radeon_sanity.c | 322 struct reg { struct
324 struct reg_names *closest; argument
334 static struct reg regs[ARRAY_SIZE(reg_names)+1]; argument
370 static int find_or_add_value( struct reg *reg, int val ) in find_or_add_value()
388 static struct reg *lookup_reg( struct reg *tab, int reg ) in lookup_reg()
402 static const char *get_reg_name( struct reg *reg ) in get_reg_name()
429 static int print_int_reg_assignment( struct reg *reg, int data ) in print_int_reg_assignment()
453 static int print_float_reg_assignment( struct reg *reg, float data ) in print_float_reg_assignment()
484 static int print_reg_assignment( struct reg *reg, int data ) in print_reg_assignment()
495 static void print_reg( struct reg *reg ) in print_reg()
[all …]
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | r600_cs.h | 114 static inline void radeon_set_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned nu… in radeon_set_config_reg_seq()
122 static inline void radeon_set_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) in radeon_set_config_reg()
128 static inline void radeon_set_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned n… in radeon_set_context_reg_seq()
136 static inline void radeon_set_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) in radeon_set_context_reg()
143 unsigned reg, unsigned idx, in radeon_set_context_reg_idx()
153 static inline void radeon_set_sh_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) in radeon_set_sh_reg_seq()
161 static inline void radeon_set_sh_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) in radeon_set_sh_reg()
167 static inline void radeon_set_uconfig_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned n… in radeon_set_uconfig_reg_seq()
175 static inline void radeon_set_uconfig_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) in radeon_set_uconfig_reg()
182 unsigned reg, unsigned idx, in radeon_set_uconfig_reg_idx()
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| /external/compiler-rt/lib/sanitizer_common/ |
| D | sanitizer_asm.h | 27 # define CFI_REL_OFFSET(reg, n) .cfi_rel_offset reg, n argument
28 # define CFI_OFFSET(reg, n) .cfi_offset reg, n argument
29 # define CFI_DEF_CFA_REGISTER(reg) .cfi_def_cfa_register reg argument
30 # define CFI_DEF_CFA(reg, n) .cfi_def_cfa reg, n argument
31 # define CFI_RESTORE(reg) .cfi_restore reg argument
39 # define CFI_REL_OFFSET(reg, n) argument
40 # define CFI_OFFSET(reg, n) argument
41 # define CFI_DEF_CFA_REGISTER(reg) argument
42 # define CFI_DEF_CFA(reg, n) argument
43 # define CFI_RESTORE(reg) argument
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| /external/mesa3d/src/mesa/drivers/dri/r200/ |
| D | r200_sanity.c | 600 struct reg { struct
602 struct reg_names *closest; argument
612 static struct reg regs[ARRAY_SIZE(reg_names)+1]; argument
648 static int find_or_add_value( struct reg *reg, int val ) in find_or_add_value()
666 static struct reg *lookup_reg( struct reg *tab, int reg ) in lookup_reg()
680 static const char *get_reg_name( struct reg *reg ) in get_reg_name()
707 static int print_int_reg_assignment( struct reg *reg, int data ) in print_int_reg_assignment()
731 static int print_float_reg_assignment( struct reg *reg, float data ) in print_float_reg_assignment()
762 static int print_reg_assignment( struct reg *reg, int data ) in print_reg_assignment()
773 static void print_reg( struct reg *reg ) in print_reg()
[all …]
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| /external/mesa3d/src/mesa/state_tracker/ |
| D | st_glsl_to_tgsi_private.cpp | 53 st_src_reg *reg = ralloc(input, st_src_reg); in dup_reladdr() local
135 st_src_reg::st_src_reg(const st_src_reg ®) in st_src_reg()
140 void st_src_reg::operator=(const st_src_reg ®) in operator =()
157 st_src_reg::st_src_reg(st_dst_reg reg) in st_src_reg()
176 st_src_reg reg = *this; in get_abs() local
182 st_dst_reg::st_dst_reg(st_src_reg reg) in st_dst_reg()
236 st_dst_reg::st_dst_reg(const st_dst_reg ®) in st_dst_reg()
241 void st_dst_reg::operator=(const st_dst_reg ®) in operator =()
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| /external/u-boot/arch/riscv/lib/ |
| D | setjmp.S | 10 #define STORE_IDX(reg, idx) sd reg, (idx*8)(a0) argument
11 #define LOAD_IDX(reg, idx) ld reg, (idx*8)(a0) argument
13 #define STORE_IDX(reg, idx) sw reg, (idx*4)(a0) argument
14 #define LOAD_IDX(reg, idx) lw reg, (idx*4)(a0) argument
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| /external/mesa3d/src/gallium/drivers/r600/ |
| D | r600_cs.h | 131 static inline void radeon_set_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned nu… in radeon_set_config_reg_seq()
139 static inline void radeon_set_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) in radeon_set_config_reg()
145 static inline void radeon_set_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned n… in radeon_set_context_reg_seq()
153 static inline void radeon_set_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) in radeon_set_context_reg()
160 unsigned reg, unsigned idx, in radeon_set_context_reg_idx()
170 static inline void radeon_set_sh_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) in radeon_set_sh_reg_seq()
178 static inline void radeon_set_sh_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) in radeon_set_sh_reg()
184 static inline void radeon_set_uconfig_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned n… in radeon_set_uconfig_reg_seq()
192 static inline void radeon_set_uconfig_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) in radeon_set_uconfig_reg()
199 unsigned reg, unsigned idx, in radeon_set_uconfig_reg_idx()
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| /external/mesa3d/src/intel/compiler/ |
| D | brw_ir_vec4.h | 56 retype(src_reg reg, enum brw_reg_type type) in retype()
65 add_byte_offset(backend_reg *reg, unsigned bytes) in add_byte_offset()
99 byte_offset(src_reg reg, unsigned bytes) in byte_offset()
106 offset(src_reg reg, unsigned width, unsigned delta) in offset()
114 horiz_offset(src_reg reg, unsigned delta) in horiz_offset()
124 swizzle(src_reg reg, unsigned swizzle) in swizzle()
135 negate(src_reg reg) in negate()
143 is_uniform(const src_reg ®) in is_uniform()
173 retype(dst_reg reg, enum brw_reg_type type) in retype()
180 byte_offset(dst_reg reg, unsigned bytes) in byte_offset()
[all …]
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| /external/tensorflow/tensorflow/lite/kernels/internal/optimized/ |
| D | depthwiseconv_uint8_transitional.h | 44 #define vst1_lane_8x4(dst, reg, lane_num) \ argument
47 #define vst1q_lane_8x4(dst, reg, lane_num) \ argument
51 #define vld1q_lane_s8x8(src, reg, lane_num) \ argument
53 #define vld1_lane_8x4(src, reg, lane_num) \ argument
55 #define vld1q_lane_8x4(src, reg, lane_num) \ argument
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| /external/u-boot/arch/arm/mach-socfpga/ |
| D | clock_manager_gen5.c | 320 u32 reg, clock; in cm_get_main_vco_clk_hz() local
335 u32 reg, clock = 0; in cm_get_per_vco_clk_hz() local
360 u32 reg, clock; in cm_get_mpu_clk_hz() local
374 u32 reg, clock = 0; in cm_get_sdram_clk_hz() local
405 u32 reg, clock = 0; in cm_get_l4_sp_clk_hz() local
439 u32 reg, clock = 0; in cm_get_mmc_controller_clk_hz() local
469 u32 reg, clock = 0; in cm_get_qspi_controller_clk_hz() local
497 u32 reg, clock = 0; in cm_get_spi_controller_clk_hz() local
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| /external/mesa3d/src/mesa/drivers/dri/i915/ |
| D | i915_program.c | 42 #define A0_DEST( reg ) (((reg)&UREG_TYPE_NR_MASK)>>UREG_A0_DEST_SHIFT_LEFT) argument
43 #define D0_DEST( reg ) (((reg)&UREG_TYPE_NR_MASK)>>UREG_A0_DEST_SHIFT_LEFT) argument
44 #define T0_DEST( reg ) (((reg)&UREG_TYPE_NR_MASK)>>UREG_A0_DEST_SHIFT_LEFT) argument
45 #define A0_SRC0( reg ) (((reg)&UREG_MASK)>>UREG_A0_SRC0_SHIFT_LEFT) argument
46 #define A1_SRC0( reg ) (((reg)&UREG_MASK)<<UREG_A1_SRC0_SHIFT_RIGHT) argument
47 #define A1_SRC1( reg ) (((reg)&UREG_MASK)>>UREG_A1_SRC1_SHIFT_LEFT) argument
48 #define A2_SRC1( reg ) (((reg)&UREG_MASK)<<UREG_A2_SRC1_SHIFT_RIGHT) argument
49 #define A2_SRC2( reg ) (((reg)&UREG_MASK)>>UREG_A2_SRC2_SHIFT_LEFT) argument
53 #define T0_SAMPLER( reg ) (GET_UREG_NR(reg)<<T0_SAMPLER_NR_SHIFT) argument
54 #define T1_ADDRESS_REG( reg ) ((GET_UREG_NR(reg)<<T1_ADDRESS_REG_NR_SHIFT) | \ argument
[all …]
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| /external/v8/src/x64/ |
| D | assembler-x64-inl.h | 64 void Assembler::emit_rex_64(Register reg, Register rm_reg) { in emit_rex_64()
69 void Assembler::emit_rex_64(XMMRegister reg, Register rm_reg) { in emit_rex_64()
74 void Assembler::emit_rex_64(Register reg, XMMRegister rm_reg) { in emit_rex_64()
78 void Assembler::emit_rex_64(XMMRegister reg, XMMRegister rm_reg) { in emit_rex_64()
82 void Assembler::emit_rex_64(Register reg, Operand op) { in emit_rex_64()
86 void Assembler::emit_rex_64(XMMRegister reg, Operand op) { in emit_rex_64()
98 void Assembler::emit_rex_32(Register reg, Register rm_reg) { in emit_rex_32()
102 void Assembler::emit_rex_32(Register reg, Operand op) { in emit_rex_32()
113 void Assembler::emit_optional_rex_32(Register reg, Register rm_reg) { in emit_optional_rex_32()
118 void Assembler::emit_optional_rex_32(Register reg, Operand op) { in emit_optional_rex_32()
[all …]
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| /external/u-boot/arch/arm/mach-imx/mx6/ |
| D | clock.c | 29 u32 reg; in enable_ocotp_clk() local
83 u32 reg; in enable_usboh3_clk() local
156 u32 reg; in enable_i2c_clk() local
196 u32 reg; in enable_spi_clk() local
310 u32 reg, freq; in get_mcu_main_clk() local
322 u32 reg, div = 0, freq = 0; in get_periph_clk() local
372 u32 reg, ipg_podf; in get_ipg_clk() local
383 u32 reg, perclk_podf; in get_ipg_per_clk() local
399 u32 reg, uart_podf; in get_uart_clk() local
417 u32 reg, cspi_podf; in get_cspi_clk() local
[all …]
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| /external/u-boot/drivers/misc/ |
| D | smsc_sio1007.c | 11 static inline u8 sio1007_read(int port, int reg) in sio1007_read()
18 static inline void sio1007_write(int port, int reg, int val) in sio1007_write()
24 static inline void sio1007_clrsetbits(int port, int reg, u8 clr, u8 set) in sio1007_clrsetbits()
69 int reg = GPIO0_DIR; in sio1007_gpio_config() local
92 int reg = GPIO0_DATA; in sio1007_gpio_get_value() local
111 int reg = GPIO0_DATA; in sio1007_gpio_set_value() local
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| /external/u-boot/arch/arm/mach-imx/mx7ulp/ |
| D | pcc.c | 83 u32 reg, val; in pcc_clock_enable() local
113 u32 reg, val, i, clksrc_type; in pcc_clock_sel() local
162 u32 reg, val; in pcc_clock_div_config() local
198 u32 reg, val; in pcc_clock_is_enable() local
214 u32 reg, val, clksrc_type; in pcc_clock_get_clksrc() local
255 u32 reg, val, rate, frac, div; in pcc_clock_get_rate() local
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| /external/u-boot/board/freescale/t208xrdb/ |
| D | cpld.c | 12 u8 cpld_read(unsigned int reg) in cpld_read()
19 void cpld_write(unsigned int reg, u8 value) in cpld_write()
29 u8 reg = CPLD_READ(flash_csr); in cpld_set_altbank() local
39 u8 reg = CPLD_READ(flash_csr); in cpld_set_defbank() local
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